Planar light-emitting transistor device capable of surface light source emission, and preparation method therefor and application thereof

Abstract

The present invention discloses a planar light-emitting transistor device that emits light from a planar light source, a method for manufacturing the same, and an application. By inserting a charge buffer layer between a semiconductor charge transport layer and a light-emitting unit, the manufactured planar light-emitting transistor can achieve stable light-emitting from a planar light source, thereby effectively overcoming the disadvantage that the emitted light of conventional planar light-emitting transistors is linear or strip-shaped. The planar light-emitting transistor device that emits light from the planar light source has high integration density and can achieve stable light-emitting from a planar light source. It effectively improves the aperture ratio of the transistor device, possesses good gate control capabilities, high loop stability, and arbitrary controllability, is easy to miniaturize, enables mass production, and has good compatibility with flexible wearable devices, thus playing an important role in promoting the application of light-emitting transistor devices in the field of light-emitting displays.

Description

Technology Field

[0001] The present invention claims priority to two prior applications, patent application number 202111288584.3 submitted by the applicant to the National Intellectual Property Administration of China on November 2, 2021, with the title of the invention "Planar light-emitting field-effect transistor emitting from a planar light source, method of manufacturing the same, and application"; and patent application number 202111460089.6 submitted by the applicant to the National Intellectual Property Administration of China on December 1, 2021, with the title of the invention "Planar light-emitting field-effect transistor emitting from a planar light source, method of manufacturing the same, and application", the entire contents of said prior applications are incorporated into the present invention by reference.

[0002] The present invention relates to the field of electroluminescent devices, and specifically to a planar light-emitting transistor that emits light from a planar light source, a method for manufacturing the same, and an application. Background Technology

[0003] The display industry has established itself as a core industry of the information technology (IT) sector. Light-emitting transistors (LEDs) are a type of highly integrated electroluminescent device; by combining the current amplification function of organic transistors with the electroluminescent function of organic light-emitting diodes (OLEDs) into a single device, they possess unique advantages such as high integration density and simple manufacturing processes. Consequently, they are considered a critical component for realizing innovative next-generation display technologies featuring miniaturization, flexibility, and high resolution.

[0004] Currently, the classical configurations of light-emitting transistors are classified into planar and vertical types. Vertical light-emitting transistors have short channels, making it easy to implement low-voltage driving and planar light source emission, but they require the installation of porous source electrodes that are difficult to manufacture due to the operating mechanism, which affects the stability and uniformity of the device; planar light-emitting transistor processes have good compatibility with existing industries and the devices are relatively stable, but they are not suitable for application in displays because electrons and holes generally recombine at one side of the channel and electrode, resulting in a linear light source.

[0005] Enabling light-emitting transistors to possess not only good device processability and stability but also stable planar light emission through the rational design of device structures is a technical challenge that the industry urgently needs to address.

[0006] The present invention provides a planar light source emitting transistor, comprising a source electrode, a drain electrode, and a charge buffer layer installed below the source electrode or the drain electrode.

[0007] According to an embodiment of the present invention, the planar light source planar light-emitting transistor further comprises a semiconductor charge transport layer.

[0008] Preferably, the semiconductor charge transport layer is installed below the source electrode. In one embodiment of the present invention, the charge buffer layer is installed above the semiconductor charge transport layer.

[0009] According to an embodiment of the present invention, the transistor further comprises a light-emitting unit, and preferably, the light-emitting unit is installed below the drain electrode.

[0010] In one embodiment of the present invention, the charge buffer layer is installed below the light-emitting unit. In another embodiment of the present invention, the charge buffer layer is installed below the source electrode and the light-emitting unit.

[0011] According to an embodiment of the present invention, the charge buffer layer may be installed between the drain electrode (or source electrode) and the semiconductor charge transport layer or between the semiconductor charge transport layer and the light-emitting unit.

[0012] According to an embodiment of the present invention, the light-emitting surface (including the light-emitting unit) of the transistor is U-shaped, and the source electrode is installed on the U-shaped opening side.

[0013] According to one embodiment of the present invention, the planar shape of the drain electrode, the light-emitting unit, and the charge buffer layer is U-shaped, and the source electrode is installed on the U-shaped opening side.

[0014] According to another embodiment of the present invention, the planar shape of the drain electrode and the light-emitting unit is U-shaped, the source electrode is installed on the U-shaped opening side, and preferably, the charge buffer layer is installed below the source electrode.

[0015] Preferably, the planar light source planar light-emitting transistor is,

[0016] Support substrate;

[0017] A gate electrode installed on the surface of the above-mentioned support substrate;

[0018] A dielectric layer installed on the gate electrode above;

[0019] A semiconductor charge transport layer installed on the above dielectric layer;

[0020] A source electrode and a charge buffer layer installed on the semiconductor charge transport layer, preferably on different sides of the charge transport layer; and

[0021] It includes a light-emitting unit and a drain electrode installed sequentially on a charge buffer layer.

[0022] Preferably, the planar light source planar light-emitting transistor is,

[0023] Support substrate;

[0024] A gate electrode installed on the surface of the above-mentioned support substrate;

[0025] A dielectric layer installed on the gate electrode above;

[0026] A semiconductor charge transport layer installed on the above dielectric layer;

[0027] A charge buffer layer installed on the semiconductor charge transport layer above;

[0028] Source electrodes and light-emitting units sequentially installed on a charge buffer layer, preferably on different sides of the charge buffer layer; and

[0029] It includes a drain electrode installed on the light-emitting unit.

[0030] When an element such as a layer, film, crystal, region, or substrate is referred to as being installed "above another element" / "below another element" or "between two elements," it should be noted that it may be installed directly above or below another element, or that there may be one or more layers interposed in between.

[0031] According to an embodiment of the present invention, the source electrode and the drain electrode are arranged in a non-planar manner, that is, there is a height difference between them. For example, both the source electrode and the charge buffer layer are located on a semiconductor charge transport layer, and there may or may not be a gap between them, and the thickness may or may not be the same or different, and optionally the charge buffer layer may cover the source electrode or the two may be independent of each other, and the drain electrode is installed on the charge buffer layer (the drain electrode may completely cover or partially cover the charge buffer layer), and a conductive channel is formed between the drain electrode and the source electrode; optionally, a light-emitting unit is installed between the drain electrode and the charge buffer layer, and the light-emitting unit may completely cover or partially cover the charge buffer layer and / or the source electrode. For example, both the source electrode and the light-emitting power source are installed on a charge buffer layer, the drain electrode is installed on a light-emitting unit, a conductive channel is formed between the drain electrode and the source electrode, optionally the thicknesses of the source electrode and the light-emitting unit are the same or different, optionally there may or may not be a gap between the light-emitting unit and the source electrode, optionally the light-emitting unit covers the source electrode or the two are independent of each other. The light-emitting portion is the entire effective area of ​​the source electrode or the drain electrode, and the gate voltage can control the light emission brightness.

[0032] According to an embodiment of the present invention, the charge buffer layer and the source electrode may be installed on different sides of the semiconductor charge transport layer. The inventors have proposed the introduction of the charge buffer layer and its location for the first time, and those skilled in the art may adjust the thickness and area of ​​the charge buffer layer and other layers according to actual needs.

[0033] According to an embodiment of the present invention, the material in the semiconductor charge transport layer has good electrical performance, and preferably, the mobility of the semiconductor charge transport layer is 0.1 cm 2 V -1 s -1 It is not lower than. For example, the semiconductor charge transport layer comprises an organic semiconductor material and / or an inorganic semiconductor material, and for example, the organic semiconductor material is selected from small molecule materials and / or polymer materials.

[0034] Preferably, the organic semiconductor material is 2,7-dioctyl[1]benzothieno[3,2-b]benzothiophene (C8-BTBT), 2,6-diphenylanthracene (DPA), 2,6-dinaphthylanthracene (dNaAnt), 2,6-bis(pn-hexylbenzene)anthracene (C6-DPA), 2,6-bis(p-octylbenzene)anthracene (C8-DPA), and 2,6-bis(p-decylbenzene)anthracene (C 10 It is selected from one or more of the following materials, including but not limited to -DPA), poly(3-hexylthiophene)(P3HT), 9,9-di-n-octylfluorene-benzothiadiazole copolymer (F8BT), and poly[2,5-(2-octyldodecyl)-3,6-diketopyrrolopyrrole-alt-5,5-(2,5-bis(thiophene-2-yl)thieno[3,2-b]thiophene)](DPP-DTT), and more preferably C8-BTBT.

[0035] Preferably, the inorganic semiconductor material is selected from one or more materials including but not limited to carbon nanotubes (CNTs), zinc tin oxide (ZTO), gallium nitride (GaN), silicon carbide (SiC), and zinc selenide (ZnSe).

[0036] According to an embodiment of the present invention, the material in the charge buffer layer has suitable electrical performance and is selected from one or more of, for example, low mobility organic materials, metallic materials, pnp junctions, etc.; preferably, the low mobility means a size that is 2 to 5 times smaller than the mobility of the semiconductor charge transport layer. For example, the charge buffer layer is a layer formed of one or more of the low mobility organic materials 4,4'-cyclohexylbis[N,N-bis(4-methylphenyl)aniline] (TAPC), N,N'-diphenyl-N,N'-(1-naphthyl)-1,1'-biphenyl-4,4'-diamine (NPB), and polyvinylcarbazole (PVK), and more preferably, a layer formed of TAPC. As another example, the work function of the metallic material is matched with the highest occupied molecular orbital (HOMO) energy level of the light-emitting unit, and the work function of the metallic material can be defined as 4.5 eV to 6 eV; Preferably, the charge buffer layer is a layer formed from one or more of the following metal materials: Au, for example, Au, Ni, Pt, etc., for example, an ultrathin film layer, and the layer thickness may be 0.5 to 10 nm, for example, 1 nm, 2 nm, 3 nm. As another example, the charge buffer layer is a layer formed from one or more of the following pnp junctions: C60-pentacene-C60, C70-tetracene-C70, C60-tetracene-C70, etc.

[0037] According to an embodiment of the present invention, when the material in the charge buffer layer is a low-mobility organic material or a pnp junction, the thickness of the charge buffer layer is 20 to 80 nm, for example, 30 nm, 40 nm, or 50 nm.

[0038] According to an embodiment of the present invention, the light-emitting unit comprises a light-emitting layer and an electron transport layer, a hole transport layer, an electron injection layer, and / or a hole injection layer that matches the energy level of the light-emitting layer.

[0039] Furthermore, the light-emitting layer may be a layer formed of a light-emitting material having a light-emitting mechanism known in the art, and, for example, the light-emitting material is selected from one or more materials including, but not limited to, fluorescent materials, phosphorescent materials, and thermally active delayed fluorescent materials.

[0040] Preferably, the fluorescent material is selected from one or more of octahydroxyquinoline aluminum (Alq3), 5,6,11,12-tetraphenyltetracene (i.e., Rubrene), and 4,4'-bis[4-(diphenylamino)styryl]biphenyl (BDAVBi).

[0041] Preferably, the phosphorescent material is selected from one or more of tris(2-phenylpyridine)iridium (Ir(ppy)3), bis(2-phenylpyridine-C2,N)acetylacetonate iridium (Ir(ppy)2(acac)) and iridium(III)tris[N,N'-diphenylbenzimidazole-2-ylidene-C2,C2'] (Ir(dpbic)3).

[0042] Preferably, the heat-activated delayed fluorescent material is selected from one or two of 9,9'-(5-(4,6-diphenyl-1,3,5-triazol-2-yl)-1,3-phenylene)bis(9H-carbazole)(DCzTRZ), (N-phenoxazine)phenyl]thiosulfone (PXZ-DPS), and 10-(4-(4,6-diphenyl-1,3,5-triazol-2-yl)phenyl)-9,9-dimethyl-9,10-dihydroacridine (DMAC-TRZ).

[0043] Furthermore, the spectrum of light emitted by the above-mentioned light-emitting unit is between 390 nm and 780 nm.

[0044] As another example, the light-emitting layer of the light-emitting unit may be a single light-emitting material or a guest doping host material. In the present invention, the term "doping" means that a material of one layer having different physical properties from the material occupying the largest weight percent of the layer is added to the material occupying the largest weight percent in an amount not exceeding 30% by weight. The matrix material of one layer and the dopant material are distinguished from each other.

[0045] According to an embodiment of the present invention, the single luminescent material is preferably Alq3, DPA, or dNaAnt; the guest doping material in the guest doping host material may be one or more, and the host material may be a single material or a mixture; and the guest doping material is preferably 1,4-bis(10-phenylanthracene-9-yl)benzene (BD-1), BDAVBi, perylene, bisdimethyl-dihydroacridinephenylthiosulfone (DMAC-DPS), bis[2-(5-cyano-4,6-difluorophenyl)pyridine-C2,N)]pyridinecarboxylidium (FCNirPic), iridium(III)bis[(2,3,4-difluorophenyl)-pyridine-N,C2']picolinate (Ir(tfpd)2pic), bis[2,4-dimethyl-6-(4-methyl-2-quinolyl- N)phenyl- C](2,2,6,6-tetramethyl-3,5-heptanedione- O3(Ir(mphmq)2tmd), 4,4'-bis[4-(di-p-tolylamino)styryl]biphenyl(DPAVBi), 9,9'-(5-(4,6-diphenyl-1,3,5-triazine-2-yl)-1,3-benzene)bis(9H-carbazole)(DCzTrz), 5,5-dibromo-4,4-tetrakis-2,2-bithiophene(fac-Ir(dpbic)3), tris(2-phenylpyridine)iridium(Ir(ppy)3), tris[2-(p-tolyl)pyridine]iridium(III)(Ir(mppy)3), bis(2-phenylpyridine-C2,N)acetylacetonate iridium(III)(Ir(ppy)2(acac)), Bis(2-(napt-2-yl)pyridine)(acetylacetone)iridium(III)(Ir(npy)2acac), tris[2-(3-methyl-2-pyridyl)phenyl]iridium(Ir(3mppy)3), bis(2-(3,5-dimethylphenyl)quinoline-C2,N')(acetylacetone)iridium(III)(Ir(dmpq)2acac), bis(2-(2'-benzothienyl)-pyridine-N,C3')iridium(acetylacetone)(Ir(btp)2(acac)), 4-(dicyanomethylene)-2-methyl-6-[2-(2,3,6,7-tetrahydro-1H,5H-benzo[ij]quinolizine-9-yl)vinyl]-4H-pyran(DCM2), One or more of 5,6,11,12-tetraphenyltetracene (i.e., Rubrene), tris(2-(3,5-dimethylphenyl)quinoline-C2,N')iridium(III)(Ir(dmpq)3), and 2,8-di-tert-butyl-5,11-bis(4-tert-butylphenyl)-6,12-diphenyltetracene (TBRb);The host material is preferably Alq3, 4,4'-bis(N-carbazole)-1,1'-biphenyl (CBP), 4,4'-bis(2,2-diphenyl-vinyl-1-yl)-4,4'-dimethylphenyl (p-DMDPVBi), 4,4'-bis(2,2-diphenylvinyl)-1,1'-biphenyl (DPVBi), 2-tert-butyl-9,10-bis(2-naphthyl)anthracene (TBADN), diphenyl[4-(triphenylsilyl)phenyl]phosphine oxide (TSPO1), 3-(3-(9H-carbazole-9-yl)phenyl)benzofuran[2,3-b]pyridine (PCz-BFP), 2,4,6-tris[3-(diphenylphosphineoxy)phenyl]-1,3,5-triazole (PO-T2T), It is one or more of 2,4,6-tris(3-(carbazole-9-yl)phenyl)-1,3,5-triazine (TCPZ), 4,4'-bis(triphenylsilyl)-1,1'-biphenyl (BSB), 2,7-bis[9,9-bis(4-methylphenyl)-fluoren-2-yl]-9,9-bis(4-methylphenyl)fluoren (TDAF), 3',3'',3'''-(1,3,5-triazine-2,4,6-triyl)tris(([1,1'-biphenyl]-3-nitrile))(CN-T2T), and 10-(4-(4,6-diphenyl-1,3,5-triazole-2-yl)phenyl)-9,9-dimethyl-9,10-dihydroacridine (DMAC-TRZ).

[0046] Preferably, the light-emitting unit is a green light-emitting unit 10% Ir(ppy)3:CBP / 3TPYMB, a red light-emitting unit 5% Ir(mphmq)2tmd:CBP / Tmpypb, or a blue light-emitting unit 10% BD-1:CBP / B3pypb; exemplarily, 20 nm 10% Ir(ppy)3:CBP / 40 nm 3TPYMB, 20 nm 5% Ir(mphmq)2tmd:CBP / 40 nm Tmpypb, or 20 nm 10% BD-1:CBP / 40 nm B3pypb.

[0047] In one embodiment, the light-emitting unit is a white light-emitting unit, for example, 2% Rubrene:DMAC-TRZ / 3TPYMB, and in another example, 30 nm 2% Rubrene:DMAC-TRZ / 40 nm 3TPYMB.

[0048] According to an embodiment of the present invention, the semiconductor charge transport layer, charge buffer layer, and light-emitting unit may be obtained using processing methods known in the art that are advantageous for charge transport and visible light emission, and said processing methods include, but are not limited to, vacuum thermal evaporation, physical vapor transport, solution shearing, solution epitaxy, spin coating, and inkjet printing. Those skilled in the art will understand that a specific method can be specifically selected depending on the physical properties of the semiconductor material actually used (e.g., solubility, melting point, boiling point, etc.).

[0049] For example, a method for manufacturing an active layer including the semiconductor charge transport layer, charge buffer layer, and light-emitting unit is,

[0050] Method 1 for obtaining an active layer by depositing a film of the small molecule material on the dielectric layer and electrode through vacuum evaporation deposition in a deposition chamber;

[0051] Method 2 for obtaining an active layer by spin-coating a solution of an active layer material onto the dielectric layer and electrode using a spin-coating method;

[0052] Preparation and growth of a single-crystal film of the above-mentioned small molecule material through solution epitaxy: a uniformly mixed solution obtained by dissolving the above-mentioned small molecule material in a solvent that does not mix with water is slowly added dropwise to a water surface, the mixed solution spreads on the water surface, and after the solvent within it evaporates, the above-mentioned single-crystal film is obtained; a method 3 for obtaining an active layer by inserting a support substrate having a dielectric layer into water and transferring the above-mentioned single-crystal film to the surface of the dielectric layer; and

[0053] Preparation of a single-crystal film of the above-mentioned small molecule material through a solution shearing method: This can be selected from any one of the following methods: dissolving the above-mentioned small molecule material in an organic solvent, dropping the obtained uniformly mixed solution onto a supporting substrate having a dielectric layer, and then slowly shearing and stretching the dropped solution to form an active layer.

[0054] Charge is injected from one end of the semiconductor charge transport layer (e.g., source electrode) and transferred to the other end through an extremely thin conductive channel formed under an external gate voltage, and through the action of the charge buffer layer, a relatively uniform current injection is formed under the other electrode (e.g., drain electrode), which recombines with electrons injected from the drain electrode to produce a uniform surface light source.

[0055] According to an embodiment of the present invention, the thicknesses of the semiconductor charge transport layer, the charge buffer layer, and the light-emitting unit are all at the nanometer to submicron level, for example, the thickness of each layer may independently be 5 to 500 nm, for example, 10 to 100 nm.

[0056] According to an embodiment of the present invention, the number of light-emitting members (meaning a charge buffer layer and a light-emitting unit) is at least one, for example, two, or three or more. When the number of light-emitting members is two or three or more, the charge buffer layer and the light-emitting unit among them may optionally be the same or different. Each light-emitting member is connected to one another through a charge generating layer (CGL).

[0057] According to an embodiment of the present invention, the source electrode, drain electrode, and gate electrode of the planar light source planar light-emitting transistor may all be transparent electrodes or opaque electrodes, and independently thereof, metals such as magnesium, calcium, sodium, potassium, titanium, indium, yttrium, lithium, gadolinium, aluminum, silver, tin, nickel, gold, molybdenum, iron, and lead; alloys of the aforementioned metals; multilayer materials such as LiF / Al, LiO2 / Al, or LiF / Al / Ag; and ITO, IZO, MoO x It is selected from one or more of the following materials, including but not limited to metal oxides such as the above; and highly doped silicon. Those skilled in the art will understand that the specifically selected type of metal can be adjusted according to the energy band of the semiconductor material.

[0058] According to an embodiment of the present invention, the source electrode, drain electrode, and gate electrode are manufactured by selecting a method known in the art. For example, at least one of vacuum thermal deposition, inkjet printing, electron beam deposition, etc., may be selected.

[0059] According to an embodiment of the present invention, the type of dielectric layer is not particularly limited and may be an inorganic dielectric layer and / or an organic dielectric layer. For example, the dielectric layer is an inorganic dielectric layer such as a dielectric layer formed of an inorganic oxide (Al2O3, SiO2); and / or, the dielectric layer is an organic dielectric layer such as a dielectric layer formed of polymethyl methacrylate (PMMA).

[0060] According to an embodiment of the present invention, the dielectric layer may be manufactured by selecting a method known in the art. For example, at least one of thermal growth, physical vapor deposition, spin coating, etc., may be selected.

[0061] According to an embodiment of the present invention, the thickness of the dielectric layer is not particularly limited. For example, the thickness of the dielectric layer is 10 to 800 nm. A person skilled in the art can adjust the thickness of the dielectric layer as needed.

[0062] According to an embodiment of the present invention, the support substrate is a rigid substrate (e.g., silicon dioxide wafer, glass or quartz, etc.) or a flexible substrate (e.g., PC, PMMA, PDMS, etc.).

[0063] According to an embodiment of the present invention, the planar light source transistor may use an upper-emitting or lower-emitting device structure.

[0064] According to an embodiment of the present invention, the planar light-emitting transistor of the planar light source can emit planar light that matches the color of the light-emitting unit under an externally applied voltage.

[0065] The present invention also provides a method for manufacturing a planar light-emitting transistor that emits light from the above-described planar light source, comprising the step of installing a charge buffer layer below a drain electrode or a source electrode; wherein the drain electrode, the source electrode, and the charge buffer layer all have the meanings as described above.

[0066] According to an embodiment of the present invention, the manufacturing method comprises the step of installing a charge buffer layer between a drain electrode (or source electrode) and a semiconductor charge transport layer, or installing a charge buffer layer between a semiconductor charge transport layer and a light-emitting unit;

[0067] The above drain electrode, source electrode, semiconductor charge transport layer, light-emitting unit, and charge buffer layer all have the meanings described above.

[0068] Preferably, a structure including the semiconductor charge transport layer, charge buffer layer, and light-emitting unit is recorded as an active layer, and the active layer is manufactured according to the above embodiment.

[0069] The transistor device of the present invention has excellent compatibility with low-temperature manufacturing processes such as solution processing (inkjet printing, electrofluid printing, roll-to-roll, etc.).

[0070] The present invention also provides an application of a planar light-emitting transistor emitted from the planar light source in a wearable device.

[0071] The present invention also provides applications of planar light-emitting transistors emitted from the planar light source in fields such as lighting displays, optical communication, or new optoelectronic integration. For example, other related applications include lasers.

[0072] The present invention also provides an application of a planar light-emitting transistor emitted from the planar light source in lighting fields such as white light illumination.

[0073] The planar light-emitting transistor emitted from the above-mentioned planar light source may be a transistor comprising one light-emitting element, or a series transistor comprising at least two light-emitting elements.

[0074] The beneficial effects of the present invention are as follows.

[0075] In conventional planar light-emitting transistors, most devices emit linear or strip-shaped light, and thus cannot provide a good planar light source. To overcome the disadvantages present in conventional light-emitting transistors, the present invention proposes a light-emitting transistor having a charge buffer layer. By inserting a charge buffer layer below the source electrode or drain electrode, between the drain electrode (or source electrode) and the semiconductor charge transport layer, or between the charge transport layer and the light-emitting unit, the inventors can redistribute the current density in the transistor, thereby enabling the fabricated planar light-emitting transistor to achieve stable planar light source emission and provide uniform RGB emission. In addition, a good gate control function (on / off ratio 10 6It has high loop stability and arbitrary tunability, and a high aperture ratio adjustable according to actual needs, for example, a high aperture ratio adjustable from less than 10% of conventional technology to more than 94%. Due to the flexible characteristics of organic semiconductors, it can be integrated with wearable devices, which is more advantageous for expanding the functions and application scenarios of wearable surface light source emitting devices.

[0076] 1. A planar light-emitting transistor device that emits light from a planar light source according to the present invention can achieve planar light source emission that emits light without being affected by the gate voltage, which helps in the application of the device in the display field.

[0077] 2. A planar light-emitting transistor device emitted from a planar light source according to the present invention can realize the construction of a high aperture ratio electroluminescent device, is compatible with flexible wearable devices, and plays an important promoting role in the development of light-emitting transistor devices.

[0078] 3. By developing a light-emitting transistor device that emits light from a planar light source based on an organic semiconductor, the present invention can make full use of the advantages of an organic semiconductor material system that is abundant, inexpensive, and easy to process, and provides an effective solution for large-area control and array manufacturing of the light-emitting transistor device.

[0079] "Aperture ratio" refers to the ratio of the area of ​​the light-emitting surface to the sum of the areas of the light-emitting surface and the aperture surface. By adjusting the area ratio of the light-emitting surface, a transistor having a series of aperture ratios (for example, aperture ratios are 10%, 15%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 82%, 85%, 88%, 90%, and 94%) can be obtained. Brief explanation of the drawing

[0080] FIG. 1a is a schematic diagram of the structure of a light-emitting transistor device emitted from a surface light source manufactured in Examples 1 to 4. FIG. 1b is a schematic diagram of the structure of a light-emitting transistor device emitted from a surface light source manufactured in Example 5. FIG. 2a is a planar light source emission optical microscope image of red, green, blue, and primary color planar light-emitting transistor devices manufactured in Examples 1, 2, and 3, respectively. FIG. 2b shows the typical transfer curve (a), output curve (b), and emission spectrum (c) of the green planar light-emitting transistor device manufactured in Example 1. Figure 3 is an optical photograph and an optical photograph of a planar light-emitting transistor device having a high aperture ratio and emitting light from a planar light source in Example 4. Figure 4 shows the typical transfer curve and emission spectrum of a planar light-emitting transistor with a high turn rate emitted from a planar light source in Example 4. FIG. 5 is a schematic diagram of the structure of a planar light-emitting series transistor that emits light from a planar light source including three light-emitting members in Example 8. Figure 6 is a schematic diagram of the structure (left) and an optical photograph (right, scale 0.2 mm) of a light-emitting transistor device emitted from a surface light source manufactured in Example 9. Figure 7 shows the relationship curve between source current and drain current-luminance-gate voltage of the device of Example 9 (left) and the relationship diagram between external quantum efficiency (EQE) and luminance (right). Figure 8 is a photograph of the light emission of the device of Example 9 when the gate voltage is -5 V, -6 V, and -20 V. Specific details for implementing the invention

[0081] The present invention will be further described below with reference to specific embodiments. It should be understood that these embodiments are intended only to illustrate the invention and are not intended to limit the scope of protection of the invention. Furthermore, it should be understood that after reading the disclosure of the present invention, those skilled in the art may make various changes or modifications to the invention, and that such equivalent forms also fall within the scope of protection limited by the present invention.

[0082] The experimental methods used in the following examples are all conventional methods unless otherwise noted; and the reagents, materials, etc. used in the following examples are all commercially available unless otherwise noted.

[0083] Example 1. CBP: Planar light-emitting transistor device emitting from a planar light source of an Ir(ppy)3-based green light-emitting unit

[0084] 1) Si / SiO2 Wafer Cleaning and Water-soluble Layer Modification:

[0085] Before use, a silicon wafer having a SiO2 oxide layer was first washed with hydrogen peroxide and concentrated sulfuric acid in a volume ratio of approximately 1:2 (heated in an electric furnace and boiled for 15 minutes), then sequentially sonicated with deionized water, acetone, and isopropyl alcohol for approximately 10 minutes each, and rapidly dried using nitrogen. The surface energy levels were modified in an O2 plasma cleaner for 5 minutes to remove residual organic solvent from the surface. Then, it was dried in a 90°C oven for 90 minutes. Finally, a drop of octadecyltrichlorosilane (OTS) was placed in the middle of a Petri dish containing the silicon wafer using a capillary tube, and the Petri dish was placed in a 120°C oven and heated for 120 minutes, after which it was allowed to cool naturally.

[0086] 2) Fabrication of the organic charge transport layer (i.e., semiconductor charge transport layer) C8-BTBT

[0087] A patterned metal mask was securely fixed to the substrate, and 50 nm of C8-BTBT was thermally evaporated from the Si / SiO2 wafer modified in step 1) using a vacuum coater. Immediately after the evaporation was completed, an annealing treatment was performed at a temperature of 45°C for 20 minutes.

[0088] 3) Preparation of source electrode

[0089] Replace the mask to secure it firmly to the substrate, and use a vacuum coater to apply a 2 nm layer of MoO2 to one side of the organic charge transport layer. x and 40 nm Au was thermally evaporated.

[0090] 4) Manufacture of charge buffer layer and light-emitting unit:

[0091] The mask was replaced and securely fixed to the substrate, and a charge buffer layer 40 nm TAPC and a light-emitting unit 20 nm 10% Ir(ppy)3:CBP / 40 nm 3TPYMB were sequentially deposited on the other side of the organic charge transport layer using a vacuum coating machine.

[0092] 5) Preparation of drain electrode:

[0093] The mask was replaced and securely fixed to the substrate, and 0.5 nm LiF / 1 nm Al / 35 nm Ag were sequentially deposited as drain electrodes on the light-emitting unit using a vacuum coating machine. After the fabrication of the device was completed, the device structure is shown in Fig. 1.

[0094] 6) Performance Testing and Characterization of Light Emitting Transistors:

[0095] In a nitrogen atmosphere in a glove box, voltage was applied to the source electrode, drain electrode, and gate electrode using a probe, the gate electrode was high-concentration doped silicon, the source electrode was grounded, the voltage between the source electrode and the drain electrode was -70 V, and the voltage between the gate electrode and the source electrode was varied from 20 V to 70 V in -2 V steps, and the photocurrent of the device was tested using a 0.5 V level photomultiplier tube in a dark environment and the relationship curve between current, photocurrent, and voltage was tested; the spectrum of the device was tested using a spectrometer and light emission images were collected using a CCD.

[0096] Example 2. CBP: Planar light-emitting transistor device emitting from a planar light source of an Ir(mphmq)2tmd-based red light-emitting unit

[0097] 1) Si / SiO2 Wafer Cleaning and Water-soluble Layer Modification:

[0098] Before use, a silicon wafer having a SiO2 oxide layer was first washed with hydrogen peroxide and concentrated sulfuric acid in a volume ratio of approximately 1:2 (heated in an electric furnace and boiled for 15 minutes), then sequentially sonicated with deionized water, acetone, and isopropyl alcohol for approximately 10 minutes each, and rapidly dried using nitrogen. The surface energy levels were modified in an O2 plasma cleaner for 5 minutes to remove residual organic solvent from the surface. Then, it was dried in a 90°C oven for 90 minutes. Finally, a drop of octadecyltrichlorosilane (OTS) was placed in the middle of a Petri dish containing the silicon wafer using a capillary tube, and the Petri dish was placed in a 120°C oven and heated for 120 minutes, after which it was naturally cooled.

[0099] 2) Fabrication of the organic charge transport layer (i.e., semiconductor charge transport layer) C8-BTBT

[0100] A patterned metal mask was securely fixed to the substrate, and 50 nm of C8-BTBT was thermally evaporated from the Si / SiO2 wafer modified in step 1) using a vacuum coater. Immediately after the evaporation was completed, an annealing treatment was performed at a temperature of 45°C for 20 minutes.

[0101] 3) Preparation of source electrode

[0102] Replace the mask to secure it firmly to the substrate, and use a vacuum coater to apply a 2 nm layer of MoO2 to one side of the organic charge transport layer. x and 40 nm Au was thermally evaporated.

[0103] 4) Manufacture of charge buffer layer and light-emitting unit

[0104] The mask was replaced and securely fixed to the substrate, and a charge buffer layer 40 nm TAPC and a light-emitting unit 20 nm 5% Ir(mphmq)2tmd:CBP / 40 nm Tmpypb were sequentially deposited on the other side of the organic charge transport layer using a vacuum coating machine.

[0105] 5) Preparation of drain electrode

[0106] The mask was replaced and securely fixed to the substrate, and 0.5 nm LiF / 1 nm Al / 35 nm Ag were sequentially deposited as drain electrodes on the light-emitting unit using a vacuum coating machine. After the fabrication of the device was completed, the device structure is shown in Fig. 1.

[0107] 6) Performance Testing and Characterization of Light Emitting Transistors:

[0108] In a nitrogen atmosphere in a glove box, voltage was applied to the source electrode, drain electrode, and gate electrode using a probe, the gate electrode was high-concentration doped silicon, the source electrode was grounded, the voltage between the source electrode and the drain electrode was -70 V, and the voltage between the gate electrode and the source electrode was varied from 20 V to 70 V in -2 V steps, and the photocurrent of the device was tested using a 0.5 V level photomultiplier tube in a dark environment and the relationship curve between current, photocurrent, and voltage was tested; the spectrum of the device was tested using a spectrometer and light emission images were collected using a CCD.

[0109] Example 3. CBP: Planar light-emitting transistor device emitting from a planar light source of a BD-1-based blue light-emitting unit

[0110] 1) Si / SiO2 Wafer Cleaning and Water-soluble Layer Modification:

[0111] Before use, a silicon wafer having a SiO2 oxide layer was first washed with hydrogen peroxide and concentrated sulfuric acid in a volume ratio of approximately 1:2 (heated in an electric furnace and boiled for 15 minutes), then sequentially sonicated with deionized water, acetone, and isopropyl alcohol for approximately 10 minutes each, and rapidly dried using nitrogen. The surface energy levels were modified in an O2 plasma cleaner for 5 minutes to remove residual organic solvent from the surface. Then, it was dried in a 90°C oven for 90 minutes. Finally, a drop of octadecyltrichlorosilane (OTS) was placed in the middle of a Petri dish containing the silicon wafer using a capillary tube, and the Petri dish was placed in a 120°C oven and heated for 120 minutes, after which it was naturally cooled.

[0112] 2) Fabrication of the organic charge transport layer (i.e., semiconductor charge transport layer) C8-BTBT

[0113] A patterned metal mask was securely fixed to the substrate, and 50 nm of C8-BTBT was thermally evaporated from the Si / SiO2 wafer modified in step 1) using a vacuum coater. Immediately after the evaporation was completed, an annealing treatment was performed at a temperature of 45°C for 20 minutes.

[0114] 3) Preparation of source electrode

[0115] Replace the mask to secure it firmly to the substrate, and use a vacuum coater to apply a 2 nm layer of MoO2 to one side of the organic charge transport layer. x and 40 nm Au was thermally evaporated.

[0116] 4) Manufacture of charge buffer layer and light-emitting unit:

[0117] The mask was replaced and securely fixed to the substrate, and a charge buffer layer 40 nm TAPC and a light-emitting unit 20 nm 10% BD-1:CBP / 40 nm B3pypb were sequentially deposited on the other side of the organic charge transport layer using a vacuum coating machine.

[0118] 5) Preparation of drain electrode:

[0119] The mask was replaced and securely fixed to the substrate, and 0.5 nm LiF / 1 nm Al / 35 nm Ag were sequentially deposited as drain electrodes on the light-emitting unit using a vacuum coating machine. After the fabrication of the device was completed, the device structure is shown in Fig. 1.

[0120] 6) Performance Testing and Characterization of Light Emitting Transistors:

[0121] In a nitrogen atmosphere in a glove box, voltage was applied to the source electrode, drain electrode, and gate electrode using a probe, the gate electrode was high-concentration doped silicon, the source electrode was grounded, the voltage between the source electrode and the drain electrode was -70 V, and the voltage between the gate electrode and the source electrode was varied from 20 V to 70 V in -2 V steps, and the photocurrent of the device was tested using a 0.5 V level photomultiplier tube in a dark environment and the relationship curve between current, photocurrent, and voltage was tested; the spectrum of the device was tested using a spectrometer and light emission images were collected using a CCD.

[0122] FIG. 2a is an optical microscope image of the red, green, blue, and primary color planar emission field-effect transistor devices fabricated in Examples 1, 2, and 3, respectively, in a dark field of view, showing planar light source emission. From left to right, the emission colors are sequentially red, green, and blue, all implementing planar light source emission. FIG. 2b shows the typical transfer curve, output curve, and emission spectrum of the green planar emission field-effect transistor device fabricated in Example 1, which indicates the good gate voltage regulation characteristics of the transistor device (on / off ratio 10 6 It shows ) and luminescence performance.

[0123] Example 4. CBP: High aperture ratio planar light-emitting transistor device emitted from a planar light source of an Ir(ppy)3-based green light-emitting unit

[0124] 1) Si / SiO2 Wafer Cleaning and Water-soluble Layer Modification:

[0125] Before use, a silicon wafer having a SiO2 oxide layer was first washed with hydrogen peroxide and concentrated sulfuric acid in a volume ratio of approximately 1:2 (heated in an electric furnace and boiled for 15 minutes), then sequentially sonicated with deionized water, acetone, and isopropyl alcohol for approximately 10 minutes each, and rapidly dried using nitrogen. The surface energy levels were modified in an O2 plasma cleaner for 5 minutes to remove residual organic solvent from the surface. Then, it was dried in a 90°C oven for 90 minutes. Finally, a drop of octadecyltrichlorosilane (OTS) was placed in the middle of a Petri dish containing the silicon wafer using a capillary tube, and the Petri dish was placed in a 120°C oven and heated for 120 minutes, after which it was naturally cooled.

[0126] 2) Preparation of Organic Charge Transport Layer C8-BTBT

[0127] A patterned metal mask was securely fixed to the substrate, and 50 nm of C8-BTBT was thermally evaporated from the Si / SiO2 wafer modified in step 1) using a vacuum coater. Immediately after the evaporation was completed, an annealing treatment was performed at a temperature of 45°C for 20 minutes.

[0128] 3) Preparation of source electrode

[0129] Replace the mask to secure it firmly to the substrate, and use a vacuum coater to apply a 2 nm layer of MoO2 to one side of the organic charge transport layer. x and 40 nm Au was thermally evaporated.

[0130] 4) Manufacture of charge buffer layer and light-emitting unit:

[0131] The mask was replaced and securely fixed to the substrate, and a charge buffer layer 40 nm TAPC and a light-emitting unit 20 nm 10% Ir(ppy)3:CBP / 40 nm 3TPYMB were sequentially deposited on the other side of the organic charge transport layer using a vacuum coating machine.

[0132] 5) Preparation of drain electrode:

[0133] The mask was replaced and securely fixed to the substrate, and 0.5 nm LiF / 1 nm Al / 35 nm Ag was sequentially deposited as a drain electrode on the light-emitting unit using a vacuum coating machine. After the fabrication of the device was completed, the device structure is shown in Fig. 1, and the optical photograph (left) and light emission optical photograph (right) of the obtained device are shown in Fig. 3.

[0134] 6) Performance Testing and Characterization of Light Emitting Transistors:

[0135] In a nitrogen atmosphere in a glove box, voltage was applied to the source electrode, drain electrode, and gate electrode, respectively, using a probe, with the gate electrode being high-concentration doped silicon and the source electrode grounded. The voltage between the source and drain electrodes was -70 V, and the voltage between the gate and source electrodes was varied from 20 V to 70 V in -2 V steps. In a dark environment, the photocurrent of the device was tested using a 0.5 V level photomultiplier tube, and the relationship curve between current, photocurrent, and voltage was tested; the spectrum of the device was tested using a spectrometer, and bright-field and dark-field images of the device were collected using a CCD. The test results are shown in Figure 4, which demonstrates that increasing the light-emitting area increases the aperture ratio (approximately 90%) and enables the realization of excellent planar light source effects and luminous brightness. Planar light-emitting transistors emitted from such a planar light source can enable the construction of high aperture ratio devices.

[0136] Example 5

[0137] Referring to the manufacturing process of the transistor in Example 4, the difference from Example 4 is that in this example, a semiconductor charge transport layer is first deposited on a modified Si / SiO2 wafer, followed by the deposition of a charge buffer layer, and then a source electrode and a light-emitting unit are deposited on the charge buffer layer, wherein the source electrode and the light-emitting unit are each located on one side of the charge buffer layer, and finally, a drain electrode is deposited on the light-emitting unit. The specific structure is shown in Fig. 1b. As a result of testing, the transistor device obtained in this example also possesses good gate voltage control characteristics, light emission performance, a large aperture ratio (the aperture ratio can reach at least 80%), and stability.

[0138] Examples 6~7

[0139] Transistors of Examples 6 and 7 were fabricated by using an ultrathin metal material Au instead of TAPC of Example 4 as the charge buffer layer, or by using C60-pentacene-C60 instead of TAPC of Example 4 as the charge buffer layer. The transistors have the same or similar performance as Example 4; that is, both are planar light-emitting transistors that emit light from a planar light source and have good gate voltage control characteristics, light emission performance, and stability.

[0140] Example 8

[0141] As illustrated in FIG. 5, the device of the present embodiment comprises a source electrode, an organic charge transport layer C8-BTBT, and three light-emitting members, namely, a first light-emitting member, a charge buffer layer TAPC and a blue light-emitting unit BD-1:CBP / TmPTPB; a second light-emitting member, a charge buffer layer TAPC and a green light-emitting unit Ir(ppy)3:CBP / 3TPYMB; a third light-emitting member, a charge buffer layer TAPC and a red light-emitting unit Ir(mphmq)2tmd:CBP / Tmpypb; and a drain electrode LiF / Al / Ag. Each light-emitting member is connected to another by a CGL layer.

[0142] Example 9. DMAC-TRZ: Planar light-emitting field-effect transistor device emitting light from a planar light source of a rubrene-based white light-emitting unit

[0143] 1) Glass / Indium Tin Oxide (ITO) Wafer Cleaning and Dielectric Layer Fabrication:

[0144] Before use, a glass wafer having an ITO layer was sonicated sequentially with deionized water, acetone, and isopropyl alcohol for about 10 minutes each, and rapidly dried using nitrogen. The surface energy level was modified in an O2 plasma cleaner for 5 minutes to remove residual organic solvent from the surface.

[0145] PVA powder (average M w 205,000 g mol -1 ) with deionized water (58 mg mL -1 The solution was dissolved in ) and stirred at 800 rmp for 6 hours. Then, glutaraldehyde (GA, 50 wt%) was added to the solution (1:80 volume ratio). The prepared PVA solution was spin-coated (4200 rmp × 45 s) onto a glass / ITO substrate to obtain a film with a thickness of 350 nm. Then, the film was thermally annealed in air at 100°C for 90 minutes. A perfluororesin CYTOP (CTL-809M, M type) layer (about 10 nm) was spin-coated onto the PVA layer and annealed at 100°C for 30 minutes.

[0146] 2) Preparation of Organic Charge Transport Layer C8-BTBT

[0147] A patterned metal mask was securely fixed to the substrate, and 50 nm of C8-BTBT was thermally evaporated from the glass / ITO / dielectric layer using a vacuum coater.

[0148] 3) Preparation of source electrode

[0149] Replace the mask to secure it to the substrate, and apply a 2 nm MoO layer to glass / ITO / dielectric layer / C8-BTBT using a vacuum coater. xand 40 nm Au was thermally evaporated.

[0150] 4) Manufacture of charge buffer layer and light-emitting unit:

[0151] Replace the mask to secure it firmly to the substrate, and use a vacuum coater to coat the glass / ITO / dielectric layer / C8-BTBT / MoO x A 40 nm TAPC charge buffer layer and a 30 nm 2% Rubrene:DMAC-TRZ / 40 nm 3TPYMB light-emitting unit were deposited on / Au.

[0152] 5) Preparation of drain electrode:

[0153] Replace the mask to secure it firmly to the substrate, and use a vacuum coater to coat the glass / ITO / dielectric layer / C8-BTBT / MoO x 2 nm LiF / 120 nm Al was sequentially deposited as a drain electrode on / Au / TAPC / 2% Rubrene:DMAC-TRZ / 40 nm 3TPYMB. After the fabrication of the device was completed, a schematic diagram of the device structure (left) and an optical photograph (right) are shown in Fig. 6.

[0154] 6) Performance Testing and Characterization of Emitting Field Effect Transistors:

[0155] In a nitrogen atmosphere in a glove box, voltage was applied to the source, drain, and gate electrodes using a probe, with the gate electrode being ITO and the source electrode grounded. The voltage between the source and drain electrodes was -20 V, and the voltage between the gate and source electrodes varied from 0 V to -20 V in -1 V steps. In a dark environment, the photocurrent of the device was tested using a 0.5 V level photomultiplier tube, the relationship curve between current, photocurrent, and voltage was tested, and the relationship between external quantum efficiency (EQE) and luminance was calculated. As shown in Fig. 7, the maximum luminance of the device was 1121 nits, and the maximum EQE reached 6.9%. Emission images of the device were collected using a mobile phone camera. Emission images of the device at gate voltages of -5 V, -6 V, and -20 V are shown in Fig. 8. The uniform white light emission exhibited is of significant importance for the use of light-emitting transistors in the field of lighting.

[0156] The embodiments of the present invention have been described above. However, the present invention is not limited to the aforementioned embodiments. All modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

Claim 1 A planar light source emitting transistor, wherein the planar light source emitting transistor comprises a source electrode, a drain electrode, a charge buffer layer, a semiconductor charge transport layer, and a light-emitting unit; wherein the semiconductor charge transport layer is installed below the source electrode; wherein the light-emitting unit is installed below the drain electrode; wherein the charge buffer layer is installed between the drain electrode and the semiconductor charge transport layer, or between the source electrode and the semiconductor charge transport layer, or between the semiconductor charge transport layer and the light-emitting unit, and wherein the charge buffer layer is a layer formed of one or more of low-mobility organic materials such as 4,4'-cyclohexylbis[N,N-bis(4-methylphenyl)aniline] (TAPC), N,N'-diphenyl-N,N'-(1-naphthyl)-1,1'-biphenyl-4,4'-diamine (NPB), and PVK; or wherein the charge buffer layer is a layer formed of one or more of metallic materials such as Au, Ni, and Pt. Or, the charge buffer layer is a layer formed of one or more of C60-pentacene-C60, C70-tetracene-C70, and C60-tetracene-C70 among the pnp junction, and when the material in the charge buffer layer is a low-mobility organic material or a pnp junction, the thickness of the charge buffer layer is 20 to 80 nm, a planar light source planar light-emitting transistor. Claim 2 In claim 1, the planar light source emitting transistor comprises: a support substrate; a gate electrode installed on the surface of the support substrate; a dielectric layer installed on the gate electrode; a semiconductor charge transport layer installed on the dielectric layer; a source electrode and a charge buffer layer installed on different sides of the charge transport layer on the semiconductor charge transport layer; and a light-emitting unit and a drain electrode installed sequentially on the charge buffer layer; or, the planar light source emitting transistor comprises: a support substrate; a gate electrode installed on the surface of the support substrate; a dielectric layer installed on the gate electrode; a semiconductor charge transport layer installed on the dielectric layer; a charge buffer layer installed on the semiconductor charge transport layer; a source electrode and a light-emitting unit installed sequentially on the charge buffer layer and on different sides of the charge buffer layer; and a drain electrode installed on the light-emitting unit, wherein the source electrode and the drain electrode are arranged in a non-planar manner, the light-emitting portion is the entire effective area of ​​the source electrode or the drain electrode, and the gate voltage is used to control the light-emitting brightness. Claim 3 In claim 1, the mobility of the semiconductor charge transport layer is 0.1 cm 2 V -1 s -1 Not lower than, the semiconductor charge transport layer comprises an organic semiconductor material and / or an inorganic semiconductor material, and the organic semiconductor material comprises 2,7-dioctyl[1]benzothieno[3,2-b]benzothiophene (C8-BTBT), 2,6-diphenylanthracene (DPA), 2,6-dinaphthylanthracene (dNaAnt), 2,6-bis(pn-hexylbenzene)anthracene (C6-DPA), 2,6-bis(p-octylbenzene)anthracene (C8-DPA), and 2,6-bis(p-decylbenzene)anthracene (C 10 A planar light source planar light-emitting transistor, wherein the inorganic semiconductor material is selected from one or more of -DPA, poly(3-hexylthiophene) (P3HT), 9,9-di-n-octylfluorene-benzothiadiazole copolymer (F8BT), and poly[2,5-(2-octyldodecyl)-3,6-diketopyrrolopyrrole-alt-5,5-(2,5-bis(thiophene-2-yl)thieno[3,2-b]thiophene)] (DPP-DTT), and the inorganic semiconductor material is selected from one or more of carbon nanotubes (CNTs), zinc tin oxide (ZTO), gallium nitride (GaN), silicon carbide (SiC), and zinc selenide (ZnSe). Claim 4 In claim 1, the light-emitting unit comprises a light-emitting layer and an electron transport layer, a hole transport layer, an electron injection layer, and / or a hole injection layer that matches the energy level of the light-emitting layer; furthermore, the light-emitting layer is a layer formed of a light-emitting material, wherein the light-emitting material is selected from one or more of materials including a fluorescent material, a phosphorescent material, and a thermally activated delayed fluorescent material, wherein the fluorescent material is selected from one or more of octahydroxyquinoline aluminum (Alq3), 5,6,11,12-tetraphenyltetracene, and 4,4'-bis[4-(diphenylamino)styryl]biphenyl (BDAVBi), and wherein the phosphorescent material is tris(2-phenylpyridine)iridium (Ir(ppy)3), bis(2-phenylpyridine-C2,N)acetylacetonate iridium (Ir(ppy)2(acac)) and A planar light source planar light-emitting transistor, wherein the thermally active delayed fluorescent material is selected from one or more of iridium(III) tris[N,N'-diphenylbenzimidazole-2-ylidene-C2,C2'](Ir(dpbic)3), and the thermally active delayed fluorescent material is selected from one or two of 9,9'-(5-(4,6-diphenyl-1,3,5-triazine-2-yl)-1,3-phenylene)bis(9H-carbazole)(DCzTRZ), (N-phenoxazine)phenyl]thiosulfone (PXZ-DPS), and 10-(4-(4,6-diphenyl-1,3,5-triazol-2-yl)phenyl)-9,9-dimethyl-9,10-dihydroacridine (DMAC-TRZ). Claim 5 In claim 1, the spectrum of light emitted by the light-emitting unit is between 390 nm and 780 nm, and the light-emitting layer of the light-emitting unit is formed of a single light-emitting material or a guest doping host material; the single light-emitting material is Alq3, DPA, or dNaAnt; The guest doping substances within the above guest doping host material are 1,4-bis(10-phenylanthracene-9-yl)benzene (BD-1), BDAVBi, perylene, bis-dimethyl-dihydroacridinephenylthiosulfone (DMAC-DPS), bis[2-(5-cyano-4,6-difluorophenyl)pyridine-C2,N)]pyridinecarboxylidium (FCNirPic), iridium(III)bis[(2,3,4-difluorophenyl)-pyridine-N,C2']picolinate (Ir(tfpd)2pic), bis[2,4-dimethyl-6-(4-methyl-2-quinolyl- N)phenyl- C](2,2,6,6-tetramethyl-3,5-heptanedione- O3(Ir(mphmq)2tmd), 4,4'-bis[4-(di-p-tolylamino)styryl]biphenyl(DPAVBi), 9,9'-(5-(4,6-diphenyl-1,3,5-triazine-2-yl)-1,3-benzene)bis(9H-carbazole)(DCzTrz), 5,5-dibromo-4,4-tetrakis-2,2-bithiophene(fac-Ir(dpbic)3), tris(2-phenylpyridine)iridium(Ir(ppy)3), tris[2-(p-tolyl)pyridine]iridium(III)(Ir(mppy)3), bis(2-phenylpyridine-C2,N)acetylacetonate iridium(III)(Ir(ppy)2(acac)), Bis(2-(napt-2-yl)pyridine)(acetylacetone)iridium(III)(Ir(npy)2acac), tris[2-(3-methyl-2-pyridyl)phenyl]iridium(Ir(3mppy)3), bis(2-(3,5-dimethylphenyl)quinoline-C2,N')(acetylacetone)iridium(III)(Ir(dmpq)2acac), bis(2-(2'-benzothienyl)-pyridine-N,C3')iridium(acetylacetone)(Ir(btp)2(acac)), 4-(dicyanomethylene)-2-methyl-6-[2-(2,3,6,7-tetrahydro-1H,5H-benzo[ij]quinolizine-9-yl)vinyl]-4H-pyran(DCM2), One or more of 5,6,11,12-tetraphenyltetracene, tris(2-(3,5-dimethylphenyl)quinoline-C2,N')iridium(III)(Ir(dmpq)3), 2,8-di-tert-butyl-5,11-bis(4-tert-butylphenyl)-6,12-diphenyltetracene (TBRb), and 10-(4-(4,6-diphenyl-1,3,5-triazole-2-yl)phenyl)-9,9-dimethyl-9,10-dihydroacridine (DMAC-TRZ);The above host material is Alq3, 4,4'-bis(N-carbazole)-1,1'-biphenyl (CBP), 4,4'-bis(2,2-diphenyl-vinyl-1-yl)-4,4'-dimethylphenyl (p-DMDPVBi), 4,4'-bis(2,2-diphenylvinyl)-1,1'-biphenyl (DPVBi), 2-tert-butyl-9,10-bis(2-naphthyl)anthracene (TBADN), diphenyl[4-(triphenylsilyl)phenyl]phosphine oxide (TSPO1), 3-(3-(9H-carbazole-9-yl)phenyl)benzofuran[2,3-b]pyridine (PCz-BFP), 2,4,6-tris[3-(diphenylphosphineoxy)phenyl]-1,3,5-triazole (PO-T2T), A planar light-emitting transistor of a planar light source, one or more of 2,4,6-tris(3-(carbazole-9-yl)phenyl)-1,3,5-triazine (TCPZ), 4,4'-bis(triphenylsilyl)-1,1'-biphenyl (BSB), 2,7-bis[9,9-bis(4-methylphenyl)-fluorene-2-yl]-9,9-bis(4-methylphenyl)fluorene (TDAF), and 3',3'',3''-(1,3,5-triazine-2,4,6-triyl)tris(([1,1'-biphenyl]-3-nitrile))(CN-T2T). Claim 6 A planar light source emitting transistor according to claim 1, wherein the thickness of the semiconductor charge transport layer, charge buffer layer, and light-emitting unit is all at the nanometer to submicron level. Claim 7 In claim 6, the planar light source emitting transistor emits planar light that matches the color of the light-emitting unit under an externally applied voltage; and / or, the planar light source emitting transistor has an upper light-emitting type or lower light-emitting type device structure. Claim 8 A method for manufacturing a planar light source emitting transistor according to claim 2, comprising the step of installing a charge buffer layer between a drain electrode and a semiconductor charge transport layer, between a source electrode and a semiconductor charge transport layer, or between a semiconductor charge transport layer and a light-emitting unit. Claim 9 In claim 8, the structure comprising the semiconductor charge transport layer, the charge buffer layer, and the light-emitting unit is recorded as an active layer, wherein the active layer is obtained by: a method 1 in which a film of a small molecule material is deposited on the dielectric layer and the electrode via a vacuum evaporation deposition method within a deposition chamber; a method 2 in which a solution of the active layer material is spin-coated on the dielectric layer and the electrode via a spin-coating method to obtain an active layer; and a method 3 in which a single-crystal film of the small molecule material is prepared and grown via a solution epitaxy method: a uniformly mixed solution obtained by dissolving the small molecule material in a solvent that does not mix with water is slowly dropped onto a water surface, causing the mixed solution to spread on the water surface and, after the solvent within it evaporates, the single-crystal film is obtained; and a method 3 in which a support substrate having a dielectric layer is inserted into water to transfer the single-crystal film to the surface of the dielectric layer to obtain an active layer. A method for manufacturing a planar light source planar light-emitting transistor, wherein the single crystal film of the small molecule material is prepared through a solution shearing method, wherein the small molecule material is dissolved in an organic solvent, the obtained uniformly mixed solution is dropped onto a supporting substrate having a dielectric layer, and the dropped solution is slowly sheared and stretched to form an active layer, and the method is prepared by any one of the following methods. Claim 10 A wearable device comprising a planar light source emitting transistor according to claim 1. Claim 11 A lighting display comprising a planar light source transistor according to claim 1. Claim 12 A laser comprising a planar light source transistor according to claim 1.

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