Display device and electronic device having the same

Abstract

A display device is provided. An input sensor is disposed on a base insulating layer covering a lower signal line. A reflectance reduction pattern containing a dye or pigment is disposed on at least one inorganic layer of the input sensor. The lower signal line and the upper signal line are connected through at least one contact hole penetrating the corresponding layer among the at least one inorganic layer and the base insulating layer. The upper signal line is covered by the reflectance reduction pattern.

Description

Technology Field

[0001] The present invention relates to a display device and an electronic device including the same, and more specifically, to a display device including an input sensor and an anti-reflective layer and an electronic device including the same. Background Technology

[0002] Various display devices used in multimedia devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles are being developed. Input devices for these display devices include keyboards or mice. Additionally, display devices are equipped with input sensors. The problem to be solved

[0003] The objective of the present invention is to provide a display device with a reduced defect rate.

[0004] Another objective of the present invention is to provide an electronic device including a display device. means of solving the problem

[0005] A display device according to one embodiment of the present invention comprises a base layer including a display area and a non-display area adjacent to the display area; a lower signal line disposed in the non-display area; a base insulating layer covering the lower signal line and overlapping the display area and the non-display area; a light-emitting element disposed on the base insulating layer and overlapping the display area; a thin film encapsulation layer disposed on the base insulating layer and sealing the light-emitting element; at least one inorganic layer disposed on the thin film encapsulation layer and overlapping the display area and the non-display area; a sensing electrode disposed on the at least one inorganic layer and overlapping the display area; an upper signal line overlapping the non-display area and connecting the lower signal line and the sensing electrode; a reflectance reduction pattern disposed on the at least one inorganic layer and comprising a dye or pigment; and an overcoat layer disposed on the at least one inorganic layer and overlapping the reflectance reduction pattern. The lower signal line and the upper signal line are connected through at least one contact hole penetrating the corresponding layer among the at least one inorganic layer and the base insulating layer. The upper signal line is covered by the reflectance reduction pattern.

[0006] The base insulating layer comprises an organic layer, and the base insulating layer can cover the side of the pad portion of the lower signal line. An opening that exposes the upper surface of the pad portion of the lower signal line may be defined in the base insulating layer.

[0007] The thin film encapsulation layer, the at least one inorganic layer, and the overcoat layer may be non-overlapping on the pad portion.

[0008] The overcoat layer covers the reflectance reduction pattern, and the end of the overcoat layer may be closer to the pad portion of the lower signal line than the end of the reflectance reduction pattern.

[0009] The upper signal line may include a first conductive layer, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer.

[0010] The above reflectance reduction pattern can cover the sides of the first conductive layer, the second conductive layer, and the third conductive layer.

[0011] The above at least one contact hole may include a first contact hole penetrating the base insulating layer and a second contact hole penetrating the at least one inorganic layer.

[0012] The above at least one inorganic layer is disposed inside the first contact hole, and the second contact hole may be located inside the first contact hole.

[0013] The above at least one inorganic layer may include a first inorganic layer and a second inorganic layer disposed on the first inorganic layer. The sensing electrode may include a first sensing electrode and a second sensing electrode that are insulated and intersecting each other. The first sensing electrode has a single shape, and the second sensing electrode may include a sensing pattern disposed on the same layer as the first sensing electrode and a bridge pattern disposed on a different layer from the sensing pattern. The bridge pattern may be disposed between the first inorganic layer and the second inorganic layer and may be connected to the sensing pattern through a contact hole penetrating the second inorganic layer.

[0014] The above reflectance reduction pattern may include a black mattress containing a black pigment or a black dye. The above may each contact the upper signal line and the upper surface of the at least one inorganic layer.

[0015] The above reflectance reduction pattern is disposed on the at least one inorganic layer and further includes a color filter superimposed on the light-emitting element, and the color filter may be disposed on the black mattress.

[0016] A display device according to one embodiment of the present invention may further include a first color filter, a second color filter, and a third color filter having different colors, disposed on the at least one inorganic layer. The light-emitting element may include a first color light-emitting element disposed below the first color filter, a second color light-emitting element disposed below the second color filter, and a third color light-emitting element disposed below the third color filter. The reflectance reduction pattern may include the same material as any one of the first color filter, the second color filter, and the third color filter.

[0017] Any one of the first color filter, the second color filter, and the third color filter may come into contact with the sensing electrode. The reflectance reduction pattern may include the same material as the color filter in contact with the sensing electrode.

[0018] The above reflectance reduction pattern is superimposed on the sensing electrode, and the upper signal line may have the same stacked structure as the sensing electrode.

[0019] An electronic device according to one embodiment of the present invention includes a display device comprising a display area and a non-display area adjacent to the display area, and a circuit board electrically connected to the display device. The display device comprises a lower signal line disposed in the non-display area, a base insulating layer covering the lower signal line and overlapping the display area and the non-display area, a light-emitting element disposed on the base insulating layer and overlapping the display area, a thin film encapsulation layer disposed on the base insulating layer and sealing the light-emitting element, at least one inorganic layer disposed on the thin film encapsulation layer and overlapping the display area and the non-display area, a sensing electrode disposed on the at least one inorganic layer and overlapping the display area, an upper signal line overlapping the non-display area and connecting the lower signal line and the sensing electrode, a reflectance reduction pattern disposed on the at least one inorganic layer and comprising a dye or pigment, and an overcoat layer disposed on the at least one inorganic layer and overlapping the reflectance reduction pattern. The lower signal line and the upper signal line are connected through at least one contact hole penetrating the corresponding layer among the at least one inorganic layer and the base insulating layer, and the upper signal line is covered by the reflectance reduction pattern.

[0020] An electronic device according to one embodiment of the present invention further comprises an anisotropic conductive adhesive layer, and the circuit board comprises a substrate signal line, and the substrate signal line and the lower signal line can be electrically connected through the anisotropic conductive adhesive layer. The base insulating layer comprises an organic layer, and the base insulating layer has an opening defined therein that exposes the upper surface of the pad portion of the lower signal line, and the base insulating layer and the pad portion of the lower signal line can come into contact with the anisotropic conductive adhesive layer.

[0021] The electronic device may not include a polarizing film disposed on the inside or outside of the display device.

[0022] The upper signal line comprises a first conductive layer, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer, and the reflectance reduction pattern can cover the sides of the first conductive layer, the second conductive layer, and the third conductive layer.

[0023] The above at least one contact hole may include a first contact hole penetrating the base insulating layer and a second contact hole penetrating the at least one inorganic layer. The at least one inorganic layer may be disposed inside the first contact hole, and the second contact hole may be located inside the first contact hole.

[0024] The above reflectance reduction pattern may include a black mattress comprising a black pigment or a black dye. The black mattress may contact the upper signal line and the upper surface of the at least one inorganic layer, respectively. Effects of the invention

[0025] As described above, defects in the signal lines of the input sensor can be prevented. Short circuit defects between adjacent signal lines can be reduced. Brief explanation of the drawing

[0026] FIG. 1 is a block diagram of an electronic device according to one embodiment of the present invention. FIG. 2 is a schematic diagram of electronic devices according to one embodiment of the present invention. FIGS. 3a and FIGS. 3b are perspective views of a display device according to an embodiment of the present invention. FIG. 4 is a cross-sectional view of a display device according to one embodiment of the present invention. FIG. 5 is a plan view of a display panel according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a display device according to one embodiment of the present invention. FIG. 7a is a plan view of an input sensor according to one embodiment of the present invention. FIG. 7b is a first plan view of the input sensor shown in FIG. 7a. FIG. 7c is a second plan view of the input sensor shown in FIG. 7a. FIG. 8a is a cross-sectional view of a display device corresponding to I-I' of FIG. 7a. Figure 8b is an enlarged cross-sectional view of a portion of Figure 8a. FIG. 8c is a cross-sectional view of a display device corresponding to II-II' of FIG. 7a. FIG. 8d is a cross-sectional view of a display device corresponding to III-III' of FIG. 7a. FIG. 9a is a cross-sectional view of a display device according to one embodiment of the present invention. FIG. 9b is a cross-sectional view of a display device according to one embodiment of the present invention. Specific details for implementing the invention

[0027] In this specification, where a component (or region, layer, part, etc.) is described as being “on,” “connected,” or “joined” another component, it means that it may be directly placed / connected / joined on the other component, or that a third component may be placed between them.

[0028] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. “And / or” includes all one or more combinations that the associated components may define.

[0029] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component, part, region, layer, or part from another component, part, region, layer, or part. For example, without departing from the scope of the present invention, a first component, a first part, a first region, a first layer, or a first part may be named a second component, a second part, a second region, a second layer, or a second part, and similarly, a second component, a second part, a second region, a second layer, or a second part may be named a first component, a first part, a first region, a first layer, or a first part. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0030] Additionally, terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0031] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0033] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0035] FIG. 1 is a block diagram of an electronic device (ED) according to one embodiment of the present invention. FIG. 2 is a schematic diagram of electronic devices (ED) according to one embodiment of the present invention.

[0036] Referring to FIG. 1, an electronic device (ED) according to one embodiment may include a display device (11), a processor (12), a memory (13), and a power module (14).

[0037] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0038] The memory (15) may store data information necessary for the operation of the processor (12) or the display device (11). When the processor (12) executes an application stored in the memory (15), a video data signal and / or an input control signal is transmitted to the display device (11), and the display device (11) can process the received signal and output video information through a display screen.

[0039] The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power required for the operation of the electronic device (ED).

[0040] The above-described processor (12), power module (14), and memory (15) may be included within the display device (11) or may be distinguished from the display device (11) as separate modules. The processor (12), power module (14), and memory (15) may be located inside the housing that constitutes the exterior of the electronic device (ED) in a form distinct from the display device (11).

[0041] Referring to FIG. 2, an electronic device (ED) according to one embodiment of the present invention may include not only typical electronic devices for providing information such as a smartphone (10_1a), a tablet PC (10_1b), a laptop (10_1c), a TV (10_1d), a desk monitor (10_1e), etc., but also wearable electronic devices such as smart glasses (10_2a), a head-mounted display device (10_2b), a smart watch (10_2c), etc., and automotive electronic devices (10_3) such as a CID (Center Information Display) and a room mirror display placed on the instrument panel, center fascia, or dashboard of a car.

[0043] FIGS. 3a and 3b are perspective views of a display device (DD) according to an embodiment of the present invention. The display device (DD) described below may be the display device (11) described with reference to FIGS. 1 and FIG. 2.

[0044] As illustrated in FIG. 2a and FIG. 1b, the display surface (SS) on which the image is displayed is parallel to the plane defined by the first direction axis (DR1) and the second direction axis (DR2). The normal direction of the display surface (SS), i.e., the thickness direction of the display device (DD), is indicated by the third direction axis (DR3). The front (or top) and back (or bottom) surfaces of each member are distinguished by the third direction axis (DR3). Hereinafter, the first to third directions refer to the same reference numerals in the directions indicated by the first to third direction axes (DR1, DR2, DR3), respectively.

[0045] As illustrated in FIGS. 3a and 3b, a display device (DD) includes a display area (DA) where an image is displayed and a non-display area (NDA) adjacent to the display area (DA). Pixels (PX) are arranged in the display area (DA). The pixels (PX) may be divided into multiple groups according to the color of the light they generate or emit.

[0046] The non-display area (NDA) is an area where an image is not displayed. The non-display area (NDA) may surround the display area (DA). However, it is not limited to this, and the shape of the display area (DA) and the shape of the non-display area (NDA) may be changed. For example, the non-display area (NDA) may be placed adjacent to only a part of the display area (DA).

[0047] According to the present embodiment, a display device (DD) may have a portion of its area bent. The display device (DD) includes a first non-bending area (NBA1, or a first area), a second non-bending area (NBA2, or a third area) spaced apart from the first non-bending area (NBA1) in a first direction (DR1), and a bending area (BA, or a second area) defined between the first non-bending area (NBA1) and the second non-bending area (NBA2). The first non-bending area (NBA1) may include a portion of the display area (DA) and the non-display area (NDA). Both the second non-bending area (NBA2) and the bending area (BA) correspond to the non-display area (NDA), and the second non-bending area (NBA2) and the bending area (BA) may correspond to different portions of the non-display area (NDA).

[0048] The bending area (BA) can be bent along the bending axis (BX). The bending axis (BX) can be parallel to the second direction (DR2). As the bending area (BA) is bent, the second non-bending area (NBA2) can face the first non-bending area (NBA1). The bending area (BA) and the second non-bending area (NBA2) can have a width in the second direction (DR2) that is smaller than that of the first non-bending area (NBA1).

[0049] The distinction between the above-described display area (DA), non-display area (NDA), first non-bending area (NBA1), second non-bending area (NBA2), and bending area (BA) can be equally applied to the display panel (DP), input sensor (ISL), and anti-reflective layer (ARL), which are components of the display device (DD).

[0051] FIG. 4 is a cross-sectional view of a display device (DD) according to an embodiment of the present invention. FIG. 2 illustrates a cross-section defined by a second directional axis (DR2) and a third directional axis (DR3).

[0052] As illustrated in FIG. 4, the display device (DD) includes a display panel (DP), an input sensor (ISL), and an anti-reflection layer (ARL). Although not separately illustrated, the display device (DD) according to one embodiment of the present invention may further include a protective member disposed on the lower surface of the display panel (DP), an anti-reflection member disposed on the upper surface of the input sensor (ISL), and / or a window member.

[0053] The display panel (DP) may be a light-emitting display panel, but is not particularly limited. For example, the display panel (DP) may be an organic light-emitting display panel or an inorganic light-emitting display panel. An organic light-emitting display panel has a light-emitting layer comprising an organic light-emitting material. An inorganic light-emitting display panel has a light-emitting layer comprising quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel.

[0054] A display panel (DP) comprises a base layer (BL), a circuit element layer (DP-CL) disposed on the base layer (BL), a display element layer (DP-EL), and a thin film encapsulation layer (TFE). An input sensor (ISL) may be disposed directly on the thin film encapsulation layer (TFE). An anti-reflective layer (ARL) may be disposed directly on the input sensor (ISL). FIG. 4 is a cross-sectional view of a display device (DD) according to an embodiment of the present invention. In this specification, "configuration A is disposed directly on configuration B" means that an adhesive layer is not disposed between configuration A and configuration B.

[0055] The base layer (BL) may include a synthetic resin substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate. The display area (DA), non-display area (NDA), first non-bending area (NBA1), second non-bending area (NBA2), and bending area (BA) described with reference to FIGS. 3a and 3b may be defined identically in the base layer (BL).

[0056] The circuit element layer (DP-CL) includes at least one insulating layer and a circuit element. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit element may include signal lines and pixel circuits. The circuit element layer (DP-CL) can be formed through a process of forming an insulating layer, a semiconductor layer, and a conductive layer by coating, deposition, etc., and a patterning process of an insulating layer, a semiconductor layer, and a conductive layer by photolithography.

[0057] The display element layer (DP-EL) includes a display element. The display element layer (DP-EL) may further include an organic layer, such as a pixel definition film. The thin film encapsulation layer (TFE) includes a plurality of thin films and seals the display element.

[0058] The input sensor (ISL) acquires coordinate information of an external input. The input sensor (ISL) may have a multilayer structure. The input sensor (ISL) may include a single layer or a multilayer conductive layer. The input sensor (ISL) may include a single layer or a multilayer insulating layer. The input sensor (ISL) may detect an external input, for example, by a capacitive method. In the present invention, the operation method of the input sensor (ISL) is not particularly limited, and in one embodiment of the present invention, the input sensor (ISL) may detect an external input by an electromagnetic induction method or a pressure sensing method.

[0059] The anti-reflective layer (ARL) reduces external light reflectivity. The anti-reflective layer (ARL) can absorb light incident from the outside. The anti-reflective layer (ARL) may include an organic layer containing dyes or pigments.

[0061] FIG. 5 is a plan view of a display panel (DP) according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a display device (DD) according to one embodiment of the present invention.

[0062] As illustrated in FIG. 5, the display panel (DP) may include a driving circuit (GDC), a plurality of signal lines (SGL), and a plurality of pixels (PX). The plurality of pixels (PX) are placed in a display area (DA).

[0063] The driving circuit (GDC) may include a scanning driving circuit. The scanning driving circuit (GDC) generates a plurality of scanning signals and sequentially outputs the plurality of scanning signals to a plurality of scanning lines (GL) described below. The scanning driving circuit (GDC) may further output another control signal to the driving circuit of the pixels (PX).

[0064] The scanning driving circuit (GDC) may include a plurality of thin-film transistors formed through the same process as the driving circuit of the pixels (PX), such as the LTPS (Low Temperature Polycrystalline Silicon) process or the LTPO (Low Temperature Polycrystalline Oxide) process.

[0065] A plurality of signal lines (SGL) include scan lines (GL), data lines (DL), power lines (PL), and control signal lines (CSL). Each of the scan lines (GL) is connected to a corresponding pixel (PX) among a plurality of pixels (PX), and each of the data lines (DL) is connected to a corresponding pixel (PX) among a plurality of pixels (PX). The power line (PL) is connected to a plurality of pixels (PX). The control signal line (CSL) can provide control signals to the scan driving circuit (GDC).

[0066] Signal lines (SGL) include line portions (SGL-L) and pad portions (SGL-P) located at the ends of the line portions (SGL-L). The line portions (SGL-L) may be placed on the same layer and have a single shape. One of the line portions (SGL-L) and the other may be placed on different insulating layers, and each may have a single shape. The line portions (SGL-L) may include multiple portions placed on different layers. For example, one line portion (SGL-L) may include three portions placed on different layers. Two of the three portions that are connected to each other may be placed on different layers and connected through a contact hole penetrating the insulating layer placed between them.

[0067] The pad portions (SGL-P) can be electrically connected to the signal lines (F-SL) of the circuit board (FPCB), respectively. The pad portions (SGL-P) and the signal lines (F-SL) can be electrically connected to each other through an anisotropic conductive adhesive layer.

[0068] The display panel (DP) may include an insulating pattern (DMP). The insulating pattern (DMP) is placed in a non-display area (NDA) and surrounds a display area (DA). The insulating pattern (DMP) may have a closed-line shape. The insulating pattern (DMP) acts as a dam to prevent liquid organic material from overflowing during the inkjet process of the display panel (DP).

[0069] FIG. 6 illustrates a cross-section corresponding to the pixel (PX) of FIG. 5. FIG. 6 is illustrated with the light-emitting element (LD) as the center of the display element. In addition, FIG. 6 exemplarily illustrates the transistor (TFT) and signal line (SCL) of the pixel circuit placed in the circuit element layer (DP-CL).

[0070] A buffer layer (BFL) may be disposed on a base layer (BL). The buffer layer (BFL) may include a plurality of inorganic layers. A semiconductor pattern (SC) is disposed on the buffer layer (BFL). The buffer layer (BFL) enhances the bonding strength between the base layer (BL) and the semiconductor pattern (SC).

[0071] The semiconductor pattern (SC) may include polysilicon. However, it is not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide. FIG. 6 illustrates only some of the semiconductor patterns (SC), and the semiconductor patterns (SC) may be arranged according to specific rules for each pixel.

[0072] The semiconductor pattern (SC) has different electrical properties depending on whether it is doped. The semiconductor pattern (SC) may include a first region (AC1) with low doping concentration and conductivity and a second region (SE1, DE1) with relatively high doping concentration and conductivity. One second region (SE1) may be placed on one side of the first region (AE1), and another second region (DE1) may be placed on the other side of the first region (AE1). The second regions (SE1, DE1) may be doped with an N-type dopant or a P-type dopant. A P-type transistor includes a doped region doped with a P-type dopant. The first region (AE1) may be a non-doped region or may be doped at a lower concentration compared to the second regions (SE1, DE1).

[0073] The second region (SE1, DE1) substantially functions as an electrode or a signal line. One second region (SE1) may correspond to the source of the transistor, and one second region (DE1) may correspond to the drain. FIG. 6 illustrates a signal line (SCL) formed from a semiconductor pattern (SC). The signal line (SCL) may be a semiconductor pattern with high doping concentration and conductivity, and may contain the same material as the aforementioned second region (SE1, DE1). The signal line (SCL) can connect different circuit elements. The signal line (SCL) may be connected to a transistor (TFT) on a plane.

[0074] A first insulating layer (10) is disposed on a buffer layer (BFL). The first insulating layer (10) completely overlaps at least the display area (DA, see FIG. 3a) and covers the semiconductor pattern (SC). The first insulating layer (10) may also be disposed in the non-display area (NDA, see FIG. 3a). The first insulating layer (10) may be an inorganic layer and may have a single layer or a multilayer structure. The first insulating layer (10) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. As well as the first insulating layer (10), the second insulating layer (20) to the fourth insulating layer (40) described later may be inorganic layers, but are not limited thereto, and at least one of the first insulating layer (10) to the fourth insulating layer (40) may be changed to an organic layer.

[0075] A gate (GT1) is disposed on the first insulating layer (10). The gate (GT1) may include a multilayer metal layer. The gate (GT1) overlaps the first region (AC1). In the process of doping the semiconductor pattern (SC), the gate (GT1) acts as a mask that blocks the dopant.

[0076] A second insulating layer (20) covering a gate (GT1) is disposed on a first insulating layer (10). The second insulating layer (20) overlaps at least the display area (DA, see FIG. 3a) and may also be disposed in a non-display area (NDA, see FIG. 3a). An upper electrode (UE) may be disposed on the second insulating layer (20). The upper electrode (UE) may overlap with the gate (GT1). The upper electrode (UE) may include a multilayer metal layer. In one embodiment of the present invention, the upper electrode (UE) may be omitted.

[0077] A third insulating layer (30) covering an upper electrode (UE) is disposed on the second insulating layer (20). A first connecting electrode (CNE1) may be disposed on the third insulating layer (30). The first connecting electrode (CNE1) may be connected to a signal line (SCL) through a contact hole (CNT-1) penetrating the first to third insulating layers (10 to 30).

[0078] A fourth insulating layer (40) is disposed on the third insulating layer (30). A fifth insulating layer (50) is disposed on the fourth insulating layer (40). The fifth insulating layer (50) may be an organic layer that provides a flat surface. A second connecting electrode (CNE2) may be disposed on the fifth insulating layer (50). The second connecting electrode (CNE2) may be connected to the first connecting electrode (CNE1) through a contact hole (CNT-2) that penetrates the fourth insulating layer (40) and the fifth insulating layer (50).

[0079] A sixth insulating layer (60) covering a second connecting electrode (CNE2) is disposed on the fifth insulating layer (50). The sixth insulating layer (60) may be an organic layer. An organic light-emitting diode, which is a light-emitting element (LD), is disposed on the sixth insulating layer (60).

[0080] A first electrode (AE, or anode) is disposed on the sixth insulating layer (60). The first electrode (AE) is connected to a second connecting electrode (CNE2) through a contact hole (CNT-3) penetrating the sixth insulating layer (60). An opening (PDL-OP) is defined in the pixel defining film (PDL). The opening (PDL-OP) of the pixel defining film (PDL) exposes at least a portion of the first electrode (AE). The pixel defining film (PDL) may be an organic layer.

[0081] As illustrated in FIG. 6, the display area (DA) may include a light-emitting area (LA) and a non-light-emitting area (NLA) adjacent to the light-emitting area (LA). The non-light-emitting area (NLA) may surround the light-emitting area (LA). In this embodiment, the light-emitting area (LA) is defined to correspond to a portion of the first electrode (AE) exposed by the opening (PDL-OP).

[0082] A hole control layer (HCL) can be placed in common in the light-emitting region (LA) and the non-light-emitting region (NLA). The hole control layer (HCL) includes a hole transport layer and may further include a hole injection layer. A light-emitting layer (EML) is placed on the hole control layer (HCL). The light-emitting layer (EML) is placed at least inside the aperture (PDL-OP). The light-emitting layer (EML) may also partially overlap with the pixel definition film (PDL). The light-emitting layer (EML) may be placed separately for each pixel (PX, see FIG. 3a).

[0083] An electronic control layer (ECL) is disposed on an emitting layer (EML). The electronic control layer (ECL) includes an electron transport layer and may further include an electron injection layer. The hole control layer (HCL) and the electronic control layer (ECL) can be formed commonly across a plurality of pixels (PX, see FIG. 3a) using an open mask. A second electrode (CE, or cathode) is disposed on the electronic control layer (ECL). The second electrode (CE) has a single shape and is disposed commonly across a plurality of pixels (PX, see FIG. 3a). As shown in FIG. 6, a thin film encapsulation layer (TFE) is disposed on the second electrode (CE).

[0084] The thin film encapsulation layer (TFE) may include a first inorganic layer (IOL1), an organic layer (OL), and a second inorganic layer (IOL2). The first inorganic layer (IOL1) and the second inorganic layer (IOL2) protect the display element layer (DP-EL) from moisture / oxygen, and the organic layer (OL) separates the first inorganic layer (IOL1) and the second inorganic layer (IOL2) to separate the pinholes formed in the first inorganic layer (IOL1) from the pinholes formed in the second inorganic layer (IOL2). Thus, the movement of moisture / oxygen through the pinholes can be reduced.

[0085] As illustrated in FIG. 6, the input sensor (ISL) may include at least one inorganic layer and at least one conductive layer disposed on a thin film encapsulation layer (TFE). It may overlap at least one display area (DA) and non-display area (NDA) of FIG. 3a.

[0086] According to the present embodiment, the input sensor (ISL) may include a first sensor insulating layer (210, hereinafter the first insulating layer), a first sensor conductive layer (220, hereinafter the second conductive layer), a second sensor insulating layer (230, hereinafter the second insulating layer), and a second sensor conductive layer (240, hereinafter the second conductive layer). The first insulating layer (210) may be placed directly on a thin film encapsulation layer (TFE). A first conductive layer (220) is placed on the first insulating layer (210). A second insulating layer (230) covering the first conductive layer (220) is placed on the first insulating layer (210). A second conductive layer (240) is placed on the second insulating layer (230).

[0087] Each of the first conductive layer (220) and the second conductive layer (240) may include a plurality of conductive patterns. The conductive pattern of the second conductive layer (240) may be connected to the conductive pattern of the second conductive layer (240) through a contact hole (230-CNT) penetrating the second insulating layer (230).

[0088] Each of the first conductive layer (220) and the second conductive layer (240) may have a single-layer structure or a multilayer structure stacked along the third directional axis (DR3). The conductive pattern of the multilayer structure may include at least two of transparent conductive layers and metal layers. The conductive pattern of the multilayer structure may include metal layers containing different metals. In this embodiment, each of the first conductive layer (220) and the second conductive layer (240) may include a titanium layer, an aluminum layer, and a titanium layer stacked continuously.

[0089] Each of the first insulating layer (210) and the second insulating layer (230) overlaps the entire display area (DA, see FIG. 3a) and may also be placed in the non-display area (NDA, see FIG. 3a). Each of the first insulating layer (210) and the second insulating layer (230) may be an inorganic layer and may include, for example, silicon nitride, silicon oxide, or silicon oxynitride. In one embodiment of the present invention, the first insulating layer (210) may be omitted. In one embodiment of the present invention, one of the first insulating layer (210) and the second insulating layer (230) may be omitted.

[0090] The anti-reflection layer (ARL) placed on the input sensor (ISL) includes a reflectance reduction pattern. The reflectance reduction pattern absorbs light incident from the outside. Accordingly, it prevents or reduces the supply of light from the outside to the conductive patterns placed underneath.

[0091] The reflectance reduction pattern includes a material capable of absorbing light, such as a dye or a pigment. The reflectance reduction pattern may have different colors depending on the color of the dye or pigment. The reflectance reduction pattern according to the present embodiment can replace a polarizing film. Typically, a polarizing film comprises a polyvinyl alcohol film and an iodine and / or dichroic dye disposed on one side thereof. The iodine and / or dichroic dye is arranged in the stretching direction of the stretched polyvinyl alcohol film. A polarizing film increases the thickness of the display device and increases the manufacturing cost of the display device. The display device according to the present embodiment does not include a polarizing film, and the electronic device according to the present embodiment may not include a polarizing film disposed on the inside or outside of the display device.

[0092] The reflectance reduction pattern may include a black mattress (310). The black mattress (310) may include a black dye or a black pigment. However, it is not limited thereto, and the black mattress (310) may include a metal such as chrome or an oxide thereof or carbon black.

[0093] The black mattress (310) can cover the conductive pattern of the second conductive layer (240). The black mattress (310) can cover the side and top surfaces of the conductive pattern. The black mattress (310) can come into contact with the second insulating layer (230). An opening (310-OP) corresponding to a light-emitting region (LA) can be defined in the black mattress (310). The opening (310-OP) has a larger area than the light-emitting region (LA), and the light-emitting region (LA) can be positioned inside the opening (310-OP) on a plane.

[0094] The reflectance reduction pattern may include a color filter (CF). The color filter (CF) may include a dye or pigment having a predetermined color. The color filter (CF) may include a first color filter, a second color filter, and a third color filter. The first color may be red, the second color may be green, and the third color may be blue.

[0095] The color of the color filter (CF) can be determined by light generated from the light-emitting element (LD). When the light-emitting element (LD) generates a first color light, the color filter (CF) may have a first color to allow the first color light to pass through. Referring to FIG. 5, pixels include a first pixel including a first color light-emitting element, a second pixel including a second color light-emitting element, and a third pixel including a third color light-emitting element. The color filter (CF) may include a first color filter placed on the first color light-emitting element, a second color filter placed on the second color light-emitting element, and a third color filter placed on the third color light-emitting element.

[0096] The anti-reflective layer (ARL) includes an overcoat layer (330) that covers the color filter (CF). The overcoat layer (330) provides a flat upper surface. The overcoat layer (330) may include an organic layer.

[0098] FIG. 7a is a plan view of an input sensor (ISL) according to one embodiment of the present invention. FIG. 7b is a first plan view of an input sensor (ISL) according to one embodiment of the present invention. FIG. 7c is a second plan view of an input sensor (ISL) according to one embodiment of the present invention.

[0099] As illustrated in FIG. 7a, the input sensor (ISL) overlaps the display area (DA) and the non-display area (NDA). The input sensor (ISL) overlaps the display area (DA) and includes first sensing electrodes (E1-1 to E1-5) and second sensing electrodes (E2-1 to E2-4) that are insulated and intersecting with each other.

[0100] Each of the first sensing electrodes (E1-1 to E1-5) and the second sensing electrodes (E2-1 to E2-4) may have a mesh shape with a plurality of defined openings. The plurality of openings are defined to correspond to the light-emitting area (LA, see FIG. 6) of the display panel (DP). The second sensing electrodes (E2-1 to E2-4) intersect insulatingly with the first sensing electrodes (E1-1 to E1-5). Either of the first sensing electrodes (E1-1 to E1-5) or the second sensing electrodes (E2-1 to E2-4) may have a single shape. In this embodiment, the first sensing electrodes (E1-1 to E1-5) having a single shape are exemplified. The first sensing electrodes (E1-1 to E1-5) may include sensing portions (SP1) and intermediate portions (CP1).

[0101] Each of the second sensing electrodes (E2-1 to E2-4) may include sensing patterns (SP2) and bridge patterns (CP2, or connection patterns). Two adjacent sensing patterns (SP2) may be connected by two bridge patterns (CP2), but the number of bridge patterns is not limited. The bridge patterns (CP2) may be included in the first conductive layer (220) shown in FIG. 6, and a plurality of first sensing electrodes (E1-1 to E1-5) and sensing patterns (SP2) may be included in the second conductive layer (240).

[0102] The input sensor (ISL) overlaps the non-display area (NDA) and includes first signal lines (SL1) connected to first sensing electrodes (E1-1 to E1-5) and second signal lines (SL2) electrically connected to second sensing electrodes (E2-1 to E2-4). Either of the first signal lines (SL1) or the second signal lines (SL2) transmits a transmission signal to the corresponding electrodes to detect an external input from an external circuit, and the other transmits a change in capacitance between the first sensing electrodes (E1-1 to E1-5) and the second sensing electrodes (E2-1 to E2-4) to the external circuit as a reception signal.

[0103] Each of the first signal lines (SL1) and the second signal lines (SL2) may include a plurality of distinct portions. Each of the first signal lines (SL1) and the second signal lines (SL2) may include an upper signal line (SL-1) and a lower signal line (SL-2) disposed on different layers. The upper signal line (SL-1) and the lower signal line (SL-2) may be connected through a contact hole (CNT) penetrating an insulating layer disposed between them. Unless otherwise specified, if configuration A and configuration B are disposed on the same layer, they are described as being formed by the same process and having the same stacked structure. Furthermore, unless otherwise specified, if configuration A and configuration B are disposed on different layers, they are described as being formed by different processes and having different stacked structures.

[0104] The lower signal line (SL-2) illustrated in FIGS. 7a and 7b may include a line portion (SL-L) and a pad portion (SL-P). The pad portions (SL-P) of the lower signal line (SL-2) may be electrically connected to the signal lines (F-SL) of the circuit board (FPCB), respectively. The lower signal line (SL-2) may be placed on the same layer as the signal lines (SGL) described with reference to FIG. 5. Although each of the signal lines (SGL) is depicted as a single line in FIG. 5, this does not limit the shape of the signal lines (SGL). For example, the signal lines (SGL) may also include multiple portions placed on different layers. Accordingly, the lower signal line (SL-2) may be placed on the same layer as the portion placed in the second non-bending region (NBA2) of the signal lines (SGL) in FIG. 5.

[0105] The lower signal line (SL-2) may be placed on the same layer as any one of the conductive layers shown in 6. For example, the lower signal line (SL-2) may be placed on the same layer as any one of the gate (GT1), the upper electrode (UE), the first connecting electrode (CNE1), and the second connecting electrode (CNE2).

[0106] The upper signal line (SL-1) shown in FIGS. 7a and 7c may have an integral shape. The upper signal line (SL-1) may be placed on the same layer as the first sensing electrodes (E1-1 to E1-5) and the second sensing electrodes (E2-1 to E2-4). The upper signal line (SL-1) may be placed on the same layer as the first conductive layer (220) shown in FIG. 6, or on the same layer as the second conductive layer (240) shown in FIG. 6.

[0108] FIG. 8a is a cross-sectional view of a display device (DD) corresponding to I-I' in FIG. 7a. FIG. 8b is an enlarged cross-sectional view of a part of FIG. 8a. FIG. 8c is a cross-sectional view of a display device (DD) corresponding to II-II' in FIG. 7a. FIG. 8d is a cross-sectional view of a display device (DD) corresponding to III-III' in FIG. 7a. In FIG. 8c, the configuration of the lower side of the first insulating layer (210) is not shown.

[0109] The stacked structure of the circuit element layer (DP-CL), the display element layer (DP-EL), and the thin film encapsulation layer (TFE) placed in the display area (DA) is the same as the configuration described with reference to FIG. 6, and a detailed description is provided by referring to FIG. 6.

[0110] As illustrated in FIG. 8a, a power electrode (PWE) providing a power voltage (ELVSS) may be placed in the non-marking area (NDA) of the first non-bending area (NBA1). The power electrode (PWE) may be placed on the fifth insulating layer (50) and may be formed by the same process as the second connecting electrode (CNE2). A power connecting electrode (PWE-C) is placed on the sixth insulating layer (60). The power connecting electrode (PWE-C) connects the power electrode (PWE) and the second electrode (CE). The power connecting electrode (PWE-C) may be formed by the same process as the first electrode (AE).

[0111] The insulation pattern (DMP) can overlap with the power electrode (PWE). The insulation pattern (DMP) can be formed through the same process as the pixel definition film (PDL). An organic layer (OL) of the thin film encapsulation layer (TFE) is placed inside the insulation pattern (DMP).

[0112] In the bending region (BA), an opening (I-OP) of the first to fourth insulating layers (10 to 40) may be defined. Unlike FIG. 8a, the opening (I-OP) may extend to the buffer layer (BFL). The opening (I-OP) can be formed through an etching process after stacking the first to fourth insulating layers (10 to 40). A portion of the fifth insulating layer (50) is disposed inside the opening (I-OP).

[0113] A lower signal line (SL-2) may be disposed on the fifth insulating layer (50). The lower signal line (SL-2) may be formed through the same process as the second connecting electrode (CNE2). The lower signal line (SL-2) may be covered by a sixth insulating layer (60). The sixth insulating layer (60), which covers the lower signal line (SL-2) and supports the first electrode (AE), may be defined as a base insulating layer.

[0114] As illustrated in FIGS. 8a and 8d, the pad portion (SL-P) of the lower signal line (SL-2) may be exposed from the sixth insulating layer (60). An opening (60-OP) that exposes the pad portion (SL-P) may be defined in the sixth insulating layer (60). An anisotropic conductive adhesive layer (ACF) that contacts the pad portion (SL-P) through the opening (60-OP) can electrically connect the pad portion (SL-P) to a circuit board (FPCB).

[0115] As illustrated in FIG. 8c, a bridge pattern (CP2) may be disposed on the first insulating layer (210) within the display area (DA). A first sensing portion (SP1) may be disposed on the second insulating layer (230), and sensing patterns (SP2) may be disposed. Each of the sensing patterns (SP2) is connected to the bridge pattern (CP2) through a contact hole (230-CNT) penetrating the second insulating layer (230).

[0116] Referring to FIGS. 8a and 8b, an upper signal line (SL-1) may be disposed on a second insulating layer (230). The upper signal line (SL-1) may extend from a display area (DA) to a non-display area (NDA). The upper signal line (SL-1) may be connected to a lower signal line (SL-2) through at least one contact hole (CNT). The contact hole (CNT) may be disposed in a second non-bending area (NBA2). The upper signal line (SL-1) may be formed through the same process as the first sensing portion (SP1) and sensing patterns (SP2) shown in FIG. 8c.

[0117] Referring to FIGS. 8a through 8c, the upper signal line (SL-1), the detection portion (SP1), and the detection pattern (SP2) can be covered by a black mattress (310). Referring to FIGS. 8a and 8d, the first insulating layer (210), the second insulating layer (230), the black mattress (310), and the overcoat layer (330) can be non-overlapping with the pad portion (SL-P).

[0118] Referring to FIG. 8a, the overcoat layer (330) can cover the black mattress (310) and surround the end of the black mattress (310). The end of the overcoat layer (330) faces the end of the black mattress (310) and can be positioned closer to the pad portion (SL-P) than the end of the black mattress (310).

[0119] The ends of the first insulating layer (210) and the second insulating layer (230), respectively, can be aligned with the ends of the overcoat layer (330). The first insulating layer (210) and the second insulating layer (230), which protected the pad portion (SL-P) during the manufacturing process of the display device (DD), can be dry-etched using the overcoat layer (330) as a mask after the overcoat layer (330) is patterned. Accordingly, the first insulating layer (210) and the second insulating layer (230) that do not overlap with the overcoat layer (330) can be removed. As a result, the thin film encapsulation layer (TFE), the first insulating layer (210), the second insulating layer (230), and the overcoat layer (330) do not overlap with the pad portion (SL-P), and the pad portion (SL-P) can be exposed from the insulating layers of the display device (DD).

[0120] Referring to FIGS. 8b through 8d, the upper signal line (SL-1) and the lower signal line (SL-2) may each have a multilayer structure. The upper signal line (SL-1) and the lower signal line (SL-2) may each include a first conductive layer (CL1) with relatively high conductivity, a second conductive layer (CL2) disposed above the first conductive layer (CL1), and a third conductive layer (CL3) disposed below the first conductive layer (CL1). The third conductive layer (CL3) may have a greater bonding strength to an insulating layer disposed below the first conductive layer (CL1), and the second conductive layer (CL2) may have a lower external light reflectance than the first conductive layer (CL1). The second conductive layer (CL2) and the third conductive layer (CL3) may contain the same material. The first conductive layer (CL1) may be aluminum, and the second conductive layer (CL2) and the third conductive layer (CL3) may be titanium.

[0121] Referring to FIG. 8b, a contact hole (60-CNT) is defined in the sixth insulating layer (60) to expose a portion of the lower signal line (SL-2). The contact hole (60-CNT) has a relatively large area. A first insulating layer (210) and a second insulating layer (230) may be disposed respectively inside the contact hole (60-CNT). A contact hole (200-CNT) penetrating the first insulating layer (210) and the second insulating layer (230) is defined. The contact holes (200-CNT) of the first insulating layer (210) and the second insulating layer (230) are disposed inside the contact hole (60-CNT) of the sixth insulating layer (60). When the contact hole (60-CNT) is defined as the first contact hole, the contact hole (200-CNT) may be defined as the second contact hole.

[0122] Referring to FIGS. 8a to 8d, the process of forming a color filter (320) includes an etching process that partially removes the color filter. The aluminum layer exposed to the etching solution is etched more than the titanium layers and cannot support the titanium layers. A portion of the titanium layer that is not supported by the aluminum layer is separated into pieces and may cause a short circuit defect between the multiple pad portions (SL-P) shown in FIG. 7a.

[0123] According to the present embodiment, damage to the lower signal line (SL-2) and the upper signal line (SL-1) caused by the etching liquid used in the etching process can be suppressed. The aluminum layer of the lower signal line (SL-2) and the aluminum layer of the upper signal line (SL-1) are sealed by a structure to prevent the etching liquid from accessing them. As shown in FIG. 8a, the side of the lower signal line (SL-2) is sealed by the sixth insulating layer (60), and as shown in FIG. 8b, the side of the upper signal line (SL-1), specifically the sides of the first conductive layer (CL1), the second conductive layer (CL2), and the third conductive layer (CL3), are covered (or sealed) by a black mattress (310). That is, the lower signal line (SL-2) and the upper signal line (SL-1) can be protected from the etching liquid.

[0125] FIG. 9a is a cross-sectional view of a display device (DD) corresponding to I-I' in FIG. 7a. FIG. 9b and FIG. 8c are cross-sectional views of a display device (DD) corresponding to II-II' in FIG. 7a. Hereinafter, for a description of a configuration identical to the configuration described with reference to FIG. 8a to 8d, refer to FIG. 8a to 8d.

[0126] Referring to FIGS. 9a and 9b, a black mattress (310, see FIG. 8) is not placed between the color filter (320) and the second insulating layer (230). As shown in FIG. 9a, the color filter (320) can cover the upper signal line (SL-1). The color filter (320) placed in the non-display area (NDA) corresponds to a reflectance reduction pattern. As shown in FIG. 9b, the color filter (320) can cover the first detection portion (SP1) and detection patterns (SP2).

[0127] The black mattress (310) may be omitted or its stacking position may be changed. Although not shown in FIG. 9a and FIG. 9b, the black mattress (310) may be placed between the color filter (320) and the overcoat layer (330).

[0128] The color filter (320) may include, for example, a first color filter (320-1), a second color filter (320-2), and a third color filter (320-3). The first color filter (320-1) may have one of blue, red, and green, the second color filter (320-2) may have another of blue, red, and green, and the third color filter (320-3) may have yet another of blue, red, and green. Any one of the three types of color filters formed first may simultaneously cover the upper signal line (SL-1), the first detection part (SP1), and the detection patterns (SP2), and may come into contact with the first detection part (SP1) and the detection patterns (SP2).

[0131] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the relevant technical field will understand that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0132] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0133] display panel DP Display area, non-display area DA, NDA Input sensor ISL signal line SL1, SL2 1st Challenge Floor CL1 2nd Challenge Floor CL2 Third challenge layer CL3 Detection pattern SP2 Bridge pattern CP2 base layer BL transistor TFT thin film encapsulation layer TFE Gate G1

Claims

Claim 1 A base layer comprising a display area and a non-display area adjacent to the display area; a lower signal line disposed in the non-display area; a base insulating layer covering the lower signal line and overlapping the display area and the non-display area; a light-emitting element disposed on the base insulating layer and overlapping the display area; a thin film encapsulation layer disposed on the base insulating layer and sealing the light-emitting element; at least one inorganic layer disposed on the thin film encapsulation layer and overlapping the display area and the non-display area; a sensing electrode disposed on the at least one inorganic layer and overlapping the display area; an upper signal line overlapping the non-display area and connecting the lower signal line and the sensing electrode; and a reflectance reduction pattern disposed on the at least one inorganic layer and comprising a dye or pigment. A display device comprising an overcoat layer disposed on the at least one inorganic layer and superimposed on the reflectance reduction pattern, wherein the lower signal line and the upper signal line are connected through at least one contact hole penetrating a corresponding layer among the at least one inorganic layer and the base insulating layer, and the upper signal line is covered by the reflectance reduction pattern. Claim 2 A display device according to claim 1, wherein the base insulating layer comprises an organic layer, the base insulating layer covers the side of the pad portion of the lower signal line, and the base insulating layer has an opening defined therein that exposes the upper surface of the pad portion of the lower signal line. Claim 3 In claim 2, the thin film encapsulation layer, the at least one inorganic layer, and the overcoat layer are non-overlapping with the pad portion of the display device. Claim 4 In claim 3, the overcoat layer covers the reflectance reduction pattern, and the end of the overcoat layer is closer to the pad portion of the lower signal line than the end of the reflectance reduction pattern. Claim 5 In claim 1, the upper signal line comprises a first conductive layer, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. Claim 6 In claim 5, the reflectance reduction pattern is a display device covering the sides of the first conductive layer, the second conductive layer, and the third conductive layer. Claim 7 A display device according to claim 1, wherein the at least one contact hole comprises: a first contact hole penetrating the base insulating layer; and a second contact hole penetrating the at least one inorganic layer. Claim 8 In claim 7, the at least one inorganic layer is disposed inside the first contact hole, and the second contact hole is located inside the first contact hole. Claim 9 In claim 1, the at least one inorganic layer comprises a first inorganic layer and a second inorganic layer disposed on the first inorganic layer, the sensing electrode comprises a first sensing electrode and a second sensing electrode that are insulated and intersecting each other, the first sensing electrode has an integral shape, and the second sensing electrode comprises a sensing pattern disposed on the same layer as the first sensing electrode and a bridge pattern disposed on a different layer from the sensing pattern, the bridge pattern is disposed between the first inorganic layer and the second inorganic layer and is connected to the sensing pattern through a contact hole penetrating the second inorganic layer. Claim 10 In claim 1, the reflectance reduction pattern comprises a black mattress containing a black pigment or a black dye, and the black mattress is a display device that contacts the upper signal line and the upper surface of the at least one inorganic layer, respectively. Claim 11 In claim 10, the reflectance reduction pattern is disposed on the at least one inorganic layer and further comprises a color filter superimposed on the light-emitting element, and the color filter is disposed on the black mattress. Claim 12 A display device according to claim 1, further comprising a first color filter, a second color filter, and a third color filter disposed on the at least one inorganic layer and having different colors, wherein the light-emitting element comprises a first color light-emitting element disposed below the first color filter, a second color light-emitting element disposed below the second color filter, and a third color light-emitting element disposed below the third color filter, and wherein the reflectance reduction pattern comprises a material identical to any one of the first color filter, the second color filter, and the third color filter. Claim 13 A display device according to claim 12, wherein any one of the first color filter, the second color filter, and the third color filter contacts the sensing electrode, and the reflectance reduction pattern comprises the same material as the color filter contacting the sensing electrode. Claim 14 A display device according to claim 1, wherein the reflectance reduction pattern is superimposed on the sensing electrode, and the upper signal line has the same stacked structure as the sensing electrode. Claim 15 A display device comprising a display area and a non-display area adjacent to the display area; and a circuit board electrically connected to the display device, wherein the display device comprises: a lower signal line disposed in the non-display area; a base insulating layer covering the lower signal line and overlapping the display area and the non-display area; a light-emitting element disposed on the base insulating layer and overlapping the display area; a thin film encapsulation layer disposed on the base insulating layer and sealing the light-emitting element; at least one inorganic layer disposed on the thin film encapsulation layer and overlapping the display area and the non-display area; a sensing electrode disposed on the at least one inorganic layer and overlapping the display area; an upper signal line overlapping the non-display area and connecting the lower signal line and the sensing electrode; and a reflectance reduction pattern disposed on the at least one inorganic layer and comprising a dye or pigment. The electronic device comprises an overcoat layer disposed on the at least one inorganic layer and superimposed on the reflectance reduction pattern, wherein the lower signal line and the upper signal line are connected through at least one contact hole penetrating a corresponding layer among the at least one inorganic layer and the base insulating layer, and the upper signal line is covered by the reflectance reduction pattern. Claim 16 An electronic device according to claim 15, further comprising an anisotropic conductive adhesive layer, wherein the circuit board comprises a substrate signal line, the substrate signal line and the lower signal line are electrically connected through the anisotropic conductive adhesive layer, the base insulating layer comprises an organic layer, and the base insulating layer has an opening defined therein that exposes the upper surface of the pad portion of the lower signal line, and the base insulating layer and the pad portion of the lower signal line are in contact with the anisotropic conductive adhesive layer. Claim 17 In claim 15, the electronic device is an electronic device that does not include a polarizing film disposed on the inside or outside of the display device. Claim 18 An electronic device according to claim 15, wherein the upper signal line comprises a first conductive layer, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer, and the reflectance reduction pattern covers the sides of the first conductive layer, the second conductive layer, and the third conductive layer. Claim 19 An electronic device according to claim 15, wherein the at least one contact hole comprises: a first contact hole penetrating the base insulating layer; and a second contact hole penetrating the at least one inorganic layer, wherein the at least one inorganic layer is disposed inside the first contact hole and the second contact hole is located inside the first contact hole. Claim 20 In claim 15, the reflectance reduction pattern comprises a black mattress containing a black pigment or a black dye, and the black mattress is an electronic device in contact with the upper signal line and the upper surface of the at least one inorganic layer, respectively.

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