Deposition mask, method of manufacturing the same, method of manufacturing display panel using the same, and electronic device manufactured by using the same

Abstract

A deposition mask, a method for manufacturing the same, and an electronic device manufactured using the same are provided. The deposition mask comprises a mask substrate having a cell opening and a membrane disposed on the front surface of the mask substrate and having a plurality of pixel openings communicating with the cell opening. The inner surface of the cell opening has a striped surface profile extending in the thickness direction of the mask substrate.

Description

Technology Field

[0001] The present invention relates to a deposition mask, a method for manufacturing the same, a method for manufacturing a display panel using the same, and an electronic device manufactured using the same. Background Technology

[0002] Wearable devices are being developed in the form of glasses or helmets that form a focus at a close distance in front of the user's eyes. For example, the wearable device may be a head-mounted display (HMD) device or AR glasses. Such wearable devices can provide the user with an augmented reality (AR) screen or a virtual reality (VR) screen.

[0003] For wearable devices such as HMDs or AR glasses, display specifications of approximately 3,000 PPI (pixels per inch) or higher are required to allow users to use them for extended periods without dizziness. To achieve this, OLEDoS (Organic Light Emitting Diode on Silicon) technology, which is used in high-resolution, small organic light-emitting displays, is emerging. The OLEDoS technology is a technique for placing Organic Light Emitting Diodes (OLEDs) on a semiconductor substrate on which Complementary Metal Oxide Semiconductor (CMOS) devices are placed.

[0004] In order to manufacture a high-resolution display panel with a resolution of approximately 3000 PPI or higher, a high-resolution deposition mask is required. For example, a deposition mask can be manufactured by forming a membrane having a plurality of pixel openings on the front surface of a mask substrate and forming cell openings that expose the pixel openings by partially removing the mask substrate.

[0005] Cell openings can be formed by forming a back inorganic film having back openings on the back surface of a mask substrate and then performing an etching process using the back inorganic film as an etching mask. For example, cell openings can be formed by a wet etching process using an etching solution such as TMAH (tetramethylammonium hydroxide) solution, potassium hydroxide (KOH) solution, EDP (ethylene diamine pyrocatechol) solution, etc. In this case, the cell openings may have a width that gradually decreases from the back surface of the mask substrate toward the front surface of the mask substrate. Consequently, the cross-sectional area of ​​the rib region of the mask substrate defining the cell openings may be reduced, and consequently, the structural stability of the deposition mask may be degraded. The problem to be solved

[0006] The problem to be solved by the present invention is to provide a deposition mask with improved structural stability, a method for manufacturing the same, a method for manufacturing a display panel using the same, and an electronic device manufactured using the same.

[0007] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0008] According to one aspect of the present invention for solving the above problem, a deposition mask may include a mask substrate having a cell opening and a membrane having a plurality of pixel openings disposed on the front surface of the mask substrate and communicating with the cell opening, and the inner surface of the cell opening may have a striped surface profile extending in the thickness direction of the mask substrate.

[0009] According to one embodiment, the inner surface of the cell opening may be perpendicular to the rear surface of the mask substrate or have an angle of inclination of about 85° or more with respect to the rear surface of the mask substrate.

[0010] According to one embodiment, the deposition mask may further include a rear inorganic film disposed on the rear surface of the mask substrate and having a rear opening that exposes the cell opening.

[0011] According to one embodiment, the rear opening may have the same width as the cell opening.

[0012] According to one embodiment, the back inorganic film may be made of the same material as the membrane and may have the same thickness as the membrane.

[0013] According to one embodiment, the cell opening includes a first opening adjacent to the rear inorganic membrane and a second opening adjacent to the membrane, and the striped surface profile may be formed on the inner surface of the first opening.

[0014] According to one embodiment, the inner surface of the first opening may be perpendicular to the rear surface of the mask substrate or may have an angle of inclination of about 85° or more with respect to the rear surface of the mask substrate, and the second opening may have a width that gradually decreases from the first opening toward the membrane.

[0015] According to one embodiment, the inner surface of the second opening may have an inclination angle of about 54.7° with respect to the rear surface of the mask substrate.

[0016] According to one embodiment, the rear opening may have the same width as the first opening.

[0017] According to one aspect of the present invention for solving the above problem, a method for manufacturing a deposition mask may include the steps of forming a membrane having a plurality of pixel openings on the front surface of a mask substrate and partially removing the mask substrate to form a cell opening communicating with the pixel openings, and the inner surface of the cell opening may have a striped surface profile extending in the thickness direction of the mask substrate.

[0018] According to one embodiment, the step of forming the cell opening may include forming a metal catalyst pattern on the back surface of the mask substrate and performing a metal-assisted chemical etching process using the metal catalyst pattern to form the cell opening.

[0019] According to one embodiment, during the metal-assisted chemical etching process, the metal catalyst pattern may be moved in the thickness direction of the mask substrate, and the striped surface profile may be formed while the metal catalyst pattern is moved.

[0020] According to one embodiment, the metal catalyst pattern may include at least one selected from the group consisting of gold (Au), silver (Ag), platinum (Pt) and palladium (Pd).

[0021] According to one embodiment, the metal catalyst pattern may have a single-layer structure or a double-layer structure.

[0022] According to one embodiment, the metal catalyst pattern may have a thickness in the range of about 3 nm to about 10 nm.

[0023] According to one embodiment, the metal-assisted chemical etching process can be performed using an etching solution comprising an oxidizing agent, an etchant, and a solvent.

[0024] According to one embodiment, the oxidizing agent may include at least one selected from the group consisting of hydrogen peroxide (H2O2), silver nitrate (AgNO3), chlorauric acid (HAuCl4), chloroplatinic acid (H2PtCl6), iron(III) nitrate (Fe(NO3)3), nickel(II) nitrate (Ni(NO3)2), magnesium nitrate (Mg(NO3)2), sodium persulfate (Na2S2O8), potassium permanganate (KMnO4), and potassium dichromate (K2Cr2O7).

[0025] According to one embodiment, the etchant may include hydrofluoric acid (HF).

[0026] According to one embodiment, the solvent may include water, ethanol, or a mixed solution of water and ethanol.

[0027] According to one embodiment, the step of forming the cell opening may further include the step of removing the metal catalyst pattern after performing the metal-assisted chemical etching process.

[0028] According to one embodiment, the step of forming the cell opening may further include the step of removing etching residue after performing the metal-assisted chemical etching process.

[0029] According to one embodiment, the step of forming the cell opening may include forming a plurality of metal catalyst patterns on the back surface of the mask substrate and performing a metal-assisted chemical etching process using the metal catalyst patterns to form the cell opening.

[0030] According to one embodiment, the step of forming the cell opening may include forming a plurality of metal catalyst patterns on the back surface of the mask substrate, performing a metal-assisted chemical etching process using the metal catalyst patterns to form preliminary cell openings penetrating the mask substrate, and removing partitions between the preliminary cell openings to form the cell opening.

[0031] According to one embodiment, the inner surface of the cell opening may be formed to be perpendicular to the rear surface of the mask substrate or to have an inclination angle of 85° or more with respect to the rear surface of the mask substrate.

[0032] According to one embodiment, the method for manufacturing the deposition mask may further include the step of forming a rear inorganic film on the rear surface of the mask substrate and the step of patterning the rear inorganic film to form a rear opening that partially exposes the rear surface of the mask substrate.

[0033] According to one embodiment, the cell opening may be formed to penetrate the rear portion of the mask substrate exposed by the rear opening.

[0034] According to one embodiment, the step of forming the cell opening may include forming a metal catalyst pattern on a rear portion of the mask substrate exposed by the rear opening, and performing a metal-assisted chemical etching process using the metal catalyst pattern to form the cell opening.

[0035] According to one embodiment, the step of forming the cell opening may include: forming a metal catalyst pattern on a rear portion of the mask substrate exposed by the rear opening; performing a metal-assisted chemical etching process using the metal catalyst pattern to form a first opening extending from the rear portion of the mask substrate in the thickness direction of the mask substrate; removing the metal catalyst pattern; and forming a second opening connecting the first opening and the pixel openings.

[0036] According to one embodiment, the inner surface of the first opening may be formed to be perpendicular to the rear surface of the mask substrate or to have an angle of inclination of 85° or more to the rear surface of the mask substrate, and the second opening may be formed to have a width that gradually decreases from the first opening toward the membrane.

[0037] According to one embodiment, the inner surface of the second opening may be formed to have an inclination angle of about 54.7° with respect to the rear surface of the mask substrate.

[0038] According to one embodiment, the second opening may be formed by a wet etching process using a TMAH solution, a KOH solution, or an EDP solution.

[0039] According to one embodiment, the step of forming the cell opening may further include the step of forming a liner pattern on the inner surfaces of the first opening and the step of removing the liner pattern after forming the second opening.

[0040] According to one embodiment, the step of forming the liner pattern may include the step of forming a rear passivation film on the inner surfaces of the rear opening and the first opening and on the rear inorganic film, and the step of removing the rear passivation film portion on the rear inorganic film and the rear passivation film portion on the bottom surface of the first opening.

[0041] According to one embodiment, the step of forming the cell opening may further include the step of forming a front passivation film on the inner surfaces of the pixel openings and on the membrane after forming the first opening, and the step of removing the front passivation film after forming the second opening.

[0042] According to one aspect of the present invention for solving the above problem, a method for manufacturing a deposition mask may include the step of forming a membrane having a plurality of pixel openings on the front surface of a mask substrate and the step of partially removing the mask substrate to form a cell opening communicating with the pixel openings, and at least a portion of the cell opening may be formed using a metal-assisted chemical etching process.

[0043] According to one aspect of the present invention for solving the above problem, a method for manufacturing a display panel may include the steps of positioning a backplane substrate on a deposition mask and providing a gaseous light-emitting material through the deposition mask to form a plurality of light-emitting layers on the backplane substrate. The deposition mask may include a mask substrate having a cell opening and a membrane having a plurality of pixel openings disposed on the front surface of the mask substrate and communicating with the cell opening, wherein the inner surface of the cell opening may have a striped surface profile extending in the thickness direction of the mask substrate. The gaseous light-emitting material may be provided onto the backplane substrate through the cell opening and the pixel openings.

[0044] According to one aspect of the present invention for solving the above problem, an electronic device including a display panel may include a backplane substrate and a plurality of light-emitting layers formed on the backplane substrate using a deposition mask. The deposition mask comprises a mask substrate having a cell opening and a membrane having a plurality of pixel openings disposed on the front surface of the mask substrate and communicating with the cell opening, wherein the inner surface of the cell opening may have a striped surface profile extending in the thickness direction of the mask substrate.

[0045] According to one embodiment, the electronic device may further include at least one of a processor, a memory, and a power module.

[0046] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0047] According to the embodiments described above, the cross-sectional area of ​​the lip region of the mask substrate defining the cell opening can be increased. As a result, the structural stability of the deposition mask can be improved, and accordingly, the warpage of the deposition mask can be reduced.

[0048] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0049] FIG. 1 is a block diagram for illustrating an electronic device according to one embodiment. Figure 2 is a schematic diagram illustrating examples of the electronic device shown in Figure 1. FIG. 3 is an exploded perspective view for explaining a display device according to one embodiment. FIG. 4 is a block diagram for explaining the display device illustrated in FIG. 3. FIG. 5 is an equivalent circuit diagram to explain an example of the first subpixel shown in FIG. 4. FIG. 6 is a schematic plan view to illustrate an example of a display panel shown in FIG. 3. FIG. 7 is a schematic enlarged plan view to illustrate an example of the display area shown in FIG. 6. FIG. 8 is a schematic enlarged plan view to illustrate another example of the display area shown in FIG. 6. FIG. 9 is a schematic cross-sectional view to illustrate an example of a display panel obtained along the line I1-I1' shown in FIG. 7. FIG. 10 is a schematic cross-sectional view illustrating another example of a display panel obtained along the line I1-I1' shown in FIG. 7. FIG. 11 is a schematic cross-sectional view to illustrate another example of a display panel obtained along the line I1-I1' shown in FIG. 7. FIG. 12 is a schematic perspective view illustrating an example of a head-mounted display device. FIG. 13 is a schematic exploded perspective view for explaining the head-mounted display device illustrated in FIG. 12. FIG. 14 is a schematic perspective view illustrating another example of a head-mounted display device. FIG. 15 is a schematic diagram illustrating a deposition mask and a deposition apparatus including the same according to one embodiment. FIG. 16 is a schematic bottom view illustrating the backplane substrate shown in FIG. 15. FIG. 17 is a schematic plan view illustrating the deposition mask shown in FIG. 15. FIG. 18 is a schematic enlarged plan view for explaining the mask cell regions illustrated in FIG. 17. FIG. 19 is a schematic cross-sectional view obtained along the line I2-I2' shown in FIG. 18. FIG. 20 is a schematic cross-sectional view illustrating another example of a deposition mask shown in FIG. 19. FIG. 21 is a schematic cross-sectional view illustrating another example of a deposition mask shown in FIG. 19. FIGS. 22 to 27 are schematic cross-sectional views illustrating a method for manufacturing a deposition mask according to one embodiment of the present invention. FIGS. 28 to 30 are schematic drawings for explaining a method for manufacturing a deposition mask according to another embodiment of the present invention. FIG. 28 is a schematic cross-sectional view illustrating metal catalyst patterns formed on the back surface of a mask substrate. FIG. 29 is a schematic plan view illustrating the metal catalyst patterns shown in FIG. 28. FIG. 30 is a schematic cross-sectional view illustrating a cell opening formed by the metal catalyst patterns shown in FIG. 28. FIGS. 31 to 33 are schematic cross-sectional views illustrating a method for manufacturing a deposition mask according to another embodiment of the present invention. FIGS. 34 to 37 are schematic cross-sectional views illustrating a method for manufacturing a deposition mask according to another embodiment of the present invention. FIGS. 38 to 45 are schematic cross-sectional views illustrating a method for manufacturing a deposition mask according to another embodiment of the present invention. Specific details for implementing the invention

[0050] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0051] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0052] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0053] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0054] Specific embodiments will be described below with reference to the attached drawings.

[0055] A display device according to one embodiment can be applied to various electronic devices. An electronic device according to one embodiment may include a display device and may further include a module or device having other additional functions in addition to the display device.

[0056] FIG. 1 is a block diagram for illustrating an electronic device according to one embodiment.

[0057] Referring to FIG. 1, an electronic device (10) according to one embodiment may include a display module (11), a processor (12), a memory (13), a power module (14), etc.

[0058] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0059] The memory (13) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (13), an image data signal and / or an input control signal are transmitted to the display module (11), and the display module (11) can process the received signal and output image information through a display screen.

[0060] The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (10).

[0061] At least one of each component of the electronic device (10) described above may be included in a display device (20) according to embodiments to be described later. Additionally, some of the individual modules functionally included in one module may be included in the display device (20), while others may be provided separately from the display device (20). For example, the display device (20) may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device (20).

[0062] Figure 2 is a schematic diagram illustrating examples of the electronic device shown in Figure 1.

[0063] Referring to FIG. 2, various electronic devices (10) to which a display device (20) (see FIG. 3) according to embodiments is applied may include electronic devices for displaying images such as a smartphone (10_1a), a tablet PC (10_1b), a laptop (10_1c), a TV (10_1d), a desk monitor (10_1e), etc. Electronic devices (10) to which a display device (20) according to embodiments is applied may be applied to wearable electronic devices including a display module (11) such as smart glasses (10_2a), a head-mounted display (10_2b), a smart watch (10_2c), etc. Additionally, electronic devices (10) to which a display device (20) according to embodiments is applied may include electronic devices for vehicles (10_3), etc., including a display module (11) such as a CID (Center Information Display), a room mirror display, etc., placed on the instrument panel, center fascia, or dashboard of a vehicle.

[0064] FIG. 3 is an exploded perspective view for explaining a display device according to one embodiment. FIG. 4 is a block diagram for explaining the display device shown in FIG. 3.

[0065] Referring to FIGS. 3 and 4, a display device (20) according to one embodiment is a device for displaying video or still images. A display device (20) according to one embodiment can be used as an electronic device (10) or as a display module (11) of an electronic device (10). For example, a display device (20) according to one embodiment can be applied to a portable electronic device (10) such as a mobile phone, a smartphone, a tablet personal computer, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation system, an ultra mobile PC (UMPC), etc. A display device (20) according to one embodiment can be applied to a display module (11) of an electronic device (10) such as a television, a laptop, a monitor, an advertising board, an Internet of Things (IOT) device, etc. A display device (20) according to one embodiment can be applied to electronic devices (10) such as a smart watch, a watch phone, a head-mounted display (HMD) for implementing virtual reality and augmented reality.

[0066] A display device (20) according to one embodiment may include a display panel (100), a heat dissipation layer (200), a circuit board (300), a timing control circuit (400) (or a timing control unit), and a power supply circuit (500) (or a power supply unit).

[0067] The display panel (100) may be formed in a planar shape similar to a rectangle. For example, the display panel (100) may have a planar shape similar to a rectangle having a short side in a first direction (DR1) and a long side in a second direction (DR2) that intersects the first direction (DR1). The corners where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet in the display panel (100) may be formed rounded to have a predetermined curvature or formed at a right angle. The planar shape of the display panel (100) is not limited to a rectangle and may be formed similarly to other polygons, circles, or ellipses. The planar shape of the display device (20) may follow the planar shape of the display panel (100), but the embodiments of this specification are not limited thereto.

[0068] The display panel (100) may include a plurality of pixels (PX), a plurality of scan lines (SL), a plurality of light emission control lines (EL), and a plurality of data lines (DL), a scan driving unit (610), a light emission driving unit (620), and a data driving unit (700). As shown in FIG. 4, the display panel (100) may be divided into a display area (DAA) that displays an image and a non-display area (NDA) that does not display an image.

[0069] Multiple pixels (PX) may be placed in a display area (DAA). Multiple pixels (PX) may be arranged in a matrix form along a first direction (DR1) and a second direction (DR2). Multiple scan lines (SL) and multiple light emission control lines (EL) may extend in the first direction (DR1) and be arranged in the second direction (DR2). Multiple data lines (DL) may extend in the second direction (DR2) and be arranged in the first direction (DR1).

[0070] A plurality of scan lines (SL) may include a plurality of write scan lines (GWL), a plurality of control scan lines (GCL), and a plurality of bias scan lines (GBL). A plurality of light emission control lines (EL) include a plurality of first light emission control lines (ECL1) and a plurality of second light emission control lines (ECL2).

[0071] A plurality of pixels (PX) may include a plurality of sub-pixels (SP1, SP2, SP3). The plurality of sub-pixels (SP1, SP2, SP3) include a plurality of pixel transistors as shown in FIG. 5, and the plurality of pixel transistors are formed by a semiconductor process and may be placed on a semiconductor substrate (SSUB in FIG. 9). For example, the plurality of pixel transistors of the data driving unit (700) may be formed as CMOS (Complementary Metal Oxide Semiconductor), but the embodiments of the present specification are not limited thereto.

[0072] Each of the plurality of subpixels (SP1, SP2, SP3) can be connected to one write scan line (GWL), one control scan line (GCL), one bias scan line (GBL), one first light emission control line (ECL1), one second light emission control line (ECL2), and one data line (DL). Each of the plurality of subpixels (SP1, SP2, SP3) receives a data voltage of the data line (DL) according to the write scan signal of the write scan line (GWL), and can emit light from a light-emitting element according to the data voltage.

[0073] The scan drive unit (610), light-emitting drive unit (620), and data drive unit (700) can be placed in the non-display area (NDA).

[0074] The scan driving unit (610) includes a plurality of scan transistors, and the light-emitting driving unit (620) includes a plurality of light-emitting transistors. The plurality of scan transistors and the plurality of light-emitting transistors are formed by a semiconductor process and can be formed on a semiconductor substrate (SSUB of FIG. 9). For example, the plurality of scan transistors and the plurality of light-emitting transistors can be formed by CMOS, but the embodiments of the present specification are not limited thereto.

[0075] The scan driving unit (610) may include a write scan signal output unit (611), a control scan signal output unit (612), and a bias scan signal output unit (613). Each of the write scan signal output unit (611), the control scan signal output unit (612), and the bias scan signal output unit (613) may receive a scan timing control signal (SCS) from the timing control circuit (400). The write scan signal output unit (611) may generate write scan signals according to the scan timing control signal (SCS) of the timing control circuit (400) and output them sequentially to the write scan lines (GWL). The control scan signal output unit (612) may generate control scan signals according to the scan timing control signal (SCS) and output them sequentially to the control scan lines (GCL). The bias scan signal output unit (613) may generate bias scan signals according to the scan timing control signal (SCS) and output them sequentially to the bias scan lines (GBL).

[0076] The light-emitting driver (620) includes a first light-emitting control driver (621) and a second light-emitting control driver (622). Each of the first light-emitting control driver (621) and the second light-emitting control driver (622) can receive a light-emitting timing control signal (ECS) from the timing control circuit (400). The first light-emitting control driver (621) can generate first light-emitting control signals according to the light-emitting timing control signal (ECS) and output them sequentially to the first light-emitting control lines (ECL1). The second light-emitting control driver (622) can generate second light-emitting control signals according to the light-emitting timing control signal (ECS) and output them sequentially to the second light-emitting control lines (ECL2).

[0077] The data driving unit (700) includes a plurality of data transistors, and the plurality of data transistors are formed by a semiconductor process and can be formed on a semiconductor substrate (SSUB of FIG. 9). For example, the plurality of data transistors may be formed by CMOS, but the embodiments of the present specification are not limited thereto.

[0078] The data driver (700) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control circuit (400). The data driver (700) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs them to the data lines (DL). In this case, subpixels (SP1, SP2, SP3) are selected by the write scan signal of the scan driver (610), and data voltages can be supplied to the selected subpixels (SP1, SP2, SP3).

[0079] The heat dissipation layer (200) may overlap with the display panel (100) in a third direction (DR3), which is the thickness direction of the display panel (100). The heat dissipation layer (200) may be placed on one side of the display panel (100), for example, on the back side. The heat dissipation layer (200) serves to dissipate heat generated from the display panel (100). The heat dissipation layer (200) may include a metal layer such as graphite, silver (Ag), copper (Cu), or aluminum (Al), which has high thermal conductivity.

[0080] The circuit board (300) can be electrically connected to a first plurality of pads (PD1 in FIG. 6) of a first pad portion (PDA1 in FIG. 6) of a display panel (100) using a conductive adhesive member such as an anisotropic conductive film. The circuit board (300) may be a flexible printed circuit board having a flexible material or a flexible film. Although FIG. 3 illustrates the circuit board (300) unfolded, the circuit board (300) may be bent. In this case, one end of the circuit board (300) may be placed on the back surface of the display panel (100) and / or the back surface of the heat dissipation layer (200). The other end of the circuit board (300) may be connected to a plurality of first pads (PD1 in FIG. 6) of a first pad portion (PDA1 in FIG. 6) of the display panel (100) using a conductive adhesive member. One end of the circuit board (300) can be the opposite end of the other end of the circuit board (300).

[0081] The timing control circuit (400) can receive digital video data and timing signals from an external source. The timing control circuit (400) can generate a scan timing control signal (SCS), a light emission timing control signal (ECS), and a data timing control signal (DCS) to control the display panel (100) according to the timing signals. The timing control circuit (400) can output the scan timing control signal (SCS) to the scan driver (610) and the light emission timing control signal (ECS) to the light emission driver (620). The timing control circuit (400) can output the digital video data and the data timing control signal (DCS) to the data driver (700).

[0082] The power supply circuit (500) can generate a plurality of panel driving voltages according to the power supply voltage from an external source. For example, the power supply circuit (500) can generate a first driving voltage (VSS), a second driving voltage (VDD), and a third driving voltage (VINT) and supply them to the display panel (100). The first driving voltage (VSS), the second driving voltage (VDD), and the third driving voltage (VINT) will be described later in conjunction with FIG. 5.

[0083] The timing control circuit (400) and the power supply circuit (500) can each be formed as an integrated circuit (IC) and attached to one side of the circuit board (300). In this case, the scan timing control signal (SCS), light emission timing control signal (ECS), digital video data (DATA), and data timing control signal (DCS) of the timing control circuit (400) can be supplied to the display panel (100) through the circuit board (300). Additionally, the first driving voltage (VSS), the second driving voltage (VDD), and the third driving voltage (VINT) of the power supply circuit (500) can be supplied to the display panel (100) through the circuit board (300).

[0084] Alternatively, the timing control circuit (400) and the power supply circuit (500) may each be placed in the non-display area (NDA) of the display panel (100), similar to the scan driver (610), light-emitting driver (620), and data driver (700). In this case, the timing control circuit (400) may include a plurality of timing transistors, and each of the power supply circuits (500) may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors are formed by a semiconductor process and may be formed on a semiconductor substrate (SSUB of FIG. 9). For example, the plurality of timing transistors and the plurality of power transistors may be formed by CMOS, but the embodiments of this specification are not limited thereto. The timing control circuit (400) and the power supply circuit (500) may each be placed between the data driver (700) and the first pad unit (PDA1 of FIG. 6).

[0085] FIG. 5 is an equivalent circuit diagram to explain an example of the first subpixel shown in FIG. 4.

[0086] Referring to FIG. 5, the first subpixel (SP1) can be connected to a write scan line (GWL), a control scan line (GCL), a bias scan line (GBL), a first light emission control line (ECL1), a second light emission control line (ECL2), and a data line (DL). Additionally, the first subpixel (SP1) can be connected to a first driving voltage line (VSL) to which a first driving voltage (VSS) corresponding to a low potential voltage is applied, a second driving voltage line (VDL) to which a second driving voltage (VDD) corresponding to a high potential voltage is applied, and a third driving voltage line (VIL) to which a third driving voltage (VINT) corresponding to an initialization voltage is applied.

[0087] The first subpixel (SP1) may include a plurality of transistors (T1 to T6), a light-emitting element (LE), a first capacitor (CP1), and a second capacitor (CP2).

[0088] The light-emitting element (LE) emits light according to the driving current (Ids) flowing through the channel of the first transistor (T1). The amount of light emitted by the light-emitting element (LE) may be proportional to the driving current (Ids). The first electrode of the light-emitting element (LE) may be an anode electrode, and the second electrode of the light-emitting element (LE) may be a cathode electrode. The light-emitting element (LE) may be an organic light-emitting diode comprising a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the embodiments of the present specification are not limited thereto. For example, the light-emitting element (LE) may be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode, in which case the light-emitting element (LE) may be a micro light-emitting diode.

[0089] The first transistor (T1) may be a driving transistor that controls the source-drain current (Ids, hereinafter referred to as “driving current”) flowing between the source electrode and the drain electrode according to the voltage applied to the gate electrode.

[0090] The second transistor (T2) can be placed between one electrode of the first capacitor (CP1) and the data line (DL). The second transistor (T2) is turned on by a write scan signal of the write scan line (GWL) to connect one electrode of the first capacitor (CP1) to the data line (DL). As a result, the data voltage of the data line (DL) can be applied to one electrode of the first capacitor (CP1).

[0091] The third transistor (T3) can be placed between the first node (N1) and the second node (N2). The third transistor (T3) is turned on by a control scan signal of the control scan line (GCL) to connect the first node (N1) to the second node (N2). As a result, when the gate electrode and the source electrode of the first transistor (T1) are connected, the first transistor (T1) can operate like a diode.

[0092] The fourth transistor (T4) can be connected between the second node (N2) and the third node (N3). The fourth transistor (T4) is turned on by the first light emission control signal of the first light emission control line (ECL1) to connect the second node (N2) to the third node (N3). As a result, the driving current of the first transistor (T1) can be supplied to the light-emitting element (LE). The fifth transistor (T5) can be placed between the third node (N3) and the third driving voltage line (VIL). The fifth transistor (T5) is turned on by the bias scan signal of the bias scan line (GBL) to connect the third node (N3) to the third driving voltage line (VIL). As a result, the third driving voltage (VINT) of the third driving voltage line (VIL) can be applied to the first electrode of the light-emitting element (LE).

[0093] The sixth transistor (T6) can be placed between the source electrode of the first transistor (T1) and the second driving voltage line (VDL). The sixth transistor (T6) is turned on by a second light emission control signal of the second light emission control line (ECL2) to connect the source electrode of the first transistor (T1) to the second driving voltage line (VDL). As a result, the second driving voltage (VDD) of the second driving voltage line (VDL) can be applied to the source electrode of the first transistor (T1).

[0094] The first capacitor (CP1) is formed between the first node (N1) and the drain electrode of the second transistor (T2). The second capacitor (CP2) is formed between the gate electrode of the first transistor (T1) and the second driving voltage line (VDL).

[0095] Each of the first to sixth transistors (T1 to T6) may be a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). For example, each of the first to sixth transistors (T1 to T6) may be a p-type MOSFET, but the embodiments of this specification are not limited thereto. Each of the first to sixth transistors (T1 to T6) may be an n-type MOSFET. Alternatively, among the first to sixth transistors (T1 to T6), some of the transistors may be p-type MOSFETs and the remaining transistors may be n-type MOSFETs.

[0096] In FIG. 5, the first subpixel (SP1) is illustrated as including six transistors (T1 to T6) and two capacitors (C1, C2), but it should be noted that the equivalent circuit diagram of the first subpixel (SP1) is not limited to that shown in FIG. 5. For example, the number of transistors and capacitors of the first subpixel (SP1) is not limited to that shown in FIG. 5.

[0097] In addition, the equivalent circuit diagram of the second subpixel (SP2) and the equivalent circuit diagram of the third subpixel (SP3) may be substantially the same as the equivalent circuit diagram of the first subpixel (SP1) described in conjunction with FIG. 5. Therefore, the description of the equivalent circuit diagram of the second subpixel (SP2) and the equivalent circuit diagram of the third subpixel (SP3) is omitted in this specification.

[0098] FIG. 6 is a schematic plan view to illustrate an example of a display panel shown in FIG. 3.

[0099] Referring to FIG. 6, the display area (DAA) of the display panel (100) according to one embodiment includes a plurality of pixels (PX) arranged in a matrix form. The non-display area (NDA) of the display panel (100) according to one embodiment includes a scan driving unit (610), a light-emitting driving unit (620), a data driving unit (700), a first distribution circuit (710), a second distribution circuit (720), a first pad unit (PDA1), and a second pad unit (PDA2).

[0100] The scan drive unit (610) may be positioned on the first side of the display area (DAA), and the light-emitting drive unit (620) may be positioned on the second side of the display area (DAA). For example, the scan drive unit (610) may be positioned on one side of the first direction (DR1) of the display area (DAA), and the light-emitting drive unit (620) may be positioned on the other side of the first direction (DR1) of the display area (DAA). However, the embodiments of this specification are not limited thereto, and the scan drive unit (610) and the light-emitting drive unit (620) may be positioned on both the first side and the second side of the display area (DAA).

[0101] The first pad portion (PDA1) may include a plurality of first pads (PD1) connected to pads or bumps of the circuit board (300) through a conductive adhesive member. The first pad portion (PDA1) may be positioned on the third side of the display area (DAA). For example, the first pad portion (PDA1) may be positioned on one side of the second direction (DR2) of the display area (DAA). The first pad portion (PDA1) may be positioned outside the data driving unit (700) in the second direction (DR2).

[0102] The second pad section (PDA2) may include a plurality of second pads (PD2) corresponding to test pads that test whether the display panel (100) is operating normally. The plurality of second pads (PD2) may be connected to a jig or probe pin in the inspection process or connected to a test circuit board. The test circuit board may be a printed circuit board made of a rigid material or a flexible printed circuit board having a flexible material.

[0103] The second pad portion (PDA2) may be positioned on the fourth side of the display area (DAA). For example, the second pad portion (PDA2) may be positioned on the other side of the second direction (DR2) of the display area (DAA). The second pad portion (PDA2) may be positioned outside the second distribution circuit (720) in the second direction (DR2).

[0104] The first distribution circuit (710) distributes data voltages applied through the first pad section (PDA1) to a plurality of data lines (DL). For example, the first distribution circuit (710) can distribute data voltages applied through one first pad (PD1) of the first pad section (PDA1) to P data lines (DL) (where P is a positive integer greater than or equal to 2), thereby reducing the number of multiple first pads (PD1). The first distribution circuit (710) may be placed on the third side of the display area (DAA) of the display panel (100). For example, the first distribution circuit (710) may be placed on one side of the second direction (DR2) of the display area (DAA).

[0105] The second distribution circuit (720) distributes signals applied through the second pad section (PDA2) to the scan driver (610), the light-emitting driver (620), and the data lines (DL). The second pad section (PDA2) and the second distribution circuit (720) may be configured to inspect the operation of each pixel (PX) of the display area (DAA). The second distribution circuit (720) may be placed on the fourth side of the display area (DAA) of the display panel (100). For example, the second distribution circuit (720) may be placed on the other side of the second direction (DR2) of the display area (DAA).

[0106] The cathode connection portion (CCA) may be an area where the second electrode (CAT in FIG. 9) of the display element layer (EML in FIG. 9) is connected to the first driving voltage line (VSL) of the non-display area (NDA). The cathode connection portion (CCA) may be positioned outside at least one side of the display area (DAA). For example, the cathode connection portion (CCA) may be positioned outside at least one side among the left, right, upper, and lower sides of the display area (DAA). Alternatively, the cathode connection portion (CCA) may be positioned to surround the display area (DAA) as shown in FIG. 6 to minimize deviations in the first driving voltage (VSS) caused by a voltage drop (IR drop) or voltage rise (IR rising) of the second electrode (CAT) in the display area (DAA).

[0107] FIG. 7 is a schematic enlarged plan view to illustrate one example of the display area shown in FIG. 6. FIG. 8 is a schematic enlarged plan view to illustrate another example of the display area shown in FIG. 6.

[0108] Referring to FIGS. 7 and 8, each of the plurality of pixels (PX) includes a first light-emitting region (EA1) which is a light-emitting region of the first subpixel (SP1), a second light-emitting region (EA2) which is a light-emitting region of the second subpixel (SP2), and a third light-emitting region (EA3) which is a light-emitting region of the third subpixel (SP3).

[0109] The first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) may have a planar shape of a square or a hexagon as shown in FIGS. 7 and 8, but the embodiments of the present specification are not limited thereto. The first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) may have a planar shape of a polygon, circle, ellipse, or irregular shape other than a square and a hexagon.

[0110] As shown in FIG. 7, in each of the plurality of pixels (PX), the first light-emitting region (EA1) and the second light-emitting region (EA2) may be adjacent in the first direction (DR1). Additionally, the first light-emitting region (EA1) and the third light-emitting region (EA3) may be adjacent in the first direction (DR1). Additionally, the second light-emitting region (EA2) and the third light-emitting region (EA3) may be adjacent in the second direction (DR2). The area of ​​the first light-emitting region (EA1), the area of ​​the second light-emitting region (EA2), and the area of ​​the third light-emitting region (EA3) may be different.

[0111] Alternatively, as shown in FIG. 8, the light-emitting regions (EA1, EA2, EA3, EA4) may have a hexagonal planar shape. In this case, the first light-emitting region (EA1) and the third light-emitting region (EA3) may be adjacent in the first direction (DR1), and the second light-emitting region (EA2) and the fourth light-emitting region (EA4) may be adjacent in the second direction (DR2). Additionally, the first light-emitting region (EA1) and the second light-emitting region (EA2) may be adjacent in the first diagonal direction (DD1), and the second light-emitting region (EA2) and the third light-emitting region (EA3) may be adjacent in the second diagonal direction (DD2). Additionally, the first light-emitting region (EA1) and the fourth light-emitting region (EA4) may be adjacent in the second diagonal direction (DD2), and the third light-emitting region (EA3) and the fourth light-emitting region (EA4) may be adjacent in the first diagonal direction (DD1). The first diagonal direction (DD1) is a direction between the first direction (DR1) and the second direction (DR2), and is a direction tilted at 45° relative to the first direction (DR1) and the second direction (DR2), and the second diagonal direction (DD2) may be a direction orthogonal to the first diagonal direction (DD1).

[0112] The first subpixel (SP1) may emit a first light, the second subpixel (SP2) may emit a second light, and the third subpixel (SP3) may emit a third light. Here, the first light may be light in the blue wavelength band, the second light may be light in the green wavelength band, and the third light may be light in the red wavelength band. For example, the blue wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 370 nm to 460 nm, the green wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 480 nm to 560 nm, and the red wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 600 nm to 750 nm.

[0113] As shown in FIG. 7, each of the plurality of pixels (PX) may include three light-emitting regions (EA1, EA2, EA3), or as shown in FIG. 8, four light-emitting regions (EA1, EA2, EA3, EA4). In this case, the fourth light-emitting region (EA4) may emit a second light identical to that of the second light-emitting region (EA2), but the embodiments of the present specification are not limited thereto.

[0114] The light-emitting regions of multiple pixels (PX) can be arranged in a stripe structure in which the light-emitting regions are arranged in a first direction (DR1), a PenTile® structure in which the light-emitting regions (EA1, EA2, EA3, EA4) have a rhombus-shaped arrangement as shown in FIG. 8, or a hexagonal structure in which the light-emitting regions have a hexagonal arrangement.

[0115] FIG. 9 is a schematic cross-sectional view to illustrate an example of a display panel obtained along the line I1-I1' shown in FIG. 7.

[0116] Referring to FIG. 9, the display panel (100) includes a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), an encapsulation layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizer (POL).

[0117] A semiconductor backplane (SBP) comprises a semiconductor substrate (SSUB) including a plurality of pixel transistors (PTRs), a plurality of semiconductor insulating films covering the plurality of pixel transistors (PTRs), and a plurality of contact terminals (CTE) electrically connected to each of the plurality of pixel transistors (PTRs). The plurality of pixel transistors (PTRs) may be the first to sixth transistors (T1 to T6) described in conjunction with FIG. 5.

[0118] The semiconductor substrate (SSUB) may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate (SSUB) may be a substrate doped with a first type impurity. A plurality of well regions (WA) may be disposed on the upper surface of the semiconductor substrate (SSUB). The plurality of well regions (WA) may be regions doped with a second type impurity. The second type impurity may be different from the first type impurity described above. For example, if the first type impurity is a p-type impurity, the second type impurity may be an n-type impurity. Or, if the first type impurity is an n-type impurity, the second type impurity may be a p-type impurity.

[0119] Each of the plurality of well regions (WA) includes a source region (SA) corresponding to the source electrode of the pixel transistor (PTR), a drain region (DA) corresponding to the drain electrode, and a channel region (CH) disposed between the source region (SA) and the drain region (DA).

[0120] A bottom insulating layer (BINS) may be disposed between the gate electrode (GE) and the well region (WA). A side insulating layer (SINS) may be disposed on the side of the gate electrode (GE). The side insulating layer (SINS) may be disposed on the bottom insulating layer (BINS).

[0121] Each of the source region (SA) and the drain region (DA) may be a region doped with a first type of impurity. The gate electrode (GE) of the pixel transistor (PTR) may overlap with the well region (WA) in the third direction (DR3), which is the thickness direction of the semiconductor substrate (SSUB). The channel region (CH) may overlap with the gate electrode (GE) in the third direction (DR3). The source region (SA) may be placed on one side of the gate electrode (GE), and the drain region (DA) may be placed on the other side of the gate electrode (GE).

[0122] Each of the plurality of well regions (WA) further includes a first low-concentration impurity region (LDD1) disposed between the channel region (CH) and the source region (SA), and a second low-concentration impurity region (LDD2) disposed between the channel region (CH) and the drain region (DA). The first low-concentration impurity region (LDD1) may be a region having a lower impurity concentration than the source region (SA) due to the lower insulating layer (BINS). The second low-concentration impurity region (LDD2) may be a region having a lower impurity concentration than the drain region (DA) due to the lower insulating layer (BINS). The distance between the source region (SA) and the drain region (DA) may be increased by the first low-concentration impurity region (LDD1) and the second low-concentration impurity region (LDD2), and this may increase the length of the channel region (CH) of each pixel transistor (PTR).

[0123] The first semiconductor insulating film (SINS1) can be disposed on a semiconductor substrate (SSUB). The second semiconductor insulating film (SINS2) can be disposed on the first semiconductor insulating film (SINS1).

[0124] A plurality of contact terminals (CTE) may be disposed on a second semiconductor insulating film (SINS2). Each of the plurality of contact terminals (CTE) may be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through a hole penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The plurality of contact terminals (CTE) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of these.

[0125] A third semiconductor insulating film (SINS3) may be disposed on the side of each of the plurality of contact terminals (CTE). The upper surface of each of the plurality of contact terminals (CTE) may be exposed without being covered by the third semiconductor insulating film (SINS3).

[0126] Each of the first semiconductor insulating film (SINS1), the second semiconductor insulating film (SINS2), and the third semiconductor insulating film (SINS3) may be formed from an inorganic film of the silicon nitride (SiCN) or silicon oxide (SiOx) series, but the embodiments of this specification are not limited thereto.

[0127] The semiconductor substrate (SSUB) can be replaced with a glass substrate or a polymer resin substrate such as polyimide. In this case, thin film transistors can be placed on the glass substrate or the polymer resin substrate. The glass substrate is a rigid substrate that cannot be bent, and the polymer resin substrate can be a flexible substrate that can be bent or curved.

[0128] The light-emitting device backplane (EBP) includes a plurality of conductive layers (ML1 to ML8), a plurality of vias (VA1 to VA9), and a plurality of interlayer insulating films (INS1 to INS9).

[0129] The first to ninth interlayer insulating films (INS1~INS9) serve to insulate the first to eighth conductive layers (ML1~ML8). The first to eighth conductive layers (ML1~ML8) serve to implement the circuit of the first subpixel (SP1) shown in FIG. 5 by connecting a plurality of contact terminals (CTE) exposed in the semiconductor backplane (SBP).

[0130] For example, the semiconductor backplane (SBP) only has first to sixth transistors (T1 to T6) formed therein, and the connection of the first to sixth transistors (T1 to T6), as well as the first capacitor (C1) and the second capacitor (C2), is made through the first to eighth conductive layers (ML1 to ML8). In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor (T4), the source region corresponding to the source electrode of the fifth transistor (T5), and the first electrode (AND) of the light-emitting element (LE) is also made through the first to eighth conductive layers (ML1 to ML8).

[0131] The first to eighth conductive layers (ML1–ML8) and the first to eighth vias (VA1–VA8) may be made of substantially the same material. The first to eighth conductive layers (ML1–ML8) and the first to eighth vias (VA1–VA8) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of these. The first to eighth vias (VA1–VA8) may be made of substantially the same material. The first to eighth interlayer insulating films (INS1–INS8) are silicon oxide (SiO2). x It may be formed with an inorganic film of the ) series, but the embodiments of this specification are not limited thereto.

[0132] The ninth interlayer insulating film (INS9) may be disposed on the eighth interlayer insulating film (INS8) and the eighth conductive layer (ML8). The ninth interlayer insulating film (INS9) is silicon oxide (SiO₂). x It may be formed with an inorganic film of the ) series, but the embodiments of this specification are not limited thereto.

[0133] Each of the ninth vias (VA9) can be connected to the eighth conductive layer (ML8) exposed through the ninth interlayer insulating film (INS9). The ninth vias (VA9) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these.

[0134] The display element layer (EML) may be disposed on the light-emitting element backplane (EBP). The display element layer (EML) may include 10th and 11th interlayer insulating films (INS10, INS11), reflective electrodes (RL), first electrodes (AND), light-emitting stack (IL), second electrode (CAT), pixel defining film (PDL), and a plurality of trenches (TRC).

[0135] Reflective electrodes (RL) may be disposed on the ninth interlayer insulating film (INS9). Each of the reflective electrodes (RL) may include at least one reflective electrode (RL1, RL2, RL3, RL4). For example, each of the reflective electrodes (RL) may include first to fourth reflective electrodes (RL1, RL2, RL3, RL4) as shown in FIG. 9.

[0136] The first reflective electrodes (RL1) are disposed on the ninth interlayer insulating film (INS9) and can be connected to the ninth via (VA9). Each of the second reflective electrodes (RL2) can be disposed on the corresponding first reflective electrode (RL1). Each of the third reflective electrodes (RL3) can be disposed on the corresponding second reflective electrode (RL2). Each of the fourth reflective electrodes (RL4) can be disposed on the corresponding third reflective electrode (RL3).

[0137] Since the second reflective electrode (RL2) is an electrode that substantially reflects light from light-emitting elements (LE), the thickness of the second reflective electrode (RL2) may be greater than the thickness of the first reflective electrode (RL1), the thickness of the third reflective electrode (RL3), and the thickness of the fourth reflective electrode (RL4).

[0138] The first reflective electrodes (RL1) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the first reflective electrodes (RL1) may contain titanium nitride (TiN), the second reflective electrodes (RL2) may contain aluminum (Al), the third reflective electrodes (RL3) may contain titanium nitride (TiN), and the fourth reflective electrodes (RL4) may contain titanium (Ti).

[0139] The 10th interlayer insulating film (INS10) may be disposed on the 9th interlayer insulating film (INS9). The 10th interlayer insulating film (INS10) may be disposed between adjacent reflective electrodes (RL). The 10th interlayer insulating film (INS10) may be a film for flattening the step difference caused by the reflective electrodes (RL). The 11th interlayer insulating film (INS11) may be disposed on the 10th interlayer insulating film (INS10) and the reflective electrodes (RL).

[0140] The 10th interlayer insulating film (INS10) and the 11th interlayer insulating film (INS11) may be formed of an inorganic film of the silicon oxide (SiOx) series, but the embodiments of this specification are not limited thereto.

[0141] The eleventh interlayer insulating film (INS11) may be an optical auxiliary layer for matching the resonance distance of light emitted from the light-emitting stack (IL) in at least one of the first subpixel (SP1), the second subpixel (SP2), and the third subpixel (SP3). The thickness of the eleventh interlayer insulating film (INS11) in the first subpixel (SP1), the second subpixel (SP2), and the third subpixel (SP3) may be different. That is, the thickness of the eleventh interlayer insulating film (INS11) in each of the first subpixel (SP1), the second subpixel (SP2), and the third subpixel (SP3) may be set to adjust the distance from the reflection electrode (RL) to the second electrode (CAT) according to the main wavelength of the light emitted in each of the first subpixel (SP1), the second subpixel (SP2), and the third subpixel (SP3).

[0142] For example, as shown in FIG. 9, the thickness of the 11th interlayer insulating film (INS11) in the first subpixel (SP1) may be greater than the thickness of the 11th interlayer insulating film (INS11) in the second subpixel (SP2), and the thickness of the 11th interlayer insulating film (INS11) in the second subpixel (SP2) may be greater than the thickness of the 11th interlayer insulating film (INS11) in the third subpixel (SP3). In this case, the distance between the first electrode (AND) and the reflective electrode (RL) in the first subpixel (SP1) may be greater than the distance between the first electrode (AND) and the reflective electrode (RL) in the second subpixel (SP2). Additionally, the distance between the first electrode (AND) and the reflective electrode (RL) in the second subpixel (SP2) may be greater than the distance between the first electrode (AND) and the reflective electrode (RL) in the third subpixel (SP3).

[0143] Each of the 10 vias (VA10) can be connected to the 4th reflective electrodes (RL4) exposed through the 11th interlayer insulating film (INS11). The 10 vias (VA10) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of these. The thickness of the 10 via (VA10) in the first subpixel (SP1) may be greater than the thickness of the 10 via (VA10) in the second subpixel (SP2), and the thickness of the 10 via (VA10) in the second subpixel (SP2) may be greater than the thickness of the 10 via (VA10) in the third subpixel (SP3).

[0144] The first electrode (AND) of each of the light-emitting elements (LE) is disposed on the 11th interlayer insulating film (INS11) and can be connected to the 10th via (VA10). The first electrode (AND) of each of the light-emitting elements (LE) can be connected to the drain region (DA) or source region (SA) of the pixel transistor (PTR) through the 10th via (VA10), the reflective electrode (RL), the 1st to 9th vias (VA1~VA9), the 1st to 8th metal layers (ML1~ML8), and the contact terminal (CTE). The first electrode (AND) of each of the light-emitting elements (LE) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of these. For example, the first electrode (AND) of each of the light-emitting elements (LE) may be titanium nitride (TiN).

[0145] A pixel defining film (PDL) may be placed on a portion of the first electrode (AND) of each of the light-emitting elements (LE). The pixel defining film (PDL) may cover the edge of the first electrode (AND) of each of the light-emitting elements (LE). The pixel defining film (PDL) may define first light-emitting regions (EA1), second light-emitting regions (EA2), and third light-emitting regions (EA3). Each of the first light-emitting region (EA1), second light-emitting region (EA2), and third light-emitting region (EA3) may be an area where a light-emitting element (LE), comprising a first electrode (AND), a light-emitting stack (IL), and a second electrode (CAT), is placed.

[0146] The first light-emitting region (EA1) can be defined as a region in which a first electrode (AND), a light-emitting stack (IL), and a second electrode (CAT) are sequentially stacked to emit light in the first subpixel (SP1). The second light-emitting region (EA2) can be defined as a region in which a first electrode (AND), a light-emitting stack (IL), and a second electrode (CAT) are sequentially stacked to emit light in the second subpixel (SP2). The third light-emitting region (EA3) can be defined as a region in which a first electrode (AND), a light-emitting stack (IL), and a second electrode (CAT) are sequentially stacked to emit light in the third subpixel (SP3).

[0147] A pixel defining film (PDL) may include first to third pixel defining films (PDL1, PDL2, PDL3). A first pixel defining film (PDL1) may be disposed on the edge of the first electrode (AND) of each of the light-emitting elements (LE), a second pixel defining film (PDL2) may be disposed on the first pixel defining film (PDL1), and a third pixel defining film (PDL3) may be disposed on the second pixel defining film (PDL2). The first pixel defining film (PDL1), the second pixel defining film (PDL2), and the third pixel defining film (PDL3) may be formed from an inorganic film of the silicon oxide (SiOx) series. Alternatively, while the first pixel defining film (PDL1) and the third pixel defining film (PDL3) are formed from an inorganic film of the silicon nitride (SiNx) series, the second pixel defining film (PDL2) may be formed from an inorganic film of the silicon oxide (SiOx) series. The thickness of the first pixel defining film (PDL1), the thickness of the second pixel defining film (PDL2), and the thickness of the third pixel defining film (PDL3) may each be approximately 500 Å.

[0148] To prevent the first encapsulation inorganic film (TFE1) from breaking due to step coverage, the first pixel defining film (PDL1), the second pixel defining film (PDL2), and the third pixel defining film (PDL3) may have a cross-sectional structure having a step-shaped step difference. Step coverage refers to the ratio of the degree to which a thin film is applied to a slanted portion to the degree to which a thin film is applied to a flat portion. The lower the step coverage, the higher the likelihood that the thin film will break in the slanted portion.

[0149] Each of the plurality of trenches (TRC) can penetrate the first pixel defining film (PDL1), the second pixel defining film (PDL2), and the third pixel defining film (PDL3). In each of the plurality of trenches (TRC), at least a portion of the eleventh interlayer insulating film (INS11) may have a recessed shape.

[0150] At least one trench (TRC) may be placed between adjacent subpixels (SP1, SP2, SP3). FIG. 9 illustrates the placement of two trenches (TRC) between adjacent subpixels (SP1, SP2, SP3), but embodiments of the present specification are not limited thereto.

[0151] The light-emitting stack (IL) may include a plurality of stack layers (IL1, IL2, IL3). FIG. 9 illustrates a light-emitting stack (IL) having a 3-tandem structure including a first stack layer (IL1), a second stack layer (IL2), and a third stack layer (IL3), but embodiments of the present specification are not limited thereto. For example, the light-emitting stack (IL) may have a 2-tandem structure including two stack layers as shown in FIG. 10.

[0152] 3. In a tandem structure, the light-emitting stack (IL) may have a tandem structure comprising a plurality of intermediate layers (IL1, IL2, IL3) that emit different light. For example, the light-emitting stack (IL) may include a first stack layer (IL1) that emits a first light, a second stack layer (IL2) that emits a second light, and a third stack layer (IL3) that emits a third light. The first stack layer (IL1), the second stack layer (IL2), and the third stack layer (IL3) may be stacked sequentially.

[0153] The first stack layer (IL1) may have a structure in which a first hole transport layer, a first light-emitting layer, and a first electron transport layer are sequentially stacked. The second stack layer (IL2) may have a structure in which a second hole transport layer, a second light-emitting layer, and a second electron transport layer are sequentially stacked. The third stack layer (IL3) may have a structure in which a third hole transport layer, a third light-emitting layer, and a third electron transport layer are sequentially stacked.

[0154] A first charge generating layer may be disposed between the first stack layer (IL1) and the second stack layer (IL2) to supply charge to the second stack layer (IL2) and to supply electrons to the first stack layer (IL1). The first charge generating layer may include an n-type charge generating layer that supplies electrons to the first stack layer (IL1) and a p-type charge generating layer that supplies holes to the second stack layer (IL2). The n-type charge generating layer may include a dopant of a metallic material.

[0155] A second charge generating layer may be disposed between the second stack layer (IL2) and the third stack layer (IL3) to supply charge to the third stack layer (IL3) and to supply electrons to the second stack layer (IL2). The second charge generating layer may include an n-type charge generating layer that supplies electrons to the second stack layer (IL2) and a p-type charge generating layer that supplies holes to the third stack layer (IL3).

[0156] A first stack layer (IL1) is disposed on the first electrodes (AND) and the pixel definition film (PDL), and the residual film (RIL) disposed on the bottom surface of each trench (TRC) may be the same material as the first stack layer (IL1). Due to the trench (TRC), the first stack layer (IL1) may be separated between adjacent subpixels (SP1, SP2, SP3). A second stack layer (IL2) may be disposed on the first stack layer (IL1). Due to the trench (TRC), the second stack layer (IL2) may be separated between adjacent subpixels (SP1, SP2, SP3). A void (ESS) or empty space may be disposed between the residual film (IL) and the second stack layer (IL2) in the trench (TRC). A third stack layer (IL3) may be disposed on the second stack layer (IL2). The third stack layer (IL3) is not interrupted by the trench (TRC) and can be positioned to cover the second stack layer (IL2) in each of the trenches (TRC).

[0157] In a 3-tandem structure, each of the plurality of trenches (TRC) may be a structure for severing the first to third hole transport layers, the first charge generation layer, and the second charge generation layer of the first to third stack layers (IL1, IL2, IL3) of the display element layer (EML) between adjacent subpixels (SP1, SP2, SP3). Additionally, in a 2-tandem structure, each of the plurality of trenches (TRC) may be a structure for severing the charge generation layer and the lower stack layer disposed between the lower stack layer and the upper stack layer.

[0158] To reliably separate the first and second stack layers (IL1, IL2) of the display element layer (EML) between adjacent subpixels (SP1, SP2, SP3), the height of each of the plurality of trenches (TRC) may be greater than the height of the pixel defining film (PDL). The height of each of the plurality of trenches (TRC) indicates the length of each of the plurality of trenches (TRC) in the third direction (DR3). The height of the pixel defining film (PDL) indicates the length of the pixel defining film (PDL) in the third direction (DR3). To separate the hole transport layers and charge generation layers of the light-emitting stack (IL) of the display element layer (EML) between adjacent subpixels (SP1, SP2, SP3), other structures may exist instead of the trenches (TRC). For example, instead of the trenches (TRC), a barrier in the form of an inverse taper may be disposed on the pixel defining film (PDL).

[0159] Additionally, FIG. 9 illustrates a light-emitting stack (IL) being disposed in all of the first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3), but the embodiments of the present specification are not limited thereto. For example, instead of the light-emitting stack (IL), a first light-emitting layer may be disposed in the first light-emitting region (EA1) and not disposed in the second light-emitting region (EA2) and the third light-emitting region (EA3). Also, a second light-emitting layer may be disposed in the second light-emitting region (EA2) and not disposed in the first light-emitting region (EA1) and the third light-emitting region (EA3). Also, a third light-emitting layer may be disposed in the third light-emitting region (EA3) and not disposed in the first light-emitting region (EA1) and the second light-emitting region (EA2). In this case, the first to third color filters (CF1, CF2, CF3) of the optical layer (OPL) may be omitted.

[0160] The second electrode (CAT) can be placed on the light-emitting stack (IL). That is, the second electrode (CAT) can be placed on the third stack layer (IL3). The second electrode (CAT) can be formed from a transparent conductive material (TCO, Transparent Conductive Material) such as ITO or IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode (CAT) is formed from a semi-transmissive conductive material, the light emission efficiency in each of the first to third subpixels (SP1, SP2, SP3) can be increased by micro-cavity.

[0161] The encapsulation layer (TFE) may be disposed on the display element layer (EML). The encapsulation layer (TFE) may include at least one inorganic film (TFE1, TFE3) to prevent oxygen or moisture from penetrating into the display element layer (EML). The first encapsulation inorganic film (TFE1) may be disposed on the second electrode (CAT), and the second encapsulation inorganic film (TFE3) may be disposed on the first encapsulation inorganic film (TFE1). The first encapsulation inorganic film (TFE1) and the second encapsulation inorganic film (TFE3) may be formed as a multilayer film in which one or more inorganic films selected from silicon nitride (SiNx), silicon oxynitride (SiON), silicon oxide (SiOx), titanium oxide (TiOx), and aluminum oxide (AlOx) are alternately stacked.

[0162] Additionally, the encapsulation layer (TFE) may include at least one organic film (TFE2) to protect the labeling element layer (EML) from foreign substances such as dust. The encapsulation organic film (TFE2) may be placed between the first encapsulation inorganic film (TFE1) and the second encapsulation inorganic film (TFE3). The encapsulation organic film (TFE2) may be a monomer. Alternatively, the encapsulation organic film (TFE2) may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0163] The adhesive layer (ADL) may be a layer for bonding the encapsulation layer (TFE) and the optical layer (OPL). The adhesive layer (ADL) may be a double-sided adhesive member. Additionally, the adhesive layer (ADL) may be a transparent adhesive member, such as a transparent adhesive or a transparent adhesive resin.

[0164] The optical layer (OPL) includes a plurality of color filters (CF1, CF2, CF3), a plurality of lenses (LNS), and a filling layer (FIL). The plurality of color filters (CF1, CF2, CF3) may include first to third color filters (CF1, CF2, CF3). The first to third color filters (CF1, CF2, CF3) may be disposed on an adhesive layer (ADL).

[0165] The first color filter (CF1) can overlap with the first light-emitting region (EA1) of the first subpixel (SP1). The first color filter (CF1) can transmit light of the first color, that is, light in the blue wavelength band. The blue wavelength band may be approximately 370 nm to 460 nm. Therefore, the first color filter (CF1) can transmit light of the first color among the light emitted from the first light-emitting region (EA1).

[0166] The second color filter (CF2) can overlap with the second light-emitting region (EA2) of the second subpixel (SP2). The second color filter (CF2) can transmit light of the second color, that is, light in the green wavelength band. The green wavelength band may be approximately 480 nm to 560 nm. Therefore, the second color filter (CF2) can transmit light of the second color among the light emitted from the second light-emitting region (EA2).

[0167] The third color filter (CF3) can overlap with the third light-emitting region (EA3) of the third subpixel (SP3). The third color filter (CF3) can transmit light of the third color, that is, light in the red wavelength band. The red wavelength band may be approximately 600 nm to 750 nm. Therefore, the third color filter (CF3) can transmit light of the third color among the light emitted from the third light-emitting region (EA3).

[0168] Each of the plurality of lenses (LNS) may be placed on the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3), respectively. Each of the plurality of lenses (LNS) may be a structure for increasing the ratio of light directed toward the front of the display device (20). Each of the plurality of lenses (LNS) may have a cross-sectional shape that is convex in the upward direction.

[0169] The filling layer (FIL) may be disposed on a plurality of lenses (LNS). The filling layer (FIL) may have a predetermined refractive index so that light travels in a third direction (DR3) at the interface between the plurality of lenses (LNS) and the filling layer (FIL). Additionally, the filling layer (FIL) may be a planarization layer. The filling layer (FIL) may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0170] The cover layer (CVL) can be placed on the fill layer (FIL). The cover layer (CVL) can be a glass substrate or a polymer resin such as resin. If the cover layer (CVL) is a glass substrate, it can be attached to the fill layer (FIL). In this case, the fill layer (FIL) can serve to adhere the cover layer (CVL). If the cover layer (CVL) is a glass substrate, it can serve as an encapsulation substrate. If the cover layer (CVL) is a polymer resin such as resin, it can be applied directly onto the fill layer (FIL).

[0171] A polarizer may be disposed on one side of a cover layer (CVL). The polarizer may be a structure for preventing a decrease in visibility due to external light reflection. The polarizer may include a linear polarizer and a phase delay film. For example, the phase delay film may be a quarter-wave plate, but the embodiments of this specification are not limited thereto. However, if visibility due to external light reflection is sufficiently improved by the first to third color filters (CF1, CF2, CF3), the polarizer may be omitted.

[0172] FIG. 10 is a schematic cross-sectional view illustrating another example of a display panel obtained along the line I1-I1' shown in FIG. 7.

[0173] The embodiment of FIG. 10 differs from the embodiment of FIG. 9 in that the first electrode (AND) of each of the light-emitting elements (LE) is electrically connected by contacting the side of the connecting electrode (ANC) connected to the eighth conductive layer (ML8). Additionally, the embodiment of FIG. 10 differs from the embodiment of FIG. 9 in that the trench (TRC) is omitted, and instead, the third pixel defining film (PDL3) and the fourth pixel defining film (PDL4) have an eaves-shaped or mushroom-shaped cross-sectional structure. In the embodiment of FIG. 10, descriptions that overlap with the embodiment of FIG. 9 are omitted.

[0174] Referring to FIG. 10, a plurality of connecting electrodes (ANCs) may each be disposed on first portions (AA1) of the ninth interlayer insulating film (INS9). Each of the plurality of connecting electrodes (ANCs) may be disposed on the corresponding first portion (AA1) of the ninth interlayer insulating film (INS9). The plurality of connecting electrodes (ANCs) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), an alloy comprising any one of these, or a transparent conductive oxide. For example, the plurality of connecting electrodes (ANCs) may include titanium (Ti), titanium nitride (TiN), ITO (Indium Tin Oxide), or IZO (Indium Zinc Oxide), but the embodiments of this specification are not limited thereto.

[0175] A plurality of reflective electrodes (RL) may each be placed on a plurality of connecting electrodes (ANC). Each of the plurality of reflective electrodes (RL) may be placed on a corresponding connecting electrode (ANC). The plurality of reflective electrodes (RL) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, each of the plurality of reflective electrodes (RL) may include aluminum (Al), which has a high reflectivity.

[0176] A plurality of optical auxiliary films (OALs) may each be disposed on a plurality of reflective electrodes (RL). Each of the plurality of optical auxiliary films (OALs) may be disposed on a corresponding reflective electrode (RL). The plurality of optical auxiliary films (OALs) may be formed of inorganic films of the silicon oxide (SiOx) series, but the embodiments of this specification are not limited thereto.

[0177] A step layer (STPL) is disposed on a reflective electrode (RL) in each of the first light-emitting region (EA1) and the third light-emitting region (EA3), and an optical auxiliary film (OAL) may be disposed on the step layer (STPL). In the second light-emitting region (EA2), only an optical auxiliary film (OAL) may be disposed on the reflective electrode (RL). The thickness of the optical auxiliary film (OAL) in the first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) may be substantially the same.

[0178] Due to the step layer (STPL), the distance between the reflective electrode (RL) and the first electrode (AND) in the first light-emitting region (EA1) and the third light-emitting region (EA3) may be greater than the distance between the reflective electrode (RL) and the first electrode (AND) in the second light-emitting region (EA2). The thickness of the step layer (STPL) and the thickness of the optical auxiliary film (OAL) can be set by considering the wavelength and resonance distance of the light emitted from the first stack layer (IL1) of the light-emitting stack (IL), and the wavelength and resonance distance of the light emitted from the second stack layer (IL2).

[0179] Each of the light-emitting elements (LE) may include a first electrode (AND), a light-emitting stack (IL), and a second electrode (CAT).

[0180] The first electrode (AND) of each light-emitting element (LE) can be placed on the corresponding optical auxiliary film (OAL). Since the connecting electrode (ANC), the reflective electrode (RL), and the optical auxiliary film (OAL) are stacked sequentially, the first electrode (AND) of each light-emitting element (LE) can be placed on the upper and side surfaces of the optical auxiliary film (OAL), the side surface of the reflective electrode (RL), and the side surface of the connecting electrode (ANC). As a result, the first electrode (AND) of each light-emitting element (LE) can be electrically connected by contacting the side surface of the reflective electrode (RL) and the side surface of the connecting electrode (ANC). Therefore, compared to when the first electrode (AND) of each light-emitting element (LE) is connected to the reflective electrode (RL) exposed through a through hole penetrating the optical auxiliary film (OAL), the number of mask processes can be reduced, which has the advantage of reducing manufacturing costs and increasing manufacturing efficiency.

[0181] The first electrode (AND) of each of the light-emitting elements (LE) can be connected to the drain region (DA) or source region (SA) of the pixel transistor (PTR) through the connection electrode (ANC), the first to ninth vias (VA1 to VA9), the first to eighth conductive layers (ML1 to ML8), and the contact terminal (CTE).

[0182] The ninth interlayer insulating film (INS9) may include a first portion (AA1) that overlaps with the connecting electrode (ANC) in the third direction (DR3) and a second portion (AA2) that does not overlap with the connecting electrode (ANC) in the third direction (DR3). The thickness of the first portion (AA1) and the thickness of the second portion (AA2) of the ninth interlayer insulating film (INS9) may be substantially the same.

[0183] Alternatively, the thickness of the first portion (AA1) of the ninth interlayer insulating film (INS9) may be greater than the thickness of the second portion (AA2). In this case, the side of the first portion (AA1) of the ninth interlayer insulating film (INS9) is exposed, and the first electrode (AND) of each of the light-emitting elements (LE) may be placed on the exposed side of the first portion (AA1) of the ninth interlayer insulating film (INS9).

[0184] The first electrode (AND) of each of the light-emitting elements (LE) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of these, or a transparent conductive oxide. For example, the first electrode (AND) of each of the light-emitting elements (LE) may include titanium nitride (TiN), ITO (Indium Tin Oxide), or IZO (Indium Zinc Oxide), but the embodiments of this specification are not limited thereto.

[0185] A pixel defining film (PDL) may be placed on a portion of the first electrode (AND) of each of the light-emitting elements (LE). The pixel defining film (PDL) may cover the edge of the first electrode (AND) of each of the light-emitting elements (LE). The pixel defining film (PDL) may define first light-emitting regions (EA1), second light-emitting regions (EA2), and third light-emitting regions (EA3).

[0186] The pixel defining layer (PDL) may include first to fourth pixel defining layers (PDL1, PDL2, PDL3, PDL4).

[0187] The first pixel defining film (PDL1) may be disposed on the first electrode (AND) of each of the light-emitting elements (LE). Specifically, the first pixel defining film (PDL1) may cover a portion of the upper surface of the first electrode (AND) disposed on the optical auxiliary film (OAL). Additionally, the first pixel defining film (PDL1) may cover the first electrode (AND) disposed on the side of the connecting electrode (ANC), the side of the reflective electrode (RL), and the side of the optical auxiliary film (OAL). The first pixel defining film (PDL1) may be disposed on the upper surface of the second portion (AA2) of the ninth interlayer insulating film (INS9).

[0188] The planarization film (PNS) is a film for planarizing the step difference caused by the connecting electrode (ANC), the reflective electrode (RL), and the optical auxiliary film (OAL).

[0189] A planarization film (PNS) may be disposed on a first pixel defining film (PDL1) covering a first electrode (AND) disposed on the side of the connecting electrode (ANC), the side of the reflective electrode (RL), and the side of the optical auxiliary film (OAL). A planarization film (PNS) may be disposed on a first pixel defining film (PDL1) disposed on a second portion (AA2) of the ninth interlayer insulating film (INS9).

[0190] A planarization film (PNS) may be placed between adjacent connecting electrodes (ANC) in a first direction (DR1) or a second direction (DR2). A planarization film (PNS) may be placed between adjacent reflecting electrodes (RL) in a first direction (DR1) or a second direction (DR2). A planarization film (PNS) may be placed between adjacent optical auxiliary films (OAL) in a first direction (DR1) or a second direction (DR2).

[0191] While the step layer (STPL) does not exist in the second light-emitting region (EA2), the step layer (STPL) exists in each of the first light-emitting region (EA1) and the third light-emitting region (EA3). As a result, the height of the connecting electrode (ANC), the reflective electrode (RL), and the optical auxiliary film (OAL) in the second light-emitting region (EA2) may be smaller than the height of the connecting electrode (ANC), the reflective electrode (RL), the step layer (STPL), and the optical auxiliary film (OAL) in each of the first light-emitting region (EA1) and the third light-emitting region (EA3). Therefore, the planarization film (PNS) can cover the upper surface of the first pixel defining film (PDL1) disposed on the upper surface of the first electrode (AND) disposed in the second light-emitting region (EA2).

[0192] In contrast, the upper surface of the planarization film (PNS) can be flatly connected to the upper surface of the first pixel defining film (PDL1) disposed on the upper surface of the first electrode (AND) disposed in the first light-emitting region (EA1) and the third light-emitting region (EA3). That is, the planarization film (PNS) may not cover the upper surface of the first pixel defining film (PDL1) disposed on the upper surface of the first electrode (AND) disposed in each of the first light-emitting region (EA1) and the third light-emitting region (EA3).

[0193] A second pixel defining film (PDL2) may be placed on the first pixel defining film (PDL1) and the planarization film (PNS), a third pixel defining film (PDL3) may be placed on the second pixel defining film (PDL2), and a fourth pixel defining film (PDL4) may be placed on the third pixel defining film (PDL3). While the first pixel defining film (PDL1) and the third pixel defining film (PDL3) are formed from silicon nitride (SiNx) series inorganic films, the second pixel defining film (PDL2), the fourth pixel defining film (PDL4), and the planarization film (PNS) may be formed from silicon oxide (SiOx) series inorganic films. Since the first pixel defining film (PDL1) is formed from a material different from the planarization film (PNS), it can act as a stopper in the chemical mechanical polishing process of the planarization film (PNS).

[0194] When the planarization film (PNS) and the second pixel defining film (PDL2) are formed identically as silicon oxide (SiOx) series inorganic films, the planarization film (PNS) and the second pixel defining film (PDL2) can be formed as a single film.

[0195] Since the length of one direction of the third pixel defining film (PDL3) is smaller than the length of one direction of the fourth pixel defining film (PDL4), the lower surface of the fourth pixel defining film (PDL4) can be exposed without being covered by the third pixel defining film (PDL3). That is, the third pixel defining film (PDL3) and the fourth pixel defining film (PDL4) can have an eaves-shaped or mushroom-shaped cross-sectional structure.

[0196] A light-emitting stack (IL) may be disposed on a first electrode (AND) and a pixel definition film (PDL). The light-emitting stack (IL) may include a first stack layer (IL1) and a second stack layer (IL2) that emit different light. When the light-emitting stack (IL) has a 2-tandem structure, either the first stack layer (IL1) or the second stack layer (IL2) may emit light that includes a wavelength range of any one of the first light, the second light, and the third light, and the other may emit light that includes a wavelength range of the other two lights. For example, the first stack layer (IL1) may emit light that includes a wavelength range of the first light and a wavelength range of the third light, and the second stack layer (IL2) may emit light that includes a wavelength range of the second light. Here, the first light may be light in the blue wavelength band, the second light may be light in the green wavelength band, and the third light may be light in the red wavelength band.

[0197] A charge generation layer may be disposed between the first stack layer (IL1) and the second stack layer (IL2) to supply charge to the second stack layer (IL2) and to supply electrons to the first stack layer (IL1). The charge generation layer may include an n-type charge generation layer that supplies electrons to the first stack layer (IL1) and a p-type charge generation layer that supplies holes to the second stack layer (IL2). The n-type charge generation layer may include a dopant of a metallic material.

[0198] Since the first stack layer (IL1) is not covered by the third pixel defining film (PDL3) and cannot be formed on the lower surface of the exposed fourth pixel defining film (PDL4), it may be broken by an eaves-shaped or mushroom-shaped cross-sectional structure formed by the third pixel defining film (PDL3) and the fourth pixel defining film (PDL4). In this case, the first hole transport layer of the first stack layer (IL1) and the charge generation layer disposed between the first stack layer (IL1) and the second stack layer (IL2) may also be broken. Additionally, although FIG. 10 illustrates the second stack layer (IL2) being connected without being broken, the second hole transport layer of the second stack layer (IL2) may be broken, while the second electron transport layer of the second stack layer (IL2) may be connected without being broken. Therefore, it is possible to prevent leakage current from flowing through the first hole transport layer of the first stack layer (IL1), the second hole transport layer of the second stack layer (IL2), and the charge generation layer between adjacent light-emitting regions (EA1, EA2, EA3). Thus, it is possible to prevent the light-emitting stack (IL) in the adjacent light-emitting regions (EA1, EA2, EA3) from being affected by the current and emitting light other than the originally intended light.

[0199] FIG. 10 illustrates a 2-tandem structure in which the light-emitting stack (IL) includes two stack layers (IL1, IL2), but the embodiments of this specification are not limited thereto. For example, the light-emitting stack (IL) may have a 3-tandem structure including three stack layers as shown in FIG. 9. In this case, the height of the third pixel defining layer (PDL3) may be adjusted so that the charge generating layer between the first stack layer (IL1) and the second stack layer (IL2), and the charge generating layer between the second stack layer (IL2) and the third stack layer (IL3) are separated. Alternatively, a trench (TRC) penetrating the first pixel defining layer (PDL1), the second pixel defining layer (PDL2), and the third pixel defining layer (PDL3) may be added as shown in FIG. 9. In this case, the trench (TRC) may penetrate at least a portion of the ninth interlayer insulating layer (INS9), but the embodiments of this specification are not limited thereto.

[0200] FIG. 11 is a schematic cross-sectional view to illustrate another example of a display panel obtained along the line I1-I1' shown in FIG. 7.

[0201] The embodiment of FIG. 11 differs from the embodiment of FIG. 10 in that the light-emitting elements (LE) have a single stack structure. In the embodiment of FIG. 11, descriptions that overlap with the embodiment of FIG. 10 are omitted.

[0202] Referring to FIG. 11, a pixel defining film (PDL) may be disposed on the ninth interlayer insulating film (INS9) and the first electrodes (AND), and a planarization film (PNS) may be disposed on the pixel defining film (PDL). The planarization film (PNS) and the pixel defining film (PDL) may have openings that expose the first electrodes (AND), and light-emitting layers (IL) may be disposed on the first electrodes (AND). For example, the pixel defining film (PDL) may have openings that expose the first electrodes (AND) in a first light-emitting region (EA1), a second light-emitting region (EA2), and a third light-emitting region (EA3), and the planarization film (PNS) may have openings that expose the first electrode (AND) in the second light-emitting region (EA2).

[0203] The first light-emitting layer (IL1_1) may be disposed on the first electrode (AND) exposed by the pixel defining film (PDL) in the first light-emitting region (EA1). The first light-emitting layer (IL1_1) may also be disposed on a portion of the pixel defining film (PDL).

[0204] The second light-emitting layer (IL1_2) may be disposed on the first electrode (AND) exposed by the planarization film (PNS) and the pixel definition film (PDL) in the second light-emitting region (EA2). The second light-emitting layer (IL1_2) may also be disposed on a portion of the planarization film (PNS).

[0205] The third light-emitting layer (IL1_3) may be disposed on the first electrode (AND) exposed by the pixel defining film (PDL) in the third light-emitting region (EA3). The third light-emitting layer (IL1_3) may also be disposed on a portion of the pixel defining film (PDL).

[0206] The first light-emitting layer (IL1_1), the second light-emitting layer (IL1_2), and the third light-emitting layer (IL1_3) may be spaced apart from each other, and accordingly, the second to fourth pixel defining layers (PDL2, PDL3, PDL4) used to break the light-emitting stack (IL) in the embodiment of FIG. 10 may be omitted.

[0207] The first light-emitting layer (IL1_1) of the first light-emitting region (EA1) emits a first light, the second light-emitting layer (IL1_2) of the second light-emitting region (EA2) emits a second light, and the third light-emitting layer (IL1_3) of the third light-emitting region (EA3) emits a third light. Accordingly, the first to third color filters (CF1, CF2, CF3) of the optical layer (OPL) used in the embodiment of FIG. 9, the plurality of lenses (LNS), and the filling layer (FIL) may be omitted.

[0208] FIG. 12 is a schematic perspective view illustrating an example of a head-mounted display device. FIG. 13 is a schematic exploded perspective view illustrating the head-mounted display device shown in FIG. 12.

[0209] Referring to FIGS. 12 and 13, a head-mounted display device (1000) according to one embodiment includes a first display device (20_1), a second display device (20_2), a display device storage unit (1100), a storage unit cover (1200), a first eyepiece (1210), a second eyepiece (1220), a head-mounted band (1300), a middle frame (1400), a first optical member (1510), a second optical member (1520), and a control circuit board (1600).

[0210] The first display device (20_1) provides an image to the user's left eye, and the second display device (20_2) provides an image to the user's right eye. Since the first display device (20_1) and the second display device (20_2) are substantially identical to the display device (20) described in conjunction with FIGS. 3 to 11, the description of the first display device (20_1) and the second display device (20_2) is omitted.

[0211] The first optical member (1510) may be positioned between the first display device (20_1) and the first eyepiece (1210). The second optical member (1520) may be positioned between the second display device (20_2) and the second eyepiece (1220). Each of the first optical member (1510) and the second optical member (1520) may include at least one convex lens.

[0212] The middle frame (1400) is positioned between the first display device (20_1) and the control circuit board (1600), and may be positioned between the second display device (20_2) and the control circuit board (1600). The middle frame (1400) serves to support and fix the first display device (20_1), the second display device (20_2), and the control circuit board (1600).

[0213] The control circuit board (1600) may be placed between the middle frame (1400) and the display device housing (1100). The control circuit board (1600) may be connected to the first display device (20_1) and the second display device (20_2) through a connector. The control circuit board (1600) may convert an image source input from the outside into digital video data (DATA) and transmit the digital video data (DATA) to the first display device (20_1) and the second display device (20_2) through the connector.

[0214] The control circuit board (1600) can transmit digital video data (DATA) corresponding to a left-eye image optimized for the user's left eye to the first display device (20_1) and digital video data (DATA) corresponding to a right-eye image optimized for the user's right eye to the second display device (20_2). Alternatively, the control circuit board (1600) can transmit the same digital video data (DATA) to the first display device (20_1) and the second display device (20_2).

[0215] The display device housing (1100) serves to house a first display device (20_1), a second display device (20_2), a middle frame (1400), a first optical member (1510), a second optical member (1520), and a control circuit board (1600). The housing cover (1200) is positioned to cover an open side of the display device housing (1100). The housing cover (1200) may include a first eyepiece (1210) in which the user's left eye is positioned and a second eyepiece (1220) in which the user's right eye is positioned. Although FIGS. 12 and 13 illustrate the first eyepiece (1210) and the second eyepiece (1220) being positioned separately, the embodiments of this specification are not limited thereto. The first eyepiece (1210) and the second eyepiece (1220) may be combined into one.

[0216] The first eyepiece (1210) is aligned with the first display device (20_1) and the first optical member (1510), and the second eyepiece (1220) can be aligned with the second display device (20_2) and the second optical member (1520). Accordingly, the user can view an image of the first display device (20_1) magnified into a virtual image by the first optical member (1510) through the first eyepiece (1210), and can view an image of the second display device (20_2) magnified into a virtual image by the second optical member (1520) through the second eyepiece (1220).

[0217] The head mounting band (1300) serves to secure the display device storage unit (1100) to the user's head so that the first eyepiece (1210) and the second eyepiece (1220) of the storage unit cover (1200) can be positioned on the user's left and right eyes, respectively. When the display device storage unit (1200) is implemented as a lightweight and compact unit, the head-mounted display device (1000) may be equipped with an eyeglass frame instead of the head mounting band (1300), as shown in FIG. 14.

[0218] FIG. 14 is a schematic perspective view illustrating another example of a head-mounted display device.

[0219] Referring to FIG. 14, a head-mounted display device (1000_1) according to one embodiment may be a display device in the form of glasses in which a display device housing (1200_1) is implemented in a lightweight and compact manner. A head-mounted display device (1000_1) according to one embodiment may include a display device (20_3), a left eye lens (1010), a right eye lens (1020), a support frame (1030), temples (1040, 1050), an optical member (1600), an optical path conversion member (1070), and a display device housing (1200_1).

[0220] The display device housing (1200_1) may include a display device (20_3), an optical member (1600), and an optical path conversion member (1070). An image displayed on the display device (20_3) may be magnified by the optical member (1600), and the optical path may be converted by the optical path conversion member (1070) and provided to the user's right eye through the right eye lens (1020). As a result, the user can view an augmented reality image in which a virtual image displayed on the display device (20_3) and a real image seen through the right eye lens (1020) are combined.

[0221] FIG. 14 illustrates that the display device housing (1200_1) is positioned at the right end of the support frame (1030), but the embodiments of the present specification are not limited thereto. For example, the display device housing (1200_1) may be positioned at the left end of the support frame (1030), in which case the image of the display device (20_3) may be provided to the user's left eye. Alternatively, the display device housing (1200_1) may be positioned at both the left and right ends of the support frame (1030), in which case the user may view the image displayed on the display device (20_3) through both the left and right eyes.

[0222] FIG. 15 is a schematic diagram illustrating a deposition mask and a deposition apparatus including the same according to one embodiment.

[0223] Referring to FIG. 15, a deposition apparatus (2000) according to one embodiment may be used to form a deposition material layer on a substrate (3000). For example, a deposition apparatus (2000) according to one embodiment may be used to form light-emitting layers on a backplane substrate (3000) (or a display substrate) in a manufacturing process of a display panel (100; see FIG. 3). For example, as shown in FIG. 11, a semiconductor backplane (SBP) and a light-emitting element backplane (EBP) may be disposed on the backplane substrate (3000), and electrode patterns, for example, first electrodes (AND) functioning as anode electrodes, may be disposed on the light-emitting element backplane (EBP). Additionally, a pixel defining film (PDL) having openings that expose the first electrodes (AND) may be disposed on the light-emitting element backplane (EBP). As an example, the deposition apparatus (2000) can form first light-emitting layers (IL1_1) on the first electrodes (AND) of the first light-emitting regions (EA1). As another example, the deposition apparatus (2000) can form second light-emitting layers (IL1_2) on the first electrodes (AND) of the second light-emitting regions (EA2). As yet another example, the deposition apparatus (2000) can form third light-emitting layers (IL1_3) on the first electrodes (AND) of the third light-emitting regions (EA3).

[0224] A deposition apparatus (2000) may include a deposition source (2200) for providing a deposition material in a gaseous phase on a backplane substrate (3000), a substrate chuck (2300) for supporting the backplane substrate (3000) toward the deposition source (2200), and a mask chuck (2400) disposed between the deposition source (2200) and the substrate chuck (2300) for supporting a deposition mask (4000) toward the backplane substrate (3000). The deposition source (2200), the substrate chuck (2300), and the mask chuck (2400) may be disposed within a process chamber (or evaporation chamber) (2100).

[0225] The process chamber (2100) may have an internal space, and a deposition process for forming a deposition material layer on a backplane substrate (3000) may be performed in the internal space of the process chamber (2100). The process chamber (2100) may be connected to a vacuum pump (not shown), and the internal space of the process chamber (2100) may be created into a vacuum atmosphere by the vacuum pump. An opening (not shown) for the entry and exit of the backplane substrate (3000) and the deposition mask (4000) may be provided on one side wall of the process chamber (2100), and the opening may be opened and closed by a gate valve (not shown).

[0226] A deposition source (2200) may be placed inside a process chamber (2100), and a deposition material may be contained within the deposition source (2200). The deposition source (2200) may evaporate a deposition material, such as an organic material, an inorganic material, a conductive material, etc., toward a backplane substrate (3000), and the evaporated deposition material may be deposited on the backplane substrate (3000) through a deposition mask (4000). For example, the deposition source (2200) may evaporate an organic light-emitting material to form light-emitting layers on the backplane substrate (3000), and may be equipped with a heater (not shown) for evaporating the organic light-emitting material. The evaporated organic light-emitting material may be deposited on electrode patterns on the backplane substrate (3000) through the deposition mask (4000), thereby forming light-emitting layers on the electrode patterns of the backplane substrate (3000). As illustrated in FIG. 15, the deposition source (2200) is positioned on the central portion of the bottom surface of the process chamber (2100), but alternatively, the deposition source (2200) may be configured to be movable in a horizontal direction by a separate driving unit (not shown).

[0227] A substrate chuck (2300) may be positioned above a deposition source (2200) and may support the backplane substrate (3000) so that the backplane substrate (3000) faces the deposition source (2200). For example, the substrate chuck (2300) may be an electrostatic chuck that grips the rear surface of the backplane substrate (3000) using electrostatic force. Specifically, electrode patterns, for example, first electrodes (AND), may be arranged on the front surface of the backplane substrate (3000), and the substrate chuck (2300) may grip the rear surface of the backplane substrate (3000) so that the front surface of the backplane substrate (3000) faces downward, i.e., toward the deposition source (2200).

[0228] A plurality of lift fingers (2350) for loading a backplane substrate (3000) onto a substrate chuck (2300) may be disposed within the process chamber (2100). The lift fingers (2350) may be disposed around the substrate chuck (2300) and the mask chuck (2400) and each may be moved in a vertical direction by finger drivers (2360). For example, three or four lift fingers (2350) may be disposed around the substrate chuck (2300) and the mask chuck (2400) and may be moved in a third direction (DR3) by finger drivers (2350).

[0229] The backplane substrate (3000) can be brought into the interior of the process chamber (2100) by a transfer robot (not shown) and transferred from the transfer robot onto the lift fingers (2350) from below the substrate chuck (2300). At this time, the rear surface of the backplane substrate (3000) may face the lower surface of the substrate chuck (2300), and the lift fingers (2350) may support the front edge portions of the backplane substrate (3000). The finger driving units (2360) may raise the lift fingers (2350) so that the backplane substrate (3000) is adjacent to the lower surface of the substrate chuck (2300), and the rear surface of the backplane substrate (3000) may be gripped on the lower surface of the substrate chuck (2300) by electrostatic force.

[0230] Each of the finger drivers (2360) may be positioned on the upper lid of the process chamber (2100) and may be connected to each of the lift fingers (2350) via drive axes (2362) extending vertically through the upper lid of the process chamber (2100). The finger drivers (2360) may move the lift fingers (2350) vertically to load or unload the backplane substrate (3000). Additionally, the finger drivers (2360) may rotate the lift fingers (2350) with respect to each of the drive axes (2362). For example, the finger driving units (2360) can rotate the lift fingers (2350) so that the ends of the lift fingers (2350) do not overlap with the substrate chuck (2300) and the mask chuck (2400), thereby enabling vertical movement of the lift fingers (2350). Additionally, the finger driving units (2360) can rotate the lift fingers (2350) so that the ends of the lift fingers (2250) overlap with the edge portions of the backplane substrate (3000) in order to support the edge portions of the backplane substrate (3000).

[0231] A deposition mask (4000) can be brought into the interior of a process chamber (2100) by a transfer robot and transferred onto lift fingers (2350) from the top of a mask chuck (2400). Edge portions of the deposition mask (4000) can be placed on the ends of the lift fingers (2350), and finger drivers (2360) can lower the lift fingers (2350) to load the deposition mask (4000) onto the mask chuck (2300). In this case, the edge portions of the mask chuck (2400) may be provided with recesses (not shown) into which the ends of the lift fingers (2350) are inserted, and the finger driving units (2360) may rotate the lift fingers (2350) so that the lift fingers (2350) do not overlap with the mask chuck (2400) after the deposition mask (4000) is loaded onto the mask chuck (2400).

[0232] The mask chuck (2400) can support the edge portion of the deposition mask (4000). For example, the mask chuck (2400) may be an electrostatic chuck that grips the edge portion of the deposition mask (4000) using electrostatic force. In particular, the mask chuck (2400) may have a circular opening so that the deposition mask (4000) is exposed toward the deposition source (2200). For example, the mask chuck (2400) may have a disc shape or a square plate shape having a circular opening.

[0233] The deposition apparatus (2000) may include a chuck drive unit for controlling the position and orientation of a backplane substrate (3000) and a deposition mask (4000). For example, the deposition apparatus (2000) may include a substrate chuck drive unit (2500) for moving a substrate chuck (2300) and a mask chuck drive unit (2600) for moving a mask chuck (2400).

[0234] The substrate chuck drive unit (2500) can move the substrate chuck (2300) in a first direction (DR1), a second direction (DR2), and a third direction (DR3) to adjust the position of the backplane substrate (3000). In this case, the first direction (DR1) may be a first horizontal direction, the second direction (DR2) may be a second horizontal direction perpendicular to the first direction (DR1), and the third direction (DR3) may be a vertical direction. For example, the first direction (DR1), the second direction (DR2), and the third direction (DR3) may be the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively.

[0235] The substrate chuck drive unit (2500) can rotate the substrate chuck (2300) around the Z-axis to adjust the azimuth angle of the backplane substrate (3000), that is, the angle at which the backplane substrate (3000) is gripped on the lower surface of the substrate chuck (2300). In addition, to adjust the tilt of the backplane substrate (3000), the substrate chuck drive unit (2500) can rotate the substrate chuck (2300) around the X-axis and can also rotate the substrate chuck (2300) around the Y-axis. For example, the substrate chuck drive unit (2500) may include a hexapod actuator (2510) that provides 6 degrees of freedom (X, Y, Z, θx, θy, and θz) motion.

[0236] The substrate chuck drive unit (2500) may include a substrate stage (2520) on which a hexapod actuator (2510) is mounted, and a second actuator (2530) connected to the substrate stage (2520). The substrate stage (2520) may be positioned horizontally within the process chamber (2100), and the second actuator (2530) may be positioned on the upper part of the process chamber (2100). The second actuator (2530) may be connected to the substrate stage (2520) by a plurality of drive axes (2532) extending in a third direction (DR3), i.e., a vertical direction (Z-axis direction), through the upper lid of the process chamber (2100), and may move the substrate stage (2520) in the direction of the central axis of the hexapod actuator (2510), i.e., a vertical direction. For example, the second actuator (2530) can be configured using a brushless DC motor, a linear motor, a DD (direct drive) motor, etc., and can adjust the height of the substrate chuck (2300) for loading or unloading the backplane substrate (3000).

[0237] The hexapod actuator (2510) may include a first platform connected to a substrate chuck (2300), a second platform mounted on a substrate stage (2520), and six sub-actors positioned between the first platform and the second platform. For example, the six sub-actors may each be configured using a brushless DC motor, a voice coil linear motor, a stepper motor, a DD (direct drive) motor, a servo motor, etc., and may move and rotate the first platform to adjust the horizontal position, vertical position, azimuth, and tilt of the backplane substrate (3000).

[0238] The mask chuck drive unit (2600) can move and rotate the mask chuck (2400) to adjust the horizontal position of the deposition mask (4000) and the azimuth angle of the deposition mask (4000), that is, the angle at which the deposition mask (4000) is placed on the mask chuck (2400). The mask chuck drive unit (2600) can move the mask chuck (2400) in a direction parallel to the deposition mask (4000) and rotate the mask chuck (2400) around the central axis of the mask chuck (2400). For example, the mask chuck drive unit (2600) can move the mask chuck (2400) in a first direction (DR1) (X-axis) and a second direction (DR2) (Y-axis), and can rotate the mask chuck (2400) around a third direction (DR3) (Z-axis).

[0239] The mask chuck drive unit (2600) may include, as an example, a piezo actuator (2610) that provides three degrees of freedom (X, Y and θz) motion. The piezo actuator (2610) may have an opening communicating with a circular opening of the mask chuck (2400). The mask chuck (2400) may be positioned so as to be spaced upward from the piezo actuator (2610) by a predetermined distance. For example, a plurality of support members (2612) may be positioned on the piezo actuator (2610), and the mask chuck (2400) may be positioned on the plurality of support members (2612).

[0240] The mask chuck drive unit (2600) may include a mask stage (2620) that is horizontally positioned within the process chamber (2100) and supports a piezo actuator (2610). For example, the mask stage (2620) may have an opening communicating with the opening of the piezo actuator (2610) and may be supported by a plurality of posts (2622) connected to the upper lead of the process chamber (2100).

[0241] After the backplane substrate (3000) and the deposition mask (4000) are loaded onto the substrate chuck (2300) and the mask chuck (2400), respectively, the second actuator (2530) can lower the substrate chuck (2300) so that the backplane substrate (3000) is adjacent to the deposition mask (4000). The hexapod actuator (2510) can adjust the gap between the backplane substrate (3000) and the deposition mask (4000), and can adjust the tilt of the substrate chuck (2300) to adjust the parallelism between the substrate chuck (2300) and the mask chuck (2400). For example, although not illustrated, a plurality of gap sensors (not illustrated) for measuring the gap between the substrate chuck (2300) and the mask chuck (2400) may be mounted on the substrate chuck (2300), and the hexapod actuator (2510) may adjust the parallelism between the substrate chuck (2300) and the mask chuck (2400) based on the measurements of the gap sensors.

[0242] The deposition apparatus (2000) may include cameras (2700) for acquiring position information of the backplane substrate (3000) and the deposition mask (4000) for alignment between the backplane substrate (3000) and the deposition mask (4000). For example, substrate alignment keys (3100; see FIG. 16) may be placed on edge portions of the backplane substrate (3000), and mask alignment keys (4600; see FIG. 17) may be placed on edge portions of the deposition mask (4000). The deposition apparatus (2000) may include cameras (2700) for detecting substrate alignment keys (3100) and mask alignment keys (4600), and the substrate chuck driving unit (2500) or the mask chuck driving unit (2600) may align the backplane substrate (3000) and the deposition mask (4000) with each other based on the position information of the substrate alignment keys (3100) and the mask alignment keys (4600) obtained by the cameras (2700).

[0243] As described above, after the parallelism between the substrate chuck (2300) and the mask chuck (2400) and the position alignment between the backplane substrate (3000) and the deposition mask (4000) are performed, the backplane substrate (3000) can be positioned on the deposition mask (4000). For example, the hexapod actuator (2510) can adjust the height of the substrate chuck (2300) so that the gap between the backplane substrate (3000) and the deposition mask (4000) is a preset gap, for example, a gap of several μm. As another example, the hexapod actuator (2510) can adjust the height of the substrate chuck (2300) so that the backplane substrate (3000) comes into contact with the deposition mask (4000).

[0244] After the backplane substrate (3000) is positioned on the deposition mask (4000), the deposition source (2200) may provide a deposition material in gaseous form onto the backplane substrate (3000) through the deposition mask (4000), thereby forming a deposition material layer on the backplane substrate (3000). For example, the deposition source (2200) may provide a emitting material in gaseous form to form emitting layers on the backplane substrate (3000), and the emitting material in gaseous form may be deposited on the electrode patterns of the backplane substrate (3000) through the pixel openings (4212; see FIG. 18) of the deposition mask (4000).

[0245] FIG. 16 is a schematic bottom view illustrating the backplane substrate shown in FIG. 15.

[0246] Referring to FIG. 16, the backplane substrate (3000) may include a plurality of display cell regions (3010) and scribe lane regions (3020) disposed between the display cell regions (3010). The display cell regions (3010) may be arranged in a matrix form along a first direction (DR1) and a second direction (DR2) as shown in FIG. 16, and may be individualized into display panels (100; see FIG. 3) through a dicing process after the display manufacturing process is completed. For example, the first direction (DR1) may be a first horizontal direction, and the second direction (DR2) may be a second horizontal direction perpendicular to the first direction (DR1). Additionally, each of the display cell regions (3010) may have a rectangular shape as shown as an example.

[0247] For example, each of the display cell regions (3010) may include a semiconductor backplane (SBP) and a light-emitting element backplane (EBP) disposed on the semiconductor backplane (SBP), as illustrated in FIG. 11. Additionally, a plurality of electrode patterns, for example, a plurality of first electrodes (AND), may be disposed on the light-emitting element backplane (EBP), and a pixel defining film (PDL) having openings that expose the first electrodes (AND) may be disposed on the light-emitting element backplane (EBP) and the first electrodes (AND). At this time, the electrode patterns of the display cell regions (3010) may be disposed on the front surface of the backplane substrate (3000), and the substrate chuck (2300) may hold the rear surface of the backplane substrate (3000) so that the electrode patterns of the display cell regions (3010) face downward, that is, toward the deposition source (2200).

[0248] FIG. 17 is a schematic plan view illustrating the deposition mask illustrated in FIG. 15. FIG. 18 is a schematic enlarged plan view illustrating the mask cell regions illustrated in FIG. 17. FIG. 19 is a schematic cross-sectional view obtained along the line I2-I2' illustrated in FIG. 18.

[0249] Referring to FIGS. 17 to 19, the deposition mask (4000) may include mask cell regions (4210) corresponding to display cell regions (3010) of the backplane substrate (3000) and grid regions (4220) corresponding to scribe lane regions (3020) of the backplane substrate (3000). Each of the mask cell regions (4210) may have a plurality of pixel openings (4212) corresponding to electrode patterns of each of the display cell regions (3010). For example, when a backplane substrate (3000) is positioned on a deposition mask (4000), electrode patterns of the backplane substrate (3000), for example, first electrodes (AND), may be positioned on pixel openings (4212), and accordingly, the first electrodes (AND) may be exposed toward a deposition source (2200) through the pixel openings (4212).

[0250] According to one embodiment, the deposition mask (4000) may include a mask substrate (4100) and a membrane (4200) disposed on the mask substrate (4100). In this case, the membrane (4200) may include a plurality of mask cell regions (4210) and a grid region (4220) disposed between the mask cell regions (4210), and each of the mask cell regions (4210) may have a plurality of pixel openings (4212).

[0251] The mask substrate (4100) may have mask cell regions (4210) and corresponding cell openings (4110), and may include a lip region (4120) defining the cell openings (4110). According to one embodiment, the mask cell regions (4210) of the membrane (4200) may be regions exposed through the cell openings (4110) of the mask substrate (4100), and the grid region (4220) of the membrane (4200) may be placed on the lip region (4120) of the mask substrate (4100). Pixel openings (4212) may be formed to penetrate the mask cell regions (4210) and may be connected to the cell openings (4110). In this case, the deposition material in the phase provided from the deposition source (2200) can be deposited on the first electrodes (AND) of the backplane substrate (3000) through the cell openings (4110) and pixel openings (4212).

[0252] The mask cell regions (4210) may be arranged in a matrix form along a first direction (DR1) and a second direction (DR2), as shown in FIG. 17. For example, the first direction (DR1) may be a first horizontal direction, and the second direction (DR2) may be a second horizontal direction perpendicular to the first direction (DR1). The mask cell regions (4210) may have a rectangular shape as shown as an example, and the pixel openings (4212) may be arranged to correspond to the first electrodes (AND) of any one of the first light-emitting regions (EA1), the second light-emitting regions (EA2), and the third light-emitting regions (EA3).

[0253] The mask substrate (4100) may be made of single-crystal silicon. For example, a single-crystal silicon substrate having a thickness of about 700 μm to about 800 μm, for example, about 775 μm, may be used as the mask substrate (4100). The membrane (4200) may be made of an inorganic material, for example, silicon nitride (SiNx), and may be formed on the front surface (4102) of the mask substrate (4100) to have a thickness of about 0.3 μm to about 3 μm through a chemical vapor deposition (CVD) process.

[0254] According to one embodiment, the inner surfaces (4112) of the cell openings (4110) may have a striped surface profile (4114) extending in the thickness direction of the mask substrate (4100), for example, in a third direction (DR3). For example, the cell openings (4110) may be formed by a metal assisted chemical etching (MACE) process using a metal catalyst material such as gold (Au), silver (Ag), platinum (Pt), palladium (Pd), etc., and a striped surface profile (4114) extending in a third direction (DR3) may be formed on the inner surfaces (4112) of the cell openings (4110) while the MACE process is performed.

[0255] According to one embodiment, cell openings (4110) can be formed approximately perpendicular to the rear surface (4104) of the mask substrate (4100) by a MACE process. For example, the inner surfaces (4112) of the cell openings (4110) can be perpendicular to the rear surface (4104) of the mask substrate (4100) or have an angle of inclination of about 85° or more to the rear surface (4104) of the mask substrate (4100). Accordingly, compared to a conventional deposition mask, the cross-sectional area of ​​the lip region (4120) defining the cell openings (4110) can be increased, and the rigidity of the mask substrate (4100) can be increased. As a result, the structural stability of the deposition mask (4000) can be improved, and accordingly, the warpage of the deposition mask (4000) can be reduced.

[0256] FIG. 20 is a schematic cross-sectional view illustrating another example of a deposition mask shown in FIG. 19.

[0257] Referring to FIG. 20, the deposition mask (4000) may include a back inorganic film (4300) disposed on the back surface (4104) of the mask substrate (4100). According to one embodiment, the back inorganic film (4300) may be used to reduce the bending of the deposition mask (4000). The back inorganic film (4300) may have residual stress similar to that of the membrane (4200) and may be used to offset the force applied to the mask substrate (4100) by the residual stress of the membrane (4200). For example, the back inorganic film (4300) may be made of silicon nitride (SiNx) and may be formed on the back surface (4104) of the mask substrate (4100) by a CVD process with a thickness of about 0.3 μm to about 3 μm. Additionally, for example, the back inorganic film (4300) can be formed simultaneously with the membrane (4200) through a CVD process, and accordingly, the back inorganic film (4300) and the membrane (4200) can be made of the same material and have the same thickness.

[0258] According to one embodiment, the back inorganic film (4300) may have back openings (4310) that expose cell openings (4110), that is, connected to the cell openings (4110). For example, the cell openings (4110) and the back openings (4310) may have approximately the same width, and the cell openings (4110) may be placed on the back openings (4310). In this case, a vapor deposition material provided from a deposition source (2200) may be deposited on the first electrodes (AND) of the backplane substrate (3000) through the back openings (4310), the cell openings (4110), and the pixel openings (4212).

[0259] FIG. 21 is a schematic cross-sectional view illustrating another example of a deposition mask shown in FIG. 19.

[0260] Referring to FIG. 21, a deposition mask (4000) may include a mask substrate (4100), a membrane (4200), and a rear inorganic film (4300). The membrane (4200) may be placed on the front surface (4102) of the mask substrate (4100) and may include mask cell regions (4210) having a plurality of pixel openings (4212). The mask substrate (4100) may have cell openings (4130) that expose the mask cell regions (4210) and may include a lip region (4160) that defines the cell openings (4130). The rear inorganic film (4300) may be placed on the rear surface (4104) of the mask substrate (4100) and may have rear openings (4320) that expose the cell openings (4130).

[0261] According to one embodiment, each of the cell openings (4130) may include a first opening (4140) adjacent to the back inorganic film (4300) and a second opening (4150) adjacent to the membrane (4200). The first opening (4140) may extend in the thickness direction of the mask substrate (4100), for example, in the third direction (DR3), and may have a roughly constant width. Additionally, the width of the first opening (4140) may be roughly the same as the width of the back opening (4320). The second opening (4150) may connect between the first opening (4140) and the pixel openings (4212) and may have a width that gradually decreases in the direction from the first opening (4140) toward the mask cell region (4210).

[0262] For example, the first opening (4140) can be formed through a MACE process, and accordingly, a striped surface profile (4144) extending in the thickness direction of the mask substrate (4100) can be formed on the inner surfaces (4142) of the first opening (4140). Additionally, the inner surfaces (4142) of the first opening (4140) can be perpendicular to the rear surface (4104) of the mask substrate (4100) or have an angle of inclination of about 85° or more with respect to the rear surface (4104) of the mask substrate (4100). Accordingly, the cross-sectional area of ​​the lip region (4160) defining the cell openings (4130) can be increased compared to a conventional deposition mask, and the rigidity of the mask substrate (4100) can be increased. As a result, the structural stability of the deposition mask (4000) can be improved, and accordingly, the warpage of the deposition mask (4000) can be reduced.

[0263] For example, the second opening (4150) may be formed by a wet etching process using an etching solution such as TMAH solution, KOH solution, EDP solution, etc., and accordingly, the second opening (4150) may have a width that gradually decreases in the direction toward the membrane (4200) from the first opening (4140). For example, of a single-crystal silicon substrate used as a mask substrate (4100). <100> The direction of determination may be the third direction (DR3), and accordingly, the inner surfaces (4152) of the second opening (4150) may have an angle of inclination of about 54.7° with respect to the rear surface (4104) of the mask substrate (4100).

[0264] FIGS. 22 to 27 are schematic cross-sectional views illustrating a method for manufacturing a deposition mask according to one embodiment of the present invention.

[0265] Referring to FIG. 22, a membrane (4200) may be formed on a mask substrate (4100). For example, the mask substrate (4100) may have a front surface (4102) and a rear surface (4104), and the membrane (4200) may be formed on the front surface (4102) of the mask substrate (4100). According to one embodiment, the mask substrate (4100) may be made of single-crystal silicon. For example, a single-crystal silicon substrate having a thickness of about 700 μm to about 800 μm, for example, about 775 μm, may be used as the mask substrate (4100).

[0266] According to one embodiment, the membrane (4200) may be made of an inorganic material, for example, silicon nitride (SiNx), and may be formed on the front surface (4102) of the mask substrate (4100) through a CVD process. For example, a silicon source gas such as monosilane (SiH4), disilane (Si2H6), dichlorosilane (DCS) (SiH2Cl2), etc. and a nitrogen source gas such as nitrogen (N2), ammonia (NH3), etc. may be supplied onto the mask substrate (4100), and the membrane (4200) may be formed on the front surface (4102) of the mask substrate (4100) with a thickness of about 0.3 μm to about 3 μm by a reaction between the silicon source gas and the nitrogen source gas.

[0267] Referring to FIG. 23, pixel openings (4212) penetrating the membrane (4200) can be formed by patterning the membrane (4200). According to one embodiment, the membrane (4200) can be partially removed by an anisotropic etching process, thereby forming pixel openings (4212) penetrating the membrane (4200). For example, a photoresist pattern (not shown) that exposes areas where pixel openings (4212) are to be formed on the membrane (4200) can be formed, and an anisotropic etching process, such as a reactive ion etching (RIE) process, can be performed using the photoresist pattern as an etching mask.

[0268] For example, if the membrane (4200) is made of silicon nitride (SiNx), the RIE process can be performed until the mask substrate (4100) is exposed using a first reaction gas containing fluorine, such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, SF6, etc., a second reaction gas containing oxygen, such as O2, NO, NO2, etc., and a sputtering gas such as He, Ne, Ar, Xe, etc., thereby forming pixel openings (4212) penetrating the membrane (4200). Meanwhile, the photoresist pattern can be removed by an ashing and / or stripping process after the pixel openings (4212) are formed.

[0269] Referring to FIGS. 24 to 27, a cell opening (4110) that exposes pixel openings (4212) can be formed by patterning a mask substrate (4100). According to one embodiment, the cell opening (4110) can be formed by a MACE process. For example, the cell opening (4110) can be formed by forming a metal catalyst pattern (4400) on the back surface (4104) of the mask substrate (4100) and performing a wet etching process using an etching solution containing hydrogen peroxide (H2O2) and hydrofluoric acid (HF). In this case, silicon of the mask substrate (4100) can be etched at the interface between the metal catalyst pattern (4400) and the mask substrate (4100), and the silicon etching can be continuously performed by mass transfer of reactants and products through pinholes of the metal catalyst pattern (4400).

[0270] According to one embodiment, as illustrated in FIG. 24, a metal catalyst pattern (4400) may be formed on the back surface (4104) of a mask substrate (4100). For example, a metal catalyst layer (not shown) may be formed on the back surface (4104) of the mask substrate (4100). The metal catalyst layer may include, for example, gold (Au), silver (Ag), platinum (Pt), palladium (Pd), etc., and may be formed through a physical vapor deposition (PVD) process such as a thermal evaporation process, an electron beam evaporation process, a sputtering process, etc. Subsequently, a metal catalyst pattern (4400) may be formed on the back surface (4104) of the mask substrate (4100) by patterning the metal catalyst layer. For example, a metal catalyst pattern (4400) can be formed on the back surface (4104) of a mask substrate (4100) by forming a photoresist pattern (not shown) that exposes the remaining areas excluding the area where the metal catalyst pattern (4400) is to be formed on the metal catalyst layer, and then performing an etching process using the photoresist pattern as an etching mask.

[0271] As another example, a photoresist pattern (not shown) that exposes the area where a metal catalyst pattern (4400) is to be formed on the back surface (4104) of a mask substrate (4100) can be formed, and then a metal catalyst layer can be formed, and subsequently, a metal catalyst pattern (4400) can be formed on the back surface (4104) of the mask substrate (4100) by removing the photoresist pattern.

[0272] After forming a metal catalyst pattern (4400), the mask substrate (4100) can be partially removed through a wet etching process using an etching solution containing hydrogen peroxide (H2O2) and hydrofluoric acid (HF), thereby forming a cell opening (4110) that penetrates the mask substrate (4100) as shown in FIGS. 25 and 26. According to one embodiment, in the wet etching process, the metal catalyst pattern (4400) can function as a cathode simultaneously with the catalyst, and holes can be created by reducing hydrogen peroxide (H2O2) by the metal catalyst pattern (4400) as shown in the reaction equation (1) below.

[0273] (1)

[0274] The above holes can be diffused through the metal catalyst pattern (4400) and injected into the mask substrate (4100). In this case, the mask substrate (4100) can function as an anode, and the silicon of the mask substrate (4100) can be oxidized by the injected holes and dissolved at the interface between the metal catalyst pattern (4400) and the mask substrate (4100) by hydrofluoric acid (HF) as in the reaction equation (2) below.

[0275] (2)

[0276] In the above wet etching process, hydrogen peroxide (H2O2) may be used as an oxidizing agent. For example, the concentration of hydrogen peroxide (H2O2) may be about 0.2 M to about 0.8 M. In the above wet etching process, hydrofluoric acid (HF) may be used as an etchant. For example, the concentration of hydrofluoric acid (HF) may be about 5 M to 8 M. As a solvent, water, ethanol, or a mixed solution of water and ethanol may be used.

[0277] As other examples, silver nitrate (AgNO3), chlorauric acid (HAuCl4), chloroplatinic acid (H2PtCl6), iron(III) nitrate (Fe(NO3)3), nickel(II) nitrate (Ni(NO3)2), magnesium nitrate (Mg(NO3)2), sodium persulfate (Na2S2O8), potassium permanganate (KMnO4), and potassium dichromate (K2Cr2O7) can be used as oxidizing agents.

[0278] In the above wet etching process, reactants and products can be delivered through pinholes in the metal catalyst pattern (4400) and diffused along the interface between the metal catalyst pattern (4400) and the mask substrate (4100). According to one embodiment, silicon etching can be continuously performed at the interface between the metal catalyst pattern (4400) and the mask substrate (4100), so that the metal catalyst pattern (4400) can be moved in the thickness direction of the mask substrate (4100), for example, in a third direction (DR3) as shown in FIGS. 25 and 26. Additionally, by moving the metal catalyst pattern (4400), a striped surface profile (4114) extending in the third direction (DR3) can be formed on the inner surfaces (4112) of the cell opening (4110).

[0279] According to one embodiment, the pinholes of the metal catalyst pattern (4400) are about 100 to about 300 / µm. 2It is desirable to have a density of a certain degree, and to this end, the metal catalyst pattern (4400) may be formed to have a thickness of about 3 nm to about 10 nm. If the thickness of the metal catalyst pattern (4400) is less than 3 nm, the density of pinholes may become excessively high, and if the thickness of the metal catalyst pattern (4400) exceeds 10 nm, the density of pinholes may become significantly lower. If the density of pinholes is excessively high or low, the etching rate of the mask substrate (4100) may decrease. For example, if the thickness of the metal catalyst pattern (4400) is about 3 nm to about 10 nm, the etching rate of the mask substrate (4100) may be about 0.2 μm / min to about 0.45 μm / min. Also, for example, if the thickness of the metal catalyst pattern (4400) is about 5 nm, the etching rate of the mask substrate (4100) may be about 0.4 μm / min or higher.

[0280] According to one embodiment, the metal catalyst pattern (4400) may include gold (Au), silver (Ag), platinum (Pt), palladium (Pd), etc. According to one embodiment, the metal catalyst pattern (4400) may have a single-layer structure or a double-layer structure. For example, a gold (Au) single-layer pattern or a silver (Ag) single-layer pattern may be used as the metal catalyst pattern (4400). As another example, a gold / silver (Au / Ag) double-layer pattern may be used as the metal catalyst pattern (4400). In this case, the silver (Ag) pattern layer may function as an adhesive layer between the mask substrate (4100) and the gold (Au) pattern layer.

[0281] The MACE process can be performed until the metal catalyst pattern (4400) reaches the membrane (4200), as shown in FIG. 26, thereby forming a cell opening (4110) that penetrates the mask substrate (4100). According to one embodiment, after forming the cell opening (4110) through the MACE process, the metal catalyst pattern (4400) can be removed as shown in FIG. 27. For example, the metal catalyst pattern (4400) can be removed by a wet etching process. For example, if the metal catalyst pattern (4400) contains gold (Au) or platinum (Pt), the metal catalyst pattern (4400) can be removed using an etching solution containing hydrochloric acid (HCl) and nitric acid (HNO3). As another example, if the metal catalyst pattern (4400) contains silver (Ag), the metal catalyst pattern (4400) can be removed using an etching solution containing phosphoric acid (H3PO4) and nitric acid (HNO3).

[0282] Meanwhile, although not illustrated, silicon residues (not illustrated) may remain on the back surface of the membrane (4200) after the metal catalyst pattern (4400) is removed. For example, the silicon portion between the metal catalyst pattern (4400) and the membrane (4200) may not be completely removed by the MACE process, and thus silicon residues may remain on the back surface of the membrane (4200). In this case, a wet etching process may be additionally performed to remove the silicon residues. For example, a wet etching process using an etching solution such as TMAH solution, KOH solution, EDP solution, etc., may be performed, thereby removing the silicon residues.

[0283] FIGS. 28 to 30 are schematic drawings for explaining a method for manufacturing a deposition mask according to another embodiment of the present invention.

[0284] FIG. 28 is a schematic cross-sectional view illustrating metal catalyst patterns formed on the back surface of a mask substrate. FIG. 29 is a schematic top view illustrating the metal catalyst patterns shown in FIG. 28. FIG. 30 is a schematic cross-sectional view illustrating cell openings formed by the metal catalyst patterns shown in FIG. 28.

[0285] Referring to FIGS. 28 to 30, a membrane (4200) having a plurality of pixel openings (4212) is formed on the front surface (4102) of a mask substrate (4100), and then a MACE process is performed to form a cell opening (4110). For example, a plurality of metal catalyst patterns (4410) may be formed on the rear surface (4104) of the mask substrate (4100), and a cell opening (4110) penetrating the mask substrate (4100) may be formed by a wet etching process using an etching solution containing hydrogen peroxide (H2O2) and hydrofluoric acid (HF). This embodiment differs from the embodiment previously described with reference to FIGS. 22 to 27 in that the cell opening (4110) is formed using a plurality of metal catalyst patterns (4410). In this embodiment, descriptions that overlap with the embodiments previously described with reference to FIGS. 22 to 27 are omitted.

[0286] Referring to FIGS. 28 and 29, a plurality of metal catalyst patterns (4410) may be formed on the back surface (4104) of a mask substrate (4100). According to one embodiment, the metal catalyst patterns (4410) may be spaced apart from each other at a predetermined interval to facilitate the transfer of reactants and products in the wet etching process, and the transfer of reactants and products may be performed between the metal catalyst patterns (4410). For example, the spacing (d1) between the metal catalyst patterns (4410) may be about 0.01 μm to about 1 μm, and the silicon portions between the metal catalyst patterns (4410) may be removed by a MACE process. According to one embodiment, holes generated by the reduction of hydrogen peroxide (H2O2) can be injected into a mask substrate (4100) through metal catalyst patterns (4410), and some of the injected holes can diffuse into silicon regions between the metal catalyst patterns (4410). The silicon regions between the metal catalyst patterns (4410) can be oxidized by the diffused holes and can be dissolved and removed by hydrofluoric acid (HF).

[0287] According to one embodiment, each of the metal catalyst patterns (4410) may have a square shape and may be arranged in a matrix form along a first direction (DR1) and a second direction (DR2). As illustrated, 16 metal catalyst patterns (4410) are used, but the size and number of metal catalyst patterns (4410) can be changed, and thus the scope of the invention will not be limited by the size and number of metal catalyst patterns (4410). For example, although not illustrated, each of the metal catalyst patterns (4410) may have a hexagonal shape and may be arranged in a honeycomb shape. As another example, each of the metal catalyst patterns (4410) may have a rod shape extending in the first direction (DR1) or the second direction (DR2) and may be arranged in the second direction (DR2) or the first direction (DR1).

[0288] Referring to FIG. 30, after forming metal catalyst patterns (4410), a wet etching process using an etching solution containing hydrogen peroxide (H2O2) and hydrofluoric acid (HF) may be performed, thereby forming a cell opening (4110) that penetrates the mask substrate (4100). While forming the cell opening (4110), the metal catalyst patterns (4410) may be moved in a third direction (DR3), and accordingly, a striped surface profile (4114) extending in the third direction (DR3) may be formed on the inner surfaces (4112) of the cell opening (4110).

[0289] After the MACE process is performed, the metal catalyst patterns (4410) can be removed by a wet etching process using a metal etchant such as hydrochloric acid (HCl), phosphoric acid (H3PO4), nitric acid (HNO3), etc., and accordingly, the fabrication of the deposition mask (4000) as shown in FIG. 27 can be completed. Meanwhile, silicon residues may remain on the back surface of the membrane (4200) after the metal catalyst patterns (4410) are removed. For example, silicon regions between the metal catalyst patterns (4410) and the membrane (4200) and silicon regions between the metal patterns (4410) may not be completely removed by the MACE process, and accordingly, silicon residues may remain on the back surface of the membrane (4200). In this case, a wet etching process may be additionally performed to remove the silicon residues. For example, a wet etching process using an etching solution such as TMAH solution, KOH solution, EDP solution, etc. can be performed, and the silicon residues can be removed by this.

[0290] FIGS. 31 to 33 are schematic cross-sectional views illustrating a method for manufacturing a deposition mask according to another embodiment of the present invention.

[0291] Referring to FIGS. 31 to 33, a membrane (4200) having a plurality of pixel openings (4212) is formed on the front surface (4102) of a mask substrate (4100), and then a MACE process is performed to form a cell opening (4110). For example, a plurality of metal catalyst patterns (4420) may be formed on the rear surface (4104) of the mask substrate (4100), and a cell opening (4110) penetrating the mask substrate (4100) may be formed by a wet etching process using an etching solution containing hydrogen peroxide (H2O2) and hydrofluoric acid (HF). This embodiment differs from the embodiment previously described with reference to FIGS. 22 to 27 in that the cell opening (4110) is formed using a plurality of metal catalyst patterns (4420). In addition, this embodiment differs from the embodiment previously described with reference to FIGS. 28 to 30 in that the spacing (d2) between the metal catalyst patterns (4420) is relatively large. In this embodiment, descriptions that overlap with the embodiments previously described with reference to FIGS. 22 to 30 are omitted.

[0292] Referring to FIG. 31, a plurality of metal catalyst patterns (4420) may be formed on the back surface (4104) of a mask substrate (4100). The plurality of metal catalyst patterns (4420) may be spaced apart at a predetermined interval. According to one embodiment, the spacing (d2) between the metal catalyst patterns (4420) may be approximately 1 μm to approximately 20 μm. If the spacing (d2) between the metal catalyst patterns (4420) is smaller than approximately 1 μm, there is a possibility that the metal catalyst patterns (4420) may become connected to each other during the MACE process, and if the spacing (d2) between the metal catalyst patterns (4420) is larger than approximately 20 μm, the cell opening (4110) may be excessively expanded while removing the silicon regions (4430; partitions) remaining between the metal catalyst patterns (4420) after the MACE process is performed.

[0293] Referring to FIG. 32, after metal catalyst patterns (4420) are formed, a wet etching process using an etching solution containing hydrogen peroxide (H2O2) and hydrofluoric acid (HF) may be performed, thereby forming a plurality of pre-cell openings (4110A) that penetrate the mask substrate (4100). While forming the pre-cell openings (4110A), the metal catalyst patterns (4420) may be moved in a third direction (DR3), thereby forming silicon partitions (4430) between the metal catalyst patterns (4420), i.e., between the pre-cell openings (4110A). In this case, the pre-cell openings (4110A) may be defined by the partitions (4430).

[0294] Referring to FIG. 33, after the MACE process is performed, the metal catalyst patterns (4420) can be removed by a wet etching process using a metal etchant such as hydrochloric acid (HCl), phosphoric acid (H3PO4), nitric acid (HNO3), etc. Subsequently, the silicon barriers (4430) between the preliminary cell openings (4410A) can be removed by a wet etching process, thereby forming a cell opening (4110) that exposes the pixel openings (4212) as shown in FIG. 27. For example, a wet etching process using an etching solution such as TMAH solution, KOH solution, EDP solution, etc. can be performed, thereby removing the silicon barriers (4430). Additionally, silicon residues remaining on the back surface of the membrane (4200) can be removed together while removing the silicon barriers (4430). In this case, the width of the cell opening (4110) can be expanded somewhat.

[0295] FIGS. 34 to 37 are schematic cross-sectional views illustrating a method for manufacturing a deposition mask according to another embodiment of the present invention.

[0296] Referring to FIGS. 34 to 37, a rear inorganic film (4300) having a rear opening (4310) can be formed on the rear surface (4104) of a mask substrate (4100). Subsequently, a MACE process can be performed to form a cell opening (4110) connecting the pixel openings (4212) and the rear opening (4310). This embodiment differs from the embodiment previously described with reference to FIGS. 22 to 27 in that the rear inorganic film (4300) is formed on the rear surface (4104) of the mask substrate (4100). In this embodiment, descriptions that overlap with the embodiment previously described with reference to FIGS. 22 to 27 are omitted.

[0297] Referring to FIG. 34, a rear inorganic film (4300) can be formed on the rear surface (4104) of a mask substrate (4100). According to one embodiment, the rear inorganic film (4300) can be formed on the rear surface (4104) of the mask substrate (4100) by a CVD process to have a thickness of about 0.3 μm to about 3 μm. For example, a silicon source gas such as monosilane (SiH4), disilane (Si2H6), dichlorosilane (DCS) (SiH2Cl2), etc. and a nitrogen source gas such as nitrogen (N2), ammonia (NH3), etc. can be supplied on the rear surface (4104) of the mask substrate (4100), and the rear inorganic film (4300) can be formed on the rear surface (4104) of the mask substrate (4100) with a thickness of about 0.3 μm to about 3 μm by a reaction between the silicon source gas and the nitrogen source gas.

[0298] Next, a rear inorganic film (4300) may be patterned to form a rear opening (4310) that penetrates the rear inorganic film (4300) and partially exposes the rear surface (4104) of the mask substrate (4100). According to one embodiment, the rear inorganic film (4300) may be partially removed by an anisotropic etching process, thereby forming a rear opening (4310) that penetrates the rear inorganic film (4300). For example, a photoresist pattern (not shown) that exposes the area where the rear opening (4310) is to be formed on the rear inorganic film (4300) may be formed, and an anisotropic etching process, such as an RIE process, may be performed using the photoresist pattern as an etching mask.

[0299] For example, if the back inorganic film (4300) is made of silicon nitride (SiNx), the RIE process can be performed using a first reaction gas containing fluorine, such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, SF6, etc., a second reaction gas containing oxygen, such as O2, NO, NO2, etc., and a sputtering gas such as He, Ne, Ar, Xe, etc., until the back surface (4104) of the mask substrate (4100) is exposed, thereby forming a back opening (4310) that penetrates the back inorganic film (4300). Meanwhile, the photoresist pattern can be removed by an ashing and / or stripping process after the back opening (4310) is formed.

[0300] According to one embodiment, the rear inorganic film (4300) can be formed simultaneously with the membrane (4200) through a CVD process. In this case, the rear opening (4310) can be formed after pixel openings (4212) penetrating the membrane (4200) are formed. As another example, pixel openings (4212) may be formed after the rear opening (4310) is formed.

[0301] Referring to FIG. 35, a metal catalyst pattern (4400) can be formed on a rear portion (4104A; see FIG. 34) of a mask substrate (4100) exposed by a rear opening (4310). According to one embodiment, a metal catalyst layer (not shown) can be formed on a rear inorganic film (4300) and on the rear portion (4104A) of the exposed mask substrate (4100), and then the metal catalyst layer can be patterned to form a metal catalyst pattern (4400) on the rear portion (4104A) of the exposed mask substrate (4100). As another example, a photoresist pattern (not shown) that exposes the area where the metal catalyst pattern (4400) is to be formed can be formed, and then the metal catalyst pattern (4400) can be formed on the area exposed by the photoresist pattern. In this embodiment, the method for forming the metal catalyst pattern (4400) may be substantially the same as described above with reference to FIG. 24, and accordingly, a detailed description of the method for forming the metal catalyst pattern (4400) is omitted.

[0302] Referring to FIG. 36, a cell opening (4110) penetrating a mask substrate (4100) can be formed by performing a MACE process using a metal catalyst pattern (4400). For example, after forming the metal catalyst pattern (4400), a wet etching process using an etching solution containing hydrogen peroxide (H2O2) and hydrofluoric acid (HF) can be performed. While forming the cell opening (4110), the metal catalyst pattern (4400) can be moved in a third direction (DR3), and accordingly, a striped surface profile (4114) extending in the third direction (DR3) can be formed on the inner surfaces (4112) of the cell opening (4110).

[0303] Referring to FIG. 37, after the MACE process is performed, the metal catalyst pattern (4400) can be removed by a wet etching process using a metal etchant such as hydrochloric acid (HCl), phosphoric acid (H3PO4), nitric acid (HNO3), etc. Additionally, a wet etching process may be performed to remove silicon residues remaining on the back surface of the membrane (4200). For example, a wet etching process using an etching solution such as TMAH solution, KOH solution, EDP solution, etc. may be performed to remove the silicon residues.

[0304] According to another embodiment of the present invention, although not illustrated, a plurality of metal catalyst patterns (not illustrated) may be formed on a rear portion (4104A) of a mask substrate (4100) exposed through a rear opening (4310), and a cell opening (4110) may be formed by a MACE process using the metal catalyst patterns. The method of forming the cell opening (4110) using the metal catalyst patterns may be substantially the same as the embodiments previously described with reference to FIGS. 28 to 33, and accordingly, a detailed description of the method of forming the cell opening using the metal catalyst patterns is omitted.

[0305] FIGS. 38 to 45 are schematic cross-sectional views illustrating a method for manufacturing a deposition mask according to another embodiment of the present invention.

[0306] Referring to FIGS. 38 to 45, the cell opening (4130) may include a first opening (4140) adjacent to the rear inorganic film (4300) and a second opening (4150) adjacent to the membrane (4200). This embodiment differs from the embodiment previously described with reference to FIGS. 22 to 27 in that the rear inorganic film (4300) is formed on the rear surface (4104) of the mask substrate (4100). Additionally, this embodiment differs from the embodiments previously described with reference to FIGS. 22 to 27 and FIGS. 34 to 37 in that the cell opening (4130) includes the first opening (4140) and the second opening (4150). In this embodiment, descriptions that overlap with the embodiments previously described with reference to FIGS. 22 to 27 and FIGS. 34 to 37 are omitted.

[0307] Referring to FIG. 38, a membrane (4200) can be formed on the front surface (4102) of a mask substrate (4100), and the membrane (4200) can be patterned to form a plurality of pixel openings (4212). Additionally, a rear inorganic film (4300) can be formed on the rear surface (4104) of a mask substrate (4100), and the rear inorganic film (4300) can be patterned to form a rear opening (4320).

[0308] Referring to FIGS. 39 and 40, a metal catalyst pattern (4440) can be formed on a rear portion (4104B; see FIG. 38) of a mask substrate (4100) exposed by a rear opening (4320). Subsequently, a first opening (4140) extending from the rear portion (4104) of the mask substrate (4100) toward the front portion (4102) of the mask substrate (4100) can be formed by performing a MACE process using the metal catalyst pattern (4440). According to one embodiment, while forming the first opening (4140), the metal catalyst pattern (4440) can be moved in a third direction (DR3), and accordingly, a striped surface profile (4144) extending in the third direction (DR3) can be formed on the inner surfaces (4142) of the first opening (4140).

[0309] According to one embodiment, the depth of the first opening (4140) may be approximately 300 μm to approximately 700 μm. According to one embodiment, the width of the rear opening (4320) may be larger than the rear opening (4310) shown in FIGS. 34 to 37, and the width of the first opening (4140) may be larger than the width of the cell opening (4110) shown in FIGS. 36 and 37. Additionally, the width of the metal catalyst pattern (4440) may be larger than the metal catalyst pattern (4400) shown in FIGS. 35 and 36. According to one embodiment, the rear opening (4320), the first opening (4140), and the metal catalyst pattern (4440) are formed relatively larger compared to the embodiment described with reference to FIGS. 34 to 37, thereby making it easier to align the cell opening (4130) and the pixel openings (4212).

[0310] Referring to FIG. 41, the metal catalyst pattern (4440) can be removed after forming the first opening (4140). For example, the metal catalyst pattern (4440) can be removed by a wet etching process using a metal etchant such as hydrochloric acid (HCl), phosphoric acid (H3PO4), nitric acid (HNO3), etc.

[0311] Referring to FIG. 42, a front passivation film (4500) can be formed on the inner surfaces of pixel openings (4212) and on the membrane (4200). For example, the front passivation film (4500) may include silicon oxide (SiOx) and may be formed with a thickness of about 0.2 μm to about 2 μm by a CVD process. According to one embodiment, a rear passivation film (4510) can be formed on the inner surfaces of the rear opening (4320) and the first opening (4140) and on the rear inorganic film (4300). For example, the rear passivation film (4510) may include silicon oxide (SiOx) and may be formed with a thickness of about 0.2 μm to about 2 μm by a CVD process.

[0312] According to one embodiment, the front passivation film (4500) and the rear passivation film (4510) can be formed simultaneously by a CVD process. For example, a silicon source gas such as monosilane (SiH4), disilane (Si2H6), dichlorosilane (DCS) (SiH2Cl2), etc. and an oxygen source gas such as oxygen (O2), nitrous oxide (N2O), nitric oxide (NO), etc. can be supplied onto a mask substrate (4100), and the front passivation film (4500) and the rear passivation film (4510) can be formed by a reaction between the silicon source gas and the oxygen source gas.

[0313] Referring to FIG. 43, a back passivation film (4510) can be partially removed to form a liner pattern (4520) on the inner surfaces of the first opening (4140). According to one embodiment, an anisotropic etching process, for example, an RIE process, can be performed to remove the back passivation film (4510) portion on the back inorganic film (4300) and the back passivation film (4510) portion on the bottom surface of the first opening (4140), thereby forming a liner pattern (4520) on the inner surfaces of the first opening (4140). For example, the above RIE process can be performed using a reaction gas containing fluorine, such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, SF6, etc., and a sputtering gas such as He, Ne, Ar, Xe, etc., until the bottom surface of the first opening (4140) is exposed.

[0314] Referring to FIG. 44, the mask substrate (4100) can be partially removed to form a second opening (4150) connecting the first opening (4140) and the pixel openings (4212) of the membrane (4200). According to one embodiment, a wet etching process using an etching solution such as TMAH solution, KOH solution, EDP solution, etc. can be performed, thereby forming a second opening (4150) connecting the first opening (4140) and the pixel openings (4212) of the membrane (4200). For example, the wet etching process can be performed until the back surface of the membrane (4200) is exposed, and the front passivation film (4500), the back inorganic film (4300), and the liner pattern (4520) can function as etching masks.

[0315] According to one embodiment, a single-crystal silicon substrate used as a mask substrate (4100) <100> The crystal direction may be a third direction (DR3), and accordingly, the second opening (4150) may have a width that gradually decreases in the direction toward the membrane (4200) from the first opening (4140). For example, the inner surfaces (4152) of the second opening (4150) may have an angle of inclination of about 54.7° with respect to the back surface (4104) of the mask substrate (4100).

[0316] According to one embodiment, hydrogen (H2) bubbles may be generated by a reaction between the mask substrate (4100) and the etching solution while forming the second opening (4150). For example, if the front passivation film (4500) is omitted, the etching solution may be provided onto the front (4102) of the mask substrate (4100) through the pixel openings (4212), and thus hydrogen (H2) bubbles may be generated within the pixel openings (4212). In this case, the membrane (4200) may be damaged by the hydrogen (H2) bubbles, and the front passivation film (4500) may be used to prevent the etching solution from being provided onto the front (4102) of the mask substrate (4100) through the pixel openings (4212).

[0317] Referring to FIG. 45, the front passivation film (4500) and the liner pattern (4520) can be removed, and accordingly, the pixel openings (4212) can be connected to the second opening (4150) of the cell opening (4130). For example, if the front passivation film (4500) and the liner pattern (4520) are made of silicon oxide (SiOx), the front passivation film (4500) and the liner pattern (4520) can be formed by a wet etching process using an etching solution such as buffered oxide etchant (BOE), diluted hydrofluoric acid (diluted HF), etc.

[0318] According to another embodiment of the present invention, although not illustrated, a plurality of metal catalyst patterns (not illustrated) may be formed on a rear portion (4104B) of a mask substrate (4100) exposed through a rear opening (4320), and a first opening (4140) may be formed by a MACE process using the metal catalyst patterns. The method of forming the first opening (4140) using the metal catalyst patterns may be substantially the same as the method of forming the cell opening (4110) in the embodiments previously described with reference to FIGS. 28 to 33, and accordingly, a detailed description of the method of forming the first opening (4140) using the metal catalyst patterns is omitted.

[0319] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0320] 10: Electronic devices 20 : Display device 100 : Display panel 2000: Deposition device 2100: Process chamber 2200 : Deposition source 2300 : Substrate chuck 2400 : Mask Chuck 2500 : Substrate chuck drive unit 2510 : Hexapod Actuator 2600 : Mask chuck drive unit 2610 : Piezo actuator 2700 : Camera 3000 : Backplane board 3010 : Display cell area 4000 : Deposition mask 4100 : Mask substrate 4102: Front side of the mask substrate 4104: Back side of the mask substrate 4110 : Cell opening 4112: Inner surface of the cell opening 4114: Surface Profile 4120 : Lip area 4130 : Cell opening 4140 : First opening 4142: Inner surface of the first opening 4144 : Surface Profile 4150 : Second opening 4160 : Lip area 4200 : Membrane 4210 : Mask cell area 4212 : Pixel aperture 4300 : Rear Weapon Shield 4310 : Rear opening 4320 : Rear opening 4400 : Metal catalyst pattern 4410 : Metal catalyst pattern 4420 : Metal catalyst pattern 4430 : Bulkhead 4440 : Metal catalyst pattern 4500 : Front passivation membrane 4510 : Rear passivation membrane 4520 : Liner Pattern

Claims

Claim 1 A deposition mask comprising: a mask substrate having a cell opening; and a membrane disposed on the front surface of the mask substrate and having a plurality of pixel openings communicating with the cell opening, wherein the inner surface of the cell opening has a striped surface profile extending in the thickness direction of the mask substrate. Claim 2 A deposition mask according to claim 1, wherein the inner surface of the cell opening is perpendicular to the rear surface of the mask substrate or has an inclination angle of 85° or more with respect to the rear surface of the mask substrate. Claim 3 A deposition mask according to claim 1, further comprising a rear inorganic film disposed on the rear surface of the mask substrate and having a rear opening that exposes the cell opening. Claim 4 In paragraph 3, the rear opening is a deposition mask having the same width as the cell opening. Claim 5 In paragraph 3, the back inorganic film is made of the same material as the membrane and is a deposition mask having the same thickness as the membrane. Claim 6 In paragraph 3, the cell opening comprises a first opening adjacent to the rear inorganic film and a second opening adjacent to the membrane, and the striped surface profile is a deposition mask formed on the inner surface of the first opening. Claim 7 A deposition mask according to claim 6, wherein the inner surface of the first opening is perpendicular to the rear surface of the mask substrate or has an angle of inclination of 85° or more with respect to the rear surface of the mask substrate, and the second opening has a width that gradually decreases from the first opening toward the membrane. Claim 8 In claim 7, the inner surface of the second opening is a deposition mask having an inclination angle of 54.7° with respect to the rear surface of the mask substrate. Claim 9 In claim 6, the rear opening is a deposition mask having the same width as the first opening. Claim 10 A method for manufacturing a deposition mask comprising: a step of forming a membrane having a plurality of pixel openings on the front surface of a mask substrate; and a step of partially removing the mask substrate to form a cell opening communicating with the pixel openings, wherein the inner surface of the cell opening has a striped surface profile extending in the thickness direction of the mask substrate. Claim 11 A method for manufacturing a deposition mask according to claim 10, wherein the step of forming the cell opening comprises the step of forming a metal catalyst pattern on the back surface of the mask substrate and the step of performing a metal-assisted chemical etching process using the metal catalyst pattern to form the cell opening. Claim 12 A method for manufacturing a deposition mask according to claim 11, wherein, while performing the metal-assisted chemical etching process, the metal catalyst pattern is moved in the thickness direction of the mask substrate, and the striped surface profile is formed while the metal catalyst pattern is moved. Claim 13 A method for manufacturing a deposition mask according to claim 11, wherein the metal catalyst pattern comprises at least one selected from the group consisting of gold (Au), silver (Ag), platinum (Pt) and palladium (Pd). Claim 14 In paragraph 13, the metal catalyst pattern is a method for manufacturing a deposition mask having a single-layer structure or a double-layer structure. Claim 15 In claim 11, the metal catalyst pattern is a method for manufacturing a deposition mask having a thickness in the range of 3 nm to 10 nm. Claim 16 In claim 11, the metal-assisted chemical etching process is a method for manufacturing a deposition mask, wherein the etching solution comprising an oxidizing agent, an etchant, and a solvent is used. Claim 17 A method for manufacturing a deposition mask according to claim 16, wherein the oxidizing agent comprises at least one selected from the group consisting of hydrogen peroxide (H2O2), silver nitrate (AgNO3), gold chloride acid (HAuCl4), platinum chloride acid (H2PtCl6), iron nitrate (Fe(NO3)3), nickel nitrate (Ni(NO3)2), magnesium nitrate (Mg(NO3)2), sodium persulfate (Na2S2O8), potassium permanganate (KMnO4), and potassium dichromate (K2Cr2O7). Claim 18 In claim 16, the above etching agent is a method for manufacturing a deposition mask comprising hydrofluoric acid (HF). Claim 19 In claim 16, the method for manufacturing a deposition mask comprises the solvent being water, ethanol, or a mixed solution of water and ethanol. Claim 20 A method for manufacturing a deposition mask according to claim 11, wherein the step of forming the cell opening further comprises the step of removing the metal catalyst pattern after performing the metal-assisted chemical etching process. Claim 21 A method for manufacturing a deposition mask according to claim 11, wherein the step of forming the cell opening further comprises the step of removing etching residue after performing the metal-assisted chemical etching process. Claim 22 A method for manufacturing a deposition mask according to claim 10, wherein the step of forming the cell opening comprises the step of forming a plurality of metal catalyst patterns on the back surface of the mask substrate and the step of performing a metal-assisted chemical etching process using the metal catalyst patterns to form the cell opening. Claim 23 A method for manufacturing a deposition mask according to claim 10, wherein the step of forming the cell opening comprises: forming a plurality of metal catalyst patterns on the back surface of the mask substrate; performing a metal-assisted chemical etching process using the metal catalyst patterns to form preliminary cell openings penetrating the mask substrate; and removing partitions between the preliminary cell openings to form the cell opening. Claim 24 A method for manufacturing a deposition mask according to claim 10, wherein the inner surface of the cell opening is perpendicular to the rear surface of the mask substrate or has an inclination angle of 85° or more with respect to the rear surface of the mask substrate. Claim 25 A method for manufacturing a deposition mask according to claim 10, further comprising the steps of forming a rear inorganic film on the rear surface of the mask substrate and patterning the rear inorganic film to form a rear opening that partially exposes the rear surface of the mask substrate. Claim 26 A method for manufacturing a deposition mask according to claim 25, wherein the cell opening is formed to penetrate the rear portion of the mask substrate exposed by the rear opening. Claim 27 A method for manufacturing a deposition mask according to claim 25, wherein the step of forming the cell opening comprises the step of forming a metal catalyst pattern on a rear portion of the mask substrate exposed by the rear opening, and the step of performing a metal-assisted chemical etching process using the metal catalyst pattern to form the cell opening. Claim 28 A method for manufacturing a deposition mask according to claim 25, wherein the step of forming the cell opening comprises: forming a metal catalyst pattern on a rear portion of the mask substrate exposed by the rear opening; performing a metal-assisted chemical etching process using the metal catalyst pattern to form a first opening extending from the rear portion of the mask substrate in the thickness direction of the mask substrate; removing the metal catalyst pattern; and forming a second opening connecting the first opening and the pixel openings. Claim 29 A method for manufacturing a deposition mask according to claim 28, wherein the inner surface of the first opening is perpendicular to the rear surface of the mask substrate or has an angle of inclination of 85° or more with respect to the rear surface of the mask substrate, and the second opening has a width that gradually decreases from the first opening toward the membrane. Claim 30 A method for manufacturing a deposition mask according to claim 29, wherein the inner surface of the second opening has an inclination angle of 54.7° with respect to the rear surface of the mask substrate. Claim 31 In claim 28, the method for manufacturing a deposition mask in which the second opening is formed by a wet etching process using a TMAH solution, a KOH solution, or an EDP solution. Claim 32 A method for manufacturing a deposition mask according to claim 28, wherein the step of forming the cell opening further comprises the step of forming a liner pattern on the inner surfaces of the first opening and the step of removing the liner pattern after forming the second opening. Claim 33 A method for manufacturing a deposition mask according to claim 32, wherein the step of forming the liner pattern comprises the step of forming a rear passivation film on the inner surfaces of the rear opening and the first opening and on the rear inorganic film, and the step of removing the rear passivation film portion on the rear inorganic film and the rear passivation film portion on the bottom surface of the first opening. Claim 34 A method for manufacturing a deposition mask according to claim 28, wherein the step of forming the cell opening further comprises the step of forming a front passivation film on the inner surfaces of the pixel openings and on the membrane after forming the first opening, and the step of removing the front passivation film after forming the second opening. Claim 35 A method for manufacturing a deposition mask comprising: a step of forming a membrane having a plurality of pixel openings on the front surface of a mask substrate; and a step of partially removing the mask substrate to form a cell opening communicating with the pixel openings, wherein at least a portion of the cell opening is formed using a metal-assisted chemical etching process. Claim 36 A method for manufacturing a display panel comprising: a step of positioning a backplane substrate on a deposition mask; and a step of providing a gaseous light-emitting material through the deposition mask to form a plurality of light-emitting layers on the backplane substrate, wherein the deposition mask comprises a mask substrate having a cell opening and a membrane having a plurality of pixel openings disposed on the front surface of the mask substrate and communicating with the cell opening, the inner surface of the cell opening has a striped surface profile extending in the thickness direction of the mask substrate, and the gaseous light-emitting material is provided onto the backplane substrate through the cell opening and the pixel openings. Claim 37 An electronic device comprising a display panel, wherein the display panel comprises a backplane substrate and a plurality of light-emitting layers formed on the backplane substrate using a deposition mask, and wherein the deposition mask comprises a mask substrate having a cell opening and a membrane disposed on the front surface of the mask substrate and having a plurality of pixel openings communicating with the cell opening, and wherein the inner surface of the cell opening has a striped surface profile extending in the thickness direction of the mask substrate. Claim 38 An electronic device according to claim 37, further comprising at least one of a processor, a memory, and a power module.

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