Semiconductor package and method for fabricating the same

Abstract

A semiconductor package is provided. The semiconductor package comprises: a package substrate; an interposer disposed on the package substrate and including a first region and a second region adjacent to each other; a processor disposed on the first region; a logic die disposed on the second region; and a plurality of memory dies sequentially stacked on the logic die, wherein at least one of the plurality of memory dies includes a stacked first chip and a second chip, wherein the first chip includes a memory cell region and the second chip includes a PIM (Processing In Memory) region.

Description

Technology Field

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same. Background Technology

[0002] Recent applications, such as learning systems like deep neural networks, require significant computational and memory capabilities to train different datasets and learn with high accuracy. Furthermore, as applications such as high-performance computing and graphics operations become data-intensive and computationally intensive, energy efficiency and low latency become critical. A technology known as Processing In Memory (PIM) can address these issues by providing additional computational power through low-power technology processes as well as by scheduling complex operations on logic dies in memory (e.g., Dynamic Random Access Memory (DRAM)) that are closer to where the data is located.

[0003] High Bandwidth Memory (HBM) is a high-performance RAM interface for three-dimensional stacked memories (e.g., DRAM). It is used with network devices and high-performance graphics accelerators that access large amounts of data. HBM generally achieves wider bandwidth while consuming less power and in a substantially smaller form factor than other DRAM technologies (e.g., DDR4, GDDR5, etc.). This can be achieved by stacking multiple memory dies (e.g., eight) together. Such stacking may include an optional base die containing a memory controller. The dies can be connected by Through-Silicon Via (TSVs) and microbumps. Prior art literature

[0004] United States Patent Publication US 2023-0197686 (Published June 22, 2023) The problem to be solved

[0005] Meanwhile, when PIM technology is applied to a memory die, the memory die includes both a memory cell area and a PIM area. Consequently, the memory cell area can be reduced within a limited memory die.

[0006] The problem that the present invention aims to solve is to provide a semiconductor package that prevents a reduction in cell area in a memory die to which PIM technology is applied.

[0007] Another problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor package that prevents a reduction in cell area in a memory die to which PIM technology is applied.

[0008] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0009] A semiconductor package according to some embodiments of the present invention for achieving the above objectives comprises: a package substrate; a logic die disposed on the package substrate; and a plurality of memory dies sequentially stacked on the logic die, wherein at least one of the plurality of memory dies comprises a stacked first chip and a second chip, wherein the first chip comprises a memory cell region and the second chip comprises a PIM (Processing In Memory) region.

[0010] A semiconductor package according to some embodiments of the present invention for achieving the above objectives comprises: a package substrate; an interposer disposed on the package substrate and including a first region and a second region adjacent to each other; a processor disposed on the first region; a logic die disposed on the second region; and a plurality of memory dies sequentially stacked on the logic die, wherein at least one of the plurality of memory dies includes a stacked first chip and a second chip, the first chip includes a memory cell region, and the second chip includes a PIM (Processing In Memory) region.

[0011] A semiconductor package according to some embodiments of the present invention for achieving the above objectives comprises: a package substrate; an interposer disposed on the package substrate and including a first region and a second region adjacent to each other; a processor disposed on the first region; and a logic die disposed on the second region. and includes a plurality of memory dies sequentially stacked on the logic die, each of the plurality of memory dies including a first chip and a second chip sequentially stacked, the first chip including a memory cell region, the second chip including a PIM (Processing In Memory) region and a periphery region, the logic die including a first edge region facing the processor, each of the plurality of memory dies including a second edge region overlapping with the first edge region, a first through electrode formed in the first edge region, a second through electrode formed in the second edge region, the second through electrode including a first sub-through electrode formed in the first chip and a second sub-through electrode formed in the second chip, and the first through electrode, the first sub-through electrode and the second sub-through electrode are electrically connected to each other.

[0012] A method for manufacturing a semiconductor package according to some embodiments of the present invention for achieving the above other objectives comprises: placing an interposer on a package substrate that includes a first region and a second region adjacent to each other; placing a processor on the first region; placing a logic die on the second region; and stacking a plurality of memory dies sequentially on the logic die, wherein one of the plurality of memory dies includes a stacked first chip and a second chip, the first chip includes a memory cell region, and the second chip includes a PIM (Processing In Memory) region and a periphery region.

[0013] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0014] FIG. 1 is a conceptual diagram illustrating a semiconductor package according to some embodiments of the present invention. Figure 2 is a diagram illustrating the relationship between the processor, logic die, and memory die shown in Figure 1. Figure 3 is a diagram illustrating the memory die shown in Figure 1. Figure 4 is a conceptual diagram for explaining the first chip illustrated in Figure 3. Figure 5 is a conceptual diagram for explaining the second chip illustrated in Figure 3. Figure 6 is a diagram illustrating the structure of the memory die shown in Figure 1. FIG. 7 is a conceptual diagram illustrating the effects of a semiconductor package according to some embodiments of the present invention. FIGS. 8 to 11 are drawings for explaining the arrangement of a PIM region and a periregion in a semiconductor package according to some embodiments of the present invention. FIG. 12 is a flowchart for explaining a method for manufacturing a semiconductor package according to some embodiments of the present invention. FIGS. 13 to 18 are intermediate step drawings for explaining a method of manufacturing a memory die used in a semiconductor package according to some embodiments of the present invention. Specific details for implementing the invention

[0015] Embodiments of the present invention will be described in detail below with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0016] FIG. 1 is a conceptual diagram for explaining a semiconductor package according to some embodiments of the present invention. FIG. 2 is a diagram for explaining the relationship between the processor, logic die, and memory die shown in FIG. 1. FIG. 3 is a diagram for explaining the memory die shown in FIG. 1. FIG. 4 is a conceptual diagram for explaining the first chip shown in FIG. 3. FIG. 5 is a conceptual diagram for explaining the second chip shown in FIG. 3. FIG. 6 is an exemplary diagram for explaining the structure of the memory die shown in FIG. 1. FIG. 7 is a conceptual diagram for explaining the effects of a semiconductor package according to some embodiments of the present invention.

[0017] First, referring to FIG. 1, a semiconductor package according to some embodiments of the present invention may include a plurality of integrated circuit dies. The plurality of integrated circuit dies may be arranged, for example, into a multichip module (MCM). A multichip module may be an electronic assembly, such as a package including a plurality of conductive terminals or pins, in which a plurality of integrated circuits, semiconductor dies, and / or other distinct components are integrated on a unifying substrate and are considered as a single component (e.g., a larger IC) when in use. FIG. 1 illustrates, by way of example, a High Bandwidth Memory (HBM) device, but this is merely illustrative.

[0018] A semiconductor package (100) according to some embodiments of the present invention includes a package substrate (1220), an interposer (1200), a processor (1040), a logic die (1110), a plurality of memory dies (1120), etc.

[0019] The package substrate (1220) may be configured to communicate with other components or dies and with the outside of the semiconductor package. A plurality of balls (1222) may be installed on the lower surface of the package substrate (1220), but are not limited thereto.

[0020] The interposer (1200) may include silicon or other substrates. A plurality of bumps (1202, 1203) may be installed on the lower surface of the interposer (1200), but are not limited thereto. The interposer (1200) may be configured to enable communication between the processor (1040) and the logic die (1110). Additionally, the interposer (1200) may be configured to enable communication between the logic die (1110) and the package substrate (1220), and between the processor (1040) and the package substrate (1220).

[0021] The interposer (1200) may include a first region and a second region adjacent to each other.

[0022] A processor (1040) is placed on a first region of the interposer (1200). The processor (1040) may be configured to execute various instructions or perform logic operations.

[0023] A microbump (1042) is installed on the lower surface of the processor (1040) to electrically connect the processor (1040) and the interposer (1200).

[0024] The processor (1040) may be a central graphic processing unit (CPU) and may include specialized processing units such as a graphic processing unit (GPU), an encryption processing unit, a physics processing unit, a machine learning processing unit, etc. The foregoing is merely some illustrated embodiments and the present invention is not limited thereto.

[0025] The stack (1080) is placed on a second region of the interposer (1200). The stack (1080) includes a logic die (1110) and a plurality of stacked memory dies (1120).

[0026] The logic die (1110) may be configured to perform standard memory access harmonization functions (e.g., page table translations, address mapping, write combinations, etc.). In various embodiments, the logic die (1110) may include a memory management unit (MMU) concentrated on a plurality of memory dies (1120), but is not limited thereto. Microbumps (1112, 1114) are installed on the lower surface of the logic die (1110) to electrically connect the logic die (1110) and the interposer (1200).

[0027] Multiple memory dies (1120) may be arranged vertically relative to each other. That is, one memory die (1120) may be stacked on top of another memory die (1120). The memory die (1120) may be, for example, a DRAM memory die, but is not limited thereto. Microbumps (1124) are installed on the lower surface of each of the multiple memory dies (1120) to electrically connect the logic die (1110) and the memory die (1120). Additionally, the memory dies (1120) stacked above and below may be electrically connected through the microbumps (1124).

[0028] The device formed on the memory die (1120) can be implemented in various forms. For example, it can be implemented as a BCAT (Buried Channel Array Transistor Cell), VCT (Vertical Channel Transistor), VS-DRAM (Vertical Stack DRAM), etc. In addition, the channel material can be made not only of silicon but also of SiGe, amorphous oxide (e.g., IGZO (InGaZnO)), etc.

[0029] Meanwhile, the memory die (1120) can be implemented to enable PIM (Processing In Memory) functionality.

[0030] Additionally, communication between a plurality of memory dies (1120) and logic dies (1110) can be achieved through through electrodes (e.g., through-silicon vias (TSVs)) and vertical wiring. As illustrated in FIG. 1, through electrodes (1118) and / or vertical wiring (1116) are formed within the logic die (1110). Through electrodes (1128) and / or vertical wiring (1126) are formed within the memory die (1120).

[0031] In particular, the through electrode (1118) in the logic die (1110) and the through electrode (1128) in the memory die (1120) are placed within the edge region (ER).

[0032] Here, referring to FIG. 2, the logic die (1110) has an edge region (ER1) located on the side facing the processor (1040). Additionally, the processor (1040) has an edge region (ER0) located on the side facing the logic die (1110).

[0033] Here, a physical layer interface is located in the edge region (ER0) of the processor (1040). Also, a physical layer interface is located in the edge region (ER1) of the logic die (1110).

[0034] Additionally, the edge region (ER2) of the memory die (1120) is positioned to overlap with the edge region (ER1) of the logic die (1110).

[0035] According to some embodiments of the present invention, a through electrode (see 1128 in FIG. 1) is installed in an edge region (ER2) of a memory die (1120), and a through electrode (see 1118 in FIG. 1) is installed in an edge region (ER1) of a logic die (1110). The through electrode (1128) and the through electrode (1118) are electrically connected.

[0036] Referring to FIG. 3, at least one of the plurality of memory dies (1120) includes a stacked first chip (110) and a second chip (120). Although the drawing shows the first chip (110) below and the second chip (120) above, it is not limited thereto. Conversely, the second chip (120) may be placed below and the first chip (110) above. Each of the plurality of memory dies (1120) may include a stacked first chip (110) and a second chip (120).

[0037] Referring to FIGS. 4 and 5, the first chip (110) includes a memory cell region (112). In the drawings, the memory cell region (112) is illustrated as including eight memory banks for example, but is not limited thereto. A sub-penetrating electrode region (111) is disposed in an edge region (refer to ER2 in FIG. 2).

[0038] The second chip (120) includes a Processing In Memory (PIM) region (122). Additionally, the second chip (120) may further include a peripheral region (124). A sub-through electrode region (121) is placed in the edge region (see ER2 in FIG. 2).

[0039] The through electrode (1128) within the aforementioned memory die (1120) includes a sub-through electrode region (111) formed in the first chip (110) and a sub-through electrode region (121) formed in the second chip (120). The sub-through electrode region (111) formed in the first chip (110) and the sub-through electrode region (121) formed in the second chip (120) are electrically connected to each other.

[0040] Additionally, the ferri area (124) may be placed within the first chip (110) depending on the design.

[0041] Additionally, the periphery region (124) may be positioned between the PIM region (122) and the sub-through electrode region (121) (or edge region (ER2). This is because the periphery region (124) is positioned closer to the sub-through electrode region (121) so that the signal provided through the sub-through electrode region (121) can be processed more quickly.

[0042] In this way, by configuring the memory die (1120) with two stacked chips (110, 120), the size of the memory cell area (112) can be sufficiently secured even if a PIM area (122) is added.

[0043] If the memory die is configured as a single chip, the memory cell area, PIM area, and peri-area must be implemented within the single chip. Consequently, the size of the memory cell area is inevitably reduced. On the other hand, as in some embodiments of the present invention, if the memory die (1120) is configured as two stacked chips (110, 120), not only the PIM area (122) but also the memory cell area (112) can be sufficiently secured.

[0044] Here, with reference to FIG. 6, an exemplary structure of a memory die (1120) will be described.

[0045] The memory die (1120) includes a first chip (110) and a second chip (120) disposed on the first chip (110). A plurality of memory cells are formed on a substrate (115) of the first chip (110) (see reference numeral 116). A sub-through electrode (118) is disposed in an edge region (see ER2 in FIG. 2) of the first chip (110). A PIM circuit (126) and a peri-circuit (127) are formed on a substrate (125) of the second chip (120). A sub-through electrode (128) is disposed in an edge region (see ER2 in FIG. 2) of the second chip (120). The sub-through electrodes (128, 129) may use tungsten, copper, polymer, carbon nanotube, polysilicon, etc. as fillers.

[0046] Here, with reference to FIG. 7, the advantages of the case where the through electrodes (1118, 1128) are placed in the edge region (ER) will be explained.

[0047] The memory die (1120) can exchange signals / data with the processor (1040) through through electrodes (1118, 1128) and vertical wiring (1116, 1126) placed in the edge region (ER).

[0048] On the other hand, when the through electrode (1128a), etc., is placed in the center region (CT), the signal / data provided by the processor (1040) is transmitted to the memory die (1120) through the microbump (1114), horizontal wiring (1116a), and through electrode (1118a) (see reference numeral A). Therefore, due to the horizontal wiring (1116a), a delay occurs between the through electrode (1118a) and the physical layer interface.

[0049] On the other hand, as in some embodiments of the present invention, when a through electrode (1128) or the like is placed in an edge region (ER), the signal / data provided by the processor (1040) is transmitted to the memory die (1120) through the microbump (1114), vertical wiring (1116), and through electrode (1118) (see reference numeral B). Therefore, no delay occurs between the through electrode (1118) and the physical layer interface.

[0050] Referring to FIGS. 1 to 7, according to a semiconductor package (100) according to some embodiments of the present invention, a memory die (1120) is separated into a first chip (110) and a second chip (120) through C2O (Cell Core Overlap) technology. The first chip (110) includes a memory cell region (112), and the second chip (120) includes a PIM region (122) and a peri-region (124). Therefore, even if a PIM region (122) is added within the memory die (1120), the memory cell region (112) can be sufficiently secured.

[0051] In addition, a through electrode (1118) is placed in an edge region (ER1 in FIG. 2) of a logic die (1110) facing the processor (1040). Also, a through electrode (1128) is placed in an edge region (ER2 in FIG. 2) of a memory die (1120) that overlaps with the edge region (ER1 in FIG. 2) of the logic die (1110). Thus, the delay in communication between the memory die (1120) and the processor (1040) can be reduced.

[0052] FIGS. 8 to 11 are drawings illustrating the arrangement of the PIM region and the periregion in a semiconductor package according to some embodiments of the present invention. For convenience of explanation, the differences from the description using FIGS. 1 to 7 will be explained primarily.

[0053] The second chip (120) illustrated in FIGS. 5, 8 to 11 includes a PIM region (122), a periphery region (124), and an edge region (ER2 in FIG. 2). In the second chip (120), the positions of the edge region (ER2) are identical, but the arrangement of the PIM region (122) and the periphery region (124) may vary depending on the design.

[0054] In FIG. 5, the peri region (124) may be positioned between the PIM region (122) and the edge region (ER2) (or, sub-penetrating electrode region (121)).

[0055] Referring to FIG. 8, the PIM region (122a) and the peri region (124a) are positioned to be in direct contact with the edge region (ER2) (or, the sub-penetrating electrode region (121)). The edge region (ER2) may have a shape extending in a first direction (e.g., vertical direction in the drawing), and the PIM region (122a) and the peri region (124a) may have a shape extending in a second direction (e.g., horizontal direction in the drawing).

[0056] Referring to FIG. 9, there are multiple periphery regions (124b), and periphery regions (124b) can be placed on both sides of the PIM region (122b).

[0057] Referring to FIG. 10, the PIM region (122c) may be positioned adjacent to the edge region (ER2) (or sub-through electrode region (121)). That is, the PIM region (122c) may be positioned between the peri region (124c) and the edge region (ER2) (or sub-through electrode region (121)).

[0058] Referring to FIG. 11, there are multiple PIM regions (122d), and PIM regions (122d) can be placed on both sides of the peri region (124d).

[0059] FIG. 12 is a flowchart for explaining a method for manufacturing a semiconductor package according to some embodiments of the present invention.

[0060] Referring to FIGS. 1 and FIGS. 12, an interposer (1200) including a first region and a second region adjacent to each other is placed on a package substrate (1220) (S10).

[0061] A processor (1040) is placed on the first region (S20).

[0062] A logic die (1110) is placed on the second region (S30).

[0063] A plurality of memory dies (1120) are sequentially stacked and arranged on a logic die (1110) (S40). One of the plurality of memory dies (1120) includes a stacked first chip and a second chip, the first chip includes a memory cell region, and the second chip includes a PIM (Processing In Memory) region and a periregion.

[0064] Here, the order of S20 and S30 may be changed.

[0065] Additionally, after performing S30 and S40, a logic die (1110) having a plurality of memory dies (1120) stacked thereon may be placed on the second region.

[0066] Using FIGS. 13 to 18, a method for manufacturing a memory die used in a semiconductor package according to some embodiments of the present invention is described. FIGS. 13 to 18 are intermediate step drawings for describing a method for manufacturing a memory die used in a semiconductor package according to some embodiments of the present invention.

[0067] Referring to FIG. 13, a memory cell circuit (116) and a sub-through electrode (118) are formed on a first substrate (115). The memory cell can be implemented in various forms. For example, it can be implemented as a BCAT (Buried Channel Array Transistor Cell), VCT (Vertical Channel Transistor), VS-DRAM (Vertical Stack DRAM), etc. In addition, the channel material can be not only silicon but also SiGe, amorphous oxide (e.g., IGZO (InGaZnO)), etc. The sub-through electrode (118) can be filled with tungsten, copper, polymer, carbon nanotube, polysilicon, etc.

[0068] Referring to FIG. 14, a ferry circuit (127) and a PIM circuit (126) are formed on the second substrate (125).

[0069] Referring to FIG. 15, a transfer wafer (199) is bonded onto a second substrate (125) to form a bonding structure.

[0070] Referring to FIG. 16, the bonding structure is flipped (or turned over) so that the rear surface of the second substrate (125) faces upward. Then, the rear surface of the second substrate (125) is recessed to reduce the thickness of the second substrate (125).

[0071] Referring to FIG. 17, after reducing the thickness of the second substrate, the bonding structure is flipped again so that the transfer wafer (199) faces upward. Then, the second substrate (125) with reduced thickness is bonded onto the first substrate (115).

[0072] Referring to FIG. 18, the transfer wafer (199) is removed. Then, a sub-through electrode (refer to 128 in FIG. 6) is formed on the second chip (120). The sub-through electrode (118) of the first chip (110) and the sub-through electrode (128) of the second chip (120) are electrically connected to each other.

[0073] FIG. 19 is a conceptual diagram illustrating a semiconductor package according to some embodiments of the present invention. FIG. 20 is a conceptual diagram illustrating a semiconductor package according to some embodiments of the present invention. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 1 to FIG. 18.

[0074] In the semiconductor package of FIG. 1, a logic die (1100) and a memory die (1120) are connected via microbumps (1124), and adjacent memory dies (1120) are also connected via microbumps. On the other hand, in the semiconductor package of FIG. 19, the logic die (1100) and the memory die (1120) can be connected by a direct bonding method. Additionally, adjacent memory dies (1120) can also be connected by a direct bonding method. Examples of direct bonding methods include, but are not limited to, hybrid copper bonding.

[0075] Additionally, in the semiconductor package of FIG. 1, the logic die (1110) and the interposer (1200) are connected via microbumps (1112, 1114). Also, the processor (1040) and the interposer (1200) are connected via microbumps (1042, 1044). On the other hand, in the semiconductor package of FIG. 20, the logic die (1110) and the interposer (1200) are connected via a direct bonding method, and the processor (1040) and the interposer (1200) can be connected via a direct bonding method. Examples of direct bonding methods include, but are not limited to, hybrid copper bonding.

[0076] In another embodiment, the interposer (1200) and the package substrate (1220) may be connected without using a plurality of bumps (see 1202, 1203 in FIG. 1).

[0077] Additionally, FIGS. 1, 19, and 20 illustrate an embodiment in which a processor and a logic die / memory die are electrically connected through an interposer, but the scope of the present invention is not limited thereto. That is, in a semiconductor package in which an interposer and a processor are not used, at least one of the stacked memory dies may be divided into a stacked first chip and a second chip. Here, the first chip may include a memory cell region, and the second chip may include a PIM region.

[0078] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0079] 110: 1st chip 112: Memory cell area 120: The second chip 122: PIM area 124: Ferry Area 1220: Package substrate 1200: Interposer 1040: Processor 1110: Logic Die 1120: Memory die

Claims

Claim 1 A semiconductor package comprising: a package substrate; a logic die disposed on the package substrate; and a plurality of memory dies sequentially stacked on the logic die, wherein at least one of the plurality of memory dies comprises a stacked first chip and a second chip, wherein the first chip comprises a memory cell region and the second chip comprises a PIM (Processing In Memory) region. Claim 2 A semiconductor package according to claim 1, wherein the second chip does not include a memory cell region and further includes a ferri region. Claim 3 A semiconductor package according to claim 1, wherein the logic die includes a first edge region and the memory die includes a second edge region, a first through-electrode is formed in the first edge region and a second through-electrode is formed in the second edge region, and the first through-electrode and the second through-electrode are electrically connected. Claim 4 In claim 3, the second through-hole electrode comprises a first sub-through-hole electrode formed on the first chip and a second sub-through-hole electrode formed on the second chip, and the first sub-through-hole electrode and the second sub-through-hole electrode are electrically connected to each other, in a semiconductor package. Claim 5 A semiconductor package according to claim 3, wherein a physical layer interface is disposed in the first edge region of the logic die. Claim 6 A semiconductor package comprising: a package substrate; an interposer disposed on the package substrate and including a first region and a second region adjacent to each other; a processor disposed on the first region; a logic die disposed on the second region; and a plurality of memory dies sequentially stacked on the logic die, wherein at least one of the plurality of memory dies includes a stacked first chip and a second chip, wherein the first chip includes a memory cell region and the second chip includes a PIM (Processing In Memory) region. Claim 7 In claim 6, the semiconductor package wherein the second chip does not include a memory cell region and further includes a ferri region. Claim 8 In claim 6, the logic die includes a first edge region facing the processor, the memory die includes a second edge region, a first through-electrode is formed in the first edge region, a second through-electrode is formed in the second edge region, and the first through-electrode and the second through-electrode are electrically connected, a semiconductor package. Claim 9 In claim 8, the second through-hole electrode comprises a first sub-through-hole electrode formed on the first chip and a second sub-through-hole electrode formed on the second chip, wherein the first sub-through-hole electrode and the second sub-through-hole electrode are electrically connected to each other, in a semiconductor package. Claim 10 A semiconductor package comprising: a package substrate; an interposer disposed on the package substrate and including a first region and a second region adjacent to each other; a processor disposed on the first region; a logic die disposed on the second region; and a plurality of memory dies sequentially stacked on the logic die, wherein each of the plurality of memory dies includes a first chip and a second chip sequentially stacked, wherein the first chip includes a memory cell region, and the second chip includes a PIM (Processing In Memory) region and a periphery region, wherein the logic die includes a first edge region facing the processor, and each of the plurality of memory dies includes a second edge region overlapping with the first edge region, wherein a first through electrode is formed in the first edge region and a second through electrode is formed in the second edge region, and the second through electrode includes a first sub-through electrode formed in the first chip and a second sub-through electrode formed in the second chip, and wherein the first through electrode, the first sub-through electrode and the second sub-through electrode are electrically connected to each other.

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