Power semiconductor device and power semiconductor chip including the same

Abstract

A power semiconductor device according to one embodiment of the present specification comprises a collector electrode, an emitter electrode disposed on the collector electrode, a semiconductor substrate disposed between the collector electrode and the emitter electrode and defining a plurality of trenches recessed from the upper surface, a trench gate electrode disposed within the plurality of trenches and insulated from the emitter electrode, a trench emitter electrode disposed within the plurality of trenches and electrically connected to the emitter electrode, and a floating region including a first floating region covering the lower portion of the trench emitter electrode and a second floating region covering the lower portion of the trench gate electrode, wherein the first floating region and the second floating region are disposed on different layers.

Description

Technology Field

[0001] This specification relates to a power semiconductor device and a power semiconductor chip including the same. Background Technology

[0002] Power semiconductor devices refer to semiconductor devices capable of performing switching operations in high-voltage and high-current environments. Power semiconductor devices are primarily used in fields requiring high-power switching (i.e., switching operations in high-voltage and high-current environments) (e.g., inverter devices).

[0003] Examples of power semiconductor devices include insulated gate bipolar transistors (IGBTs) and power MOSFETs. These power semiconductor devices are fundamentally required to have high voltage withstand capability, and recently, high-speed switching operation is additionally required. The problem to be solved

[0004] The problem that this specification aims to solve is to provide a power semiconductor device with reduced turn-off loss and a power semiconductor chip including the same.

[0005] Another problem that this specification aims to solve is to provide a power semiconductor device with improved switching characteristics by reducing turn-off losses, and a power semiconductor chip including the same.

[0006] Another problem that this specification aims to solve is to provide a power semiconductor device and a power semiconductor chip including the same, which can improve reliability by controlling the maximum electric field position.

[0007] The problems of this specification are not limited to those mentioned above, and other technical problems may be inferred from the following embodiments. means of solving the problem

[0008] A power semiconductor device according to one embodiment of the present specification comprises a collector electrode, an emitter electrode disposed on the collector electrode, a semiconductor substrate disposed between the collector electrode and the emitter electrode and defining a plurality of trenches recessed from the upper surface, a trench gate electrode disposed within the plurality of trenches and insulated from the emitter electrode, a trench emitter electrode disposed within the plurality of trenches and electrically connected to the emitter electrode, and a floating region including a first floating region covering the lower portion of the trench emitter electrode and a second floating region covering the lower portion of the trench gate electrode, wherein the first floating region and the second floating region are disposed on different layers.

[0009] A power semiconductor according to another embodiment of the present specification comprises a collector electrode, an emitter electrode disposed on the collector electrode, a drift region disposed between the collector electrode and the emitter electrode and including a first drift region and a second drift region sequentially stacked, a floating region including a first floating region disposed within the first drift region and a second floating region disposed within the second drift region, a collector region disposed between the second drift region and the collector electrode, a first proton irradiation region formed around the boundary between the first drift region and the second drift region, and a second proton irradiation region formed around the boundary between the collector region and the collector electrode, wherein the first proton irradiation region and the second proton irradiation region are regions where silicon (Si) lattice defects occur.

[0010] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0011] According to the embodiments of the present specification, a power semiconductor device with reduced turn-off loss and a power semiconductor chip including the same can be provided.

[0012] According to the embodiments of the present specification, a power semiconductor device with improved switching characteristics by reducing turn-off loss and a power semiconductor chip including the same can be provided.

[0013] According to the embodiments of the present specification, a power semiconductor device and a power semiconductor chip including the same can be provided, wherein reliability can be improved by controlling the maximum electric field position.

[0014] However, the effects obtainable in this specification are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art to which this specification belongs from the description below. Brief explanation of the drawing

[0015] FIG. 1 is a circuit diagram of a power semiconductor device according to one embodiment. Figure 2 is a simplified diagram showing a power semiconductor chip including the power semiconductor device of Figure 1. Figure 3 is an enlarged view of a portion of the cell area shown in Figure 2. Figure 4 is a cross-sectional view taken along the line AA' of Figure 4. Figure 5 is a graph showing the magnitude of the electric field according to the position of the semiconductor substrate. Figure 6 shows the breakdown voltage (BV, BV, Breakdown Voltage) according to the P doping ratio in the floating region and the drift region. FIG. 7 is an enlarged view of a portion of a cell area according to another embodiment. Figure 8 is a cross-sectional view taken along the BB' line of Figure 7. FIG. 9 is a cross-sectional view of a power semiconductor device according to another embodiment. Specific details for implementing the invention

[0016] Hereinafter, embodiments are described with reference to the drawings. In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "joined" to another component, it means that it may be directly connected / joined to the other component or that a third component may be placed between them.

[0017] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the effective illustration of the technical content. "And / or" includes all of one or more combinations that the associated components may define.

[0018] Terms such as "first," "second," etc., may be used to describe various components, but said components are not limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the embodiments, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0019] Terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0020] Terms such as "include" or "have" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0021] FIG. 1 is a circuit diagram of a power semiconductor device according to one embodiment.

[0022] As illustrated in FIG. 1, the power semiconductor device (10) may include an insulated gate bipolar transistor (IGBT). In the following description, the power semiconductor device (10) in this embodiment is described as an insulated gate bipolar transistor (IGBT). However, it is not limited thereto, and the power semiconductor device (10) may be implemented as another type of power transistor (e.g., a silicon carbide-based MOSFET (metal oxide semiconductor field effect transistor)).

[0023] The power semiconductor device (10) may have a structure in which the gate of a MOSFET is combined with the emitter and collector of a bipolar transistor. Therefore, the power semiconductor device (10) may have both the voltage withstand characteristics of a bipolar transistor and the relatively fast switching speed of a MOSFET.

[0024] The power semiconductor device (10) may be a self-extinguishing type device in which the gate-emitter voltage (Vge) changes according to the driving voltage applied to the gate, thereby turning on or off. Here, a self-extinguishing type device may mean a device that receives an input signal without relying on an external source and can control whether current flows between two terminals (i.e., emitter and collector) or not by means of self-control.

[0025] A power semiconductor device (10) may include a gate terminal (G) connected to a gate, an emitter terminal (E) connected to an emitter, and a collector terminal (C) connected to a collector. The power semiconductor device (10) may be turned on or off depending on a driving voltage input to the gate terminal (G), thereby allowing or preventing current from flowing between the emitter terminal (E) and the collector terminal (C). The gate terminal (G) may be connected to a driver circuit (not shown) that transmits the driving voltage, and the emitter terminal (E) and the collector terminal (C) may be connected to a load (not shown) to provide a switching function.

[0026] According to one embodiment, the power semiconductor device (10) may further include a freewheeling diode (Df) connected between an emitter terminal (E) and a collector terminal (C). The freewheeling diode (Df) may provide a loop that allows carriers (holes or electrons) accumulated in the emitter or collector due to the ON operation of the power semiconductor device (10) to be emitted again during the OFF operation of the power semiconductor device (10). By providing such a loop, the freewheeling diode (Df) can prevent impulse voltage, thereby preventing damage to the load connected to the power semiconductor device (10).

[0027] Figure 2 is a simplified diagram showing a power semiconductor chip including the power semiconductor device of Figure 1.

[0028] Referring to FIGS. 1 and FIGS. 2, the power semiconductor chip (20) may be a semiconductor chip including the power semiconductor device (10) of FIG. 1. The power semiconductor chip (20) may include a single power semiconductor device (10) formed integrally, or, according to other embodiments, may include a plurality of power semiconductor devices (10).

[0029] The power semiconductor chip (20) may include a cell region (100) and a peripheral region (200).

[0030] The cell region (100) may include at least one power semiconductor device (10). For example, the arrangement of the power semiconductor device (10) may be a stripe type or a closed type, but the present embodiment is not limited thereto.

[0031] The cell region (100) may further include a device for monitoring the state of at least one power semiconductor device (10).

[0032] The cell region (100) may further include a current sensing transistor having a structure substantially identical to that of the power semiconductor device (10) but reduced by a predetermined ratio. For example, the current sensing transistor may be connected in parallel with the power semiconductor device (10). Here, when connected in parallel, a predetermined resistor may be connected between one terminal of the current sensing transistor and one terminal of the power semiconductor device (10). The output current of the current sensing transistor (e.g., the output current of the emitter terminal or the collector terminal) has a ratio associated with a predetermined ratio with the output current of the power semiconductor device (10), and through this ratio, the output current of the current sensing transistor can be used to indirectly monitor the state of the power semiconductor device (10).

[0033] According to another embodiment, the cell region (100) may further include a temperature sensor disposed adjacent to the power semiconductor device (10) to detect the temperature of the power semiconductor device (10). As an example, the temperature sensor may include a junction diode that outputs a current that varies with temperature. The current of such a junction diode can be used to monitor the temperature of the power semiconductor device (10).

[0034] A peripheral region (200) may be positioned at the outer edge of the cell region (100) while surrounding the cell region (100). The peripheral region (200) may include a plurality of terminals for electrical connection between an external circuit (e.g., a driving circuit, a load, a test circuit, etc.) and the cell region (100). The plurality of terminals may include a gate terminal (G), an emitter terminal (E), and a collector terminal (C) of a power semiconductor device (10). Additionally, the plurality of terminals may include each terminal of a current sensing transistor and / or a temperature sensor that may be included in the cell region (100).

[0035] FIG. 3 is an enlarged view of a portion of the cell area shown in FIG. 2. FIG. 4 is a cross-sectional view cut along the line AA' of FIG. 4.

[0036] Referring to FIGS. 3 and 4, a power semiconductor device (10) may include a semiconductor substrate (110), a collector electrode (120) disposed on one side (first side or bottom side) of the semiconductor substrate (110), an emitter electrode (130) disposed on the other side (second side or top side) of the semiconductor substrate (110), a trench gate electrode (141), a trench emitter electrode (142), a floating region (160), and an emitter region (170). Here, the one side and the other side of the semiconductor substrate (110) may refer to opposite sides.

[0037] The power semiconductor device (10) may further include at least one insulating layer disposed between each electrode.

[0038] The semiconductor substrate (110) may mean at least one semiconductor material layer (e.g., an epitaxial layer). For example, the semiconductor substrate (110) may include semiconductor materials such as silicon, germanium, silicon-germanium, etc.

[0039] A semiconductor substrate (110) can be placed between a collector electrode (120) and an emitter electrode (130).

[0040] The collector electrode (120) can be electrically connected to the collector terminal (C) of FIG. 1 and may include at least one of polysilicon, metal, metal nitride, and metal silicide. The collector region (114) and the collector electrode (120) may correspond to the collector of the IGBT of FIG. 1.

[0041] The emitter electrode (130) may comprise at least one of a conductive material, such as polysilicon, metal, metal nitride, or metal silicide. The emitter electrode (130) may be positioned to cover the upper surface of the semiconductor substrate (110) while in contact with insulating films (151, 152), a well region (118), and an emitter region (170) protruding outside the semiconductor substrate (110).

[0042] The emitter electrode (130) acts as a contact with respect to the well region (118) to apply a low voltage to the well region (118) that is lower than the voltage on the collector side of the IGBT, and with respect to the emitter region (170), it can function as an electrode that electrically connects the emitter region (170) and the emitter terminal (E) of FIG. 1. The emitter region (170) and the emitter electrode (130) may correspond to the emitter of the IGBT of FIG. 1.

[0043] The semiconductor substrate (110) may include a collector region (114), a drift region (116), a floating region (160), and a well region (118) that are sequentially stacked.

[0044] A drift region (116) may be positioned between the collector region (114) and the well region (118). The collector region (114) may be positioned between the collector electrode (120) and the drift region (116). The well region (118) may be positioned between the drift region (116) and the emitter electrode (130).

[0045] The collector region (114), drift region (116), and well region (118) may contain impurities having a first conductivity type or impurities having a second conductivity type. The first conductivity type may be the opposite conductivity type of the second conductivity type. Any one of the collector region (114), drift region (116), and well region (118) may contain impurities having a conductivity type different from the others.

[0046] For example, the drift region (116) may contain impurities having a first conductivity type, and the collector region (114) and well region (118) may contain impurities having a second conductivity type. The first conductivity type may be N-type, and the second conductivity type may be P-type.

[0047] In the following description, the drift region (116) is described as containing N-type impurities, and the collector region (114) and well region (118) are described as containing P-type impurities, but are not limited thereto.

[0048] The collector region (114) can be formed to have a predetermined thickness while in contact with the lower surface of the semiconductor substrate (110). The collector region (114) can be positioned to be in contact with the lower collector electrode (120).

[0049] The drift region (116) can provide a vertical path for charge (holes and electrons) between the collector region (114) and the emitter region (170). The drift region (116) is positioned above the collector region (114) and can extend along the elongation direction (third direction (DR3)) of the trench (TH) while in contact with the sides of the floating region (160) and the trench (TH), respectively.

[0050] The drift region (116) may be composed of multiple layers. For example, the drift region (116) may include a first drift region (DA1), a second drift region (DA2), and a third drift region (DA3) that are sequentially stacked.

[0051] The second drift area (DA2) may be positioned between the first drift area (DA1) and the third drift area (DA3). The first drift area (DA1) may be positioned between the second drift area (DA2) and the well area (118). The third drift area (DA3) may be positioned between the second drift area (DA2) and the collector area (114).

[0052] Floating regions (161, 162, 163) may each be disposed within each of the first to third drift regions (DA1, DA2, DA3).

[0053] The well region (118) may be positioned between the trench gate electrode (141) and the trench emitter electrode (142). The well region (118) may be positioned to be in contact with the drift region (116), the gate insulating film (151), the emitter insulating film (152), the emitter region (170), and the emitter electrode (130), respectively.

[0054] Additionally, the well region (118) may be located between adjacent trenches (TH) that are placed. In other words, the well region (118) may be separated by the trenches (TH). The well region (118) may be separated by a trench gate electrode (141) and a trench emitter electrode (142).

[0055] A trench (TH) can be recessed to a predetermined depth from one side of the semiconductor substrate (110) toward one side of the semiconductor substrate (110). That is, the trench (TH) can be defined by the semiconductor substrate (110). Multiple trenches (TH) may be provided. The trench (TH) extends along a second direction (DR2) and can be repeatedly arranged along a first direction (DR1).

[0056] Here, the first direction (DR1) and the second direction (DR2) are directions that intersect each other and may be perpendicular to each other, but are not limited thereto. The first direction (DR1) and the second direction (DR2) are not limited to the drawings and should be viewed as relative directions.

[0057] The trench (TH) may be formed by penetrating the well region (118) in the thickness direction (third direction (DR3)) and recessing a portion of the drift region (116), but is not limited thereto. In this case, the trench (TH) may be defined by at least some of the well region (118), the drift region (116), the floating region (160), and the emitter region (170).

[0058] For example, the trench (TH) in which the trench gate electrode (141) is placed may be defined by a well region (118), a drift region (116), and an emitter region (170). The trench (TH) in which the trench emitter electrode (142) is placed may be defined by a well region (118), a drift region (116), and a floating region (150).

[0059] The depth from the other side of the semiconductor substrate (110) to the lower surface of the well region (118) may be shallower than the depth from the other side of the semiconductor substrate (110) to the bottom surface of the trench (TH). Here, the lower surface of the well region (118) may refer to the surface facing the drift region (116).

[0060] The trench gate electrode (141) and the trench emitter electrode (142) may be placed within the trench (TH). The trench gate electrode (141) and the trench emitter electrode (142) extend in a second direction (DR2) and may be alternately and repeatedly placed along a first direction (DR1).

[0061] A trench gate electrode (141) is positioned between adjacent trench emitter electrodes (142) in a first direction (DR1), and the trench emitter electrode (142) can be positioned between adjacent trench gate electrodes (141) in a first direction (DR1).

[0062] The trench emitter electrode (142) can be electrically connected to the emitter electrode (130) through contact. Accordingly, the trench emitter electrode (142) can be supplied with the same potential as that supplied to the emitter electrode (130). For example, 0V can be supplied to the trench emitter electrode (142), but is not limited thereto.

[0063] The trench emitter electrode (142) can be spaced apart from the emitter region (170) with the well region (118) in between.

[0064] As a trench emitter electrode (142) is positioned between adjacent trench gate electrodes (141), the trench (TH) and its surroundings can be electrically protected, thereby improving the reliability of the power semiconductor device (10).

[0065] Specifically, by placing a trench gate electrode (141) between trench emitter electrodes (142), additional parasitic capacitance can be obtained between the trench gate electrode (141) and the trench emitter electrode (142). Additionally, when the power semiconductor device (10) is in operation, the capacitance between the trench gate electrode (141) and the trench emitter electrode (142) can be increased relatively compared to the capacitance between the trench gate electrode (141) and the collector electrode (120).

[0066] When the capacitance between the trench gate electrode (141) and the trench emitter electrode (142) increases, the effect of the displacement current flowing through the capacitance between the trench gate electrode (141) and the collector electrode (120) on the power semiconductor device (10) can be reduced.

[0067] Accordingly, defects such as abnormal power loss and device destruction due to excessive heat generation that may occur in the power semiconductor device (10) can be suppressed or prevented, thereby improving the reliability of the power semiconductor device (10). In other words, the internal electric field of the power semiconductor device (10) can be controlled by charge sharing and the negative gate charge phenomenon can be mitigated.

[0068] The trench gate electrode (141) is positioned between the first and third floating regions (161, 163) in a planar manner and may overlap the second floating region (162) in the thickness direction (DR3) over the entire region. The trench gate electrode (141) may not overlap the first and third floating regions (161, 163) in the thickness direction (DR3), but is not limited thereto.

[0069] The trench emitter electrode (142) is positioned in a planar manner between adjacent second floating regions (162) and may overlap with at least one of the first and third floating regions (161, 163) in the thickness direction (DR3) over the entire area. The trench emitter electrode (142) may not overlap with the second floating region (162) in the thickness direction (DR3), but is not limited thereto.

[0070] The trench emitter electrode (142) may have at least a portion inserted within the first floating region (161).

[0071] The trench gate electrode (141) and the trench emitter electrode (142) may comprise at least one of a conductive material, for example, polysilicon, metal, metal nitride, or metal silicide.

[0072] An insulating layer is disposed around the trench gate electrode (141) and the trench emitter electrode (142), and the trench gate electrode (141) and the trench emitter electrode (142) can be electrically separated by the insulating layer.

[0073] A gate insulating film (151) may be disposed around the trench gate electrode (141), and an emitter insulating film (152) may be disposed around the trench emitter electrode (142). The gate insulating film (151) may be disposed to surround the trench gate electrode (141), and the emitter insulating film (152) may be disposed to surround the trench emitter electrode (142), but is not limited thereto.

[0074] The gate insulating film (151) and the emitter insulating film (152) may be placed in at least a portion of the trench (TH).

[0075] A gate insulating film (151) can be placed between the trench gate electrode (141) and the drift region (116), between the trench gate electrode (141) and the well region (118), between the trench gate electrode (141) and the emitter region (170), and between the trench gate electrode (141) and the emitter electrode (130).

[0076] The emitter insulating film (152) can be placed between the trench emitter electrode (142) and the drift region (116), between the trench emitter electrode (142) and the well region (118), and between the trench emitter electrode (142) and the emitter electrode (130).

[0077] The gate insulating film (151) and the emitter insulating film (152) may protrude from the well region (118) toward the emitter electrode (130), but are not limited thereto.

[0078] By means of the gate insulating layer (151) and the emitter insulating layer (152), the trench gate electrode (141) and the trench emitter electrode (142) can be separated from the emitter electrode (130).

[0079] The gate insulating film (151) and the emitter insulating film (152) may include insulating materials such as silicon oxide, silicon nitride, germanium oxide, germanium nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stacked structure thereof.

[0080] The emitter region (170) may be placed on the well region (118). The emitter region (170) may be a region containing impurities of the first conductivity type. Hereinafter, the emitter region (170) is described as a region containing impurities of the P type, but is not limited thereto.

[0081] The emitter region (170) may be doped with a higher concentration of impurities than the drift region (116), but is not limited thereto.

[0082] The emitter region (170) may be extended along the extension direction of the trench gate electrode (141). The emitter region (170) may be extended along the second direction (DR2).

[0083] The emitter region (170) may be positioned around the trench gate electrode (141). The emitter region (170) may be positioned around the trench gate electrode (141) with the gate insulating film (151) in between. The emitter region (170) may be in direct contact with the side of the gate insulating film (151), but is not limited thereto. Through the gate insulating film (151), the emitter region (170) and the trench gate electrode (141) may be electrically separated.

[0084] The emitter region (170) may be positioned between the emitter electrode (130) and the well region (118). The emitter region (170) may be in contact with the well region (118) and the emitter electrode (130), and may be electrically connected to the well region (118) and the emitter electrode (130). The emitter region (170) may be in direct contact with the well region (118) and the emitter electrode (130), but is not limited thereto.

[0085] The emitter region (170) may be positioned in a plane between adjacent first floating regions (161) and adjacent third floating regions (163). The emitter region (170) may overlap with the second floating region (162) in the thickness direction (third direction (DR3)). The emitter region (170) may not overlap with the first and third floating regions (161, 163) in the thickness direction (DR3), but is not limited thereto.

[0086] The emitter region (170) may define a portion of the trench (TH) where the trench gate electrode (141) is placed. In other words, the trench (TH) where the trench gate electrode (141) is placed is defined by the semiconductor substrate (110) and the emitter region (170), and the trench (TH) where the trench emitter electrode (142) is placed may be defined by the semiconductor substrate (110).

[0087] The floating region (160: 161, 162, 163) may contain impurities having a second conductivity type. The floating region (160: 161, 162, 163) may be a floating region where no bias voltage is applied from the outside.

[0088] Each floating region (160: 161, 162, 163) can cover the lower part of at least one of the trench gate electrode (141) and the trench emitter electrode (142).

[0089] Floating regions (160: 161, 162, 163) may be placed within drift regions (116: DA1, DA2, DA3). In a plane, at least one of each floating region (161, 162, 163) is placed in a different region from the rest, and at least two of each floating region (161, 162, 163) may overlap in the thickness direction (third direction (DR3)).

[0090] The floating area (160) may include a first floating area (161) placed within a first drift area (DA1), a second floating area (162) placed within a second drift area (DA2), and a third floating area (163) placed within a third drift area (DA3).

[0091] The first floating region (161) and the third floating region (163) cover the lower part of the trench emitter electrode (142), and the second floating region (162) can cover the lower part of the trench gate electrode (141).

[0092] The first floating region (161) may be positioned in a planar manner corresponding to the arrangement of the trench emitter electrode (142). The first floating region (161) extends along the second direction (DR2) and may be repeated in the first direction (DR1). The first floating region (161) may overlap the trench emitter electrode (142) in the thickness direction (third direction (DR3)).

[0093] The second floating region (162) may be positioned in a planar manner corresponding to the arrangement of the trench gate electrode (141). The second floating region (162) extends along the second direction (DR2) and may be repeated in the first direction (DR1). The second floating region (162) may overlap with the trench gate electrode (141) in the thickness direction (third direction (DR3)).

[0094] The third floating region (163) may be positioned in a planar manner corresponding to the arrangement of the trench emitter electrode (142). The third floating region (163) extends along the second direction (DR2) and may be repeated in the first direction (DR1). The third floating region (163) may overlap the trench emitter electrode (142) in the thickness direction (third direction (DR3)).

[0095] The first floating area (161) and the third floating area (163) may be placed in substantially the same area on a plane, but are not limited thereto. The first floating area (161) and the third floating area (163) may overlap each other in the thickness direction (third direction (DR3)) over the entire area, but are not limited thereto.

[0096] In a planar view, the first floating area (161) and the third floating area (163) may be placed in areas different from the second floating area (162).

[0097] The first floating area (161) and the third floating area (163) may overlap in the thickness direction (third direction (DR3)). The first floating area (161) and the third floating area (163) may not overlap with the second floating area (162) in the thickness direction (third direction (DR3)), but are not limited thereto.

[0098] In a planar view, the first floating area (161) and the third floating area (163) may be positioned between adjacent second floating areas (162). The second floating area (162) may be positioned between adjacent first floating areas (161) or between adjacent third floating areas (163).

[0099] A first drift area (DA1) may be placed between the first floating area (161) and the second drift area (DA2). A second drift area (DA2) may be placed between the second floating area (162) and the third drift area (DA3).

[0100] However, it is not limited to this. For example, the first floating area (161) may be in direct contact with the second drift area (DA2), or the second floating area (162) may be in direct contact with the third drift area (DA3).

[0101] A third drift area (DA3) may be placed between the third floating area (163) and the collector area (114). Accordingly, it is possible to prevent the collector area (114) and the third floating area (163) from coming into direct contact and short-circuiting.

[0102] Each of the floating regions (160:161, 162, 163) can be formed by injecting a second conductive impurity through a photoresist pattern that exposes the region where each floating region (160:161, 162, 163) is placed.

[0103] Specifically, the first photoresist pattern is placed on the third drift region (DA3) to expose a portion of the area where the third floating region (163) is placed, and the third floating region (163) can be formed by injecting a second conductive impurity into the area exposed by the first photoresist pattern.

[0104] Next, a second drift region (DA2) may be placed on the third drift region (DA3) while covering the third floating region (163). A second photoresist pattern may be placed on the second drift region (DA2) to expose a portion of the area where the second floating region (162) is placed, and a second conductive impurity may be injected into the area exposed by the second photoresist pattern to form the second floating region (162).

[0105] Next, a first drift region (DA1) can be placed on a second drift region (DA2) while covering a second floating region (162). A third photoresist pattern is placed on the first drift region (DA1) to expose a portion of the area where the first floating region (161) is placed, and by injecting a second conductive impurity into the area exposed by the third photoresist pattern, the first floating region (161) can be formed.

[0106] However, the method of forming each floating region (161, 162, 163) is not limited to this.

[0107] The amount of second conductivity type impurity injected into the floating region (160) or the injection energy of the second conductivity type impurity, etc., can be determined to satisfy the size, length, position, doping amount, and ratio of capacitance formed with the surroundings of each floating region (161, 162, 163).

[0108] In this embodiment, the floating region (160: 161, 162, 163) located inside each drift region (116: DA1, DA2, DA3) is not formed by first forming the entire drift region (116) and then performing processes such as etching, photoresist, and polishing. Instead, by inserting the injection process of the floating region (160: 161, 162, 163) in the middle of the epitaxial growth for the drift region (116: DA1, DA2, DA3), the floating region (160: 161, 162, 163) can be formed to a depth that cannot be formed with general injection equipment.

[0109] The first floating area (161) may have a width (W2) wider than the width (W1) of the trench (TH) so as to completely surround the bottom surface of the trench (TH). Here, the width (W1) of the trench (TH) and the width (W2) of the first floating area (161) may refer to the width in the first direction (DR1).

[0110] The second floating area (162) may have a width (W3) wider than the width (W4) of the trench (TH) so as to cover the entire bottom surface of the trench (TH). Here, the width (W3) of the trench (TH) and the width (W4) of the second floating area (162) may refer to the width in the first direction (DR1).

[0111] The third floating area (163) may have a width (W5) wider than the width (W1) of the trench (TH) so as to completely surround the bottom surface of the trench (TH). Here, the width (W1) of the trench (TH) and the width (W5) of the third floating area (163) may refer to the width in the first direction (DR1).

[0112] The width (W5) of the third floating area (163) may be the same as the width (W1) of the first floating area (161), but is not limited thereto.

[0113] As the floating region (160: 161, 162, 163) is positioned, the location where the maximum electric field is applied can be moved toward the collector electrode (120), thereby improving the robustness of the trench gate electrode (141) and the trench emitter electrode (142) and improving the reliability of the power semiconductor device (10).

[0114] Specifically, through the first floating region (161) and the third floating region (163) covering the lower part of the trench emitter electrode (142), the location of the maximum electric field around the trench emitter electrode (142) is moved toward the collector electrode (120), thereby improving the robustness of the trench emitter electrode (142).

[0115] Through the second floating region (162) covering the lower part of the trench gate electrode (141), the position of the maximum electric field around the trench gate electrode (141) is moved toward the collector electrode (120), thereby improving the robustness of the trench gate electrode (141).

[0116] In addition, as the floating region (second floating region (162)) covering the trench gate electrode (141) and the floating region (first floating region (161) and third floating region (163)) covering the trench emitter electrode (142) are placed on different layers, even if the width between the trench gate electrode (141) and the trench emitter electrode (142) (width in the first direction (DR1)) is reduced, the distance between the first floating region (161), the second floating region (162), and the third floating region (163) can be stably maintained or increased.

[0117] To explain this, Figure 5 is further referenced.

[0118] Figure 5 is a graph showing the magnitude of the electric field according to the position of the semiconductor substrate.

[0119] Referring to FIG. 5, the horizontal axis (X-axis) represents the position from the upper surface to the other surface of the semiconductor substrate (110), and the vertical axis (Y) represents the magnitude of the electric field. As one moves from the origin of the graph toward the X-axis direction (to the right on the graph), it represents the depth from the upper surface to the other surface of the semiconductor substrate (110).

[0120] Graph P represents the magnitude of the electric field according to the depth of the semiconductor substrate (110) when the floating region (160) is not placed. Graph O represents the magnitude of the electric field according to the depth of the semiconductor substrate (110) when the floating region (160) is placed.

[0121] The maximum electric field point (EMO) with the largest electric field magnitude in graph O is positioned further to the right of the maximum electric field point (EMP) with the largest electric field magnitude in graph P. The maximum electric field point (EMO) in graph O can be located closer to the lower side of the semiconductor substrate (110) than the maximum electric field point (EMP) in graph P. That is, when the floating region (160) is positioned, the point where the maximum electric field is applied can be moved further to the lower side.

[0122] For example, if the floating region (160) is not included (graph P), the electric field may be concentrated on the bottom surface of the trench (TH) during operation of the IGBT, and the maximum electric field may be formed on the bottom surface of the trench (TH). As the electric field is concentrated on the bottom surface of the trench (TH), the breakdown voltage of the IGBT may be lowered. This reduction in breakdown voltage may make normal switching operation of the IGBT impossible.

[0123] However, when the floating region (160) is positioned (graph O), if the floating region (160) completely covers the bottom surface of the trench (TH), the electric field is not concentrated on the bottom surface of the trench (TH), but rather the electric field is concentrated on the bottom surface of the floating region (160) (the surface close to the collector electrode (120)) (charge sharing), so that the maximum electric field can be formed on the bottom surface of the floating region (160).

[0124] Therefore, the breakdown voltage of the IGBT does not decrease, and the switching performance of the IGBT can be secured. That is, due to the floating region (160), the IGBT can perform switching operations even in a high-voltage environment, so the voltage withstand characteristics can be improved.

[0125] Figure 6 shows the breakdown voltage (BV, BV, Breakdown Voltage) according to the P doping ratio in the floating region and the drift region.

[0126] Referring to FIG. 6, the horizontal axis (X-axis) represents the amount of P doping (QP) of the floating region (160) / (amount of P doping (QP) of the floating region (160) + amount of N doping (QN) of the drift region (116), and the vertical axis (Y-axis) represents the internal pressure (BV). The horizontal axis of FIG. 6 represents the ratio of the amount of P doping of the floating region (160) to the amount of P and N doping of the floating region (160) and the drift region (116) (hereinafter referred to as the P doping ratio), and may also represent the volume ratio of the floating region (160) to the combined area of ​​the floating region (160) and the drift region (116).

[0127] The P doping ratio of the floating region (160) may be 54% or higher. In this case, the withstand voltage may be 800.00V or higher. When the withstand voltage is 800.00V or higher, sufficient breakdown voltage and robustness of the power semiconductor device (10) can be secured, and the reliability of the power semiconductor device (10) can be improved.

[0128] Again, referring to FIGS. 3 and FIGS. 4, the semiconductor device (10) can be irradiated with protons in at least some regions.

[0129] As protons are irradiated onto a semiconductor device (10), defects may be created within the silicon (Si) lattice. Due to the defects in the silicon lattice, the coupling rate between holes and carriers is increased, which can improve the turn-off speed of the semiconductor device (10). The concentration of hole carriers in the region irradiated with protons may be lower than in other regions.

[0130] Although not limited thereto, proton irradiation may be performed on at least one region of the semiconductor device (10). In this embodiment, the semiconductor device (10) is described as having been irradiated with protons on two regions, but is not limited thereto.

[0131] The semiconductor device (10) may further include a first proton irradiation region (PI1) and a second proton irradiation region (PI2).

[0132] The first proton irradiation area (PI1) may be formed around the boundary between the first drift area (DA1) and the second drift area (DA2). Specifically, the first proton irradiation area (PI1) may be formed over the upper surface of the second drift area (DA2), the upper surface of the second floating area (162), the lower surface of the first drift area (DA1), and the lower surface of the first floating area (161).

[0133] A second proton irradiation area (PI2) may be formed around the boundary between the collector area (114) and the collector electrode (120). The second proton irradiation area (PI2) may be formed over the lower surface of the collector area (114) and over the upper surface of the collector electrode (120).

[0134] The first proton irradiation region (PI1) and the second proton irradiation region (PI2) may have a lower hole-carrier concentration than other regions of the semiconductor substrate (110). The closer to either the first proton irradiation region (PI1) or the second proton irradiation region (PI2) on the semiconductor substrate (110), the lower the hole-carrier concentration, and the further away from the first proton irradiation region (PI1) and the second proton irradiation region (PI2), the higher the hole-carrier concentration may be, but is not limited thereto.

[0135] The first proton irradiation region (PI1) and the second proton irradiation region (PI2) can be formed by a single proton irradiation process. In this case, by irradiating protons with different proton irradiation energies, the first proton irradiation region (PI1) and the second proton irradiation region (PI2) at different depths can be formed.

[0136] However, this is not limited thereto, and the first proton irradiation region (PI1) and the second proton irradiation region (PI2) may each be formed by a separate proton irradiation process.

[0137] The first proton irradiation region (PI1) and the second proton irradiation region (PI2) can be formed by two proton elements with different proton irradiation energies. The proton irradiation energy required to form the first proton irradiation region (PI1) may be greater than the proton irradiation energy required to form the second proton irradiation region (PI2).

[0138] For example, the proton irradiation energy required for the first proton irradiation region (PI1) may be in the range of 1 MeV to 99 MeV. The proton irradiation energy required for the second proton irradiation region (PI2) may be in the range of 1 / 5 to 1 / 20 of the proton irradiation energy required for the first proton irradiation region (PI1), or 1 / 10.

[0139] As the power semiconductor device (10) includes a first proton irradiation region (PI1) and a second proton irradiation region (PI2), a high voltage power device IGBT with improved trade-off characteristics between low saturation voltage (Vce(sat)) and offset voltage (Eoff) can be obtained.

[0140] In addition, as proton irradiation is performed in two different regions, the control of the proton irradiation dose can be made easier, thereby allowing for smoother reduction of the snapback phenomenon of the low saturation voltage Vce(sat), smoother reduction of the deviation of the low saturation voltage Vce(sat), and minimization of losses in switching characteristics.

[0141] Hereinafter, other embodiments of the present specification will be described. Among the configurations included in the other embodiments, those that are substantially identical to those described with reference to FIGS. 1 to 6 are given the same reference numerals, and duplicate content may be omitted or simplified.

[0142] FIG. 7 is an enlarged view of a portion of a cell region according to another embodiment. FIG. 8 is a cross-sectional view cut along the line BB' of FIG. 7.

[0143] Referring to FIGS. 7 and 8, a power semiconductor device (10_1) according to the present embodiment may include a drift region (116_1) comprising a first drift region (DA1) and a second drift region (DA2), and a floating region (160_1) comprising a first floating region (161) disposed within the first drift region (DA1) and a second floating region (162) disposed within the second drift region (DA2).

[0144] In other words, in the embodiments of FIGS. 3 and 4, the third drift region (DA3, see FIG. 4) and the third floating region (163, see FIG. 4) may be omitted.

[0145] The second drift area (DA2) can be in direct contact with the collector area (114). The second drift area (DA2) can be positioned between the second floating area (162) and the collector area (114). Accordingly, it is possible to prevent the collector area (114) and the second floating area (162) from being in direct contact and short-circuited.

[0146] Accordingly, the process of forming the drift region (160_1) can be simplified while covering both the trench gate electrode (141) and the trench emitter electrode (142) through the first floating region (161) and the second floating region (162).

[0147] In this case as well, as the first proton irradiation region (PI1) and the second proton irradiation region (PI2) are arranged, a high-voltage power device IGBT with improved trade-off characteristics between low saturation voltage (Vce(sat)) and offset voltage (Eoff) can be obtained.

[0148] FIG. 9 is a cross-sectional view of a power semiconductor device according to another embodiment.

[0149] Referring to FIG. 9, the power semiconductor device (10_2) according to the present embodiment may include a drift region (116_2) and a floating region (160_2). The drift region (116_2) may further include a fourth drift region (DA4) disposed between a third drift region (DA3) and a collector region (114), and the floating region (160_2) may further include a fourth floating region (164) disposed within the fourth drift region (DA4).

[0150] The fourth drift area (DA4) may be substantially the same as the second drift area (DA2), and the fourth floating area (164) may be substantially the same as the second floating area (162).

[0151] The fourth floating region (164) can cover the lower part of the trench gate electrode (141). A fourth drift region (DA4) can be placed between the fourth floating region (164) and the collector region (114).

[0152] The trench gate electrode (141) is covered by a floating region (162, 164) composed of multiple layers, and the trench emitter electrode (142) can be covered by a floating region (161, 163) composed of multiple layers.

[0153] Here, the floating regions (160_2) covering each of the trench gate electrode (141) and trench emitter electrode (142) are described as having two each, but are not limited thereto, and the floating regions covering each may be provided in multiples of three or more.

[0154] Accordingly, through the fourth floating region (164), the trench gate electrode (141) can be protected more smoothly, and the robustness of the trench gate electrode (141) can be further improved.

[0155] In this case as well, as the first proton irradiation region (PI1) and the second proton irradiation region (PI2) are arranged, a high-voltage power device IGBT with improved trade-off characteristics between low saturation voltage (Vce(sat)) and offset voltage (Eoff) can be obtained.

[0157] Power semiconductor devices and power semiconductor chips including the same according to various embodiments of the present specification may be described as follows.

[0158] A power semiconductor device according to embodiments of the present specification comprises a collector electrode, an emitter electrode disposed on the collector electrode, a semiconductor substrate disposed between the collector electrode and the emitter electrode and defining a plurality of trenches recessed from the upper surface, a trench gate electrode disposed within the plurality of trenches and insulated from the emitter electrode, a trench emitter electrode disposed within the plurality of trenches and electrically connected to the emitter electrode, and a floating region including a first floating region covering the lower portion of the trench emitter electrode and a second floating region covering the lower portion of the trench gate electrode, wherein the first floating region and the second floating region are disposed on different layers.

[0159] According to various embodiments of the present specification, the semiconductor substrate further comprises a first drift region and a second drift region that are sequentially stacked, and the first floating region may be disposed within the first drift region and the second floating region may be disposed within the second drift region.

[0160] According to various embodiments of the present specification, the second drift region may further include a third drift region disposed between the first drift region and the collector electrode, a third floating region disposed between the second drift region and the collector electrode, and a third floating region disposed within the third drift region.

[0161] According to various embodiments of the present specification, the third floating region may overlap with the first floating region in the thickness direction.

[0162] According to various embodiments of the present specification, a first floating region and a second floating region on a plane are alternately arranged along a first direction and may be extended along a second direction that intersects the first direction.

[0163] According to various embodiments of the present specification, the trench gate electrode and the trench emitter electrode may be repeatedly arranged along the first direction and extended along the second direction.

[0164] According to various embodiments of the present specification, the semiconductor substrate may further include a well region disposed between the first drift region and the emitter electrode, and a collector region disposed between the second drift region and the collector electrode.

[0165] According to various embodiments of the present specification, the apparatus further comprises a collector region disposed between the second drift region and the collector electrode, wherein the second drift region is disposed between the first drift region and the collector electrode, and the second drift region and the collector region can be in direct contact.

[0166] According to various embodiments of the present specification, the semiconductor substrate further comprises a first proton irradiation region formed within the semiconductor substrate and a second proton irradiation region formed around the boundary between the semiconductor substrate and the collector electrode, wherein silicon (Si) lattice defects may occur in the first proton irradiation region and the second proton irradiation region.

[0167] According to various embodiments of the present specification, the semiconductor substrate comprises a drift region including a first drift region and a second drift region that are sequentially stacked and includes an impurity having a first conductivity type, a collector region disposed between the drift region and the collector electrode and including an impurity having a second conductivity type different from the first conductivity type, and a well region disposed between the emitter electrode and the drift region and including an impurity having the second conductivity type, wherein the first proton irradiation region may be formed around the boundary between the first drift region and the second drift region, and the second proton irradiation region may be formed around the boundary between the collector region and the collector electrode.

[0168] According to various embodiments of the present specification, the first floating region is disposed within the first drift region, the second floating region is disposed within the second drift region, and the first proton irradiation region may be formed to include a portion of the first floating region and the second floating region.

[0169] According to various embodiments of the present specification, the first floating region and the second floating region may be floating regions to which a bias voltage is not applied from the outside.

[0170] According to various embodiments of the present specification, an emitter region may be further included that is disposed around the plurality of trench gate electrodes between the emitter electrode and the semiconductor substrate and contains an impurity having a first conductivity type.

[0171] According to various embodiments of the present specification, the semiconductor substrate comprises a drift region containing an impurity having the first conductivity type, a collector region disposed between the drift region and the collector electrode and containing an impurity having a second conductivity type different from the first conductivity type, and a well region disposed between the emitter electrode and the drift region and containing an impurity having the second conductivity type, wherein the drift region may include a first drift region in which the first floating region is disposed and a second drift region in which the second floating region is disposed.

[0172] According to various embodiments of the present specification, the drift region and the emitter region may contain impurities having the N type, and the collector region and the well region may contain impurities having the P type.

[0173] A power semiconductor device according to the embodiments of the present specification comprises a collector electrode, an emitter electrode disposed on the collector electrode, a drift region disposed between the collector electrode and the emitter electrode and including a first drift region and a second drift region sequentially stacked, a floating region including a first floating region disposed within the first drift region and a second floating region disposed within the second drift region, a collector region disposed between the second drift region and the collector electrode, a first proton irradiation region formed around the boundary between the first drift region and the second drift region, and a second proton irradiation region formed around the boundary between the collector region and the collector electrode, wherein the first proton irradiation region and the second proton irradiation region are regions where silicon (Si) lattice defects occur.

[0174] According to various embodiments of the present specification, the drift region may include an impurity having a first conductivity type, the collector region may include an impurity having a second conductivity type different from the first conductivity type, the first proton irradiation region may be formed around the boundary between the first drift region and the second drift region, and the second proton irradiation region may be formed around the boundary between the collector region and the collector electrode.

[0175] According to various embodiments of the present specification, the first floating region is disposed within the first drift region, the second floating region is disposed within the second drift region, and the first proton irradiation region may be formed to include a portion of the first floating region and the second floating region.

[0176] According to various embodiments of the present specification, a plurality of trench gate electrodes and a plurality of trench emitter electrodes disposed between the first drift region and the emitter electrode are further included, wherein the first floating region covers the lower part of the trench emitter electrode and the second floating region can cover the lower part of the trench gate electrode.

[0177] According to various embodiments of the present specification, each of the first floating region and the second floating region is provided in plurality, and the plurality of first floating regions and the plurality of second floating regions are alternately and repeatedly arranged along a first direction and extend along a second direction intersecting the first direction, and the plurality of trench gate electrodes and the plurality of trench emitter electrodes are alternately and repeatedly arranged along the first direction and extend along the second direction.

[0178] Although embodiments have been described above with reference to the attached drawings, those skilled in the art to which this specification pertains will understand that the technical configurations described above may be implemented in other specific forms without altering the technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Furthermore, the scope of the embodiments is defined by the claims set forth below rather than by the detailed description. Additionally, all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of the embodiments. Explanation of the symbols

[0179] 10: Power semiconductor devices 20: Power semiconductor chip 100: Cell range 200: Surrounding area 110: Semiconductor substrate 120: Collector electrode 130: Emitter electrode 114: Collector Area 116(DA1, DA2, DA3): Drift Zone 118: Well area 141: Trench gate electrode 142: Trench emitter electrode 160(161, 162, 163): Floating region 170: Emitter area PI: Proton Irradiation Zone

Claims

Claim 1 A power semiconductor device comprising: a collector electrode; an emitter electrode disposed on the collector electrode; a semiconductor substrate disposed between the collector electrode and the emitter electrode and defining a plurality of trenches recessed from the upper surface; a trench gate electrode disposed within the plurality of trenches and insulated from the emitter electrode; a trench emitter electrode disposed within the plurality of trenches and electrically connected to the emitter electrode; and a floating region comprising a first floating region covering the lower portion of the trench emitter electrode and a second floating region covering the lower portion of the trench gate electrode, wherein the first floating region and the second floating region are disposed on different layers. Claim 2 A power semiconductor device according to claim 1, wherein the semiconductor substrate further comprises a first drift region and a second drift region that are sequentially stacked, the first floating region is disposed within the first drift region, and the second floating region is disposed within the second drift region. Claim 3 A power semiconductor device according to claim 2, wherein the second drift region is disposed between the first drift region and the collector electrode, and further comprises a third drift region disposed between the second drift region and the collector electrode, and a third floating region disposed within the third drift region. Claim 4 In claim 3, the third floating region is a power semiconductor device that overlaps the first floating region in the thickness direction. Claim 5 A power semiconductor device according to claim 2, wherein a first floating region and a second floating region on a plane are alternately and repeatedly arranged along a first direction, and extends along a second direction intersecting the first direction. Claim 6 A power semiconductor device according to claim 5, wherein the trench gate electrode and the trench emitter electrode are repeatedly arranged along the first direction and extend along the second direction. Claim 7 In claim 2, the semiconductor substrate further comprises a well region disposed between the first drift region and the emitter electrode, and a collector region disposed between the second drift region and the collector electrode, forming a power semiconductor device. Claim 8 A power semiconductor device according to claim 2, further comprising a collector region disposed between the second drift region and the collector electrode, wherein the second drift region is disposed between the first drift region and the collector electrode, and the second drift region and the collector region are in direct contact. Claim 9 The power semiconductor device according to claim 1 further comprises a first proton irradiation region formed inside the semiconductor substrate and a second proton irradiation region formed around the boundary between the semiconductor substrate and the collector electrode, wherein the first proton irradiation region and the second proton irradiation region are formed with silicon (Si) lattice defects. Claim 10 A power semiconductor device according to claim 9, wherein the semiconductor substrate comprises a drift region including a first drift region and a second drift region that are sequentially stacked and includes an impurity having a first conductivity type, a collector region disposed between the drift region and the collector electrode and including an impurity having a second conductivity type different from the first conductivity type, and a well region disposed between the emitter electrode and the drift region and including an impurity having the second conductivity type, wherein the first proton irradiation region is formed around the boundary between the first drift region and the second drift region, and the second proton irradiation region is formed around the boundary between the collector region and the collector electrode. Claim 11 A power semiconductor device according to claim 10, wherein the first floating region is disposed within the first drift region, the second floating region is disposed within the second drift region, and the first proton irradiation region is formed to include a portion of the first floating region and the second floating region. Claim 12 A power semiconductor device according to claim 1, wherein the first floating region and the second floating region are floating regions to which a bias voltage is not applied from the outside. Claim 13 A power semiconductor device according to claim 1, further comprising an emitter region disposed around a plurality of trench gate electrodes between the emitter electrode and the semiconductor substrate and including an impurity having a first conductivity type. Claim 14 A power semiconductor device according to claim 13, wherein the semiconductor substrate comprises a drift region containing an impurity having the first conductivity type, a collector region disposed between the drift region and the collector electrode and containing an impurity having a second conductivity type different from the first conductivity type, and a well region disposed between the emitter electrode and the drift region and containing an impurity having the second conductivity type, wherein the drift region comprises a first drift region in which the first floating region is disposed and a second drift region in which the second floating region is disposed. Claim 15 A power semiconductor device according to claim 14, wherein the drift region and the emitter region contain N-type impurities, and the collector region and the well region contain P-type impurities. Claim 16 A power semiconductor device comprising: a collector electrode; an emitter electrode disposed on the collector electrode; a drift region disposed between the collector electrode and the emitter electrode and including a first drift region and a second drift region sequentially stacked; a floating region including a first floating region disposed within the first drift region and a second floating region disposed within the second drift region; a collector region disposed between the second drift region and the collector electrode; a first proton irradiation region formed around the boundary between the first drift region and the second drift region; and a second proton irradiation region formed around the boundary between the collector region and the collector electrode, wherein the first proton irradiation region and the second proton irradiation region are regions in which silicon (Si) lattice defects occur. Claim 17 A power semiconductor device according to claim 16, wherein the drift region comprises an impurity having a first conductivity type, the collector region comprises an impurity having a second conductivity type different from the first conductivity type, the first proton irradiation region is formed around the boundary between the first drift region and the second drift region, and the second proton irradiation region is formed around the boundary between the collector region and the collector electrode. Claim 18 A power semiconductor device according to claim 17, wherein the first floating region is disposed within the first drift region, the second floating region is disposed within the second drift region, and the first proton irradiation region is formed to include a portion of the first floating region and the second floating region. Claim 19 A power semiconductor device according to claim 16, further comprising a plurality of trench gate electrodes and a plurality of trench emitter electrodes disposed between the first drift region and the emitter electrode, wherein the first floating region covers the lower part of the trench emitter electrode and the second floating region covers the lower part of the trench gate electrode. Claim 20 A power semiconductor device according to claim 19, wherein each of the first floating region and the second floating region is provided in plurality, and the plurality of first floating regions and the plurality of second floating regions are alternately arranged along a first direction and extend along a second direction intersecting the first direction, and the plurality of trench gate electrodes and the plurality of trench emitter electrodes are alternately arranged along the first direction and extend along the second direction.

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