Memory device and manufacturing method of the memory device

Abstract

A memory device according to an embodiment of the present invention comprises a laminate including alternatingly stacked conductive films and interlayer insulating films, cell plugs penetrating the laminate, a support pattern spaced apart from the laminate and the cell plugs and including a penetrating region, and contacts penetrating the support pattern through the penetrating region, wherein the support pattern may include openings arranged along a first direction and a second direction intersecting the first direction.

Description

Technology Field

[0001] The present invention relates to a memory device and a method for manufacturing the same, and more specifically, to a memory device including a memory block having a three-dimensional structure and a method for manufacturing the same. Background Technology

[0002] A memory device may include a non-volatile memory device in which stored data is retained even when the power supply is cut off. Non-volatile memory devices can be classified into two-dimensional or three-dimensional structures depending on the structure in which memory cells are arranged. Memory cells of a non-volatile memory device having a two-dimensional structure may be arranged in a single layer on a substrate, while memory cells of a non-volatile memory device having a three-dimensional structure may be stacked vertically on a substrate. Since the integration density of a non-volatile memory device having a three-dimensional structure is higher than that of a non-volatile memory device having a two-dimensional structure, electronic devices using non-volatile memory devices having a three-dimensional structure have recently been increasing. The problem to be solved

[0003] An embodiment of the present invention provides a memory device capable of reducing bending of the memory device and a method for manufacturing the same. means of solving the problem

[0004] A memory device according to an embodiment of the present invention comprises a laminate including alternatingly stacked conductive films and interlayer insulating films, cell plugs penetrating the laminate, a support pattern spaced apart from the laminate and the cell plugs and including a penetrating region, and contacts penetrating the support pattern through the penetrating region, wherein the support pattern may include openings arranged along a first direction and a second direction intersecting the first direction.

[0005] A method for manufacturing a memory device according to an embodiment of the present invention may include the steps of: forming a support film; removing a portion of the support film to form a support pattern comprising openings arranged along a first direction and a second direction intersecting the first direction, and a penetration area wider than the openings; forming an insulating film that fills the openings and the penetration area; and forming a contact that penetrates the insulating film and extends into the penetration area. Effects of the invention

[0006] This technology can reduce the bending of memory devices by adding a structural configuration. Brief explanation of the drawing

[0007] FIG. 1 is a drawing for explaining a memory device according to an embodiment of the present invention. FIG. 2 is a diagram for schematically explaining a memory device according to an embodiment of the present invention. FIGS. 3a to 3d are drawings for explaining support patterns included in a memory device according to an embodiment of the present invention. FIGS. 4a to 4e are drawings for explaining a method of manufacturing a support pattern according to an embodiment of the present invention. FIGS. 5A and FIGS. 5B are drawings for illustrating various embodiments of a support pattern according to the present invention. FIG. 6 is a drawing for explaining a memory card system to which the memory device of the present invention is applied. FIG. 7 is a diagram illustrating a Solid State Drive (SSD) system to which the memory device of the present invention is applied. Specific details for implementing the invention

[0008] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0009] Hereinafter, in order to explain in detail enough for a person skilled in the art to implement the technical concept of the present invention, embodiments of the present invention will be described with reference to the attached drawings.

[0011] FIG. 1 is a drawing for explaining a memory device according to an embodiment of the present invention.

[0012] Referring to FIG. 1, a memory device (100) may include a memory cell array (110), a peripheral circuit (170), and a control circuit (180).

[0013] The memory cell array (110) may include first to i-th memory blocks (BLK1 to BLKi). Each of the first to i-th memory blocks (BLK1 to BLKi) may include memory cells capable of storing data. Drain select lines (DSL), word lines (WL), source select lines (SSL), and source lines (SL) may be connected to each of the first to i-th memory blocks (BLK1 to BLKi), and bit lines (BL) may be connected in common to the first to i-th memory blocks (BLK1 to BLKi).

[0014] The first to i-th memory blocks (BLK1 to BLKi) may be formed in a three-dimensional structure. Memory blocks having a three-dimensional structure may include memory cells stacked vertically on a substrate. Memory blocks may include a laminate composed of conductive films and interlayer insulating films alternately stacked in a vertical direction. Since the laminate has a shape that extends in one direction, bending of the memory blocks may be induced. However, according to the present disclosure, defects included in the memory device (100) may be reduced by adding support patterns that can reduce the bending of the memory blocks. Support patterns will be described later with reference to FIG. 3a.

[0015] Memory cells can store 1 bit or 2 or more bits of data depending on the programming method. For example, the method of storing 1 bit of data in a single memory cell is called the single-level cell method, and the method of storing 2 bits of data is called the multi-level cell method. The method of storing 3 bits of data in a single memory cell is called the triple-level cell method, and the method of storing 4 bits of data is called the quad-level cell method. In addition, 5 bits or more of data may be stored in a single memory cell.

[0016] The peripheral circuit (170) may be configured to perform a program operation for storing data in the memory cell array (110), a read operation for outputting data stored in the memory cell array (110), and an erase operation for erasing data stored in the memory cell array (110). For example, the peripheral circuit (170) may include a voltage generator (120), a row decoder (130), a page buffer group (140), a column decoder (150), and an input / output circuit (160).

[0017] The voltage generator (120) can generate various operating voltages (Vop) used for program operation, read operation, or erase operation in response to the operation code (OPCD). For example, the voltage generator (120) can be configured to generate program voltages, turn-on voltages, turn-off voltages, negative voltages, precharge voltages, verify voltages, read voltages, pass voltages, or erase voltages in response to the operation code (OPCD). The operating voltages (Vop) generated by the voltage generator (120) can be applied to the drain select lines (DSL), word lines (WL), source select lines (SSL), and source line (SL) of the memory block selected through the row decoder (130).

[0018] Program voltages are voltages applied to a selected word line among the word lines (WL) during a program operation, and can be used to raise the threshold voltage of the memory cells connected to the selected word line. Turn-on voltages can be applied to drain select lines (DSL) or source select lines (SSL) and can be used to turn on drain select transistors or source select transistors. Turn-off voltages can be applied to drain select lines (DSL) or source select lines (SSL) and can be used to turn off drain select transistors or source select transistors. For example, the turn-off voltage can be set to 0V. Precharge voltages are voltages higher than 0V and can be applied to bit lines during a read operation. Verification voltages can be used during a verification operation to determine whether the threshold voltage of the selected memory cells has been raised to a target level. Verification voltages can be set to various levels depending on the target level and can be applied to the selected word line.

[0019] Read voltages can be applied to selected word lines during a read operation of selected memory cells. For example, read voltages can be set to various levels depending on the programming method of the selected memory cells. Pass voltages are voltages applied to unselected word lines among the word lines (WL) during a program or read operation, and can be used to turn on memory cells connected to the unselected word lines. Erase voltages can be used during an erase operation to erase memory cells included in a selected memory block, and can be applied to the source line (SL).

[0020] The row decoder (130) may be configured to transmit operating voltages (Vop) to drain select lines (DSL), word lines (WL), source select lines (SSL), and source line (SL) connected to a memory block selected according to a row address (RADD). For example, the row decoder (130) may be connected to a voltage generator (120) via global lines and to first to i-th memory blocks (BLK1 to BLKi) via drain select lines (DSL), word lines (WL), source select lines (SSL), and source line (SL).

[0021] A page buffer group (140) may include page buffers (not shown) each connected to the first to i-th memory blocks (BLK1 to BLKi). Each of the page buffers (not shown) may be connected to the first to i-th memory blocks (BLK1 to BLKi) via bit lines (BL). During a read operation, the page buffers (not shown) may sense the current or voltage of the bit lines, which vary according to the threshold voltages of the selected memory cells, in response to page buffer control signals (PBSIG), and temporarily store the sensed data.

[0022] A column decoder (150) may be configured to transmit data between a page buffer group (140) and an input / output circuit (160) in response to a column address (CADD). For example, the column decoder (150) may be connected to the page buffer group (140) via column lines (CL) and may transmit enable signals via column lines (CL). Page buffers (not shown) included in the page buffer group (140) may receive or output data via data lines (DL) in response to the enable signals.

[0023] The input / output circuit (160) may be configured to receive or output commands (CMD), addresses (ADD), or data through input / output lines (I / O). For example, the input / output circuit (160) may transmit commands (CMD) and addresses (ADD) received from an external controller through input / output lines (I / O) to the control circuit (180), and transmit data received from an external controller through input / output lines (I / O) to the page buffer group (140). Alternatively, the input / output circuit (160) may output data received from the page buffer group (140) to an external controller through input / output lines (I / O).

[0024] The control circuit (180) can output at least one of an operation code (OPCD), a row address (RADD), page buffer control signals (PBSIG), or a column address (CADD) in response to a command (CMD) and an address (ADD). For example, if the command (CMD) input to the control circuit (180) is a command corresponding to a program operation, the control circuit (180) can control the peripheral circuit (170) to perform a program operation of the memory block selected by the address (ADD). If the command (CMD) input to the control circuit (180) is a command corresponding to a read operation, the control circuit (180) can control the peripheral circuit (170) to perform a read operation of the memory block selected by the address and output the read data. If the command (CMD) input to the control circuit (180) is a command corresponding to an erase operation, the control circuit (180) can control the peripheral circuit (170) so that the erase operation of the selected memory block is performed.

[0026] FIG. 2 is a diagram for schematically explaining a memory device according to an embodiment of the present invention.

[0027] Referring to FIG. 2, the memory device (100) may include a peripheral circuit structure (PC) disposed on a substrate (SUB) and first to i-th memory blocks (BLK1 to BLKi). The first to i-th memory blocks (BLK1 to BLKi) may be superimposed on the peripheral circuit structure (PC).

[0028] The substrate (SUB) may be a single-crystal semiconductor film. For example, the substrate (SUB) may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed through a selective epitaxial growth method.

[0029] The peripheral circuit structure (PC) may include a row decoder (130), a column decoder (150), a page buffer group (140), and a control circuit (180), etc., which constitute a circuit for controlling the operation of the first to i-th memory blocks (BLK1 to BLKi). For example, the peripheral circuit structure (PC) may include an NMOS transistor, a PMOS transistor, a resistor, and a capacitor, etc., which are electrically connected to the first to i-th memory blocks (BLK1 to BLKi). The peripheral circuit structure (PC) may be placed between the substrate (SUB) and the first to i-th memory blocks (BLK1 to BLKi).

[0030] Each of the first to i-th memory blocks (BLK1 to BLKi) may include a source structure, bit lines, cell strings electrically connected to the source structure and bit lines, word lines electrically connected to the cell strings, and select lines electrically connected to the cell strings. Each of the cell strings may include memory cells and select transistors connected in series by a cell plug. Each of the select lines may be used as the gate electrode of the corresponding select transistor, and each of the word lines may be used as the gate electrode of the corresponding memory cell. The first to i-th memory blocks (BLK1 to BLKi) may be separated from one another by slits.

[0031] The first to i-th memory blocks (BLK1 to BLKi) may each have a shape that extends in the X direction. Therefore, bending may be induced within the first to i-th memory blocks (BLK1 to BLKi). However, according to the present disclosure, by adding support patterns capable of reducing bending of the first to i-th memory blocks (BLK1 to BLKi), defects included in the memory device (100) may be reduced. Support patterns will be described later with reference to FIG. 3a.

[0032] As another embodiment, the substrate (SUB), peripheral circuit structure (PC), and the first to i-th memory blocks (BLK1 to BLKi) may be stacked in reverse order of the order shown in FIG. 2. For example, the peripheral circuit structure (PC) may be placed on the first to i-th memory blocks (BLK1 to BLKi).

[0033] As another embodiment, unlike that shown in FIG. 2, the peripheral circuit structure (PC) may be placed on a portion of the substrate (SUB) that does not overlap with the first to i-th memory blocks (BLK1 to BLKi). For example, the peripheral circuit structure (PC) and the first to i-th memory blocks (BLK1 to BLKi) may each be placed on areas on the substrate (SUB) that do not overlap with each other.

[0035] FIGS. 3a to 3d are drawings for explaining support patterns included in a memory device according to an embodiment of the present invention. FIG. 3b is a plan view corresponding to the AA' cross section of FIG. 3a. FIG. 3c is a plan view corresponding to the BB' cross section of FIG. 3a. FIG. 3d is a plan view corresponding to the CC' cross section of FIG. 3a.

[0036] Referring to FIG. 3a, a memory device (e.g., memory device (100) of FIG. 1 and 2, at least one memory block among the first to i-th memory blocks (BLK1 to BLKi) of FIG. 2) may include a stack (STK) and a dummy stack (DST). A separation structure (SR) may be located between the stack (STK) and the dummy stack (DST). The dummy stack (DST) may be spaced apart from the stack (STK) with the separation structure (SR) in between.

[0037] The laminate (STK) may include conductive films (CD) and interlayer insulating films (IL). The conductive films (CD) and interlayer insulating films (IL) may be stacked alternately along the Z direction. The conductive films (CD) may include at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polysilicon (poly-Si). The interlayer insulating films (IL) may be formed of an oxide film (e.g., silicon oxide). The conductive films (CD) may correspond to gate lines (e.g., drain select line (DSL), word line (WL), source select line (SSL) of FIG. 1).

[0038] The laminate (STK) may include a step structure. The laminate (STK) may include a plurality of steps. Each of the plurality of steps may be composed of a pair of conductive films (CD) and an interlayer insulating film (IL). For example, each of the plurality of steps may include a layer of conductive film (CD) and an interlayer insulating film (IL) beneath the conductive film (CD). As another example, unlike the illustration in FIG. 3a, each of the plurality of steps may include a layer of conductive film (CD) and an interlayer insulating film (IL) on the conductive film (CD). FIG. 3a illustrates steps arranged along the X direction, but the form of the step structure is not limited by the illustration in FIG. 3a. For example, the laminate (STK) may include steps arranged along the Y direction. As another example, the laminate (STK) may include steps arranged along both the X direction and the Y direction. In addition, the steps shown in Fig. 3a illustrate only a part of the laminate (STK), and a number of steps corresponding to the number of layers of conductive films (CD) can be formed.

[0039] The dummy stack (DST) may include sacrificial films (SF) and interlayer insulating films (IL). The sacrificial films (SF) and interlayer insulating films (IL) may be stacked alternately along the Z direction. The sacrificial films (SF) may include an insulator having an etch selectivity ratio with respect to the interlayer insulating films (IL). For example, the interlayer insulating films (IL) may include an oxide film (e.g., silicon oxide), and the sacrificial films (SF) may include a nitride film. The sacrificial films (SF) of the dummy stack (DST) may be located at the same level as the conductive films (CD) of the stack (STK), respectively. The sacrificial films (SF) may be spaced apart from the conductive films (CD) by a separation structure (SR). The interlayer insulating films (IL) of the dummy stack (DST) may be located at the same level as the interlayer insulating films (IL) of the stack (STK) and may include the same material.

[0040] A first upper insulating film (UIL1) may be disposed on a laminate (STK) and a dummy laminate (DST). The first upper insulating film (UIL1) may cover the laminate (STK) and the dummy laminate (DST). The first upper insulating film (UIL1) may cover the stepped structure of the laminate (STK).

[0041] A separation structure (SR) may be placed between a laminate (STK) and a dummy laminate (DST). The separation structure (SR) may separate the dummy laminate (DST) from the laminate (STK). In one embodiment, a pre-laminated laminate is formed in which sacrificial films (SF) and interlayer insulating films (IL) are alternately stacked, and a laminate (STK) may be formed by replacing some of the sacrificial films (SF) with conductive films (CD). At this time, the sacrificial films (SF) that remain without being replaced by conductive films (CD) may constitute the dummy laminate (DST). For example, while some of the sacrificial films are removed from the pre-laminated laminate, the sacrificial films (SF) corresponding to the dummy laminate (DST) may not be removed by the separation structure (SR). The separation structure (SR) may include an insulating material such as an oxide film.

[0042] A source structure (SC) may be disposed at the bottom of a stack (STK). The source structure (SC) may be superimposed on the stack (STK). The source structure (SC) may extend from the bottom of the stack (STK) to the bottom of a dummy stack (DST). The source structure (SC) may include an upper source structure (USC), an interlayer source structure (FSC), and a lower source structure (LSC). The interlayer source structure (FSC) may be located between the upper source structure (USC) and the lower source structure (LSC). The source structure (SC) may correspond to the source line (SL) of FIG. 1.

[0043] In one embodiment, a lower source structure (LSC), a source sacrifice layer, and an upper source structure (USC) are sequentially stacked, and after cell plugs (CPL) are formed, the source sacrifice layer may be replaced by an interlayer source structure (FSC) to form a source structure (SC). A portion of the memory film (ML) may be etched through the space where the source sacrifice layer was removed, thereby exposing the channel film (CH). Thus, the interlayer source structure (FSC) can come into direct contact with the channel film (CH).

[0044] Each of the upper source structure (USC), interlayer source structure (FSC), and lower source structure (LSC) may comprise a semiconductor material (e.g., silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof). Each of the upper source structure (USC), interlayer source structure (FSC), and lower source structure (LSC) may comprise at least one of n-type impurities and p-type impurities. For example, at least one of the upper source structure (USC), interlayer source structure (FSC), or lower source structure (LSC) may comprise a polysilicon film doped with n-type impurities.

[0045] An insulating pattern (IP) may be placed on the bottom of a dummy stack (DST). The insulating pattern (IP) may overlap at least a portion of the dummy stack (DST). The insulating pattern (IP) may penetrate the source structure (SC). The insulating pattern (IP) may be located at the same level as the source structure (SC). The upper surface of the insulating pattern (IP) may be located at the same level as the upper surface of the upper source structure (USC), and the lower surface of the insulating pattern (IP) may be located at the same level as the lower surface of the lower source structure (LSC). The insulating pattern (IP) may include an insulating material (e.g., oxide, nitride).

[0046] Cell plugs (CPL) can penetrate the stack (STK). Cell plugs (CPL) can come into contact with the source structure (SC). Cell plugs (CPL) can penetrate the stack (STK) and extend into the interior of the source structure (SC). Cell plugs (CPL) can penetrate the upper source structure (USC) and the interlayer source structure (FSC), and extend into the interior of the lower source structure (LSC). A memory film (ML) can be placed between the channel film (CH) and the upper source structure (USC), and between the channel film (CH) and the lower source structure (LSC). A memory film (ML) may not be placed between the channel film (CH) and the interlayer source structure (FSC). Thus, the channel film (CH) can come into direct contact with the interlayer source structure (FSC).

[0047] Memory cells and select transistors can be formed at points where cell plugs (CPL) intersect conductive films (CD), respectively. The cell plugs (CPL) can be used as channel regions of a cell string. For example, drain select transistors, memory cells, and source select transistors can be formed at points where cell plugs (CPL) intersect conductive films (CD), respectively.

[0048] Each cell plug (CPL) may include a memory film (ML), a channel film (CH), a core pillar (CO), and a capping film (CAP). The memory film (ML) may have a cylindrical shape. The memory film (ML) may be in contact with the stack (STK). Although not illustrated, the memory film (ML) may include a blocking film, a charge trap film, and a tunnel insulating film. The blocking film, the charge trap film, and the tunnel insulating film may be arranged sequentially from the side of the stack (STK). The channel film (CH) may be formed along the inner wall of the memory film (ML). The core pillar (CO) may have a cylindrical shape surrounded by the channel film (CH). The capping film (CAP) may be connected to the channel film (CH) on the core pillar (CO).

[0049] The blocking film and tunnel insulating film included in the memory film (ML) may be formed of an oxide film (e.g., silicon oxide) or an oxynitride film (e.g., silicon oxynitride), or a combination thereof. The charge trap film included in the memory film (ML) may include a nitride film or a variable resistance material. The channel film (CH) and the capping film (CAP) may be formed of an undoped silicon film or a doped silicon film. Since the capping film (CAP) and the channel film (CH) are formed of the same material or a homogeneous material, their interface may not be clearly visible. The core pillar (CO) may be formed of an insulating film or a conductive film.

[0050] A second upper insulating film (UIL2) may be disposed over the stack (STK) and the dummy stack (DST). The second upper insulating film (UIL2) may cover the stack (STK) and the dummy stack (DST). The second upper insulating film (UIL2) may overlap the cell plugs (CPL). The second upper insulating film (UIL2) may be in contact with the upper surface of the first upper insulating film (UIL1).

[0051] Cell contacts (CCT) may be formed within the second upper insulating layer (UIL2). The cell contacts (CCT) may penetrate the second upper insulating layer (UIL2). The cell contacts (CCT) may each be connected to cell plugs (CPL). The cell contacts (CCT) may come into direct contact with the capping layer (CAP) of the cell plugs (CPL). The cell contacts (CCT) may include a conductive material such as tungsten.

[0052] Gate line contacts (GCTs) can be connected to the conductive films (CDs) of the stack (STK), respectively. Gate line contacts (GCTs) can be electrically connected to the conductive films (CDs), respectively. Gate line contacts (GCTs) can be in contact with the conductive films (CDs), respectively. Gate line contacts (GCTs) can be in contact with the steps included in the stack (STK), respectively. Gate line contacts (GCTs) can extend in the Z direction from the conductive films (CDs). Gate line contacts (GCTs) can penetrate the first upper insulating film (UIL1) and the second upper insulating film (UIL2). The gate line contacts (GCTs) shown in FIG. 3a are only partially illustrated, and the memory block may include gate line contacts (GCTs) corresponding to the number of layers of the conductive films (CDs).

[0053] A peripheral circuit structure (PC) and a substrate (SUB) may be located below the source structure (SC) and the insulation pattern (IP). The peripheral circuit structure (PC) may be located on the substrate (SUB). The peripheral circuit structure (PC) may include a transistor (TR), a peripheral contact plug (PPL), and a peripheral line (PLN). The transistor (TR), peripheral contact plug (PPL), and peripheral line (PLN) may have various patterns depending on the configuration of the peripheral circuit. For example, the number or arrangement of the transistor (TR), peripheral contact plug (PPL), and peripheral line (PLN) may be varied. A lower insulating layer (LIL) may be located between the transistor (TR), peripheral contact plug (PPL), and peripheral line (PLN). For example, the transistor (TR), peripheral contact plug (PPL), and peripheral line (PLN) may be formed inside the lower insulating layer (LIL). The lower insulating layer (LIL) may include an insulating material such as an oxide film.

[0054] Peripheral circuit contacts (PCTs) can penetrate the dummy stack (DST) and the insulation pattern (IP). Peripheral circuit contacts (PCTs) can penetrate the sacrificial films (SF) and interlayer insulating films (IL) of the dummy stack (DST). Peripheral circuit contacts (PCTs) can penetrate the first upper insulating film (UIL1) and the second upper insulating film (UIL2). Peripheral circuit contacts (PCTs) can extend into the interior of the lower insulating film (LIL) and be connected to the peripheral circuit structure (PC). For example, the peripheral circuit contacts (PCTs) can be in contact with at least one peripheral line (PLN) included in the peripheral circuit structure (PC).

[0055] The peripheral circuit contact (PCT) may include a first part (PCT1) and a second part (PCT2). The first part (PCT1) may penetrate the insulation pattern (IP) and extend into the lower insulating layer (LIL). The first part (PCT1) may be in direct contact with the peripheral line (PLN). The second part (PCT2) may be located on the first part (PCT1). The second part (PCT2) may be electrically connected to the first part (PCT1). The second part (PCT2) may penetrate the dummy stack (DST), the first upper insulating layer (UIL1), and the second upper insulating layer (UIL2). The width of the first part (PCT1) may be greater than the width of the second part (PCT2). The first part (PCT1) and the second part (PCT2) may each include a conductive material.

[0056] A third upper insulating layer (UIL3), a fourth upper insulating layer (UIL4), a fifth upper insulating layer (UIL5), a sixth upper insulating layer (UIL6), and a seventh upper insulating layer (UIL7) may be sequentially disposed on a second upper insulating layer (UIL2). The third upper insulating layer (UIL3), the fifth upper insulating layer (UIL5), and the seventh upper insulating layer (UIL7) may include insulating materials such as oxide films. The fourth upper insulating layer (UIL4) and the sixth upper insulating layer (UIL6) may include insulating materials such as nitride films.

[0057] A wiring structure may be formed within the third upper insulating layer (UIL3), the fourth upper insulating layer (UIL4), the fifth upper insulating layer (UIL5), the sixth upper insulating layer (UIL6), and the seventh upper insulating layer (UIL7). The wiring structure shown in FIG. 3a is one example, and various other arrangements are possible.

[0058] First contacts (CT1) may be disposed within the third upper insulating layer (UIL3). The first contacts (CT1) may penetrate the third upper insulating layer (UIL3). The first contacts (CT1) may contact cell contacts (CCT), gate line contacts (GCT), and peripheral circuit contacts (PCT), respectively. The first contacts (CT1) may be electrically connected to cell contacts (CCT), gate line contacts (GCT), and peripheral circuit contacts (PCT), respectively. The first contacts (CT1) may include a conductive material.

[0059] Second contacts (CT2) may be disposed within the fourth upper insulating layer (UIL4). The second contacts (CT2) may penetrate the fourth upper insulating layer (UIL4). The second contacts (CT2) may each contact the first contacts (CT1). The second contacts (CT2) may each be electrically connected to the first contacts (CT1). The second contacts (CT2) may include a conductive material.

[0060] First upper wires (UL1) may be disposed within the fifth upper insulating layer (UIL5). The first upper wires (UL1) may penetrate the fifth upper insulating layer (UIL5). The first upper wires (UL1) may be electrically connected to the second contacts (CT2). The first upper wires (UL1) may extend in a horizontal direction. For example, among the first upper wires (UL1), the first upper wires (UL1) electrically connected to the cell plugs (CPL) may correspond to a bit line (e.g., the bit line (BL) of FIG. 1). The first upper wires (UL1) may include a conductive material.

[0061] The third contacts (CT3) can penetrate the sixth upper insulating layer (UIL6). The third contacts (CT3) can be electrically connected to the first upper wiring (UL1). The third contacts (CT3) can extend into the seventh upper insulating layer (UIL7). The second upper wiring (UL2) can be electrically connected to the third contacts (CT3). In FIG. 3a, the third contacts (CT3) are shown penetrating the bottom of the seventh upper insulating layer (UIL7) but not the top; however, in FIG. 3a, the seventh upper insulating layer (UIL7) may refer collectively to a plurality of layers formed in multiple stages. The third contacts (CT3) and the second upper wiring (UL2) may include a conductive material.

[0062] A memory device according to the present disclosure may include support patterns (SP). A memory device may include at least one support pattern (SP). Although FIG. 3a is illustrated as including all three support patterns (SP1, SP2, SP3), this is for convenience of explanation and the number of support patterns (SP) does not limit the scope of the present disclosure. For example, a memory device may include a first support pattern (SP1) and not include second and third support patterns (SP2, SP3). As another example, a memory device may include a second support pattern (SP2) and not include first and third support patterns (SP1, SP3). As yet another example, a memory device may include second and third support patterns (SP2, SP3) and not include a first support pattern (SP1). For convenience of explanation, the first to third support patterns (SP1~SP3) illustrated in one figure are described below.

[0063] Support patterns (SP) can be formed to be spaced apart from the stack (STK). Support patterns (SP) can be spaced apart from the stack (STK), the dummy stack (DST), and the cell plugs (CPL). Each of the support patterns (SP) can be spaced vertically from the stack (STK). For example, the first and second support patterns (SP1, SP2) can be located in the Z direction from the stack (STK). Additionally, the third support pattern (SP3) can be located in the opposite direction from the Z direction from the stack (STK). The second support pattern (SP2) and the third support pattern (SP3) can be located at the top and bottom of the stack (STK), respectively. The first to third support patterns (SP1 to SP3) can be spaced vertically apart from each other. For example, the second support pattern (SP2) and the third support pattern (SP3) can be formed to be spaced apart from each other with the stack (STK) in between.

[0064] The support patterns (SP) can be extended in a horizontal direction. The support patterns (SP) can each be extended in the X direction and the Y direction. The support patterns (SP) can have a plate shape that extends in a horizontal direction.

[0065] Support patterns (SP) may be formed into a mesh structure. Support patterns (SP) may have a grid pattern. Referring together to FIGS. 3b through 3d, support patterns (SP) may include openings (OP) arranged along the X and Y directions. The openings (OP) may be arranged continuously within the support patterns (SP). For example, within the support patterns (SP), the openings (OP) may be arranged continuously within the remaining area excluding the through area (PP). The spacing between the openings (OP) within the support patterns (SP) may be formed uniformly. The spacing in the X direction between the openings (OP) may be equal to each other. Also, the spacing in the Y direction between the openings (OP) may be equal to each other. The openings (OP) may be filled with an insulating film (e.g., lower insulating film (LIL), second upper insulating film (UIL2), seventh upper insulating film (UIL7)).

[0066] For example, referring to FIG. 3d, the support patterns (SP) may include first sub-patterns (SSP1) extending in the X direction and second sub-patterns (SSP2) extending in the Y direction. The first sub-patterns (SSP1) may be arranged along the Y direction. The second sub-patterns (SSP2) may be arranged along the X direction. The first sub-patterns (SSP1) and the second sub-patterns (SSP2) may intersect each other. Openings (OP) may be located between the first sub-patterns (SSP1) and the second sub-patterns (SSP2). That is, openings (OP) may be arranged parallel along the X direction between adjacent first sub-patterns (SSP1). Also, openings (OP) may be arranged parallel along the Y direction between adjacent second sub-patterns (SSP2). The openings (OP) may have a square-shaped plane.

[0067] Support patterns (SP) may include a penetration region (PP). Contacts included in the memory device (e.g., cell contacts (CCT), gate line contacts (GCT), peripheral circuit contacts (PCT)) may penetrate the support patterns (SP) through the penetration region (PP). The penetration region (PP) may be filled with an insulating film (e.g., lower insulating film (LIL), second upper insulating film (UIL2), seventh upper insulating film (UIL7)). The contacts may be separated from the support patterns (SP) by the insulating film.

[0068] A first support pattern (SP1) may be formed within the seventh upper insulating film (UIL7). The first support pattern (SP1) may be located between wiring structures over the laminate (STK). The first support pattern (SP1) may extend between wiring structures. Referring to FIGS. 3a and 3b, the first support pattern (SP1) may include through-regions (PP) corresponding to the locations of the third contacts (CT3). For example, the first support pattern (SP1) may include two through-regions (PP). The first support pattern (SP1) may include a through-region (PP) through which the third contacts (CT3) connected to the gate line contacts (GCT) pass. Additionally, the first support pattern (SP1) may include a through-region (PP) through which the third contacts (CT3) connected to the peripheral circuit contacts (PCT) pass. The penetration areas (PP) can be filled with the seventh upper insulating film (UIL7). The third contacts (CT3) can be surrounded by the seventh upper insulating film (UIL7). The third contacts (CT3) can be spaced apart from the first support pattern (SP1) by the seventh upper insulating film (UIL7). The third contacts (CT3) can penetrate the first support pattern (SP1) through the penetration areas (PP).

[0069] A second support pattern (SP2) may be formed within a second upper insulating film (UIL2). The second support pattern (SP2) may be located over a laminate (STK). The second support pattern (SP2) may extend between wiring structures connected to the laminate (STK). Referring to FIGS. 3a and 3c, the second support pattern (SP2) may include through-regions (PP) corresponding to the locations of cell contacts (CCT), gate line contacts (GCT), and peripheral circuit contacts (PCT). For example, the second support pattern (SP2) may include three through-regions (PP). The second support pattern (SP2) may include a through-region (PP) through which the cell contacts (CCT) pass, a through-region (PP) through which the gate line contacts (GCT) pass, and a through-region (PP) through which a second portion (PCT2) of the peripheral circuit contact (PCT) passes. The through-regions (PP) can be filled with a second upper insulating film (UIL2). A second portion (PCT2) of the cell contacts (CCT), gate line contacts (GCT), and peripheral circuit contacts (PCT) can be in contact with the second upper insulating film (UIL2). The second portion (PCT2) of the cell contacts (CCT), gate line contacts (GCT), and peripheral circuit contacts (PCT) can be spaced apart from the second support pattern (SP2) by the second upper insulating film (UIL2). The second portion (PCT2) of the cell contacts (CCT), gate line contacts (GCT), and peripheral circuit contacts (PCT) can extend into the interior of the through-regions (PP). The second part (PCT2) of the cell contacts (CCT), gate line contacts (GCT), and peripheral circuit contacts (PCT) can penetrate the second support pattern (SP2) through the penetration areas (PP).

[0070] A third support pattern (SP3) may be formed within the lower insulating film (LIL). The third support pattern (SP3) may be located below the laminate (STK). The third support pattern (SP3) may be located inside the peripheral circuit structure (PC). Referring to FIGS. 3a and 3d, the third support pattern (SP3) may include a penetration area (PP) corresponding to the location of the peripheral circuit contact (PCT). For example, the third support pattern (SP3) may include a penetration area (PP) through which a first portion (PCT1) of the peripheral circuit contact (PCT) penetrates. The penetration area (PP) may be filled with the lower insulating film (LIL). The first portion (PCT1) of the peripheral circuit contact (PCT) may be in contact with the lower insulating film (LIL). A first portion (PCT1) of the peripheral circuit contact (PCT) may be separated from the third support pattern (SP3) by the lower insulating film (LIL). A first portion (PCT1) of the peripheral circuit contact (PCT) may extend into the interior of the penetration area (PP). A first portion (PCT1) of the peripheral circuit contact (PCT) may penetrate the third support pattern (SP3) through the penetration area (PP).

[0071] Support patterns (SP) may have high stiffness compared to the interlayer insulating film (IL). Additionally, support patterns (SP) may have high stiffness compared to the first to seventh upper insulating films (UIL1~UIL7) or the separation structure (SR). For example, support patterns (SP) may include at least some of silicon carbide (SiC), aluminum oxide (Al2O3), boron nitride (BN), tungsten carbide (WC), tungsten (W), iron (Fe), or copper (Cu). In this disclosure, stiffness may refer to a characteristic that allows a film to maintain its shape without deformation even when stress is applied to it. A material is considered to have high stiffness if the maximum stress at which it can maintain its shape without deformation when stress is applied to it is greater. For example, an oxide film (e.g., silicon oxide) included in the first to seventh upper insulating films (UIL1 to UIL7) or the separation structure (SR) can maintain its shape until 70 to 75 GPa is applied. Silicon carbide included in the support patterns (SP) can maintain its shape up to 450 GPa, aluminum oxide up to 370 GPa, boron nitride up to 360 GPa, tungsten carbide up to 500 to 700 GPa, tungsten up to 400 GPa, iron up to 211 GPa, and copper up to 130 GPa. Thus, the rigidity of the support patterns (SP) can be higher than that of the first to seventh upper insulating films (UIL1 to UIL7) or the separation structure (SR).

[0072] Warpage of a memory device can be reduced by support patterns (SP) having high rigidity. The rigidity of a memory device can be increased by support patterns (SP) extending in the X and Y directions. The planar rigidity of the memory device can be improved by the support patterns (SP) having a mesh shape in the remaining areas, excluding some areas where contacts are formed. Accordingly, a memory device comprising at least one support pattern (SP) according to the present disclosure may have no or minimal defects (e.g., cracks) that occur when the memory device warps.

[0074] FIGS. 4a to 4e are drawings for explaining a method of manufacturing a support pattern according to an embodiment of the present invention.

[0075] FIGS. 4a to 4e illustrate a method for forming a support pattern (SP), and the following description may be modified and applied to the first to third support patterns (SP1 to SP3) shown in FIG. 3a. For convenience of explanation, the following description focuses on one support pattern (SP) having a shape similar to the first support pattern (SP1).

[0076] Referring to FIG. 4a, a support film (SPL) may be formed on a first insulating film (IIL1) and a second insulating film (IIL2). The support film (SPL) may cover the first and second insulating films (IIL1, IIL2). The support film (SPL) may extend in a horizontal direction (e.g., X direction, Y direction). The support film (SPL) may have a higher rigidity than the first and second insulating films (IIL1, IIL2). For example, the first insulating film (IIL1) may include a nitride film, and the second insulating film (IIL2) may include an oxide film. Additionally, the support film (SPL) may include at least some of silicon carbide (SiC), aluminum oxide (Al2O3), boron nitride (BN), tungsten carbide (WC), tungsten (W), iron (Fe), or copper (Cu).

[0077] Next, a hard mask (HM) may be formed on the support film (SPL). The hard mask (HM) may cover the support film (SPL). The hard mask (HM) may come into contact with the upper surface of the support film (SPL). The hard mask (HM) may contain a nitride material.

[0078] Referring to FIG. 4b, a photoresist film can be formed on a hard mask (HM). The photoresist film can cover the hard mask (HM). The photoresist film can be formed of a material whose chemical properties change upon exposure to light.

[0079] Subsequently, a portion of the photoresist film may be removed to form a photoresist (PR). For example, a mask including a light-transmitting region and a light-blocking region may be aligned on the photoresist film. Light may be applied toward the photoresist film using the mask. The exposed region and the unexposed region of the photoresist film may have different characteristics. Depending on the type of photoresist film, the exposed region may be removed and the unexposed region may remain, or the unexposed region may be removed and the exposed region may remain. The portion remaining in the photoresist film may be referred to as the photoresist (PR). The photoresist (PR) may include an aperture region corresponding to the area where the photoresist film was removed.

[0080] Next, the hard mask (HM) and the support film (SPL) can be etched using a photoresist (PR). A portion of the hard mask (HM) and a portion of the support film (SPL) can be removed using an aperture area included in the photoresist (PR). A portion of the support film (SPL) can be removed to form a support pattern (SP).

[0081] The support pattern (SP) may include openings (OP) arranged along the X and Y directions. The openings (OP) may be arranged continuously within the support pattern (SP). For example, the openings (OP) may be arranged continuously within the support patterns (SP) in the remaining area excluding the penetration area (PP). The spacing between the openings (OP) within the support pattern (SP) may be formed uniformly. The spacing between the openings (OP) in the X direction may be equal to each other. Additionally, the spacing between the openings (OP) in the Y direction may be equal to each other.

[0082] The support pattern (SP) can be formed into a mesh structure. The support pattern (SP) can have a grid shape. For example, as described with reference to FIG. 3d, the support patterns (SP) may include first sub-patterns (SSP1) extending in the X direction and second sub-patterns (SSP2) extending in the Y direction. Openings (OP) may be located between the first sub-patterns (SSP1) and the second sub-patterns (SSP2).

[0083] The support pattern (SP) may include penetration areas (PP). Each penetration area (PP) may have a larger area compared to each opening (OP). The penetration areas (PP) may be surrounded by the openings (OP). The location of the penetration areas (PP) may be determined by the location where contacts will be formed later.

[0084] In one embodiment, the through-regions (PP) and the openings (OP) may be formed simultaneously. In another embodiment, the through-regions (PP) and the openings (OP) may not be formed simultaneously. For example, the through-regions (PP) may be formed using a separate photoresist after the openings (OP) are formed first. As another example, the openings (OP) may be formed using a separate photoresist after the through-regions (PP) are formed first.

[0085] Referring to Fig. 4c, the photoresist (PR) and hard mask (HM) can be removed.

[0086] Referring to FIG. 4d, a third insulating film (IIL3) covering a support pattern (SP) may be formed. The third insulating film (IIL3) may fill the openings (OP) and penetration areas (PP) of the support pattern (SP). The third insulating film (IIL3) may comprise a material equivalent to that of the second insulating film (IIL2). In this case, the interface between the second insulating film (IIL2) and the third insulating film (IIL3) may not be observed.

[0087] Referring to FIG. 4e, contacts (CTT) extending into the interior of the penetration regions (PP) may be formed. The contacts (CTT) may penetrate the first insulating film (IIL1) and the second insulating film (IIL2). The contacts (CTT) may penetrate the portions filled within the penetration regions (PP) in the third insulating film (IIL3). The contacts (CTT) may include the third contacts (CT3) of FIG. 3a, cell contacts (CCT), gate line contacts (GCT), or peripheral circuit contacts (PCT). Additionally, wiring (LN) may be formed on the contacts (CTT). The wiring (LN) may be in contact with the upper surface of the contacts (CTT). The contacts (CTT) and the wiring (LN) may be formed simultaneously, or the wiring (LN) may be formed after the contacts (CTT) are formed. The wiring (LN) can be surrounded by a third insulating layer (IIL3).

[0088] The mesh structure of the support patterns (SP) illustrated in FIGS. 3b to 3d and FIGS. 4a to 4e is merely an example and does not limit the scope of the present disclosure. Various forms of the mesh structure of the support patterns (SP) will be described later with reference to FIGS. 5a and 5b.

[0090] FIGS. 5A and FIGS. 5B are drawings for illustrating various embodiments of a support pattern according to the present invention.

[0091] Referring to FIG. 5a, the width in the X direction and the width in the Y direction of the openings (OP) may differ from each other. The openings (OP) may have a rectangular plane. The spacing between the second sub-patterns (SSP2) may be farther than the spacing between the first sub-patterns (SSP1).

[0092] Referring to FIG. 5b, the direction in which the openings (OP) are arranged may not be the X direction and the Y direction. For example, the openings (OP) may be arranged along a first direction and a second direction, the first direction may point between the X direction and the Y direction, and the second direction may point between the opposite direction of the X direction and the Y direction. The first sub-patterns (SSP1) may extend along the first direction, and the second sub-patterns (SSP2) may extend along the second direction.

[0093] FIGS. 5a and 5b represent some examples of the structure of the support patterns (SP), and they may have various other forms. For example, the openings (OP) may have a rectangular shape and be arranged along the first direction and the second direction. As another example, the openings (OP) may not be square or rectangular, but may have a rhombus shape, a circle, or an elliptical plane. As yet another example, the areas of the openings (OP) may differ from each other, the spacing between the openings (OP) may not be uniform, or the openings (OP) may be formed only in some areas of the entire area of ​​the support pattern (SP).

[0095] FIG. 6 is a drawing for explaining a memory card system to which the memory device of the present invention is applied.

[0096] Referring to FIG. 6, the memory card system (3000) includes a controller (3100), a memory device (3200), and a connector (3300).

[0097] The controller (3100) may be connected to the memory device (3200). The controller (3100) may be configured to access the memory device (3200). For example, the controller (3100) may be configured to control program operations, read operations, or erase operations of the memory device (3200), or to control background operations. The controller (3100) may be configured to provide an interface between the memory device (3200) and a host. The controller (3100) may be configured to run firmware for controlling the memory device (3200). For example, the controller (3100) may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0098] The controller (3100) can communicate with an external device through a connector (3300). The controller (3100) can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller (3100) is configured to communicate with an external device through at least one of various communication standards such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, or NVMe. For example, the connector (3300) may be defined by at least one of the various communication standards described above.

[0099] The memory device (3200) may include a plurality of memory cells and may be configured in the same way as the memory device (100) shown in FIG. 1.

[0100] The controller (3100) and the memory device (3200) can be integrated into a single semiconductor device to form a memory card. For example, the controller (3100) and the memory device (3200) can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash Card (CF), Smart Media Card (SM, SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro, eMMC), SD Card (SD, miniSD, microSD, SDHC), or Universal Flash Storage (UFS).

[0102] FIG. 7 is a diagram illustrating a Solid State Drive (SSD) system to which the memory device of the present invention is applied.

[0103] Referring to FIG. 7, the SSD system (4000) may include a host (4100) and an SSD (4200). The SSD (4200) may exchange signals with the host (4100) through a signal connector (4001) and receive power through a power connector (4002). The SSD (4200) may include a controller (4210), a plurality of memory devices (4221 to 422n), an auxiliary power supply (4230), and a buffer memory (4240).

[0104] The controller (4210) can control a plurality of memory devices (4221 to 422n) in response to a signal received from the host (4100). For example, the signal may be a signal based on the interface between the host (4100) and the SSD (4200). For example, the signal may be a signal defined by at least one of the interfaces such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, or NVMe.

[0105] A plurality of memory devices (4221 to 422n) may include a plurality of memory cells configured to store data. Each of the plurality of memory devices (4221 to 422n) may be configured identically to the memory device (100) shown in FIG. 1. The plurality of memory devices (4221 to 422n) may communicate with the controller (4210) through channels (CH1 to CHn).

[0106] The auxiliary power supply unit (4230) can be connected to the host (4100) via the power connector (4002). The auxiliary power supply unit (4230) can receive power voltage from the host (4100) and charge. The auxiliary power supply unit (4230) can provide power voltage to the SSD (4200) when power supply from the host (4100) is not smooth. For example, the auxiliary power supply unit (4230) may be located inside the SSD (4200) or outside the SSD (4200). For example, the auxiliary power supply unit (4230) may be located on the main board and can provide auxiliary power to the SSD (4200).

[0107] The buffer memory (4240) can operate as a buffer memory of the SSD (4200). For example, the buffer memory (4240) can temporarily store data received from the host (4100) or data received from a plurality of memory devices (4221 to 422n), or temporarily store metadata (e.g., mapping tables) of the memory devices (4221 to 422n). The buffer memory (4240) may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, etc., or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc. Explanation of the symbols

[0108] STK: Laminate CD: Challenge IL: Interlayer insulation film CPL: Cell plug ML: Memory film CH: Channel Block CO: Core Pillar CAP: Capping film GCT: Gate Line Contact DST: Dummy stack SF: Sacrifice PCT: Peripheral Circuit Contact PC: Peripheral Circuit Structure LIL: Lower insulating layer SUB: Substrate SP: Support Pattern PP: Penetration area OP: Opening

Claims

Claim 1 A memory device comprising: a laminate including alternatingly stacked conductive films and interlayer insulating films; cell plugs penetrating the laminate; a support pattern spaced apart from the laminate and the cell plugs and including a penetrating region; and contacts penetrating the support pattern through the penetrating region, wherein the support pattern includes openings arranged along a first direction and a second direction intersecting the first direction. Claim 2 A memory device according to claim 1, wherein the support pattern has higher rigidity than the interlayer insulating films. Claim 3 A memory device according to claim 1, wherein the support pattern comprises at least a portion of silicon carbide (SiC), aluminum oxide (Al2O3), boron nitride (BN), tungsten carbide (WC), tungsten (W), iron (Fe), or copper (Cu). Claim 4 In claim 1, the memory device, wherein the support pattern is spaced vertically from the laminate. Claim 5 In claim 1, the support pattern is a memory device extending in the first direction and the second direction. Claim 6 A memory device according to claim 1, wherein the support pattern is formed as a mesh structure. Claim 7 A memory device according to claim 1, wherein the support pattern comprises first sub-patterns extending in the first direction; and second sub-patterns extending in the second direction, and each of the openings is located between the first sub-patterns and the second sub-patterns. Claim 8 A memory device according to claim 1, wherein the openings are arranged continuously within the remaining area of ​​the support pattern, excluding the penetration area. Claim 9 A memory device according to claim 1, wherein the spacing between the openings within the support pattern is uniformly formed. Claim 10 A memory device according to claim 1, further comprising a first insulating film filling the penetration area and a second insulating film filling the openings. Claim 11 In claim 10, the above contacts penetrate the first insulating film and are spaced apart from the support pattern by the first insulating film, a memory device. Claim 12 A memory device according to claim 1, further comprising a peripheral circuit structure located at the bottom of the laminate, wherein the support pattern is located inside the peripheral circuit structure. Claim 13 A memory device according to claim 1, further comprising a dummy stack located in the first direction of the stack, wherein the contacts include a peripheral circuit contact penetrating the dummy stack, and the peripheral circuit contact extends into the interior of the penetrating region of the support pattern. Claim 14 A memory device according to claim 1, further comprising a first upper insulating film disposed on the laminate, wherein the support pattern is located inside the first upper insulating film. Claim 15 In claim 14, the above contacts include cell contacts that penetrate the first upper insulating film and are connected to the cell plugs respectively, and the cell contacts extend into the interior of the penetration area of ​​the support pattern, a memory device. Claim 16 A memory device according to claim 1, wherein the contacts each include gate line contacts connected to the conductive films, and the gate line contacts extend into the interior of the through-region of the support pattern. Claim 17 A memory device according to claim 1, comprising a wiring structure located over the laminate, wherein the support pattern extends between the wiring structures. Claim 18 A method for manufacturing a memory device, comprising: a step of forming a support film; a step of removing a portion of the support film to form a support pattern comprising openings arranged along a first direction and a second direction intersecting the first direction, and a penetration area wider than the openings; a step of forming an insulating film that fills the openings and the penetration area; and a step of forming a contact that penetrates the insulating film and extends into the penetration area. Claim 19 A method for manufacturing a memory device according to claim 18, wherein, in the step of forming the support film, the support film comprises at least a portion of silicon carbide (SiC), aluminum oxide (Al2O3), boron nitride (BN), tungsten carbide (WC), tungsten (W), iron (Fe), or copper (Cu). Claim 20 A method for manufacturing a memory device according to claim 18, wherein, in the step of forming the support film, the support film extends in the first direction and the second direction. Claim 21 A method for manufacturing a memory device according to claim 18, wherein, in the step of forming the support pattern, the support pattern is formed as a mesh structure. Claim 22 A method for manufacturing a memory device according to claim 18, wherein, in the step of forming the support pattern, the support pattern comprises: first sub-patterns extending in the first direction; and second sub-patterns extending in the second direction, and each of the openings is formed to be located between the first sub-patterns and the second sub-patterns. Claim 23 A method for manufacturing a memory device according to claim 18, wherein, in the step of forming the support pattern, the openings are formed to be arranged continuously within the remaining area of ​​the support pattern, excluding the penetration area.

Images