Semiconductor memory device

Abstract

The present disclosure relates to a semiconductor memory device having improved electrical characteristics and / or reliability. The semiconductor memory device comprises a substrate including a cell region and a connection region disposed on one side of the cell region; a bit line disposed on the substrate and extending in a first direction across the cell region and the connection region; a word line disposed on the cell region above the bit line and extending in a second direction intersecting the first direction; an active pattern disposed on one side of the word line on the cell region; and a cell region separation layer disposed on the bit line on the connection region, wherein the active pattern comprises an outermost active pattern disposed on the outside of the cell region, and the cell region separation layer comprises a first insulating film disposed on the outer surface of the outermost active pattern and extending in a second direction, and a second insulating film comprising a first portion disposed on one side of the first insulating film and a second portion extending in a first direction from the end of the first portion, wherein the lower surface of the second portion may contact the upper surface of the bit line.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor memory device. Background Technology

[0002] Semiconductor devices refer to core components used to control or amplify electrical signals in electronic devices, and various types of semiconductor devices can be manufactured. For example, semiconductor memory devices are primarily used to store and retrieve data. Semiconductor memory devices are key elements of electronic devices that play an essential role in various fields, such as computers, communication equipment, and consumer electronics.

[0003] As industry develops, demands for the performance and functionality of electronic devices are increasing. Consequently, high performance is essential for semiconductor memory devices, and to meet these demands, the integration density of these devices is continuously rising. During this development, new transistor structures, such as transistors with vertical channels and vertical stack transistors, have been proposed.

[0004] The information described above is intended to aid in understanding the background of the present invention and may include information that does not constitute prior art. The problem to be solved

[0005] The problem that the present disclosure aims to solve is to provide a semiconductor memory device with improved electrical characteristics and / or reliability. means of solving the problem

[0006] A semiconductor memory device according to some embodiments of the present disclosure comprises a substrate including a cell region and a connection region disposed on one side of the cell region, a bit line disposed on the substrate and extending in a first direction across the cell region and the connection region, a word line disposed on the upper side of the bit line on the cell region and extending in a second direction intersecting the first direction, an active pattern disposed on one side of the word line on the cell region, and a cell region separation layer disposed on the bit line on the connection region, wherein the active pattern comprises an outermost active pattern disposed on the outer side of the cell region, and the cell region separation layer comprises a first insulating film disposed on the outer side of the outermost active pattern and extending in a second direction, and a second insulating film comprising a first portion disposed on one side of the first insulating film and a second portion extending in a first direction from the end of the first portion, and the lower surface of the second portion may contact the upper surface of the bit line.

[0007] A semiconductor memory device according to some embodiments of the present disclosure comprises: a substrate including a cell region and a connection region disposed on one side of the cell region; a bit line disposed on the substrate and extending in a first direction across the cell region and the connection region; a plurality of word lines including a first word line and a second word line that are spaced apart from each other in a first direction on the bit line in the cell region and each extending in a second direction that intersects the first direction; a plurality of active patterns including a first active pattern disposed on a first side of the first word line and a second active pattern disposed on a second side opposite to the first side of the second word line in the cell region; and a cell region separation layer disposed on the bit line in the connection region, wherein the cell region separation layer comprises a first insulating film and a second insulating film disposed sequentially on the outer surface of the outermost active pattern among a plurality of active patterns defining the boundary between the cell region and the connection region, and the lower surface of the second insulating film may contact the upper surface of the bit line.

[0008] A semiconductor memory device according to some embodiments of the present disclosure comprises: a substrate including a cell region and a connection region disposed on one side of the cell region; a bit line disposed on the substrate and extending in a first direction across the cell region and the connection region; a plurality of word lines including a first word line and a second word line that are spaced apart from each other in a first direction on the bit line on the cell region and each extending in a second direction intersecting the first direction; a plurality of active patterns on the cell region including a first active pattern disposed on a first side of the first word line and a second active pattern disposed on a second side opposite to the first side of the second word line; and a cell region separation layer disposed on the bit line on the connection region, wherein the cell region separation layer comprises a first insulating film, a second insulating film, and a third insulating film that are sequentially disposed on the outer surface of the outermost active pattern among a plurality of active patterns defining the boundary between the cell region and the connection region, wherein the first insulating film and the second insulating film comprise different materials, and the first insulating film and the third insulating film comprise the same material, and the lower surface of the first insulating film and the lower surface of the second insulating film The second insulating film may include a portion disposed between the third insulating film and the bit line, in contact with the upper surface of the bit line.

[0009] A method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure may include the steps of: preparing a preliminary substrate comprising a preliminary cell region and a preliminary connection region disposed on one side of the preliminary cell region; forming a cell separation trench within the preliminary connection region; sequentially forming a first preliminary insulating film, a second preliminary insulating film, and a third preliminary insulating film on the inner wall of the cell separation trench and on the upper surface of the preliminary substrate of the preliminary cell region; forming a plurality of word lines within the preliminary cell region that are spaced apart from each other in a first direction and each extends in a second direction intersecting the first direction; forming a plurality of active patterns disposed on one side of each of the plurality of word lines within the preliminary cell region; polishing the preliminary substrate in the preliminary cell region and the preliminary connection region up to the lower surface of the first preliminary insulating film; and forming a cell separation insulating film comprising a first insulating film, a second insulating film, and a third insulating film sequentially disposed on the inner wall of the cell separation trench by polishing the first preliminary insulating film up to the lower surface of the second preliminary insulating film in the preliminary connection region.

[0010] A method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure may further include the step of forming a bit line extending in a first direction, in contact with the lower surface of an active pattern and a second insulating film.

[0011] A method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure may further include, after forming an active pattern, forming a landing pad connected to the active pattern, and forming a capacitor structure connected to the landing pad.

[0012] According to some embodiments of the present disclosure, the step of forming a cell separation insulating film may include forming a cell separation insulating film comprising a first insulating film disposed on the inner wall of a cell separation trench, a second insulating film comprising a first portion disposed on one side of the first insulating film and a second portion extending parallel to the surface of a pre-substrate at the end of the first portion, and a third insulating film disposed on the first portion and the second portion.

[0013] According to some embodiments of the present disclosure, the step of forming a cell separation insulating film may include forming a first insulating film and a second insulating film such that a first width along a first direction of the first insulating film, a second width along a first direction of the first portion, and a third width along a third direction intersecting each of the first and second directions of the second portion are equal to each other.

[0014] According to some embodiments of the present disclosure, the step of forming a cell separation insulating film may include forming a first insulating film and a second insulating film such that a first width along a first direction of the first insulating film is greater than a second width along a first direction of the first part and a third width along a third direction intersecting each of the first direction and the second direction of the second part.

[0015] According to some embodiments of the present disclosure, the step of forming a cell separation insulating film may include forming a first insulating film and a second insulating film such that a first width along a first direction of the first insulating film is smaller than a second width along a first direction of the first part and a third width along a third direction intersecting each of the first direction and the second direction of the second part.

[0016] A method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure further includes the step of forming a gate capping layer disposed between a plurality of word lines and bit lines, and the lower surface of the gate capping layer may be disposed in a co-plane with the lower surface of a second insulating film. Effects of the invention

[0018] According to some embodiments of the present disclosure, a multi-insulating film of the cell region separation layer within the connection region can act as a CMP stopper in the CMP process to improve surface flatness and thickness uniformity. This allows for the provision of a semiconductor memory device with improved electrical characteristics and reliability. Brief explanation of the drawing

[0019] FIG. 1 is a layout diagram showing a semiconductor memory device according to exemplary embodiments of the present disclosure. FIG. 2 is a layout diagram showing a semiconductor memory device according to exemplary embodiments of the present disclosure. Figure 3 is an enlarged view of the Q region of Figure 2. Figure 4 is a cross-sectional view taken along line AA of Figure 3. Figure 5 is an enlarged view of the R1 region of Figure 4. Figures 6 to 8 are enlarged views of the R2 region of Figure 4. FIG. 9 is a drawing for illustrating a semiconductor memory device according to exemplary embodiments of the present disclosure. FIGS. 10 and FIGS. 11 are layout diagrams showing a semiconductor memory device according to exemplary embodiments of the present disclosure. FIGS. 12 to 19 are intermediate step drawings for explaining a method for manufacturing a semiconductor memory device according to one embodiment of the present disclosure. FIG. 20 is a flowchart for explaining a method for manufacturing a semiconductor memory device according to one embodiment of the present disclosure. Specific details for implementing the invention

[0020] Hereinafter, various embodiments of the present invention will be described with reference to the drawings. Throughout the specification, the same reference numerals may refer to the same components.

[0021] In the drawings below, the first direction (D1) and the second direction (D2) may represent the same plane. For example, the first direction (D1) and the second direction (D2) may represent directions parallel to the surface of the substrate (100). The third direction (D3) may represent a direction perpendicular to the first direction (D1) and the second direction (D2). For example, the third direction (D3) may represent a direction perpendicular to the surface of the substrate (100). The first direction (D1) and the second direction (D2) may intersect each other.

[0022] FIG. 1 is a layout diagram showing a semiconductor memory device according to exemplary embodiments of the present disclosure.

[0023] Referring to FIG. 1, a semiconductor memory device may include a cell structure (CELL) and a peripheral circuit structure (PERI) arranged in a vertical direction (e.g., a third direction (D3)).

[0024] A cell structure (CELL) may include a plurality of cell regions (MCAs) arranged in a matrix form. A cell region (MCA) may be a memory cell region of a DRAM device. For example, a cell region (MCA) may include a memory cell transistor and a data storage element. In one embodiment, the memory cell transistor may be a vertical channel transistor (VCT). The gate of the memory cell transistor may be connected to a word line (e.g., the word line (WL) in FIG. 3). Additionally, a channel pattern of the memory cell transistor, for example, an active pattern (e.g., the active pattern (AP) in FIG. 3), may be connected to a bit line (e.g., the bit line (BL) in FIG. 3) and a data storage element. For example, the data storage element may be a capacitor structure (e.g., the capacitor structure (CAP) in FIG. 3).

[0025] The peripheral circuit structure (PERI) may be a core region or a peripheral circuit region of a DRAM device. The peripheral circuit region (PCA) may include peripheral circuit transistors for delivering signals and / or power to cell transistors included in the cell region (MCA). In exemplary embodiments, the peripheral circuit transistors may constitute various circuits such as a command decoder, control logic, address buffer, row decoder, column decoder, sense amplifier, and data input / output circuit.

[0026] FIG. 2 is a layout diagram showing a semiconductor memory device according to exemplary embodiments of the present disclosure. Specifically, FIG. 2 is a schematic layout diagram of a cell region (MCA) of a semiconductor memory device shown in FIG. 1. In the cell region (MCA) of FIG. 2, the remaining components are omitted except for the first electrode (312) of a capacitor structure (e.g., capacitor structure (CAP) of FIG. 3).

[0027] Referring to FIG. 2, a connection region (INT) may be disposed on at least one side of a cell region (MCA). For example, the cell region (MCA) may be surrounded by the connection region (INT). According to one embodiment, the connection region (INT) may include an insulating pattern disposed to separate adjacent cell regions (MCAs).

[0028] As illustrated in FIG. 2, a plurality of first electrodes (312) may be disposed on the cell region (MCA). FIG. 2 illustrates a planar arrangement of the first electrodes (312) arranged in a matrix form, but the arrangement form and number of the first electrodes (312) are exemplary and the scope of the present disclosure is not limited thereto.

[0029] Figure 3 is an enlarged view of region Q of Figure 2. Figure 4 is a cross-sectional view cut along line AA of Figure 3.

[0030] Referring to FIGS. 3 and 4, a semiconductor memory device according to some embodiments of the present disclosure may include a substrate (100), a bit line (BL), a word line (WL), an active pattern (AP), a gate capping layer (140), a gate isolation layer (150), a cell region isolation layer (CSP), a landing pad (LP), and a capacitor structure (CAP), etc.

[0031] The substrate (100) may include a semiconductor substrate, such as, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In one embodiment, the cell substrate (100) may include polysilicon (poly Si).

[0032] In some embodiments, the substrate (100) may include an insulating material. For example, the substrate (100) may be an insulating substrate. According to one embodiment, the substrate (100) may be composed of a wiring insulating layer comprising a wiring structure for connecting a cell structure (e.g., the cell structure (CELL) of FIG. 1) to a peripheral circuit structure (e.g., the peripheral circuit structure (PERI) of FIG. 1).

[0033] The substrate (100) may include a cell region (MCA) and a connection region (INT).

[0034] A memory cell array including a plurality of memory cells may be formed in the cell region (MCA). For example, a bit line (BL), a word line (WL), an active pattern (AP), etc., described later may be placed in the cell region (MCA).

[0035] A connection region (INT) can be placed around a cell region (MCA). For example, the connection region (INT) can surround the cell region (MCA). A cell region separation layer (CSP) can be placed in the connection region (INT).

[0036] In one embodiment, the substrate (100) may include a plurality of cell regions (MCA), and a connection region (INT) may be disposed between adjacent cell regions (MCA). In this case, the adjacent cell regions (MCA) may have a symmetrical structure, but the scope of the present disclosure is not limited thereto.

[0037] A plurality of bit lines (BL) may be disposed on a substrate (100). Each of the plurality of bit lines (BL) may be disposed spaced apart from each other in a second direction (D2). Each bit line (BL) may extend in a first direction (D1) parallel to the surface of the substrate (100) across a cell region (MCA) and a connection region (INT). In one embodiment, the bit lines (BL) may be cut on the connection region (INT). The bit lines (BL) may be disposed at equal intervals. The width of the bit lines (BL) or the spacing between the bit lines (BL) may be determined according to design rules.

[0038] According to one embodiment, the bit line (BL) may include a metal layer (122) and a polysilicon film (124) sequentially stacked in a third direction (D3) on a substrate (100). The polysilicon film (161) may include polysilicon doped with impurities, and the metal layer (122) may include a conductive material. The metal layer (122) may include a conductive metal nitride, for example, titanium nitride, tantalum nitride, or a combination thereof. Additionally, the metal layer (122) may include a metal silicide such as titanium silicide, cobalt silicide, or nickel silicide. However, the material included in the metal layer (122) is not limited thereto and may be varied.

[0039] A plurality of word lines (WL) may be positioned above a bit line (BL). Specifically, a plurality of word lines (WL) may be positioned spaced apart from the surface of the bit line (BL) in a third direction (D3). Additionally, each of the plurality of word lines (WL) may be positioned spaced apart from each other in a first direction (D1). Each word line (WL) may extend in a second direction (D2) that intersects the first direction (D1).

[0040] An active pattern (AP) may be placed on one side of a word line (WL). In one embodiment, a plurality of word lines (WL) may include a first word line (WL1) and a second word line (WL2) on which an active pattern (AP) is placed on different sides. The first word line (WL1) and the second word line (WL2) may be arranged alternately spaced apart along a first direction (D1). For example, the first active pattern (AP1) may be placed on the first side of the first word line (WL1). The second active pattern (AP2) may be placed on the side opposite to the first side of the second word line (WL2), that is, on the second side.

[0041] Each active pattern (AP) may include a single-crystal semiconductor material. For example, the active pattern (AP) may include single-crystal silicon.

[0042] A gate insulating film (130) may be disposed between a word line (WL) and an active pattern (AP). The gate insulating film (130) may extend in a third direction (D3) between the word line (WL) and the active pattern (AP). For example, the gate insulating film (130) may be disposed between a first word line (WL1) and a first active pattern (AP1) and extend along a first side profile of the first word line (WL1). Additionally, the gate insulating film (130) may be disposed between a second word line (WL2) and a second active pattern (AP2) and extend along a second side profile of the second word line (WL2).

[0043] The gate insulating film (130) may include silicon oxide, silicon oxynitride, a high dielectric material having a dielectric constant higher than that of silicon oxide, or a combination thereof. The high dielectric material may include a metal oxide or a metal oxynitride. For example, the high dielectric material usable as the gate insulating film (130) may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0044] The gate capping layer (140) can be placed between the word line (WL) and the bit line (BL). For example, in a structure where adjacent first word line (WL1) and second word line (WL2) face each other, the gate capping layer (140) can be placed between the lower surface of each of the first word line (WL1) and the second word line (WL2) and the upper surface of the bit line (BL).

[0045] The gate capping layer (140) may include silicon oxide, silicon nitrate, silicon nitride, a low-dielectric constant (low-k) material having a dielectric constant smaller than that of silicon oxide, or a combination thereof, but is not limited thereto.

[0046] The gate separation layer (150) may be disposed between the first word line (WL1) and the second word line (WL2) in a structure where the first word line (WL1) and the second word line (WL2) are adjacent to each other and face each other. For example, the gate separation layer (150) may be disposed on the side of each of the first word line (WL1) and the second word line (WL2) and on the upper surface of each of the first word line (WL1) and the second word line (WL2) connected thereto.

[0047] Specifically, the gate separation layer (150) may include a vertical portion (152) extending in a third direction (D3) along the second side of the first word line (WL) and the first side of the second word line (WL), and a horizontal portion (154) connected to the end of the vertical portion (152) and disposed on the upper surface of each of the first word line (WL1) and the second word line (WL2). Here, the second side of the first word line (WL1) may represent the opposite side of the first side of the first word line (WL1) where the first active pattern (AP1) is disposed, and the first side of the second word line (WL2) may represent the opposite side of the second side of the second word line (WL2) where the second active pattern (AP2) is disposed.

[0048] The gate separation layer (150) may include, for example, silicon oxide, silicon nitrate, silicon nitride, a low-dielectric constant (low-k) material having a dielectric constant smaller than that of silicon oxide, or a combination thereof, but is not limited thereto.

[0049] According to some embodiments, the semiconductor memory device may further include a back gate electrode (BG), a back gate capping layer (160), a back gate isolation layer (170), and a back gate insulating film (180).

[0050] A back gate electrode (BG) may be positioned between the first active pattern (AP1) and the second active pattern (AP2) in a structure where the first active pattern (AP1) and the second active pattern (AP2) are adjacent to each other. The back gate electrode (BG) may be positioned spaced apart in a third direction (D3) from the surface of the bit line (BL). Additionally, each of the plurality of back gate electrodes (BG) may be positioned spaced apart from each other in a first direction (D1). Each back gate electrode (BG) may extend in the same direction as the word line (WL) (e.g., the second direction (D2)). Although FIG. 4 illustrates that the height of the back gate electrode (BG) in the third direction (D3) corresponds to the height of the word line (WL) in the third direction (D3), it is not limited thereto, and the height of the back gate electrode (BG) and the height of the word line (WL) may be different.

[0051] The back gate electrode (BG) may include a conductive material. For example, the back gate electrode (BG) may include doped polysilicon, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, a metal, or a combination thereof.

[0052] In one embodiment, a negative voltage may be applied to the back gate electrode (BG) during operation of the semiconductor memory device, and the threshold voltage of the vertical channel transistor may be increased. That is, as the vertical channel transistor is miniaturized, the threshold voltage may decrease, thereby preventing the leakage current characteristics from deteriorating.

[0053] The back gate capping layer (160) may be placed on the lower surface of the back gate electrode (BG). For example, the back gate capping layer (160) may be placed between the back gate electrode (BG) and the bit line (BL).

[0054] The back gate capping layer (160) may include an insulating material. For example, it may include silicon oxide, silicon nitride, silicon nitrate, or any combination thereof, but is not limited thereto.

[0055] The back gate isolation layer (170) may be disposed on the upper surface of the back gate electrode (BG). For example, the back gate isolation layer (170) may be disposed between the back gate electrode (BG) and the contact layer inter-layer insulation layer (190) described later. Additionally, the side of the back gate isolation layer (170) may come into contact with a portion of the respective side of the first active pattern (AP1) and the second active pattern (AP2) that are adjacent to each other. That is, the respective side of the first active pattern (AP1) and the second active pattern (AP2) that are adjacent to each other may include a portion that comes into contact with the side of the back gate isolation layer (170).

[0056] The back gate separation layer (170) may include an insulating material. For example, it may include silicon oxide, silicon nitride, silicon nitrate, or any combination thereof, but is not limited thereto.

[0057] A back gate insulating film (180) may be disposed between a back gate electrode (BG) and an active pattern (AP). The back gate insulating film (180) may extend in a third direction (D3) between the back gate electrode (BG) and the active pattern (AP). For example, the back gate insulating film (180) may extend in a third direction (D3) along the side of the first direction (D1) of each of the back gate capping layer (160) and the back gate electrode (BG).

[0058] The back gate insulating film (180) may comprise silicon oxide, silicon oxynitride, a high dielectric material having a dielectric constant higher than that of silicon oxide, or a combination thereof. The high dielectric material may comprise a metal oxide or a metal oxynitride. For example, the high dielectric material usable as the gate insulating film (130) may comprise HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0059] The cell region separation layer (CSP) can be placed on the bit line (BL) on the connection region (INT).

[0060] The cell region separation layer (CSP) may include a first insulating film (210), a second insulating film (220), and a third insulating film (230) that are sequentially disposed on the outer surface (OSF) of the outermost active pattern (AP) among a plurality of active patterns (AP). Here, the outermost active pattern (AP) may represent an active pattern (AP) disposed outside the cell region (MCA), and may represent the active pattern (AP) closest to the connection region (INT) among the plurality of active patterns (AP). In one example, the outer surface (OSF) of the outermost active pattern (AP) may be one of the criteria defining the boundary between the cell region (MCA) and the connection region (INT).

[0061] The first insulating film (210) may be placed on the outer surface (OSF) of the outermost active pattern (AP). Additionally, referring to FIG. 3, a plurality of outermost active patterns (AP) may be spaced apart from each other in a second direction (D2) on one side of the outermost word line (WL) among a plurality of word lines (WL) (e.g., the side adjacent to the connection area (INT)). The first insulating film (210) may be extended in the second direction (D2) along one side of each of the plurality of outermost active patterns (AP) (e.g., the side adjacent to the connection area (INT)).

[0062] The second insulating film (220) may include a first portion (or, vertical extension) (222) disposed on one side (e.g., inner side) of the first insulating film (210) and a second portion (or, horizontal extension) (224) extending horizontally (e.g., first direction (D1) and second direction (D2)) from the end (e.g., lower end) of the first portion (222). The second portion (224) may be disposed parallel to the surface of the substrate (100) or the surface of the bit line (BL).

[0063] According to one embodiment, the lower surface of the second part (224) may come into contact with the upper surface of the bit line (BL). For example, the lower surface of the second part (224) may include a portion that comes into contact with the upper surface of the bit line (BL). If the bit line (BL) has a structure that is cut within the connection area (INT), the lower surface of the second part (224) may include a portion that does not come into contact with the upper surface of the bit line (BL).

[0064] A third insulating film (230) may be placed on the first portion (222) and the second portion (224) of the second insulating film (220). For example, the first insulating film (210) may be placed on the outer surface of the first portion (222). The third insulating film (230) may be placed on the inner surface of the first portion (222) and the upper surface of the second portion (224). The third insulating film (230) may overlap the second portion (224) in the third direction (D3). The second insulating film (220) (e.g., the first portion (222)) may include a portion placed between the first insulating film (210) and the third insulating film (230), and the second insulating film (220) (e.g., the second portion (224)) may include a portion placed between the third insulating film (230) and the bit line (BL).

[0065] The third insulating film (230) may extend in a horizontal direction (e.g., a first direction (D1) and a second direction (D2)). The third insulating film (230) may be positioned parallel to the upper surface of the substrate (100) or the upper surface of the bit line (BL). The third insulating film (230) may be a structure wrapped by the second insulating film (220). For example, both sides along the first direction (D1) of the third insulating film (230) and the lower surface of the third insulating film (230) may be surrounded by the second insulating film (220).

[0066] Referring to FIG. 3, the cell region separation layer (CSP) may have a symmetrical structure within the connection region (INT). For example, the first insulating films (210) may be spaced apart from each other in opposing directions (e.g., a first direction (D1) or a second direction (D2)). For example, each first insulating film (210) may be placed in the edge regions on both sides of the connection region (INT). A second insulating film (220) may be placed inside the first insulating film (210). The second insulating film (220) may have a U-shape. For example, the second insulating film (220) may include a first portion (222) each spaced apart inside the first insulating film (210) and a second portion (224) connecting the lower ends of the first portions (222) each spaced apart. The third insulating film (230) may be disposed on the inner surface of the first portion (222) and the upper surface of the second portion (224) of the second insulating film (220). For example, the third insulating film (230) may fill the space defined by the inner surface of the first portion (222) and the upper surface of the second portion (224), which are spaced apart in opposite directions.

[0067] According to one embodiment, the first insulating film (210) and the second insulating film (220) may comprise different materials. The first insulating film (210) and the second insulating film (220) may comprise materials with different etching selectivity ratios. For example, the first insulating film (210) may comprise silicon oxide and the second insulating film (220) may comprise silicon nitride, but is not limited thereto. Additionally, the first insulating film (210) and the third insulating film (230) may comprise the same material. However, the scope of the present disclosure is not limited thereto.

[0068] A semiconductor memory device may further include a contact interlayer insulating layer (190). The contact interlayer insulating layer (190) may be disposed on an active pattern (AP). Additionally, the contact interlayer insulating layer (190) may cover a gate isolation layer (150), a back gate isolation layer (170), and a cell region isolation layer (CSP). The contact interlayer insulating layer (190) may include an insulating material, such as silicon oxide, silicon nitride, or a combination thereof, but is not limited thereto.

[0069] A landing pad (LP) can be connected to an active pattern (AP). For example, the landing pad (LP) can penetrate the contact interlayer insulation layer (190). Each of the plurality of landing pads (LP) can be separated from one another by the contact interlayer insulation layer (190). The contact interlayer insulation layer (190) can be placed between the plurality of landing pads (LP).

[0070] The landing pad (LP) may include a conductive material. The conductive material may include, for example, doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal, or a combination thereof.

[0071] According to one embodiment, although not illustrated, a buried contact may be disposed between a landing pad (LP) and an active pattern (AP). The buried contact may include a conductive material. For example, it may include doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, a two-dimensional material, a metal, or a combination thereof, and may be composed of a single film and / or multiple films.

[0072] The capacitor structure (C_ST) may include a first electrode (312), a dielectric film (314), a conductive film (316), and a second electrode (318).

[0073] The first electrode (312) may be placed on the landing pad (LP). The first electrode (312) may be electrically connected to the landing pad (LP). A portion of the first electrode (312) may be placed within the etch stop layer (320). For example, the first electrode (312) may be connected to the landing pad (LP) by penetrating the etch stop layer (320).

[0074] According to one embodiment, the first electrode (312) may have a pillar shape and may extend in a third direction (D3). Additionally, the first electrode (312) may include, for example, at least one of a conductive metal material (cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), etc.), a metal nitride (titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), etc.), a precious metal material (platinum (Pt), ruthenium (Ru), iridium (Ir), etc.), a conductive oxide film (PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo, etc.), and a metal silicide film. However, the present disclosure is not limited thereto.

[0075] The dielectric film (314) may be disposed on the first electrode (312). The dielectric film (314) may extend along the profile of the side and top surfaces of the first electrode (312). Additionally, the dielectric film (314) may be disposed on the etch stop layer (320). Furthermore, the dielectric film (314) may include a high dielectric constant material, for example, silicon oxide, silicon nitride, silicon oxynitride, and metal. Although the dielectric film (314) is depicted as a single film, this is for convenience of explanation only and is not limited thereto. Unlike what is depicted, the dielectric film (314) may include multiple films.

[0076] A conductive film (316) may be disposed on a dielectric film (314). The conductive film (316) may extend along the profile of the dielectric film (314). The conductive film (316) may cover the dielectric film (314). The conductive film (316) may comprise, for example, at least one of a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride, etc.), a metal (e.g., ruthenium, iridium, titanium, or tantalum, etc.), and a conductive metal oxide (e.g., iridium oxide or niobium oxide, etc.), but is not limited thereto.

[0077] The second electrode (318) may be placed on the conductive film (316). For example, the second electrode (318) may fill the empty space between the first electrodes (312). The second electrode (318) may fill the space between the plurality of first electrodes (312) remaining after the dielectric film (314) and the conductive film (316) are formed. The second electrode (318) may be electrically connected to the conductive film (316). The second electrode (318) may include, for example, at least one of an elemental semiconductor material film or a compound semiconductor material film. The second electrode (318) may include doped n-type impurities or p-type impurities.

[0078] The semiconductor memory device may further include an upper interlayer insulating layer (330). The upper interlayer insulating layer (330) may be disposed on the cell region (MCA) and the connection region (INT) of the substrate (100). For example, the upper interlayer insulating layer (330) may cover the second electrode (318) in the cell region (MCA). Additionally, the upper interlayer insulating layer (330) may cover the contact interlayer insulating layer (190) disposed on the cell region separation layer (CSP) in the connection region (INT).

[0079] The upper interlayer insulating layer (330) may include an insulating material, for example, silicon oxide, silicon nitride, or a combination thereof, but is not limited thereto.

[0080] FIG. 5 is a drawing for illustrating a semiconductor memory device according to exemplary embodiments of the present disclosure. Specifically, FIG. 5 is an enlarged view of the R1 region of FIG. 4. Hereinafter, for convenience of explanation, the description will focus on configurations different from those described in FIG. 1 to FIG. 4.

[0081] According to one embodiment, the lower surface of the active pattern (AP) may be placed in a co-plane with the lower surface of the second insulating film (220). For example, the lower surface of the active pattern (AP) and the lower surface of the second insulating film (220) may be aligned along a first direction (D1). The lower surface of the active pattern (AP) and the lower surface of the second insulating film (220) may be in contact with the upper surface of the bit line (BL).

[0082] According to one embodiment, the lower surface of the gate capping layer (140) may be placed in a co-plane with the lower surface of the second insulating film (220). For example, the lower surface of the gate capping layer (140) and the lower surface of the second insulating film (220) may be aligned along a first direction (D1). The lower surface of the gate capping layer (140) and the lower surface of the second insulating film (220) may be in contact with the upper surface of the bit line (BL). Additionally, the gate capping layer (140) may be overlapped in the first direction (D1) with the second insulating film (220), for example, a second portion (224) of the second insulating film (220).

[0083] According to one embodiment, the lower surface of the back gate capping layer (160) may be placed in a co-plane with the lower surface of the second insulating film (220). For example, the lower surface of the back gate capping layer (160) and the lower surface of the second insulating film (220) may be aligned along a first direction (D1). The lower surface of the back gate capping layer (160) and the lower surface of the second insulating film (220) may be in contact with the upper surface of the bit line (BL). Additionally, the back gate capping layer (160) may overlap with the second insulating film (220), for example, a second portion (224) of the second insulating film (220) in the first direction (D1).

[0084] According to one embodiment, the first distance (H1) from the upper surface to the lower surface of the active pattern (AP) may be the same as the second distance (H2) from the upper surface to the lower surface of the first insulating film (210). For example, the vertical level of the upper surface of the active pattern (AP) may correspond to the vertical level of the upper surface of the first insulating film (210), and the vertical level of the lower surface of the active pattern (AP) may correspond to the vertical level of the lower surface of the first insulating film (210).

[0085] In the present disclosure, "vertical level" may represent a vertical level in a third direction (D3). "Vertical level" may represent a distance in the third direction (D3) from a reference level to the surface of a specific configuration. The reference level may be a vertical level corresponding to the upper or lower surface of any component having a flat surface (e.g., a substrate (100) or a bit line (BL)).

[0086] According to one embodiment, the first distance (H1) from the upper surface to the lower surface of the active pattern (AP) may be the same as the third distance (H3) from the upper surface to the lower surface of the first part (222) of the second insulating film (220). For example, the vertical level of the upper surface of the active pattern (AP) may correspond to the vertical level of the upper surface of the first part (222), and the vertical level of the lower surface of the active pattern (AP) may correspond to the vertical level of the lower surface of the first part (222).

[0087] According to one embodiment, the fourth distance (H4) from the upper surface of the horizontal portion (154) of the gate separation layer (150) to the lower surface of the gate capping layer (140) may be the same as the second distance (H2) from the upper surface to the lower surface of the first insulating film (210). For example, the vertical level of the upper surface of the horizontal portion (154) of the gate separation layer (150) may correspond to the vertical level of the upper surface of the first insulating film (210), and the vertical level of the lower surface of the gate capping layer (140) may correspond to the vertical level of the lower surface of the first insulating film (210).

[0088] According to one embodiment, the fourth distance (H4) from the upper surface of the horizontal portion (154) of the gate separation layer (150) to the lower surface of the gate capping layer (140) may be the same as the third distance (H3) from the upper surface to the lower surface of the first portion (222) of the second insulating film (220). For example, the vertical level of the upper surface of the horizontal portion (154) of the gate separation layer (150) may correspond to the vertical level of the upper surface of the first portion (222), and the vertical level of the lower surface of the gate capping layer (140) may correspond to the vertical level of the lower surface of the first portion (222).

[0089] According to one embodiment, the fifth distance (H5) from the upper surface of the back gate separation layer (170) to the lower surface of the back gate capping layer (160) may be the same as the second distance (H2) from the upper surface to the lower surface of the first insulating film (210). For example, the vertical level of the upper surface of the back gate separation layer (170) may correspond to the vertical level of the upper surface of the first insulating film (210), and the vertical level of the lower surface of the back gate capping layer (160) may correspond to the vertical level of the lower surface of the first insulating film (210).

[0090] According to one embodiment, the fifth distance (H5) from the upper surface of the back gate separation layer (170) to the lower surface of the back gate capping layer (160) may be the same as the third distance (H3) from the upper surface to the lower surface of the first part (222) of the second insulating film (220). For example, the vertical level of the upper surface of the back gate separation layer (170) may correspond to the vertical level of the upper surface of the first part (222), and the vertical level of the lower surface of the back gate capping layer (160) may correspond to the vertical level of the lower surface of the first part (222).

[0091] According to one embodiment, the first insulating film (210) and the second insulating film (220) of the cell region separation layer (CSP) may function as an etching stop layer or a polishing stop layer. The embodiments described with reference to FIG. 5 may be attributed to the first insulating film (210) and the second insulating film (220) acting as a CMP stopper in the Chemical Mechanical Polishing (CMP) process. By doing so, it is possible to provide a semiconductor memory device with improved electrical characteristics and / or reliability by improving surface flatness and thickness uniformity that occurs during the Chemical Mechanical Polishing (CMP) process.

[0092] FIGS. 6 to 8 are drawings for illustrating a semiconductor memory device according to exemplary embodiments of the present disclosure. Specifically, FIGS. 6 to 8 are enlarged views of the R2 region of FIGS. 4. Hereinafter, for convenience of explanation, the description will focus on configurations different from those described in FIGS. 1 to 5.

[0093] Referring to FIG. 6, the first width (W1) according to the first direction (D1) of the first insulating film (210), the second width (W2) according to the first direction (D1) of the first part (222), and the third width (W3) according to the third direction (D3) of the second part (224) may be the same as each other.

[0094] Referring to FIG. 7, the first width (W1) along the first direction (D1) of the first insulating film (210) may be larger than the second width (W2) along the first direction (D1) of the first part (222) and the third width (W3) along the third direction (D3) of the second part (224). That is, the second width (W2) along the first direction (D1) of the first part (222) and the third width (W3) along the third direction (D3) of the second part (224) may be smaller than the first width (W1) along the first direction (D1) of the first insulating film (210). In this case, the second width (W2) and the third width (W3) may be the same, but are not limited thereto. The second width (W2) and the third width (W3) may be different.

[0095] Referring to FIG. 8, the first width (W1) along the first direction (D1) of the first insulating film (210) may be smaller than the second width (W2) along the first direction (D1) of the first part (222) and the third width (W3) along the third direction (D3) of the second part (224). That is, the second width (W2) along the first direction (D1) of the first part (222) and the third width (W3) along the third direction (D3) of the second part (224) may be larger than the first width (W1) along the first direction (D1) of the first insulating film (210). In this case, the second width (W2) and the third width (W3) may be the same, but are not limited thereto. The second width (W2) and the third width (W3) may be different.

[0096] FIG. 9 is a drawing for illustrating a semiconductor memory device according to exemplary embodiments of the present disclosure. FIG. 9 may correspond to a cross-sectional view taken along line AA of FIG. 2. The semiconductor memory device of FIG. 9 may be substantially identical to the semiconductor memory device described with reference to FIG. 1 through 8, except for the shape of the cell region separation layer (CSP). Hereinafter, for convenience of explanation, the description will focus on configurations different from those described in FIG. 1 through 8.

[0097] According to one embodiment, the cell region separation layer (CSP) may include a first insulating film (210) and a second insulating film (220) that are sequentially disposed on the outer surface (OSF) of the outermost active pattern (AP) among a plurality of active patterns (AP). The first insulating film (210) may be disposed adjacent to the active pattern (AP) on the cell region (MCA). Additionally, the second insulating film (220) may be disposed on one side of the first insulating film (210). In this case, the lower surface of the second insulating film (220) may be in contact with the upper surface of the bit line (BL).

[0098] According to one embodiment, the distance from the upper surface to the lower surface of the first insulating film (210) may be the same as the distance from the upper surface to the lower surface of the second insulating film (220). That is, the vertical level of the upper surface of the first insulating film (210) corresponds to the vertical level of the upper surface of the second insulating film (220), and the vertical level of the lower surface of the first insulating film (210) corresponds to the vertical level of the lower surface of the second insulating film (220).

[0099] According to one embodiment, the height of the second insulating film (220), that is, the distance from the upper surface to the lower surface of the second insulating film (220), can be maintained substantially constant within the connection area (INT).

[0100] FIGS. 10 and 11 are layout diagrams showing a semiconductor memory device according to exemplary embodiments of the present disclosure. The semiconductor memory device of FIGS. 10 and 11 may be substantially the same as the semiconductor memory device described with reference to FIGS. 1 through 9, except for the arrangement shape of the cell region (MCA) and peripheral circuit region (PCA). Hereinafter, for convenience of explanation, the description will focus on configurations different from those described in FIGS. 1 through 9. The semiconductor memory device described with reference to FIGS. 1 through 9 may correspond to the drawing cut along line BB of FIG. 11.

[0101] Referring to FIGS. 10 and 11, a semiconductor memory device may include a cell region (MCA) and a peripheral circuit region (PCA) arranged in a planar manner (e.g., a first direction (D1) and a second direction (D2)).

[0102] A peripheral circuit area (PCA) may be placed around a cell area (MCA). For example, the peripheral circuit area (PCA) may surround the cell area (MCA). In this case, a connection area (INT) may be placed between the cell area (MCA) and the peripheral circuit area (PCA) surrounding the cell area (MCA). According to one embodiment, the connection area (INT) may include an insulation pattern placed to separate adjacent cell areas (MCA) and peripheral circuit areas (PCA).

[0103] FIGS. 12 to 19 are intermediate step drawings for explaining a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. FIGS. 12 to 19 may correspond to cross-sectional views taken along AA of FIG. 2 or BB of FIG. 11. For convenience of explanation, the following description will be based on an example using the cross-sectional view AA of FIG. 2.

[0104] Referring to FIG. 12, a preliminary substrate (300) may be provided, comprising a preliminary cell region (PMCA) and a preliminary connection region (PINT) disposed on one side of the preliminary cell region (PMCA). A preliminary insulating layer (310), a first mask layer (HM1), a second mask layer (HM2), and a photoresist layer (PR) may be formed on the preliminary substrate (300).

[0105] The preliminary insulating layer (310) may include silicon nitride. The first mask layer (HM1) may include a Spin on Hardmask (SOH) pattern. The second mask layer (HM2) may include silicon nitride. However, the scope of the present disclosure is not limited thereto. The materials of the preliminary insulating layer (310), the first mask layer (HM1), and the second mask layer (HM2) are not limited thereto and may be varied in many ways.

[0106] Referring to FIGS. 13 and 14, a cell separation trench (ST) can be formed within the preliminary connection area (PINT) by patterning the preliminary connection area (PINT). Subsequently, a first preliminary insulating film (210P), a second preliminary insulating film (220P), and a third preliminary insulating film (230P) can be formed sequentially on the inner wall (TW) of the cell separation trench (ST) and the upper surface of the preliminary substrate (300) of the preliminary cell area (PMCA), specifically on the upper surface of the preliminary insulating layer (310). In this case, the third preliminary insulating film (230P) can be formed such that the height of the upper surface is maintained constant in the preliminary cell area (PMCA) and the preliminary cell area (PMCA).

[0107] Referring to FIG. 15, the third preliminary insulating film (230P) can be polished. For example, the third preliminary insulating film (230P) can be polished up to the upper surface of the second preliminary insulating film (220P). Accordingly, the second preliminary insulating film (220P) can be exposed in the preliminary cell region (PMCA), and the upper surface of the third preliminary insulating film (230P) in the preliminary connection region (PINT) can be placed in a co-plane with the upper surface of the second preliminary insulating film (220P) in the preliminary cell region (PMCA). In one embodiment, the third preliminary insulating film (230P) can be polished by a chemical mechanical polishing (CMP) process.

[0108] Referring to FIG. 16, the second pre-insulating film (220P) can be polished. For example, the second pre-insulating film (220P) can be polished up to the upper surface of the first pre-insulating film (210P). Accordingly, the first pre-insulating film (210P) can be exposed in the pre-cell region (PMCA), and the upper surfaces of the second pre-insulating film (220P) and the third pre-insulating film (230P), respectively, in the pre-connection region (PINT) can be placed in a co-plane with the upper surface of the first pre-insulating film (210P) in the pre-cell region (PMCA). In one embodiment, the second pre-insulating film (220P) can be polished by a chemical mechanical polishing (CMP) process.

[0109] Referring to FIG. 17, a plurality of word lines can be formed within a preliminary substrate (300). For example, after patterning the preliminary substrate (300), a preliminary gate insulating film (132) can be formed within the patterned recess, and preliminary word lines (WL_P) can be formed spaced apart from each other thereon. A preliminary gate separation layer (150P) can be formed between the preliminary word lines (WL_P) spaced apart from each other within the recess.

[0110] A plurality of back gate electrodes can be formed within the pre-substrate (300). For example, after patterning the pre-substrate (300), a pre-back gate insulating film (182) can be formed within the patterned recess, and a pre-back gate electrode (BG_P) can be formed thereon. Subsequently, a back gate isolation layer (170) can be formed on the pre-back gate electrode (BG_P).

[0111] Multiple active patterns can be formed within the preliminary substrate (300). The area between the recess for forming a word line and the recess for forming a back gate electrode within the preliminary substrate (300) can be defined as a preliminary active pattern (AP_P).

[0112] Next, an interlayer insulating layer (190) and a landing pad (LP) can be formed, and a capacitor structure (CAP) including a first electrode (312), a dielectric film (314), a conductive film (316), and a second electrode (318) can be formed. Additionally, an upper interlayer insulating layer (330) covering the capacitor structure (CAP), for example, the second electrode (318) and the interlayer insulating layer (190) can be formed.

[0113] Referring to FIG. 18, the lower surface of the preliminary substrate (300) may be flipped so that it faces upward, and then the lower surface of the preliminary substrate (300) may be polished. For example, the preliminary substrate (300) in the preliminary cell region (PMCA) and preliminary connection region (PINT) may be polished up to the lower surface (BS1) of the first preliminary insulating film (210P). In one embodiment, the preliminary substrate (300) may be polished by a chemical mechanical polishing (CMP) process.

[0114] Referring to FIG. 19, the first pre-insulating film (210) can be polished up to the lower surface (BS2) of the second pre-insulating film (220) in the pre-connection region (PINT). In one embodiment, the first pre-insulating film (210) can be polished by a chemical mechanical polishing (CMP) process. In this process, the pre-word line (WL_P), pre-back gate electrode (BG_P), pre-active pattern (AP_P), etc., can be polished together.

[0115] Subsequently, after further patterning the preliminary word line (WL_P) and the preliminary back gate electrode (BG_P), the gate capping layer (140) and the back gate capping layer (160) are formed, thereby forming a plurality of word lines (WP), a plurality of back gate electrodes (BG), and a plurality of active patterns (AP), etc.

[0116] Next, a bit line (BL) and a landing pad (LP) and a capacitor structure (CAP) connected to a plurality of active patterns (AP) can be formed to be connected to a plurality of active patterns (AP). In this process, the preliminary insulating layer (310) can be formed as an inter-contact insulating layer (190). Through such a process, a semiconductor memory device described with reference to FIGS. 1 to 11 can be provided.

[0117] FIG. 20 is a flowchart for explaining a method for manufacturing a semiconductor memory device according to one embodiment of the present disclosure.

[0118] A method for manufacturing a semiconductor memory device (2000) may be disclosed by preparing a preliminary substrate including a preliminary cell region and a preliminary connection region disposed on one side of the preliminary cell region (S2010). A cell separation trench may be formed within the preliminary connection region (S2020). A first preliminary insulating film, a second preliminary insulating film, and a third preliminary insulating film may be formed sequentially on the inner wall of the cell separation trench and on the upper surface of the preliminary substrate of the preliminary cell region (S2030).

[0119] A plurality of word lines can be formed within a preliminary cell region, spaced apart from each other in a first direction and each extending in a second direction that intersects the first direction (S2040). A plurality of active patterns can be formed within the preliminary cell region, each placed on one side of a plurality of word lines (S2050). After forming the active patterns, a landing pad connected to the active patterns can be formed, and a capacitor structure connected to the landing pad can be formed.

[0120] The preliminary substrate in the preliminary cell region and the preliminary connection region can be polished up to the lower surface of the first preliminary insulating film (S2060). By polishing the first preliminary insulating film up to the lower surface of the second preliminary insulating film in the preliminary connection region, a cell separation insulating film comprising a first insulating film, a second insulating film, and a third insulating film that are sequentially disposed on the inner wall of the cell separation trench can be formed (S2070).

[0121] For example, a cell separation insulating film can be formed comprising a first insulating film disposed on the inner wall of a cell separation trench, a second insulating film comprising a first portion disposed on one side of the first insulating film and a second portion extending in a direction parallel to the surface of a pre-substrate (e.g., a first direction and a second direction) from the end of the first portion, and a third insulating film disposed on the first portion and the second portion.

[0122] According to one embodiment, a first insulating film and a second insulating film can be formed such that a first width along a first direction of the first insulating film, a second width along a first direction of the first part, and a third width along a third direction intersecting the first and second directions of the second part are equal to each other.

[0123] According to one embodiment, the first insulating film and the second insulating film can be formed such that the first width along the first direction of the first insulating film is greater than the second width along the first direction of the first part and the third width along the third direction of the second part.

[0124] According to one embodiment, the first insulating film and the second insulating film can be formed such that the first width along the first direction of the first insulating film is smaller than the second width along the first direction of the first part and the third width along the third direction of the second part.

[0125] It can form a bit line that contacts the lower surface of the active pattern and the second insulating film and extends in the first direction.

[0126] Although the present invention has been described above by limited embodiments and drawings, the present invention is not limited thereto, and it is obvious that various modifications and variations are possible within the scope of the technical spirit of the present invention and the equivalent scope of the claims described below by those skilled in the art to which the present invention belongs.

[0127] Exemplary embodiments are not limited to being mutually exclusive. For example, some exemplary embodiments may include features referenced in one or more drawings and may simultaneously include one or more other features referenced in other drawings. Explanation of the symbols

[0128] 100: Substrate MCA: Cell area INT: Connection area BL: Beat Line WL: Ward Reinforcement AP: Active Pattern CSP: Cell region separation layer

Claims

Claim 1 A semiconductor memory device comprising: a substrate including a cell region and a connection region disposed on one side of the cell region; a bit line disposed on the substrate and extending in a first direction across the cell region and the connection region; a word line disposed on the cell region above the bit line and extending in a second direction intersecting the first direction; an active pattern disposed on one side of the word line on the cell region; and a cell region separation layer disposed on the bit line on the connection region, wherein the active pattern includes an outermost active pattern disposed on the outside of the cell region, and the cell region separation layer includes a first insulating film disposed on the outer surface of the outermost active pattern and extending in the second direction; and a second insulating film comprising a first portion disposed on one side of the first insulating film and a second portion extending in the first direction from the end of the first portion, wherein the lower surface of the second portion contacts the upper surface of the bit line. Claim 2 A semiconductor memory device according to claim 1, wherein the cell region separation layer further comprises a third insulating film disposed on the first portion and the second portion. Claim 3 A semiconductor memory device according to paragraph 2, wherein the second portion comprises a portion disposed between the third insulating film and the bit line. Claim 4 A semiconductor memory device according to paragraph 2, wherein the first portion comprises a portion disposed between the first insulating film and the third insulating film. Claim 5 A semiconductor memory device according to claim 1, wherein the lower surface of the active pattern is disposed in a co-plane with the lower surface of the second insulating film. Claim 6 A semiconductor memory device according to claim 1, further comprising a gate capping layer disposed between the word line and the bit line, wherein the lower surface of the gate capping layer is disposed in a co-plane with the lower surface of the second insulating film. Claim 7 A semiconductor memory device comprising: a substrate including a cell region and a connection region disposed on one side of the cell region; a bit line disposed on the substrate and extending in a first direction across the cell region and the connection region; a plurality of word lines including a first word line and a second word line that are spaced apart from each other in the first direction on the bit line on the cell region and each extending in a second direction that intersects the first direction; a plurality of active patterns on the cell region, including a first active pattern disposed on a first side of the first word line and a second active pattern disposed on a second side opposite to the first side of the second word line; and a cell region separation layer disposed on the bit line on the connection region, wherein the cell region separation layer comprises a first insulating film and a second insulating film disposed sequentially on the outer surface of the outermost active pattern among the plurality of active patterns defining the boundary between the cell region and the connection region, and the lower surface of the second insulating film contacts the upper surface of the bit line. Claim 8 A semiconductor memory device according to claim 7, further comprising: a gate capping layer disposed on the lower surface of each of the first word line and the second word line; and a gate separation layer disposed between the first word line and the second word line, wherein the gate separation layer comprises: a vertical portion extending in a third direction intersecting the first direction and the second direction, respectively, along the second side of the first word line and the first side of the second word line; and a horizontal portion connected to the end of the vertical portion and disposed on the upper surface of each of the first word line and the second word line. Claim 9 A semiconductor memory device according to claim 8, wherein the distance from the upper surface of the horizontal portion of the gate separation layer to the lower surface of the gate capping layer is the same as the distance from the upper surface to the lower surface of the second insulating film. Claim 10 A substrate comprising a cell region and a connection region disposed on one side of the cell region; a bit line disposed on the substrate and extending in a first direction across the cell region and the connection region; a plurality of word lines comprising a first word line and a second word line spaced apart from each other in the first direction on the bit line on the cell region, each extending in a second direction intersecting the first direction; and a plurality of active patterns on the cell region, comprising a first active pattern disposed on a first side of the first word line and a second active pattern disposed on a second side of the second word line opposite to the first side. A semiconductor memory device comprising a cell region separation layer disposed on the bit line on the connection region, wherein the cell region separation layer comprises a first insulating film, a second insulating film, and a third insulating film sequentially disposed on the outer surface of the outermost active pattern among a plurality of active patterns defining the boundary between the cell region and the connection region, wherein the first insulating film and the second insulating film comprise different materials, and the first insulating film and the third insulating film comprise the same material, wherein the lower surface of the first insulating film and the lower surface of the second insulating film are in contact with the upper surface of the bit line, and the second insulating film comprises a portion disposed between the third insulating film and the bit line.

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