Two-dimensional cell placement optimization apparatus and method

Abstract

A two-dimensional cell placement optimization device according to one embodiment is a two-dimensional cell placement optimization device that optimizes a two-dimensional cell placement of a semiconductor circuit by executing program code loaded into one or more memory devices through one or more processors, wherein the program code is executed to generate a plurality of sequences for a plurality of cells, generates a plurality of two-dimensional placements for the plurality of cells based on the generated sequences, performs a placement evaluation for each of the plurality of two-dimensional placements, and selects a final two-dimensional placement among the plurality of two-dimensional placements based on the result of the placement evaluation.

Description

Technology Field

[0001] The present invention relates to a two-dimensional cell placement optimization apparatus and method, and more specifically, to a two-dimensional cell placement optimization apparatus and method that solves the optimization problem of semiconductor circuit design through an algorithm. Background Technology

[0002] In semiconductor circuit design, cell placement optimization is a critical process for determining the placement of logic elements within a chip. Since placement quality affects signal delay, power consumption, and area efficiency, optimization techniques are essential.

[0003] Existing methods include Sequential Placement, Monte Carlo Search, and Force-directed Placement.

[0004] In particular, the main goals of optimization include minimizing wire length, balancing power consumption, and maintaining signal integrity. Current technologies are improving batch optimization by utilizing ML-based predictive models, reinforcement learning, and metaheuristic techniques. The problem to be solved

[0005] One embodiment of the present invention aims to provide a two-dimensional cell placement optimization apparatus and method that minimizes the wire length of a circuit by representing the cells of a circuit as a sequence and optimizing the two-dimensional placement using a local search algorithm based on the sequence. means of solving the problem

[0006] Among the embodiments, the two-dimensional cell placement optimization device is a two-dimensional cell placement optimization device that optimizes the two-dimensional cell placement of a semiconductor circuit by executing program code loaded into one or more memory devices through one or more processors, wherein the program code is executed to generate a plurality of sequences for a plurality of cells, generates a plurality of two-dimensional placements for the plurality of cells based on the generated sequences, performs a placement evaluation for each of the plurality of two-dimensional placements, and determines a final two-dimensional placement among the plurality of two-dimensional placements based on the result of the placement evaluation.

[0007] Generating multiple sequences for the plurality of cells may include generating the plurality of sequences randomly without duplication.

[0008] Generating multiple sequences for the plurality of cells may include sequentially generating the plurality of sequences using a local search algorithm based on the results of the batch evaluation.

[0009] Generating multiple sequences for the plurality of cells may further include generating the plurality of sequences using a perturbation algorithm when a local optima occurs according to the local search algorithm.

[0010] Generating a plurality of 2D placements for the plurality of cells based on the above sequences may include generating the plurality of 2D placements that satisfy the feasibility of the semiconductor circuit based on cell data for the plurality of cells.

[0011] The step of generating a plurality of 2D placements for the plurality of cells based on the above sequences may further include generating the plurality of 2D placements that satisfy all predetermined constraints based on the cell data in relation to the placement of the plurality of cells.

[0012] The above cell data may include the two-dimensional shape of the cell, the location of the port within the cell, connection information of the cells, power information of the cell, and flip information of the cell considering the power.

[0013] Generating multiple 2D placements for the plurality of cells based on the above sequences may further include generating the plurality of 2D placements that minimize idle space by considering the 2D shape of the plurality of cells, provided that both the feasibility and the constraints are satisfied.

[0014] Performing a placement evaluation for each of the plurality of two-dimensional placements may include measuring the wire length of the semiconductor circuit for the plurality of two-dimensional placements and performing the placement evaluation based on the measured wire length.

[0015] Determining the final two-dimensional layout among the plurality of two-dimensional layouts based on the results of the above layout evaluation may include determining at least one layout among the plurality of two-dimensional layouts that minimizes the wiring length as the final two-dimensional layout using a local search algorithm and a perturbation algorithm.

[0016] Among the embodiments, the two-dimensional cell placement optimization method is a method for optimizing the two-dimensional cell placement of a semiconductor circuit, which is performed by a computing device including a processor and a memory, wherein the processor comprises the steps of: generating a plurality of sequences for a plurality of cells; generating a plurality of two-dimensional placements for the plurality of cells based on the generated sequences; performing a placement evaluation for each of the plurality of two-dimensional placements; and determining a final two-dimensional placement among the plurality of two-dimensional placements based on the result of the placement evaluation.

[0017] The step of generating a plurality of sequences for the plurality of cells may include the step of the processor generating the plurality of sequences randomly without duplication.

[0018] The step of generating a plurality of sequences for the plurality of cells may include the step of the processor generating the plurality of sequences sequentially using a local search algorithm based on the result of the batch evaluation.

[0019] The step of generating a plurality of sequences for the plurality of cells may further include the step of generating the plurality of sequences using a perturbation algorithm when a local obtima occurs according to the local search algorithm.

[0020] The step of generating a plurality of 2D placements for the plurality of cells based on the above sequences may include the step of the processor generating the plurality of 2D placements that satisfy the feasibility of the semiconductor circuit based on cell data for the plurality of cells.

[0021] The step of generating a plurality of 2D placements for the plurality of cells based on the above sequences may further include the step of the processor generating the plurality of 2D placements that satisfy all predetermined constraints based on the cell data in relation to the placement of the plurality of cells.

[0022] The above cell data may include the two-dimensional shape of the cell, the location of the port within the cell, connection information of the cells, power information of the cell, and flip information of the cell considering the power.

[0023] The step of generating a plurality of 2D placements for the plurality of cells based on the above sequences may further include the step of generating the plurality of 2D placements that minimize idle space by considering the 2D shape of the plurality of cells, if the processor satisfies both the feasibility and the constraints.

[0024] The step of performing a placement evaluation for each of the plurality of two-dimensional placements may include the step of the processor measuring the wire length of the semiconductor circuit for the plurality of two-dimensional placements and performing the placement evaluation based on the measured wire length.

[0025] The step of determining a final two-dimensional layout among the plurality of two-dimensional layouts based on the results of the above layout evaluation may include the step of the processor determining at least one layout among the plurality of two-dimensional layouts that minimizes the wiring length as the final two-dimensional layout using a local search algorithm and a perturbation algorithm. Effects of the invention

[0026] A two-dimensional cell placement optimization device and method according to one embodiment of the present invention can minimize the wire length of a circuit by representing the cells of the circuit as a sequence and optimizing the two-dimensional placement using a local search algorithm based on the sequence. Brief explanation of the drawing

[0027] FIG. 1 is a block diagram of a two-dimensional cell placement optimization device according to one embodiment of the present invention. FIG. 2 is a flowchart of a two-dimensional cell placement optimization method according to an embodiment of the present invention. FIG. 3 is a flowchart of a two-dimensional cell placement optimization method according to one embodiment of the present invention. FIG. 4 is a diagram illustrating a two-dimensional cell placement optimization method according to an embodiment of the present invention. FIG. 5 is a diagram illustrating a two-dimensional cell placement optimization method according to an embodiment of the present invention. FIG. 6 is a drawing for explaining a computing device according to an embodiment of the present invention. Specific details for implementing the invention

[0028] Embodiments of the present invention are described below with reference to the attached drawings so that those skilled in the art can easily implement them. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification are denoted by similar reference numerals.

[0029] Throughout the specification and claims, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. Such terms are used solely for the purpose of distinguishing one component from another.

[0030] Terms such as "...part," "...unit," and "module" as used in the specification may refer to a unit capable of processing at least one function or operation described in this specification, and may be implemented as hardware or a circuit, software, or a combination of hardware or a circuit and software.

[0031] In addition, at least some of the configurations or functions of the two-dimensional cell placement optimization device and method according to the embodiments described below may be implemented as a program or software, and the program or software may be stored on a computer-readable medium.

[0032] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0033] FIG. 1 is a block diagram of a two-dimensional cell placement optimization device according to one embodiment of the present invention.

[0034] A two-dimensional cell placement optimization device (100) according to one embodiment can execute program code or instructions loaded into one or more memory devices through one or more processors.

[0035] For example, the two-dimensional cell placement optimization device (100) may be implemented as a computing device (900) as described below in relation to FIG. 6. In this case, one or more processors may correspond to the processor (910) of the computing device (900), and one or more memory devices may correspond to the memory (930) of the computing device (900).

[0036] Program code or instructions can be executed by one or more processors to optimize two-dimensional cell layout in semiconductor circuit design. In this specification, the term "module" has been used to logically distinguish these functions performed by program code or instructions.

[0037] Referring to FIG. 1, a two-dimensional cell placement optimization device (100) includes a sequence generation module (110), a two-dimensional placement generation module (120), a placement evaluation module (130), and a final placement determination module (140).

[0038] The sequence generation module (110) can generate multiple sequences for multiple cells.

[0039] The sequence generation module (110) can randomly generate multiple sequences without duplication.

[0040] The sequence generation module (110) can generate multiple sequences sequentially using a local search algorithm.

[0041] The sequence generation module (110) can sequentially generate multiple sequences using a local search algorithm based on the results of a batch evaluation for each of the multiple sequences.

[0042] The sequence generation module (110) can generate the plurality of sequences using a perturbation algorithm when a local obtima occurs according to the local search algorithm.

[0043] The 2D placement generation module (120) can generate multiple 2D placements for multiple cells based on the generated sequences.

[0044] The two-dimensional layout generation module (120) can generate multiple two-dimensional layouts that satisfy the feasibility of semiconductor circuits based on cell data for multiple cells.

[0045] The 2D layout generation module (120) can generate multiple 2D layouts that satisfy all predetermined constraints based on cell data in relation to the layout of multiple cells.

[0046] Here, cell data may include at least one of the following: the two-dimensional shape of the cell, the location of the port within the cell, the connection information of the cells, the power or power information of the cell, and / or the flip information of the cell considering the power.

[0047] If the 2D layout generation module (120) satisfies both the feasibility and the constraints mentioned above, it can generate multiple 2D layouts that minimize idle space by considering the 2D shape of multiple cells.

[0048] The batch evaluation module (130) can perform a batch evaluation for each of the multiple two-dimensional batches.

[0049] The placement evaluation module (130) can measure the wire length of a semiconductor circuit for a plurality of two-dimensional placements and perform a placement evaluation based on the measured wire length.

[0050] The final placement decision module (140) can determine the final two-dimensional placement among a plurality of two-dimensional placements based on the results of the placement evaluation.

[0051] The final placement decision module (140) can determine at least one placement that minimizes the wiring length among a plurality of two-dimensional placements as the final two-dimensional placement by using a local search algorithm and a perturbation algorithm.

[0052] FIG. 2 is a flowchart of a two-dimensional cell placement optimization method according to an embodiment of the present invention. The two-dimensional cell placement optimization method can be performed through the two-dimensional cell placement optimization device (100) of FIG. 1.

[0053] In FIG. 2, the two-dimensional cell placement optimization device (100) can generate multiple sequences for multiple cells (step S210).

[0054] The two-dimensional cell placement optimization device (100) can randomly generate multiple sequences without duplication.

[0055] The 2D cell placement optimization device (100) can sequentially generate multiple sequences using a local search algorithm based on the results of the placement evaluation.

[0056] The 2D cell placement optimization device (100) can generate multiple sequences using a perturbation algorithm when a local optima occurs according to a local search algorithm.

[0057] The 2D cell placement optimization device (100) can generate multiple 2D placements for multiple cells based on the generated sequences (step S22).

[0058] The two-dimensional cell placement optimization device (100) can generate multiple two-dimensional placements that satisfy the feasibility of semiconductor circuits based on cell data for multiple cells.

[0059] The two-dimensional cell placement optimization device (100) can generate multiple two-dimensional placements that satisfy all predetermined constraints based on cell data in relation to the placement of multiple cells.

[0060] Cell data may include the two-dimensional shape of the cell, the location of ports within the cell, connection information of the cells, power information of the cell, and flip information of the cell considering the power.

[0061] If both feasibility and constraints are satisfied, the 2D cell layout optimization device (100) can generate multiple 2D layouts that minimize idle space by considering the 2D shape of multiple cells.

[0062] The two-dimensional cell placement optimization device (100) can measure the wire length of a semiconductor circuit for a plurality of two-dimensional placements and perform a placement evaluation based on the measured wire length (step S230).

[0063] A two-dimensional cell placement optimization device (100) can measure the wire length of a semiconductor circuit for a plurality of two-dimensional placements and perform a placement evaluation based on the measured wire length.

[0064] The 2D cell placement optimization device (100) can select a final 2D placement with minimized wiring length among a plurality of 2D placements based on the result of the placement evaluation (step S240).

[0065] The 2D cell placement optimization device (100) can determine at least one placement that minimizes the wiring length among a plurality of 2D placements as the final 2D placement by using a local search algorithm and a perturbation algorithm.

[0066] FIG. 3 is a flowchart of a two-dimensional cell placement optimization method according to one embodiment of the present invention.

[0067] In FIG. 3, the two-dimensional cell placement optimization device (100) can generate a sequence of multiple cells and generate an initial two-dimensional placement based on the sequence (step S310).

[0068] The two-dimensional cell placement optimization device (100) can generate a sequence randomly and arrange it in two dimensions to generate an initial cell placement.

[0069] The two-dimensional cell placement optimization device (100) represents the circuit optimization problem in a two-dimensional placement form and defines the structure.

[0070] The two-dimensional cell placement optimization device (100) is Displays the current state of the circuit as a sequence of cells.

[0071] The two-dimensional cell placement optimization device (100) can include the two-dimensional shape of the cell, the location of ports within the cell, and connection information of the cells in the cell information.

[0072] The 2D cell placement optimization device (100) can group and manage specific cells that can move together.

[0073] The 2D cell placement optimization device (100) displays the power information of the cell when displaying cell information and generates a cell sequence based on this.

[0074] That is, the 2D cell placement optimization device (100) can generate flip information by considering powers such as VDD, VSS, etc. when generating a cell sequence.

[0075] The 2D cell layout optimization device (100) determines the optimized final 2D cell layout by performing a local search algorithm on the initial cell layout (steps S320 to S330).

[0076] The 2D cell placement optimization device (100) can perform 2D cell placement optimization through a local search algorithm (step S320).

[0077] The 2D cell placement optimization device (100) generates a sequence of cells using a local search algorithm (step S321).

[0078] After that, the two-dimensional cell placement optimization device (100) generates a two-dimensional placement based on the generated sequence (step S322).

[0079] And, the two-dimensional cell placement optimization device (100) can perform a placement evaluation for the generated two-dimensional placement. The placement evaluation can be performed based on measuring the wire length of the semiconductor circuit and whether the measured wire length is minimized.

[0080] The two-dimensional cell placement optimization device (100) can generate a sequence of cells and generate a two-dimensional placement based on the sequence.

[0081] For example, the two-dimensional cell placement optimization device (100) can place cells from the bottom left to the right according to the generated sequence order. When a row is full of placements and the next row is placed, the two-dimensional cell placement optimization device (100) can place them from left to right in the next row.

[0082] The two-dimensional cell placement optimization device (100) is When a row is full and elements are placed in the next row, they may be arranged from right to left depending on the order of their lengths.

[0083] The two-dimensional cell placement optimization device (100) is It is possible to read cell information, the area where cells are placed, dummy area information, power information between upper and lower cells, and cell sequence information.

[0084] And, the 2D cell placement optimization device (100) can manage the top / bottom of the cell according to the cell sequence to match Power constraints such as VDD, VSS, etc.

[0085] The 2D cell placement optimization device (100) can manage the grouped cells to move in group units when specific cells are determined to be in a group in advance.

[0086] The 2D cell placement optimization device (100) places cells such that the idle space area is minimized in a feasible placement when the shape of the connection part of two consecutive cells is different.

[0087] The 2D cell placement optimization device (100) can generate a 2D placement by considering the limited number of connections when the number of connections is limited due to routing congestion.

[0088] That is, the two-dimensional cell placement optimization device (100) can place cells based on a cell sequence while satisfying legalization constraints.

[0089] The 2D cell placement optimization device (100) solves the 2D cell placement optimization problem using a local search-based optimization algorithm.

[0090] The 2D cell placement optimization device (100) performs a local search operation on cells represented in a sequence form.

[0091] The two-dimensional cell placement optimization device (100) is Perform a local search until it reaches a local optima.

[0092] For example, a two-dimensional cell placement optimization device (100) can extract cells represented as a sequence one by one and insert them into different locations.

[0093] The 2D cell placement optimization device (100) can extract and reverse a partial sequence of the cell sequence.

[0094] The 2D cell placement optimization device (100) can select two cells and change their order.

[0095] The 2D cell placement optimization device (100) can extract two consecutive cells and insert them at different locations.

[0096] The 2D cell placement optimization device (100) can extract three consecutive cells and insert them into different locations.

[0097] The 2D cell placement optimization device (100) finds a set of possible placement candidates that satisfy feasibility and constraints when creating a 2D placement and updates the placement in the direction with the greatest improvement (increment) of the placement evaluation criteria.

[0098] The 2D cell placement optimization device (100) can update the cells to have an optimal flip shape after the local search operation is finished.

[0099] A local optimal refers to a solution that is optimal locally (in a part of a region) in an optimization problem. In other words, a local optimal signifies a state where a solution is optimal within a specific range (local), but a better solution may exist when viewed from the perspective of the entire range (global).

[0100] The 2D cell placement optimization device (100) may use the following method to determine local optima.

[0101] For example, a two-dimensional cell placement optimizer (100) evaluates all solutions existing in the neighborhood of the current solution, and if the cost of all neighboring solutions (objective function value, e.g., placement evaluation result) is worse than the current solution, it determines that it corresponds to a local optimizer.

[0102] The 2D cell placement optimization device (100) determines that a local optima has been reached if the placement evaluation result in the local search algorithm is no longer improved for a certain period of time.

[0103] The 2D cell placement optimizer (100) records the search history and checks whether the current placement is similar to the optimal solution previously generated. If the same pattern is repeated, the 2D cell placement optimizer (100) determines that a local optimal has been reached.

[0104] The 2D cell placement optimization device (100) can perform a perturbation operation to create a new placement by changing a part of the placement created according to the final update when it falls into a local optima according to continuous 2D placement updates. The degree of perturbation can be managed directly by the user.

[0105] Perturbation algorithms generate a new solution in optimization problems, such as local search algorithms, by arbitrarily modifying (perturbing) the current solution.

[0106] The 2D cell layout optimization device (100) can generate a global optimum by moving away from a local optimum using a perturbation algorithm.

[0107] The 2D cell placement optimization device (100) designs various Objective functions and cost functions suitable for the user's purpose and reflects the feasibility of placement.

[0108] The 2D cell placement optimization device (100) can determine the 2D placement that achieved the highest placement evaluation result according to optimization based on a local search algorithm and a disturbance algorithm as the final 2D cell placement (step S330).

[0109] The 2D cell placement optimization device (100) forms cells into a sequence according to a cell sequence generated based on a 1D placement algorithm, generates a 2D placement based on this, and performs a placement evaluation based on HPWL (Half parameter wire length) for the generated 2D placement.

[0110] The 2D cell placement optimization device (100) can determine the final 2D placement in which HPWL is minimized as a result of the placement evaluation.

[0111] In this process, the 2D cell placement optimization device (100) optimizes the sequence of each cell through local search and perturbation.

[0112] The two-dimensional cell placement optimization device (100) can consider the constraints required for two-dimensional placement in order to perform two-dimensional placement based on the sequence.

[0113] FIG. 4 is a diagram illustrating a two-dimensional cell placement optimization method according to an embodiment of the present invention.

[0114] Figure 4 is a diagram illustrating an example of local search-based sequence generation and two-dimensional batch generation.

[0115] Figure 4 is a diagram illustrating a two-dimensional layout optimization algorithm. Figure 4 shows the structure of the linkage between a local search operation and a two-dimensional layout.

[0116] The initial sequence (41) is [1, 2, 3, 4, 5, 6, 7, 8, 9, 10]. The 2D cell placement optimizer (100) can move the position of Cell [3, 4] to the right of Cell 9 through a local search operation. The sequence (42) generated through this process is [1, 2, 5, 6, 7, 8, 9, 3, 4, 10].

[0117] The two-dimensional cell placement optimization device (100) can generate a two-dimensional placement (44) using the generated sequence (42) and measure HPWL, which is a circuit wiring length indicator.

[0118] The HPWL of the two-dimensional arrangement (43) based on the initial sequence (41) is 3524. The HPWL of the two-dimensional arrangement (44) based on the sequence (42) generated through the two-dimensional cell arrangement optimization device (100) is 3472.

[0119] Therefore, it can be seen that the wiring length has been reduced compared to the initial length according to the optimization algorithm of the 2D cell placement optimization device (100).

[0120] The 2D cell placement optimization device (100) finds candidate placements that are locally searchable in the current state and updates the cell sequence in the direction that improves the placement evaluation result the most among them.

[0121] The 2D cell placement optimization device (100) can use the First improvement strategy or the Max improvement strategy as an improvement strategy to update to a better result in the Local search.

[0122] First improvement adopts the first alternative better than the current solution as the new current solution and updates it as soon as it is found. Max improvement reviews all alternatives capable of improving the current solution and then makes the final update.

[0123] The 2D cell placement optimization device (100) may use a Max-improvement strategy prioritizing final performance.

[0124] The 2D cell layout optimization device (100) repeats the local search operation in this way to improve it into a better solution. And when it falls into a local optimization, it overcomes it by using a perturbation strategy.

[0125] That is, the two-dimensional cell placement optimization device (100) can repeat this local search-based optimization algorithm to finally generate a two-dimensional three-placement with the shortest wiring length.

[0126] FIG. 5 is a diagram illustrating a two-dimensional cell placement optimization method according to an embodiment of the present invention.

[0127] Figure 5 is an example of two-dimensional arrangement of cells in an actual circuit.

[0128] In FIG. 5, the two-dimensional cell placement optimization device (100) generates a sequence for a circuit composed of 20 cells and, after generating a two-dimensional placement, performs a placement evaluation (e.g., HPWL).

[0129] The 2D cell placement optimization device (100) can output a final cell sequence and 2D placement result through an optimization process using the local search algorithm and the disturbance algorithm described above.

[0130] The two-dimensional cell placement optimization device (100) must satisfy various constraints required for generating a two-dimensional placement for actual circuit placement.

[0131] The 2D cell placement optimization device (100) uses various types of cells for 2D placement. While circuits composed of basic rectangular cells can be placed in the case of 1D placement, the problem of 2D placement is that they must be placed considering various polygon shapes.

[0132] The 2D cell placement optimization device (100) can minimize idle space when placing cells to increase the utilization of the circuit.

[0133] The two-dimensional cell placement optimization device (100) is Perform placement while adhering to the placement limits of the dummy area.

[0134] The two-dimensional cell placement optimization device (100) is It reflects the power constraint. That is, the 2D cell placement optimization device (100) places cells connected vertically in the same power state in the part where the power is connected.

[0135] The two-dimensional cell placement optimization device (100) also generates a two-dimensional arrangement by reflecting other constraints required during circuit design. For example, the two-dimensional cell placement optimization device (100) arranges cells to satisfy a grouping function that groups specific cells together.

[0136] The 2D cell placement optimization device (100) reflects Flip information. Since the cells can be flipped up, down, left, and right and the positions of the Port and Power change depending on the flipped shape, the 2D cell placement optimization device (100) can generate a placement such that the cells have an appropriate Flip shape.

[0137] FIG. 6 is a drawing for explaining a computing device according to an embodiment of the present invention.

[0138] Referring to FIG. 6, a two-dimensional cell placement optimization device and method according to embodiments can be implemented using a computing device (900).

[0139] The computing device (900) may include at least one of a processor (910), memory (930), user interface input device (940), user interface output device (950), and storage device (560) that communicate via a bus (920). The computing device (900) may also include a network interface (970) that is electrically connected to a network (90). The network interface (970) may transmit or receive signals to or from other entities via the network (90).

[0140] The processor (910) can be implemented in various types such as an MCU (Micro Controller Unit), AP (Application Processor), CPU (Central Processing Unit), GPU (Graphic Processing Unit), NPU (Neural Processing Unit), etc., and may be any semiconductor device that executes instructions stored in memory (930) or storage device (960). The processor (910) may be configured to implement the functions and methods described above in relation to FIGS. 1 to 5.

[0141] The memory (930) and storage device (960) may include various forms of volatile or non-volatile storage media. For example, the memory may include ROM (read-only memory) (931) and RAM (random access memory) (932). In this embodiment, the memory (930) may be located inside or outside the processor (910), and the memory (930) may be connected to the processor (910) through various known means.

[0142] In some embodiments, at least some configurations or functions of the two-dimensional cell placement optimization device and method according to the embodiments may be implemented as a program or software executed on a computing device (900), and the program or software may be stored on a computer-readable medium.

[0143] In some embodiments, at least some configurations or functions of the two-dimensional cell placement optimization device and method according to the embodiments may be implemented using hardware or circuits of the computing device (900), or may be implemented using separate hardware or circuits that can be electrically connected to the computing device (900).

[0144] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art to which the present invention belongs, utilizing the basic concept of the present invention as defined in the following claims, also fall within the scope of the present invention. Explanation of the symbols

[0145] 100: 2D Cell Placement Optimizer 110: Sequence generation module 120: 2D layout creation module 130: Batch Evaluation Module 140: Final Placement Decision Module

Claims

Claim 1 A two-dimensional cell placement optimization device that optimizes a two-dimensional cell placement of a semiconductor circuit by executing program code loaded into one or more memory devices through one or more processors, wherein the program code is executed to generate a plurality of sequences for a plurality of cells, generates a plurality of two-dimensional placements for the plurality of cells based on the generated sequences, performs a placement evaluation for each of the plurality of two-dimensional placements, and determines a final two-dimensional placement among the plurality of two-dimensional placements based on the result of the placement evaluation. Claim 2 A two-dimensional cell placement optimization device according to claim 1, wherein generating a plurality of sequences for the plurality of cells includes generating the plurality of sequences randomly without duplication. Claim 3 A two-dimensional cell placement optimization device according to claim 1, wherein generating a plurality of sequences for the plurality of cells includes sequentially generating the plurality of sequences using a local search algorithm based on the result of the placement evaluation. Claim 4 A two-dimensional cell placement optimization device according to claim 3, wherein generating a plurality of sequences for the plurality of cells further includes generating the plurality of sequences using a perturbation algorithm when a local obtima according to the local search algorithm occurs. Claim 5 A two-dimensional cell placement optimization device according to claim 1, wherein generating a plurality of two-dimensional placements for the plurality of cells based on the sequences comprises generating the plurality of two-dimensional placements that satisfy the feasibility of the semiconductor circuit based on cell data for the plurality of cells. Claim 6 A two-dimensional cell placement optimization device according to claim 5, wherein the step of generating a plurality of two-dimensional placements for the plurality of cells based on the sequences further comprises generating the plurality of two-dimensional placements that satisfy all predetermined constraints based on the cell data in relation to the placement of the plurality of cells. Claim 7 A two-dimensional cell placement optimization device according to claim 6, wherein the cell data comprises at least one of the two-dimensional shape of the cell, the location of a port within the cell, connection information of the cells, power information of the cell, and flip information of the cell. Claim 8 A two-dimensional cell placement optimization device according to claim 7, wherein generating a plurality of two-dimensional placements for the plurality of cells based on the sequences further comprises generating the plurality of two-dimensional placements that minimize idle space by considering the two-dimensional shape of the plurality of cells, provided that both the feasibility and the constraints are satisfied. Claim 9 A two-dimensional cell placement optimization device according to claim 1, wherein performing a placement evaluation for each of the plurality of two-dimensional placements includes measuring the wire length of the semiconductor circuit for the plurality of two-dimensional placements and performing the placement evaluation based on the measured wire length. Claim 10 A two-dimensional cell placement optimization device according to claim 9, wherein determining the final two-dimensional placement among the plurality of two-dimensional placements based on the result of the placement evaluation includes determining at least one placement among the plurality of two-dimensional placements that minimizes the wiring length as the final two-dimensional placement using a local search algorithm and a perturbation algorithm. Claim 11 A method for optimizing a two-dimensional cell placement of a semiconductor circuit, performed by a computing device including a processor and a memory, comprising: a step in which the processor generates a plurality of sequences for a plurality of cells; a step in which the processor generates a plurality of two-dimensional placements for the plurality of cells based on the generated sequences; a step in which the processor performs a placement evaluation for each of the plurality of two-dimensional placements; and a step in which the processor determines a final two-dimensional placement among the plurality of two-dimensional placements based on the result of the placement evaluation. Claim 12 A two-dimensional cell placement optimization method according to claim 11, wherein the step of generating a plurality of sequences for the plurality of cells comprises the step of the processor generating the plurality of sequences randomly without duplication. Claim 13 A two-dimensional cell placement optimization method according to claim 11, wherein the step of generating a plurality of sequences for the plurality of cells comprises the step of the processor sequentially generating the plurality of sequences using a local search algorithm based on the result of the placement evaluation. Claim 14 A two-dimensional cell placement optimization method according to claim 13, wherein the step of generating a plurality of sequences for the plurality of cells further includes the step of the processor generating the plurality of sequences using a perturbation algorithm when a local obtima according to the local search algorithm occurs. Claim 15 A method for optimizing 2D cell placement according to claim 11, wherein the step of generating a plurality of 2D placements for the plurality of cells based on the above sequences comprises the step of the processor generating the plurality of 2D placements that satisfy the feasibility of the semiconductor circuit based on cell data for the plurality of cells. Claim 16 A method for optimizing 2D cell placement according to claim 15, wherein the step of generating a plurality of 2D placements for the plurality of cells based on the above sequences further comprises the step of the processor generating the plurality of 2D placements that satisfy all predetermined constraints based on the cell data in relation to the placement of the plurality of cells. Claim 17 A method for optimizing a two-dimensional cell layout according to claim 16, wherein the cell data comprises at least one of the two-dimensional shape of the cell, the location of a port within the cell, connection information of the cells, power information of the cell, and flip information of the cell. Claim 18 A method for optimizing 2D cell placement according to claim 17, wherein the step of generating a plurality of 2D placements for the plurality of cells based on the sequences further comprises the step of generating the plurality of 2D placements that minimize idle space by considering the 2D shape of the plurality of cells, if the processor satisfies both the feasibility and the constraints. Claim 19 A two-dimensional cell placement optimization method according to claim 11, wherein the step of performing a placement evaluation for each of the plurality of two-dimensional placements comprises the step of the processor measuring the wire length of the semiconductor circuit for the plurality of two-dimensional placements and performing the placement evaluation based on the measured wire length. Claim 20 A two-dimensional cell placement optimization method according to claim 19, wherein the step of determining a final two-dimensional placement among the plurality of two-dimensional placements based on the result of the placement evaluation comprises the step of the processor determining at least one placement among the plurality of two-dimensional placements that minimizes the wiring length as the final two-dimensional placement using a local search algorithm and a perturbation algorithm.

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