Vision sensor and image processing device including the same

Abstract

An image sensor and an image processing device including the same are disclosed. An image sensor according to an exemplary embodiment of the present disclosure includes a plurality of pixel groups, and at least one first pixel group among the plurality of pixel groups includes a first pixel for generating image data and a second pixel for generating event data, and the first pixel and the second pixel included in the same pixel group may include a pixel array that receives a light signal of the same color and a dynamic vision sensor (DVS) circuit that generates an event signal based on an electrical signal generated in the second pixel.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to a semiconductor device, and more specifically, to an image sensor and an image processing device including the same. Background Technology

[0002] Human-computer interaction (HCI) manifests and operates within user interfaces. Various user interfaces that recognize user input can provide natural interaction between humans and computers. Various sensors can be utilized to recognize user input.

[0003] An image sensor device is a device that generates electrical or digital signals based on light incident from an external source. Recently, event-based sensors that output event signals based on changes in the magnitude of externally incident light, such as dynamic vision sensors (DVS), are being developed. Event-based sensors output event signals using various components such as converters and amplifiers. The problem to be solved

[0004] The problem that the technical concept of the present disclosure aims to solve is to provide an image sensor comprising a first pixel, a CIS pixel, and a second pixel, a DVS pixel, wherein the first pixel and the second pixel are identical color pixels, and an image processing device including the same. means of solving the problem

[0005] An image sensor according to an exemplary embodiment of the present disclosure comprises a plurality of pixel groups, wherein at least one first pixel group among the plurality of pixel groups comprises a first pixel for generating image data and a second pixel for generating event data, and the first pixel and the second pixel included in the same pixel group may comprise a pixel array for receiving a light signal of the same color and a dynamic vision sensor (DVS) circuit for generating an event signal based on an electrical signal generated from the second pixel.

[0006] An image sensor according to an exemplary embodiment of the present disclosure comprises a plurality of pixel groups, and one or more of the plurality of pixel groups comprises a pixel array including a first pixel and a second pixel, a dynamic vision sensor (DVS) circuit that generates an event signal based on a first signal output from the second pixel, a pixel circuit that generates a pixel signal based on a second electrical signal output from the first pixel, a read-out circuit that generates image data based on the pixel signal, and an event detection circuit that receives the event signal and generates event data, wherein the first pixel group among the plurality of pixel groups comprises N first pixels and M second pixels, N and M are natural numbers, and the N first pixels and M second pixels can receive a first color light signal and convert it into an electrical signal.

[0007] An image processing device according to an exemplary embodiment of the present disclosure may include a plurality of pixel groups, and one or more of the plurality of pixel groups may include an image sensor comprising a pixel array including a first pixel and a second pixel, a signal processing circuit that processes a signal received from the pixel array and outputs data, and a processor that receives and processes the data and detects the movement of an object, wherein the first pixel and the second pixel included in the first pixel group among the one or more pixel groups receive a light signal of a first color, and the first color may be one of a red pixel, a green pixel, and a blue pixel. Effects of the invention

[0008] An image sensor according to an exemplary embodiment of the present disclosure may be a hybrid sensor comprising a first pixel, which is a CIS pixel, and a second pixel, which is a DVS pixel. Adjacent first pixels and second pixels included in the image sensor may be implemented as identical color pixels, and accordingly, interference between pixels that may occur when adjacent first pixels and second pixels are implemented as different color pixels may be eliminated and crosstalk may be reduced.

[0009] Therefore, the image sensor's image sensing and event sensing capabilities can be enhanced, and the image quality of the image generated by the image sensor can be improved.

[0010] An image sensor according to an exemplary embodiment of the present disclosure may include a first pixel which is a color pixel and a second pixel which is a color pixel identical to the first pixel. Since the second pixel includes a color pixel identical to the first pixel, crosstalk between pixels that occurs when the colors of adjacent first and second pixels are different during image sensor operation may be reduced.

[0011] According to an exemplary embodiment of the present disclosure, the image sensor may have first to fourth floating diffusion nodes and an event floating diffusion node separated. When the hybrid image sensor is in operation, the signal timing of the first to fourth floating diffusion nodes and the event floating diffusion node is separated, thereby suppressing interference phenomena and improving the performance of the image sensor.

[0012] The effects obtainable from the exemplary embodiments of the present disclosure are not limited to those mentioned above, and other unmentioned effects can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure belong from the following description. That is, unintended effects resulting from the implementation of the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure. Brief explanation of the drawing

[0013] FIG. 1 is a block diagram showing an image processing device according to an exemplary embodiment of the present disclosure. FIG. 2 is a block diagram showing an image sensor according to an exemplary embodiment of the present disclosure. FIG. 3 is a block diagram of pixel groups including a first pixel and a second pixel according to an exemplary embodiment of the present disclosure. FIG. 4 is a plan view of pixel groups including a first pixel and a second pixel according to an exemplary embodiment of the present disclosure. FIG. 5 is a circuit diagram of pixel groups including a first pixel and a second pixel according to an exemplary embodiment of the present disclosure. FIG. 6 is a cross-sectional view taken along A-A' of FIG. 5 according to an exemplary embodiment of the present disclosure. FIG. 7 is a block diagram of pixel groups including a first pixel and a second pixel according to an exemplary embodiment of the present disclosure. FIG. 8 is a block diagram of pixel groups including a first pixel and a second pixel according to an exemplary embodiment of the present disclosure. FIG. 9 is a block diagram of pixel groups including a first pixel and a second pixel according to an exemplary embodiment of the present disclosure. FIG. 10 is a block diagram of pixel groups including a first pixel and a second pixel according to an exemplary embodiment of the present disclosure. FIG. 11 is a plan view of pixel groups including a first pixel and a second pixel according to an exemplary embodiment of the present disclosure. FIG. 12 is a circuit diagram showing a DVS circuit according to an exemplary embodiment of the present disclosure. FIG. 13 shows a 3-stack structure of an image processing device according to an exemplary embodiment of the present disclosure. FIG. 14 is a block diagram of a pixel array including a first pixel and a second pixel according to an exemplary embodiment of the present disclosure. FIG. 15 is a block diagram showing an electronic device to which an image sensor according to an exemplary embodiment of the present disclosure is applied. Specific details for implementing the invention

[0014] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0015] FIG. 1 is a block diagram showing an image processing device (10) according to an exemplary embodiment of the present disclosure.

[0016] Referring to FIG. 1, the image processing device (10) may include an image sensor (100) and a processor (11). The image processing device (10) according to an exemplary embodiment of the present disclosure may be mounted on an electronic device having an image or light sensing function.

[0017] The image sensor (100) may include a first pixel (e.g., PX1 in FIG. 3) and a second pixel (e.g., PX2 in FIG. 3). In an embodiment of the present disclosure, the image sensor (100) may include a plurality of first pixels (PX1) and a plurality of second pixels (PX2). The number of the plurality of first pixels (PX) may be greater than the number of the plurality of second pixels (PX2). The image sensor (100) may include a first pixel (PX1) for generating image data (IDT) corresponding to an image of an object and a second pixel (PX2) for detecting movement of an object. In an embodiment of the present disclosure, the first pixel (PX1) may be a CIS (CMOS Image Sensor) pixel and the second pixel (PX2) may be a DVS (Dynamic Vision Sensor) pixel. For example, the first pixel (PX1) may be one of an RGB pixel (e.g., one of a red pixel, a green pixel, and a blue pixel), a BW pixel (black and white pixel), or an ultraviolet (UV) pixel, and the second pixel (PX2) may also be one of an RGB pixel, a BW pixel, or an ultraviolet (UV) pixel, just like the first pixel (PX1).

[0018] As described above, the image sensor (100) may be a hybrid sensor comprising both a first pixel (PX1) for generating image data (IDT) of an object and a second pixel (PX2) for detecting the movement of an object. The image sensor (100) may generate and output both image data (IDT) and vision sensor data (VDT). Additionally, the image sensor (100) may output only image data (IDT) or only vision sensor data (VDT) depending on the mode. For example, the image sensor (100) may generate image data (IDT) using signals generated from a plurality of first pixels (PX1) in an image-frame capture mode, and may generate vision sensor data (VDT) using signals generated from a plurality of second pixels (PX2) in an event-based vision sensor (EVS) mode.

[0019] For example, the first pixel (PX1) may be a color pixel. The first pixel (PX1) may be a red pixel that converts light in the red spectrum region into an electrical signal. The first pixel (PX1) may be a green pixel that converts light in the green spectrum region into an electrical signal. The first pixel (PX1) may be a blue pixel that converts light in the blue spectrum region into an electrical signal. The first pixel (PX1) may be a cyan pixel that converts light in the blue to green spectrum region into an electrical signal. The first pixel (PX1) may be a yellow pixel that converts light in the green to red spectrum region into an electrical signal. The first pixel (PX1) may be a magenta pixel that converts light in the blue to red spectrum region into an electrical signal.

[0020] In an embodiment of the present disclosure, the second pixel (PX2) may be a color pixel identical to the first pixel (PX1). For example, the first pixel (PX1) and the second pixel (PX2) included in the same pixel group may be identical color pixels. The second pixel (PX2) may be a red pixel that converts light in the red spectrum region into an electrical signal. The second pixel (PX2) may be a green pixel that converts light in the green spectrum region into an electrical signal. The second pixel (PX2) may be a blue pixel that converts light in the blue spectrum region into an electrical signal. The second pixel (PX2) may be a cyan pixel that converts light in the blue to green spectrum region into an electrical signal. The second pixel (PX2) may be a yellow pixel that converts light in the green to red spectrum region into an electrical signal. The second pixel (PX2) may be a magenta pixel that converts light in the blue to red spectrum region into an electrical signal.

[0021] According to a comparative embodiment, the color of the second pixel (PX) in the image sensor may be different from the color of the first pixel (PX1). For example, the image sensor may include a first pixel (PX1) formed by at least one of a red pixel, a green pixel, and a blue pixel, and a second pixel (PX2) which is a white pixel. Since the second pixel (PX2) is a white color pixel different from the color of the first pixel (PX1), crosstalk may occur due to interference between the adjacent first pixel (PX1) and the second pixel (PX2).

[0022] However, in an embodiment of the present disclosure, the image sensor (100) may include a first pixel (PX1) which is a color pixel and a second pixel (PX2) which is the same color pixel as the first pixel (PX1). Since the second pixel (PX2) includes the same color pixel as the first pixel (PX1), the image sensor (100) eliminates interference phenomena, thereby reducing crosstalk.

[0023] The image sensor (100) can convert an optical signal of an object into an electrical signal and generate image data (IDT) based on the electrical signals and transmit it to a processor (11). Each of the first pixel (PX1) and the second pixel (PX2) can generate an electrical signal (e.g., photocharge) based on the amount of incident light (e.g., light signal). For example, each of the first pixel (PX1) and the second pixel (PX2) can convert the incident light into a photocharge and accumulate the photocharge. The image sensor (100) can generate image data (IDT) based on electrical signals (e.g., first electrical signals) generated from a plurality of first pixels (PX1). The image sensor (100) can detect a change in the intensity of incident light based on electrical signals (e.g., second electrical signals) generated from a plurality of second pixels (PX2) and output an event signal. The change in light intensity may be caused by the movement of an object captured by the image sensor (100), or by the movement of the image sensor (100) or the image processing device (10) itself. The image sensor (100) may generate event signals periodically or non-periodically. Vision sensor data (VDT) containing event signals can be transmitted to the processor (11) periodically or non-periodically. Vision sensor data (VDT) can be generated using only event signals generated in a single frame, or it can be generated by grouping event signals generated in multiple frames.

[0024] The image sensor (100) can capture an object based on received control signals and generate image data (IDT). The image data (IDT) may include still images and video. The image sensor (100) may perform signal processing such as image quality compensation, binning, and downsizing on the image data (IDT) and vision sensor data (VDT), and image quality compensation may include signal processing such as black level compensation, lens shading compensation, crosstalk compensation, and bad pixel correction.

[0025] The processor (11) can process image data (IDT) and vision sensor data (VDT) received from the image sensor (100). The processor (11) can detect the movement of an object (or the movement of an object on an image recognized by the image processing device (10)) based on event signals within the vision sensor data (VDT). The processor (11) may be an application processor or an image signal processor.

[0026] For example, the processor (11) may include an ASIC (application specific integrated circuit), an FPGA (field-programmable gate array), a dedicated microprocessor, a microprocessor, a general purpose processor, etc. In an embodiment, the processor (11) may be an application processor or an image signal processor.

[0027] Meanwhile, the image sensor (100) and the processor (11) may each be implemented as an integrated circuit (IC) or implemented as a semiconductor substrate to form a single chip. For example, the image sensor (100) and the processor (11) may be implemented as separate semiconductor chips, or the image sensor (100) and the processor (11) implemented as separate semiconductor chips may be placed within a single package (PKG). As another example, the image sensor (100) and the processor (11) implemented as separate semiconductor substrates may be implemented as a single chip via through-silicon vias (TXV) or copper-to-copper connections.

[0028] If the image sensor (100) contains only the second pixel (PX2) without the first pixel (PX1), the image sensor (100) cannot generate an event signal when there is no movement of the object, and therefore cannot provide sensor data based on the event signal.

[0029] However, since the image sensor (100) according to the embodiment of the present disclosure includes a first pixel (PX1) (e.g., a CIS pixel) and a second pixel (PX2) (i.e., a DVS (Dynamic Vision Sensor) pixel), it can provide image data (IDT) based on an electrical signal corresponding to the amount of light incident on the first pixel (PX1) to the processor (11) even when there is no movement of the object. Accordingly, data can be provided regardless of the movement of the object. In addition, the image sensor (100) can detect a change in the amount of light incident on the second pixel (PX2) and provide vision sensor data (VDT) based on an electrical signal corresponding to the detected change to the processor (11).

[0030] The image processing device (10) can control an external device (500) and collect data. The image processing device (10) can match data collected from the device (500). The device (500) may include an accelerometer, an inertial measurement unit (IMU), a gyro sensor, an infrared (IR) LED, and a flashlight.

[0031] FIG. 2 is a block diagram showing an image sensor (100) according to an exemplary embodiment of the present disclosure.

[0032] Referring to FIGS. 1 and 2, the image sensor (100) may include a pixel array (110), a row driver (120), a control logic circuit (130), and a signal processing circuit (140). The signal processing circuit (140) may include a read-out circuit (150) and an event detection circuit (160).

[0033] A pixel array (110) may include a plurality of pixel groups (PG) arranged in rows and columns. Each of the plurality of pixel groups (PG) may include a plurality of pixels arranged in rows and columns, and each of the plurality of pixels may include a photoelectric conversion element and a transfer transistor. A pixel group (PG) may include N first pixels (PX1) and M second pixels (PX2). Here, M and N are natural numbers, and N may be greater than M.

[0034] The pixel array (110) may further include a pixel circuit (e.g., PC of FIG. 5) that generates a pixel signal (or pixel voltage, or image signal) based on an electrical signal (e.g., photocharge) generated from first pixels (PX1) (e.g., N first pixels (PX1)) each included in a pixel group (PG), and a DVS circuit (e.g., 220 of FIG. 12) that generates an event signal (e.g., on-event signal and / or off-event signal) by detecting a change in the amount of incident light based on an electrical signal generated from a second pixel (PX2). The pixel array (110) may include a plurality of pixel circuits (PC) and a plurality of DVS circuits (220).

[0035] The pixel array (110) may further include a plurality of row lines extending in the row direction (e.g., X-axis direction) and a plurality of column lines extending in the column direction (e.g., Y-axis direction). In an embodiment, the plurality of column lines may include a plurality of first column lines (e.g., CL1 in FIG. 5) connected to a plurality of pixel circuits (PC) and a plurality of second column lines (e.g., CL2 in FIG. 12) connected to a plurality of DVS circuits (220).

[0036] In an embodiment, a plurality of pixel circuits and / or a plurality of DVS circuits may be formed separately from a plurality of pixel groups (PG). For example, a pixel array (110) may include a first pixel array and a second pixel array, the first pixel array may include a plurality of pixel groups (PG), and the second pixel array may include a plurality of pixel circuits and / or a plurality of DVS circuits. The first pixel array and the second pixel array may be formed on different semiconductor layers.

[0037] The pixel array (110) may further include a plurality of row lines extending in the row direction (e.g., X-axis direction) and a plurality of column lines extending in the column direction (e.g., Y-axis direction). In an embodiment, the plurality of column lines may include a plurality of first column lines (e.g., CL1 in FIG. 5) connected to a plurality of pixel circuits (PC) and a plurality of second column lines (e.g., CL2 in FIG. 12) connected to a plurality of DVS circuits (220).

[0038] The row driver (120) can activate the first pixels (PX1) in row units under the control of the control logic circuit (130). The row driver (120) can provide control signals (e.g., transmission control signal, reset signal, selection signal, etc.) to the first pixels (PX1), the second pixels (PX2), and the pixel circuit (PC) through the row lines.

[0039] The control logic circuit (130) can control the overall operation of the image sensor (100) based on a control signal provided from the processor (11). The control logic circuit (130) can control each of the row driver (120) and the signal processing circuit (140).

[0040] The signal processing circuit (140) can generate image data (IDT) and vision sensor data (VDT) based on a first electrical signal output from the first pixels (PX1) of the pixel array (110) and a second electrical signal output from the second pixels (PX2). The vision sensor data (VDT) may include event data generated based on the second pixel signal.

[0041] The signal processing circuit (140) may include a read-out circuit (150) and an event detection circuit (160). The read-out circuit (150) may receive pixel signals from a pixel array (110) and generate image data (IDT) based on the received pixel signals. The read-out circuit (150) may receive pixel signals from the pixel array (110) through a plurality of first column lines (CL1). The read-out circuit (150) may generate image data (IDT) by converting the pixel signals from analog to digital.

[0042] In one embodiment, the read-out circuit (150) may include a ramp signal generator, a plurality of ADC circuits (analog-to-digital converter circuits), and an output buffer (output buffer; not shown), and each of the plurality of ADC circuits may include a comparator and a counter.

[0043] The event detection circuit (160) can receive event signals from the pixel array (110) and process the event signals to generate vision sensor data (VDT). The event detection circuit (160) can receive event signals from the pixel array (120) through a plurality of second column lines (CL2). The event detection circuit (160) may include a column AER (address event representation) circuit (not shown), a row AER circuit (not shown), and an output buffer (not shown).

[0044] The image sensor (100) can detect an event in which the intensity of light changes, determine the type of the event (i.e., whether the intensity of light increases or decreases), and output a value corresponding to the event. For example, the event may mainly occur on the outline of a moving object.

[0045] A DVS circuit (220) connected to at least one second pixel (PX2) that detects an event among multiple pixels can generate a signal (e.g., a column request) indicating that an event has occurred in which the light intensity increases or decreases based on an electrical signal provided from at least one second pixel (PX2), and can transmit the column request to a column AER circuit.

[0046] The column AER circuit can transmit a response signal to the DVS circuit (220) in response to a received column request. The DVS circuit (220) that receives the response signal can transmit polarity information of the event that occurred to the row AER circuit. The column AER circuit can generate a column address of at least one second pixel (PX2) that detected the event based on the column request received from the DVS circuit (220) that detected the event.

[0047] The low AER circuit can receive polarity information from a DVS circuit (220) connected to at least one second pixel (PX2) that detected an event. Based on the polarity information, the low AER circuit can generate a timestamp containing information regarding the time at which the event occurred. For example, the timestamp may be generated by a time stamper (not shown) provided in the low AER circuit. For example, the time stamper may be implemented using a timetick generated in units of several to tens of microseconds. Additionally, the low AER circuit can generate a low address of at least one second pixel (PX2) that detected an event.

[0048] The output buffer can generate packets based on timestamps, column addresses, row addresses, and polarity information. The output buffer can add a header indicating the start of the packet at the front of the packet and a tail indicating the end of the packet at the back. For example, at least some of the aforementioned column AER, row AER, and output buffer may be referred to as DVS peripheral circuits.

[0049] In an embodiment of the present disclosure, the image sensor (100) may include a first pixel (PX1) which is a color pixel and a second pixel (PX2) which is a color pixel identical to the first pixel (PX1). Since the second pixel (PX2) is implemented as a color pixel identical to the first pixel (PX1), interference between pixels that occurs when the colors of adjacent first pixels (PX1) and second pixels (PX2) are different during the operation of the image sensor (100) can be suppressed and crosstalk can be reduced.

[0050] FIG. 3 is a block diagram of a pixel group (PG1 to PG4) including a first pixel (PX1) and a second pixel (PX2) according to an exemplary embodiment of the present disclosure.

[0051] Referring to FIGS. 2 and 3, the pixel array (110) may include a plurality of pixel groups (PG1 to PG4) arranged in rows and columns. For example, the pixel array (110) may include 16 pixels arranged in a 4x4 (i.e., 4 rows and 4 columns). Herein, the pixels may include a photoelectric conversion element (e.g., a photodiode) and a transfer transistor. Hereinafter, a photodiode will be described as an example of a photoelectric conversion element in the present disclosure.

[0052] The pixel may further include a color filter and / or a micro lens. The pixel array (110) may include four first to fourth pixel groups (PG1 to PG4) arranged in a 2x2 (i.e., 2 rows and 2 columns).

[0053] At least one pixel group among the first to fourth pixel groups (PG4) may include a plurality of first pixels (PX1) and second pixels (PX2). For example, each of the first pixel group (PG1), the second pixel group (PG2), and the fourth pixel group (PG4) may include a plurality of first pixels (PX1) and at least one second pixel (PX2). For example, in each of the first pixel group (PG1), the second pixel group (PG2), and the fourth pixel group (PG4), the number of first pixels (PX1) may be greater than the number of second pixels (PX2). The third pixel group (PG3) may include a plurality of first pixels (PX1) excluding the second pixels (PX2).

[0054] In one embodiment, the first pixel group (PG1), the second pixel group (PG2), and the fourth pixel group (PG4) may each include N first pixels (PX1) and M second pixels (PX2). For example, N may be '3' and M may be '1'. The third pixel group (PG3) may include 4 first pixels (PX1).

[0055] The positions of the second pixels (PX2) included in the first pixel group (PG1), pixel group (PG2), and fourth pixel group (PG4), excluding the third pixel group (PG3), may differ within each pixel group. The second pixels (PX2) included in the second pixel group (PG2) and the third pixel group (PG3) may be placed at different positions within the first pixel group (PG1), the second pixel group (PG2), and the third pixel group (PG3).

[0056] For example, as illustrated in FIG. 3, a second pixel (PX2) provided in a first pixel group (PG1) may be placed at the lower right corner within the area where the first pixel group (PG1) is formed, a second pixel (PX2) provided in a second pixel group (PG2) may be placed at the lower left corner within the area where the second pixel group (PG2) is formed, and a second pixel (PX2) provided in a fourth pixel group (PG4) may be placed at the upper left corner within the area where the fourth pixel group (PG4) is formed. For example, a second pixel (PX2) may be placed in the second row and second column of the first pixel group (PG1), a second pixel (PX2) may be placed in the second row and third column of the second pixel group (PG2), and a second pixel (PX2) may be placed in the third row and third column of the fourth pixel group (PG4). Each of the second pixels (PX2) may be placed at the edge portion where the first to fourth pixel groups (PG4) meet. Each of the second pixels (PX2) may be placed in the middle portion within the pixel block containing the first to fourth pixel groups (PG4). For example, the second pixels (PX2) may be placed adjacent to each other.

[0057] The image sensor (100) may be implemented as a semiconductor chip or semiconductor module comprising a plurality of vertically stacked semiconductor layers, wherein the photodiodes and transmission transistors included in the first pixel group (PG1) may be formed in the first layer (e.g., L1 in FIG. 13), the photodiodes and transmission transistors included in the second pixel group (PG2) may be formed in the first layer (L1), the photodiodes and transmission transistors included in the third pixel group (PG3) may be formed in the first layer (L1), and the photodiodes and transmission transistors included in the fourth pixel group (PG4) may be formed in the first layer (L1). The reset transistors, driving transistors, and select transistors provided in the pixel circuits (e.g., PC1, PC2, PC3, PC4 of FIG. 5) electrically connected to each of the first to fourth pixel groups (PG4) may be formed on the first layer (L1), but the embodiments of the present disclosure are not limited thereto, and the pixel circuits may be formed on the second layer (L2). This will be described in detail later with reference to FIG. 13.

[0058] Each first pixel (PX1) included in the first pixel group (PG1), the second pixel group (PG2), and the third pixel group (PG3) may share a floating diffusion node. The second pixel (PX2) included in the first pixel group (PG1), the second pixel group (PG2), and the third pixel group (PG3) may share an event floating diffusion node and may share a DVS circuit (e.g., 220 in FIG. 12). For example, the second pixel (PX2) included in the first pixel group (PG1), the second pixel group (PG2), and the third pixel group (PG3) may share a current / voltage converter, an amplification circuit, and a comparison circuit. The DVS circuit (220) may be formed on the second layer (L2). This will be described in detail later through FIG. 4, FIG. 5, and FIG. 13.

[0059] The first to fourth pixel groups (PG4) may have the same or different types. The first to fourth pixel groups (PG1 to PG4) may have a Bayer pattern, such as an RGBG pattern. However, the scope of the present disclosure is not limited thereto.

[0060] In the embodiment, the first pixels (PX1) may include any one of a red pixel, a green pixel, a blue pixel, a cyan pixel, a yellow pixel, or a magenta pixel. The second pixels (PX2) may include any one of a red pixel, a green pixel, a blue pixel, a cyan pixel, a yellow pixel, or a magenta pixel.

[0061] In an embodiment of the present disclosure, a plurality of first pixels (PX1) and second pixels (PX2) included in the same pixel group may be implemented as the same color pixels. A plurality of first pixels (PX1) and second pixels (PX2) may convert an optical signal of the same color (e.g., an optical signal of the same wavelength band) into an electrical signal. For example, a first pixel group (PG1) may include first pixels (PX1) corresponding to three red pixels (R) and a second pixel (PX2) corresponding to one red pixel (R). For example, a second pixel group (PG2) may include first pixels (PX1) corresponding to three green pixels (G) and a second pixel (PX2) corresponding to one green pixel (G). For example, a third pixel group (PG3) may include first pixels (PX1) corresponding to four blue pixels (B). For example, the fourth pixel group (PG4) may include first pixels (PX1) corresponding to three green pixels (G) and second pixels (PX2) corresponding to one green pixel (G). However, embodiments of the present disclosure are not limited thereto.

[0062] FIG. 4 is a plan view of pixel groups (PG1 to PG4) including a first pixel (PX1) and a second pixel (PX2) according to an exemplary embodiment of the present disclosure. FIG. 5 is a circuit diagram of pixel groups (PG1 to PG4) including a first pixel (PX1) and a second pixel (PX2) according to an exemplary embodiment of the present disclosure.

[0063] Referring to FIGS. 4 and FIGS. 5 together, the first pixel group (PG1), the second pixel group (PX2), and the fourth pixel group (PX4) may each include three first pixels (PX1) and one second pixel (PX2). Each of the first pixels (PX1) and the second pixel (PX2) may include a photodiode and a transfer transistor connected thereto. Accordingly, the first pixel group (PG2) may include four first photodiodes (PD11~PD14) and four first transmission transistors (TX11~TX14) each connected thereto, the second pixel group (PG2) may include four second photodiodes (PD21~PD24) and four second transmission transistors (TX21~TX24) each connected thereto, the third pixel group (PG3) may include four third photodiodes (PD31~PD34) and four third transmission transistors (TX31~TX34) each connected thereto, and the fourth pixel group (PG4) may include four fourth photodiodes (PD41~PD44) and four fourth transmission transistors (TX41~TX44) each connected thereto.

[0064] Microlenses may be stacked on top of each of the first to fourth pixel groups (PG1, PG2, PG3, PG4). For example, a microlens may be placed on one first photodiode (PD11), and the first photodiode (PD11) may receive an optical signal through the microlens. Microlenses may be placed on each pixel. In addition, not only microlenses but also nanoprisms, metalenses, etc., may be placed on each pixel.

[0065] A color filter may be placed between the photodiodes (PD11~PD14, PD21~PD24, PD31~PD34, PD41~PD44) and the microlens, and the color filter provided in each of the first to fourth pixel groups (PG1~PG4) may transmit light signals of the same and / or different colors. This will be described in detail later with reference to FIG. 6.

[0066] Referring to FIG. 4, the first pixels (PX1) included in the first pixel group (PG1) may share a first floating diffusion node (FD1). The first pixels (PX1) included in the second pixel group (PG2) may share a second floating diffusion node (FD2). The first pixels (PX1) included in the third pixel group (PG3) may share a third floating diffusion node (FD3). The first pixels (PX1) included in the fourth pixel group (PG4) may share a fourth floating diffusion node (FD4). Photovoltaic charges generated at each of the photodiodes (PD11~PD13, PD21~PD23, PD31~PD34, PD41~PD43) provided in the first pixels (PX1) may be transmitted and accumulated in the shared floating diffusion nodes (FD1, FD2, FD3, FD4). For example, photocharges generated from each of the first to third photodiodes (PD11 to PD13) of the first pixel group (PG1) may be transmitted to the first floating diffusion node (FD1), photocharges generated from each of the first to third photodiodes (PD21 to PD23) of the second pixel group (PG2) may be transmitted to the second floating diffusion node (FD2), photocharges generated from each of the first to fourth photodiodes (PD31 to PD34) of the third pixel group (PG3) may be transmitted to the third floating diffusion node (FD3), and photocharges generated from each of the first to third photodiodes (PD41 to PD43) of the fourth pixel group (PG4) may be transmitted to the fourth floating diffusion node (FD4).

[0067] The concept of sharing among each pixel group (PG1~PG4) may include not only the meaning that multiple photodiodes (PD11~PD13, PD21~PD23, PD31~PD34, PD41~PD43) share a single floating diffusion node (FD1~FD4), but also the meaning that transistors other than the transfer transistors (TX11~TX13, TX21~TX23, TX31~TX34, TX41~TX43), such as the reset transistor, driving transistor, and select transistor included in the pixel circuit (e.g., PC of FIG. 5), are shared. The photovoltaic charge generated in each of the photodiodes (PD11~PD13, PD21~PD23, PD31~PD34, PD41~PD43) provided in the first pixels (PX1) is transmitted and accumulated in the shared floating diffusion nodes (FD1, FD2, FD3, FD4), and the pixel circuit (PC) can output a pixel signal corresponding to the photovoltaic charge accumulated in each of the shared floating diffusion nodes (FD1, FD2, FD3, FD4) to the read-out circuit (150 in FIG. 2).

[0068] The second pixel (PX2) included in the first pixel group (PG1), the second pixel (PX2) included in the second pixel group (PG2), and the second pixel (PX2) included in the fourth pixel group (PG4) can share an event floating diffusion node (EFD).

[0069] The concept of sharing for each pixel group may include not only the meaning that photodiodes (PD14, PD24, PD44) share a single event floating diffusion node, but also the meaning that they share a DVS circuit (220 in FIG. 12). Photocharges generated at each photodiode are transmitted and accumulated in the shared event floating diffusion node (EFD), and the DVS circuit (220) can generate an event signal based on the photocharges accumulated in the floating diffusion node (EFD).

[0070] In each pixel group, a plurality of first pixels (PX1) or a plurality of first pixels (PX1) and second pixels (PX2) may be arranged in rows and columns. A floating diffusion node may be placed in the center of each pixel group, and an event floating diffusion node (EFD) may be placed at the corners of each pixel group, and the corners where the event floating diffusion nodes (EFD) are placed may be adjacent to each other.

[0071] For example, a substrate on which a plurality of photodiodes (PD11~PD14, PD21~PD24, PD31~PD34, PD41~PD44) are formed includes a plurality of regions, and a plurality of photodiodes provided in a corresponding pixel group may be disposed in each of the plurality of regions. A floating diffusion node may be disposed (or formed) in the center of each region. Here, a region refers to a region on a two-dimensional plane extending in the X-axis and Y-axis directions.

[0072] For example, a first floating diffusion node (FD1) may be positioned in the middle of a first region where first photodiodes (PD11~PD14) are positioned, a second floating diffusion node (FD2) may be positioned in the middle of a second region where second photodiodes (PD21~PD24) are positioned, a third floating diffusion node (FD3) may be positioned in the middle of a third region where third photodiodes (PD31~PD34) are positioned, and a fourth floating diffusion node (FD4) may be positioned in the middle of a fourth region where fourth photodiodes (PD41~PD44) are positioned.

[0073] In an embodiment, each of the first, second, third, and fourth regions may include a plurality of pixel regions (e.g., first to fourth pixel regions) in which a plurality of photodiodes are disposed, and the plurality of pixel regions may include four corner regions (e.g., upper-left corner region, upper-right corner region, lower-left corner region, and lower-right corner region). Floating diffusion nodes may be disposed in different corner regions among some of the plurality of pixel regions. The different corner regions in which floating diffusion nodes are formed may be adjacent to each other.

[0074] For example, the first region in which the first photodiodes (PD11~PD14) provided in the first pixel group (PG1) are arranged may include a first pixel region in which the first photodiode PD11 is arranged, a second pixel region in which the first photodiode PD12 is arranged, a third pixel region in which the first photodiode PD13 is arranged, and a fourth pixel region in which the first photodiode PD14 is arranged, and the first floating diffusion node (FD1) may include a lower-left corner region of the first pixel region, a lower-right corner region of the second pixel region, and an upper-right corner region of the third pixel region. The corner regions in which the first floating diffusion node (FD1) is formed may represent different positions within each pixel region and may also be adjacent to each other.

[0075] An Event Floating Diffusion Node (EFD) may be placed in the corner area of ​​at least one pixel area, excluding some pixel areas where the Floating Diffusion Node is placed. The corner area where the Event Floating Diffusion Node (EFD) is formed may not be adjacent to some pixel areas where the Floating Diffusion Node is formed.

[0076] For example, an event floating diffusion node (EFD) may be placed in the lower right corner area of ​​the fourth pixel area of ​​the first area. The lower right corner area of ​​the fourth pixel area is not adjacent to the first pixel area, the second pixel area, and the third pixel area, nor is it adjacent to the corner areas where the first floating diffusion node (FD1) is formed.

[0077] In this way, the corner region where the event floating diffusion node (EFD) is formed is not adjacent to the corner regions where the floating diffusion node is formed, and the event floating diffusion node (EFD) can be electrically isolated from the floating diffusion nodes (FD1, FD2, FD3, FD4). In other words, the event floating diffusion node (EFD) may not be electrically connected to the floating diffusion node.

[0078] As illustrated in FIG. 4, the corner regions where the Event Floating Diffusion Node (EFD) is placed in the first, second, and fourth regions may be adjacent to each other. However, embodiments of the present disclosure are not limited thereto, and in the embodiments, the corner regions where the Event Floating Diffusion Node (EFD) is placed may not be adjacent to each other.

[0079] Referring to FIG. 5, the pixel array (110) may include a plurality of pixel groups (e.g., a first pixel group (PG1), a second pixel group (PG2), a third pixel group (PG3), and a fourth pixel group (PG4)) and pixel circuits (PCs) electrically connected to each of the plurality of pixel groups, such as a first pixel circuit (PC1), a second pixel circuit (PC2), a third pixel circuit (PC3), and a fourth pixel circuit (PC4).

[0080] At least one pixel group among a plurality of pixel groups (e.g., a first pixel group (PG1), a second pixel group (PG2), and a fourth pixel group (PG4)) may include a plurality of first pixels (PX1) and second pixels (PX2). Another pixel group excluding at least one pixel group among the plurality of pixel groups (e.g., a third pixel group (PG3)) may include a plurality of first pixels (PX1) excluding the second pixels (PX2). The pixel array (110) may further include a DVS circuit (220 in FIG. 12) electrically connected to the second pixels (PX) provided in the first pixel group (PG1), the second pixel group (PG2), and the fourth pixel group (PG4).

[0081] A pixel circuit (PC) may be electrically connected (or shared) to first pixels (PX1) included in a corresponding pixel group. The pixel circuit (PC) may include a reset transistor (RX), a driving transistor (DX) (or referred to as a source follower), and a select transistor (SX). Control signals provided to each pixel and to a plurality of pixel circuits (PC) may be provided from a row driver (120 in FIG. 2).

[0082] The structure of each pixel (e.g., first pixel (PX1) and second pixel (PX2)) is identical, and each pixel may include a photodiode and a transfer transistor. A first power supply voltage (VSS) (e.g., ground voltage) is applied to a first terminal of a photodiode (e.g., first photodiode PD11), and a second terminal may be connected to a first terminal of a transfer transistor (e.g., transfer transistor TX11). The second terminal of the transfer transistor (e.g., transfer transistor TX11) may be connected to a floating diffusion node (e.g., first floating diffusion node FD1). The transfer transistor may be turned on and turned off in response to a transfer control signal applied to its gate terminal, and when turned on, it may transmit an electrical signal generated in the photodiode (e.g., photocharge accumulated in the photodiode) to the floating diffusion node.

[0083] The pixel circuit (PC) may be electrically connected (or shared) to first pixels (PX1) included in a corresponding pixel group. The pixel circuit (PC) may include a reset transistor (RX), a driving transistor (DX) (or referred to as a source follower), and a select transistor (SX).

[0084] A second power supply voltage (VDD) is applied to the first terminal of the reset transistor (RX), and the second terminal can be connected to a floating diffusion node. The reset transistor (RX) can be turned on and turned off in response to a reset control signal applied to its gate terminal, and the floating diffusion node can be reset by turning on and applying the second power supply voltage (VDD) to the floating diffusion node.

[0085] A first power supply voltage (VDD) is applied to the first terminal of the driving transistor (DX), and the second terminal can be connected to the first terminal of the selection transistor (SX). The driving transistor (DX) can operate as a source follower and can generate a pixel signal (e.g., pixel voltage) corresponding to the potential of the floating diffusion node. The potential of the floating diffusion node can be varied according to the amount of photocharge accumulated in the floating diffusion node.

[0086] The select transistor (SX) can be turned on and turned off in response to a select signal received at the gate terminal, and when turned on, the pixel circuit (PC) can be connected to a corresponding column line (CL1) among a plurality of column lines (CL1). Pixel circuits (PCs), such as a first pixel circuit (PC1), a second pixel circuit (PC2), a third pixel circuit (PC3), and a fourth pixel circuit (PC4), can be connected to different first column lines (CL1). In an embodiment, some of the first pixel circuit (PC1), the second pixel circuit (PC2), the third pixel circuit (PC3), and the fourth pixel circuit (PC4) can be connected to the same first column line (CL1). For example, the first pixel circuit (PC1) and the third pixel circuit (PC3) can be connected to the same first column line (CL1), and the second pixel circuit (PC2) and the fourth pixel circuit (PC4) can be connected to the same first column line (CL1).

[0087] In the first pixel group (PG1), a plurality of transfer transistors (TX11~TX13) and first photodiodes (PD11~PD13) provided in the first pixels (PX1) may share a first floating diffusion node (FD1) and a first pixel circuit (PC1). In the second pixel group (PG2), a plurality of transfer transistors (TX21~TX23) and second photodiodes (PD21~PD23) provided in the first pixels (PX1) may share a second floating diffusion node (FD2) and a second pixel circuit (PC2). In the third pixel group (PG3), a plurality of transfer transistors (TX31~TX34) and third photodiodes (PD31~PD34) provided in the first pixels (PX1) may share a third floating diffusion node (FD3) and a third pixel circuit (PC3). In the fourth pixel group (PG4), a plurality of transfer transistors (TX41 to TX43) and fourth photodiodes (PD41 to PD43) provided in the first pixels (PX1) may share the fourth floating diffusion node (FD4) and the fourth pixel circuit (PC4). In the first pixel group (PG1), the second pixel group (PG2), and the fourth pixel group (PG4), photodiodes (PD14, PD24, PD44) connected to the transfer transistors (TX14, TX24, T44) provided in the second pixels (PX) may share the event floating diffusion node (EFD).

[0088] For example, the first transmission transistor (TX11) of the first pixel group (PG1) can be connected to the first photodiode (PD11) and the first floating diffusion node (FD1), the second transmission transistor (TX12) can be connected to the second photodiode (PD12) and the first floating diffusion node (FD1), the third transmission transistor (TX13) can be connected to the third photodiode (PD13) and the first floating diffusion node (FD1), and the fourth transmission transistor (TX14) can be connected to the fourth photodiode (PD14) and the event floating diffusion node (EFD).

[0089] For example, the first transmission transistor (TX21) of the second pixel group (PG2) may be connected to the first photodiode (PD21) and the second floating diffusion node (FD2), the second transmission transistor (TX22) may be connected to the second photodiode (PD22) and the second floating diffusion node (FD2), the third transmission transistor (TX23) may be connected to the third photodiode (PD23) and the second floating diffusion node (FD2), and the fourth transmission transistor (TX24) may be connected to the fourth photodiode (PD24) and the event floating diffusion node (EFD).

[0090] For example, the first transmission transistor (TX31) of the third pixel group (PG3) can be connected to the first photodiode (PD31) and the third floating diffusion node (FD3), the second transmission transistor (TX32) can be connected to the second photodiode (PD32) and the third floating diffusion node (FD3), the third transmission transistor (TX33) can be connected to the third photodiode (PD33) and the third floating diffusion node (FD3), and the fourth transmission transistor (TX34) can be connected to the fourth photodiode (PD34) and the third floating diffusion node (FD3).

[0091] For example, the first transmission transistor (TX41) of the fourth pixel group (PG4) can be connected to the first photodiode (PD41) and the fourth floating diffusion node (FD4), the second transmission transistor (TX42) can be connected to the second photodiode (PD42) and the fourth floating diffusion node (FD4), the third transmission transistor (TX43) can be connected to the third photodiode (PD43) and the fourth floating diffusion node (FD4), and the fourth transmission transistor (TX44) can be connected to the fourth photodiode (PD44) and the event floating diffusion node (EFD).

[0092] The event floating diffusion node (EFD) can be electrically connected to the DVS circuit (e.g., 220 in FIG. 12) via vias and metal wiring. The same transmission control signal (e.g., DVS transmission control signal (TG_DVS)) can be provided to the transmission transistors (TX14, TX24, T44). In an embodiment, the gate terminals of the transmission transistors (TX14, TX24, T44) can receive the DVS transmission control signal (TG_DVS) through the same low line.

[0094] In an image sensor (100) according to an exemplary embodiment of the present disclosure, an event floating diffusion node (EFD) is positioned so as not to be electrically connected to floating diffusion nodes, such as first to fourth floating diffusion nodes (FD1 to FD4), and can be electrically isolated. When the hybrid image sensor (100) is in operation, the signal timing of the first to fourth floating diffusion nodes (FD1 to FD4) and the event floating diffusion node (EFD) is separated, thereby suppressing interference phenomena and improving the performance of the image sensor.

[0095] FIG. 6 is a cross-sectional view of a pixel array according to an exemplary embodiment of the present disclosure.

[0096] A vertical cross-sectional view of the first pixel group (PG1) and the second pixel group (PG2) is schematically illustrated according to A-A' of FIG. 5.

[0097] A substrate (SUB) (e.g., a semiconductor substrate) on which a first pixel (PX1) and a second pixel (PX2) are formed may be provided. A first photodiode (PD13), a second photodiode (PD14), a third photodiode (PD23), and a fourth photodiode (PD24) may be disposed within the substrate (SUB). A plurality of photodiodes (PD13, PD14, PD23, PD24) may be formed in regions that are physically separated from one another by a device isolation layer (DTI). The device isolation layer (DTI) may be formed in various ways, such as FDTI (Front Deep Trench Isolation), BDTI (Backside Deep Trench Isolation), and HDTI (Hybrid Deep Trench Isolation). In a planar view, the device isolation layer (DTI) may be arranged side by side along a first direction (e.g., the X-axis direction). An event floating diffusion node (EFD) may also be formed on the substrate (SUB). An event floating diffusion node (EFD) may be formed in pixel regions PXA14 and PXA24, which are included in different pixel groups among pixel regions (PXA13, PXA14, PXA24, PXA23). FIG. 6 illustrates that an event floating diffusion node (EFD) is formed in pixel regions PXA14 and PXA24. However, it is not limited thereto, and pixel regions PXA14 and PXA24 may be completely separated by a device isolation layer (DTI), and an event floating diffusion node (EFD) may be formed in each of pixel regions PXA14 and PXA24, and the event floating diffusion nodes (EFD) may be electrically connected through vias and wiring formed in the wiring layer (WL).

[0098] A wiring layer (WL) may be disposed on a first surface (S1) of a substrate (SUB). Transistors, vias, and wirings may be formed in the wiring layer (WL). Transfer transistors corresponding to a plurality of photodiodes (PD13, PD14, PD23, PD24) may be formed in the wiring layer (WL). For example, as shown in FIG. 6, a fourth transfer transistor (TX14, TX24) may be formed in the wiring layer (WL) disposed on the first surface of the substrate (SUB).

[0099] An insulating layer (IL), a color filter (e.g., a first color filter (CF1), a second color filter (CF2)), and micro lenses (e.g., first to fourth micro lenses (ML1, ML2, ML3, ML4)) may be disposed on the second surface (S2) of the substrate (SUB).

[0100] A first pixel group (PG1) may include a first photodiode (PD13, PD14), a first color filter (CF1), a first microlens (ML1), and a second microlens (ML2). A second pixel group (PG2) may include a second photodiode (PD23, PD24), a second color filter (CF2), a third microlens (ML3), and a fourth microlens (ML4). Embodiments of the present disclosure are not limited thereto and may include nanoprisms, metalenses, etc., instead of microlenses.

[0101] An insulating layer (IL) may be disposed between a substrate (SUB) and color filters (e.g., a first color filter (CF1) and a second color filter (CF2)). For example, the insulating layer (IL) may have an anti-reflective film function. For example, the insulating layer (IL) may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxide film, and a hafnium oxide film.

[0102] The first color filter (CF1) can be placed between the first photodiode (PD13) and the first microlens (ML1), and between the second photodiode (PD14) and the second microlens (ML2). The second color filter (CF2) can be placed between the third photodiode (PD23) and the third microlens (ML3), and between the fourth photodiode (PD24) and the fourth microlens (ML4).

[0103] The first color filter (CF1) can transmit a light signal of the first color (e.g., a light signal corresponding to a first wavelength band corresponding to the first color) among the light signals received through a microlens (e.g., the first and second microlenses (ML1, ML2)). Accordingly, the first pixel (PX1) and the second pixel (PX2) of the first pixel group (PG1) can receive the light signal of the first color. The second color filter (CF2) can transmit a light signal of the second color (e.g., a light signal of a second wavelength band corresponding to the second color) among the light signals received through a microlens (e.g., the third and fourth microlenses (ML3, NL4). Accordingly, the first pixel (PX1) and the second pixel (PX2) of the first pixel group (PG1) can receive the light signal of the first color.

[0104] For example, the first color filter (CF1) may be a red color filter and the second color filter (CF2) may be a green color, but the embodiments of the present disclosure are not limited thereto.

[0105] In a hybrid image sensor (100) comprising a first pixel (PX1) which is a CIS pixel and a second pixel (PX2) which is a DVS pixel, according to an exemplary embodiment of the present disclosure, a plurality of floating diffusion nodes (e.g., first to fourth floating diffusion nodes (FD1 to FD4)) and an event floating diffusion node (EFD) are separated and are not electrically connected. When the hybrid image sensor is in operation, the timing of the first to fourth floating diffusion nodes (FD1 to FD4) and the event floating diffusion node (EFD) is separated and the signals are separated, thereby suppressing interference phenomena and improving the performance of the image sensor.

[0106] FIG. 7 is a block diagram of pixel groups (PG1 to PG4) including a first pixel (PX1) and a second pixel (PX2) according to an exemplary embodiment of the present disclosure. Content that overlaps with Figure 3 will be omitted and explained.

[0107] Referring to FIG. 7, among the first to fourth pixel groups (PG1 to PG4), two pixel groups may include a plurality of first pixels (PX1) and at least one second pixel (PX2), and the other two pixel groups may include a plurality of first pixels (PX1) excluding the second pixel (PX2). For example, each of the first pixel group (PG1) and the fourth pixel group (PG4) may include a plurality of first pixels (PX1) and at least one second pixel (PX2), and each of the second pixel group (PG2) and the third pixel group (PG3) may include a plurality of first pixels (PX1). The first pixel group (PG1) and the fourth pixel group (PG4) may be arranged in a first diagonal direction, and the second pixel group (PG2) and the third pixel group (PG3) may be arranged in a second diagonal direction different from the first diagonal direction. For example, in each of the first pixel group (PG1) and the fourth pixel group (PG4), the number of first pixels (PX1) may be greater than the number of second pixels (PX2).

[0108] In one embodiment, the first pixel group (PG1) and the fourth pixel group (PG4) may each include N first pixels (PX1) and M second pixels (PX2). For example, N may be '3' and M may be '1'. The second pixel group (PG2) and the third pixel group (PG3) may each include 4 first pixels (PX1).

[0109] In one embodiment, each of the second pixels (PX2) may be placed at an edge portion (or corner portion) where the first to fourth pixel groups (PG4) meet. Each of the second pixels (PX2) may be placed in the middle portion of the first to fourth pixel groups (PG4). The second pixels (PX2) may be adjacent to each other.

[0110] FIG. 8 is a block diagram of pixel groups (PG1 to PG4) including a first pixel (PX1) and a second pixel (PX2) according to an exemplary embodiment of the present disclosure. Content that overlaps with Figure 3 will be omitted and explained.

[0111] Referring to FIG. 8, among the first to fourth pixel groups (PG1 to PG4), two pixel groups may include a plurality of first pixels (PX1) and at least one second pixel (PX2), and the other two pixel groups may include a plurality of first pixels (PX1) excluding the second pixel (PX2). For example, each of the first pixel group (PG1) and the second pixel group (PG2) adjacent in the first direction (e.g., X-axis direction) may include a plurality of first pixels (PX1) and at least one second pixel (PX2), and each of the third pixel group (PG3) and the fourth pixel group (PG4) adjacent in the first direction may include a plurality of first pixels (PX1). For example, in each of the first pixel group (PG1) and the second pixel group (PG2), the number of first pixels (PX1) may be greater than the number of second pixels (PX2).

[0112] In one embodiment, the first pixel group (PG1) and the second pixel group (PG2) may each include N first pixels (PX1) and M second pixels (PX2). For example, N may be '3' and M may be '1'. The third pixel group (PG3) and the fourth pixel group (PG4) may each include 4 first pixels (PX1).

[0113] In one embodiment, each of the second pixels (PX2) may be placed at the edge portion where the first to fourth pixel groups (PG4) meet. Each of the second pixels (PX2) may be placed in the middle portion of the first to fourth pixel groups (PG4). The second pixels (PX2) may be adjacent to each other.

[0114] FIG. 9 is a block diagram of pixel groups (PG1 to PG4) including a first pixel (PX1) and a second pixel (PX2) according to an exemplary embodiment of the present disclosure. Content that overlaps with Figure 3 will be omitted and explained.

[0115] Referring to FIG. 9, each of the first to fourth pixel groups (PG1 to PG4) may include a plurality of first pixels (PX1) and at least one second pixel (PX2). For example, in each of the first to fourth pixel groups (PG4), the number of first pixels (PX1) may be greater than the number of second pixels (PX2).

[0116] In one embodiment, each of the first to fourth pixel groups (PG4) may include N first pixels (PX1) and M second pixels (PX2). For example, N may be '3' and M may be '1'.

[0117] In one embodiment, each of the second pixels (PX2) of the first to fourth pixel groups (PG1 to PG4) may be positioned at the edge portion where the first to fourth pixel groups (PG4) meet. Each of the second pixels (PX2) may be positioned at the center portion of the first to fourth pixel groups (PG4). The second pixels (PX2) may be adjacent to each other.

[0118] FIG. 10 is a block diagram of pixel groups (PG1 to PG4) including a first pixel (PX1) and a second pixel (PX2) according to an exemplary embodiment of the present disclosure.Content that overlaps with Figure 3 will be omitted and explained.

[0119] Referring to FIG. 10, at least one pixel group among the first to fourth pixel groups (PG1 to PG4) may include a plurality of first pixels (PX1) and at least one second pixel (PX2). For example, each of the first pixel group (PG1), the second pixel group (PG2), and the fourth pixel group (PG4) may include a plurality of first pixels (PX1) and at least one second pixel (PX2). The third pixel group (PG3) may include a plurality of first pixels (PX1) excluding the second pixel (PX2). For example, in each of the first pixel group (PG1), the second pixel group (PG2), and the fourth pixel group (PG4), the number of first pixels (PX1) may be greater than the number of second pixels (PX2).

[0120] In one embodiment, the first pixel group (PG1), the second pixel group (PG2), and the fourth pixel group (PG4) may each include N first pixels (PX1) and M second pixels (PX2). For example, N may be '3' and M may be '2'. The third pixel group (PG3) may include 4 first pixels (PX1).

[0121] The positions of the second pixels (PX2) included in the first pixel group (PG1), the second pixel group (PG2), and the fourth pixel group (PG4) may be the same within each pixel group. In other words, the second pixels (PX2) included in the second pixel group (PG2) and the fourth pixel group (PG4) may be placed at the same position within the first pixel group (PG1), the second pixel group (PG2), and the fourth pixel group (PG3). For example, the second pixels (PX2) may be placed at the lower-left corner within the area where the first pixel group (PG1), the second pixel group (PG2), and the third pixel group (PG3) are each formed. For example, the second pixels (PX2) may be placed so as not to be adjacent to each other.

[0122] FIG. 11 is a plan view of pixel groups (PG1 to PG4) including a first pixel (PX1) and a second pixel (PX2) according to an exemplary embodiment of the present disclosure. Content overlapping with FIG. 4 will be omitted from the description.

[0123] Referring to FIG. 10 and FIG. 11 together, the first pixel group (PG1), the second pixel group (PX2), and the fourth pixel group (PX4) may each include three first pixels (PX1) and one second pixel (PX2). Each of the first pixels (PX1) and the second pixel (PX2) may include a photodiode and a transfer transistor connected thereto.

[0124] Three first pixels (PX1) included in the first pixel group (PG1) share the first floating diffusion node (FD1), three first pixels (PX1) included in the second pixel group (PG2) share the second floating diffusion node (FD2), four first pixels (PX1) included in the third pixel group (PG3) share the third floating diffusion node (FD3), three first pixels (PX1) included in the fourth pixel group (PG4) share the fourth floating diffusion node (FD4), and the second pixel (PX2) included in the first pixel group (PG1), the second pixel (PX2) included in the second pixel group (PG2), and the second pixel (PX2) included in the fourth pixel group (PG4) may share the event floating diffusion node.

[0125] In each pixel group, a plurality of first pixels (PX1) or a plurality of first pixels (PX1) and second pixels (PX2) may be arranged in rows and columns. A floating diffusion node is placed in the center of each pixel group, and event floating diffusion nodes (e.g., EFD1, EFD2, EFD4) provided in each pixel group may be placed at the corners of each pixel group.

[0126] As described above with reference to FIG. 10, the second pixels (PX2) included in the second pixel group (PG2) and the fourth pixel group (PG4) can be placed at the same location within the first pixel group (PG1), the second pixel group (PG2), and the fourth pixel group (PG3). The second pixels (PX2) can be placed so as not to be adjacent to each other. Accordingly, the event floating diffusion nodes (EFD1, EFD2, EFD3) may not be adjacent to each other.

[0127] In an embodiment, each of the pixel regions where a photodiode provided in the second pixel (PX2) in each pixel group is placed (e.g., a third pixel region where the first photodiode (PD13) is placed, a fourth pixel region where the second photodiode (PD24) is placed, and a first pixel region where the fourth photodiode (PD41) is placed) may include four corner regions (e.g., an upper-left corner region, an upper-right corner region, a lower-left corner region, and a lower-right corner region), and the event floating diffusion nodes (EFD1, EFD2, EFD4) may be placed in the same corner region in each pixel region. For example, the event floating diffusion nodes (EFD1, EFD2, EFD4) may be placed in the lower-left corner region in each pixel region.

[0128] Event floating diffusion nodes (EFD1, EFD2, EFD4) can be electrically connected via vias and wiring (e.g., a first connecting wiring (W1) and a second connecting wiring (W2). Accordingly, the event floating diffusion nodes (EFD1, EFD2, EFD4) can operate as a single event floating node, and accordingly, a second pixel (PX2) included in a first pixel group (PG1), a second pixel (PX2) included in a second pixel group (PG2), and a second pixel (PX2) included in a fourth pixel group (PG4) can share an event floating diffusion node.

[0129] FIG. 12 is a circuit diagram showing a DVS circuit (220) according to an exemplary embodiment of the present disclosure.

[0130] Referring to FIG. 12, the image sensor (100) may include a DVS circuit (220) connected to second pixels (PX2). The DVS circuit (220) may include an I / V converter (210), an amplifier circuit (220), and a comparator circuit (230) for detecting changes in the amount of light incident on the photodiodes of the second pixels (PX2). The DVS circuit (220) may be connected to an event floating diffusion node (EFD) shared by a plurality of second pixels (PX2).

[0131] The current / voltage converter (210) may include a logarithmic amplifier (LA) and a feedback transistor (FB). The logarithmic amplifier (LA) can convert a photocurrent (IP) generated by at least one photodiode into a voltage and amplify the voltage. The logarithmic amplifier (LA) can output a logarithmic voltage (VLOG) on a logarithmic scale. The current / voltage converter (210) may be connected to an event floating diffusion node (EFD). The feedback transistor (FP) and the logarithmic amplifier (LA) may be connected to the event floating diffusion node (EFD).

[0132] The amplification circuit (220) may be configured to amplify the voltage (VLOG) to generate an output voltage (VDIFF). For example, the amplification circuit (220) may include capacitors (C1, C2), a differential amplifier (DA), and a switch (SW) that is operated by a reset signal (RST). For example, the capacitors (C1, C2) may store electrical energy generated by at least one photodiode. For example, the capacitances of the capacitors (C1, C2) may be appropriately selected considering the shortest time (i.e., refractory period) between two events that may occur consecutively in a single pixel. When the switch (SW) is switched on by the reset signal (RST), the pixel may be initialized. The reset signal (RST) may be received from the low AER circuit of the event detection circuit (160).

[0133] The comparison circuit (230) can determine whether an event detected at a pixel is an on-event or an off-event by comparing the output voltage (VDIFF) of the differential amplifier (DA) with the level of the reference voltage (Vref). If an event in which the light intensity increases is detected, the comparison circuit (230) can output a signal (ON) indicating that it is an on-event, and if an event in which the light intensity decreases is detected, the comparison circuit (230) can output a signal (OFF) indicating that it is an off-event.

[0134] FIG. 13 shows a 3-stack structure of an image sensor (100) according to an exemplary embodiment of the present disclosure. The image sensor (100) of FIG. 13 can correspond to the image sensor (100) of FIG. 1.

[0135] An exemplary embodiment of an image sensor (100) according to an embodiment of the present disclosure is described in terms of its physical structure. With reference to the drawings below, an exemplary embodiment of the present disclosure is described based on the layers included in the image sensor (100) of the present disclosure. To facilitate the explanation of the technical concept of the present disclosure, the components illustrated in the drawings below may be simplified and illustrated differently from actual implemented semiconductor wafers, semiconductor chips, layers, semiconductor packages, etc.

[0136] Referring to FIG. 13, the image sensor (100) may include first to third layers (L1 to L3). Each of the first to third layers (L1 to L3) may be manufactured by a different semiconductor process or from different semiconductor wafers. The first layer (L1) may be electrically connected to the second layer (L2) on the second layer (L2). The second layer (L2) may be electrically connected to the third layer (L3) on the third layer (L3). In other words, the second layer (L2) may be located between the first and third layers (L1, L3).

[0137] In one embodiment, the first layer (L1) may include a pixel array region (PA) and a first pad (PAD1). The pixel array region (PA) and the first pad (PAD1) may be physically separated from each other or spaced apart by a predetermined distance. A plurality of first pixels (PX1) and second pixels (PX2) may be disposed within the pixel array region (PA). For example, the photodiode of the first pixel (PX1) may be formed in the pixel array region (PA) of the first layer (L1). The photodiode of the second pixel (PX2) may be formed in the pixel array region (PA) of the first layer (L1).

[0138] In one embodiment, the first pixel (PX1) and the second pixel (PX2) can be connected to the CIS circuit (210) and the DVS circuit (220) of the second layer (L2).

[0139] In one embodiment, the first layer (L1) and the second layer (L2) can be connected in a copper-copper bonding manner.

[0140] In one embodiment, the second layer (L2) may include a CIS circuit (210), a DVS circuit (220), and a second pad (PAD2). For example, the CIS circuit (210) may include a reset transistor, a driving transistor, and a select transistor, etc. In an embodiment, the CIS circuit (210) may be formed on the first layer (L1).

[0141] In one embodiment, the CIS circuit (210) and DVS circuit (220) of the second layer (L2) can receive charge from the first layer (L1) and generate an output signal. The output signal generated in the first layer (L1) and / or the second layer (L2) can be transmitted to the third layer (L3) through connection structures connected to the first pad (PAD1), the second pad (PAD2) and / or the third pad (PAD3).

[0142] In one embodiment, the third layer (L3) may include a logic circuit area (LA) and a third pad (PAD3). The logic circuit area (LA) may be an area for forming the row driver (120), control logic circuit (130), and signal processing circuit (140) of FIG. 2 described above.

[0143] The third layer (L3) may include the remaining components of the image sensor (100) that are not formed in the first layer (L1) and the second layer (L2). For example, the third layer (L3) may include CIS logic, DVS logic, an Analog to Digital Converter (ADC), a Correlated-Double Sampler (CDS), etc. Although not shown herein, the third layer (L3) may further include a processor (e.g., the processor (11) of FIG. 1) or an image signal processor (ISP), etc.

[0144] FIG. 14 is a block diagram of pixel groups (PG1 to PG4) including a first pixel (PX1) and a second pixel (PX2) according to an exemplary embodiment of the present disclosure. Content that overlaps with Figure 3 will be omitted and explained.

[0145] As shown in FIG. 14, the pixel array (110) may include a plurality of unit blocks each containing '64' pixels arranged in an 8x8 (i.e., 8 rows and 8 columns), and the plurality of unit blocks may be arranged in a matrix. The unit blocks may include '16' pixel groups (PG1 to PG4) arranged in a 4x4 (i.e., 4 rows and 4 columns).

[0146] One or more pixel groups among the first to fourth pixel groups (PG4) may include a plurality of first pixels (PX1) and at least one second pixel (PX2).

[0147] An image sensor according to an exemplary embodiment of the present disclosure may be a hybrid sensor comprising a first pixel, a CIS pixel, and a second pixel, a DVS pixel. Since the image sensor includes a first pixel which is a color pixel and a second pixel which is the same color as the first pixel, interference between pixels caused by the white color pixel can be suppressed during image sensor operation, thereby reducing crosstalk.

[0148] FIG. 15 is a block diagram showing an electronic device (2000) to which an image sensor is applied according to an exemplary embodiment of the present disclosure.For example, the electronic device (2000) may be a portable terminal.

[0149] Referring to FIG. 15, an electronic device (2000) according to an exemplary embodiment of the present disclosure may include an application processor (2100), an image sensor (2200), a display device (2300), a working memory (2400), storage (2500), a user interface (2600), and a wireless transceiver (2700). An image sensor (100) according to exemplary embodiments of the present disclosure described in FIG. 1 through 14 may be applied to the image sensor (2200) shown in FIG. 15.

[0150] The application processor (2100) can control the overall operation of the electronic device (2000) and can detect the movement of an object by processing event data, i.e., event signals, received from the image sensor (2200). That is, the application processor (2100) can perform image processing on the movement of an object based on data regarding whether an event has occurred and the amount of change in illumination for the event received from the image sensor (2200).

[0151] The image sensor (2200) can sense an object to generate event signals and transmit the generated event signals to an application processor (2100). The image sensor (2200) according to an exemplary embodiment of the present disclosure can function or operate as an independent sensor in the electronic device (2000) using only the image sensor (2200).

[0152] The image sensor (2200) can generate image data, such as image data, based on a received optical signal and provide the image data to an application processor (2200). Although one image sensor (2200) is shown in FIG. 15, it is not limited thereto, and the electronic device (2000) may include a plurality of image sensors (2200).

[0153] An image sensor (2200) according to an exemplary embodiment of the present disclosure may be a hybrid sensor comprising a first pixel, a CIS pixel, and a second pixel, a DVS pixel. Adjacent first pixels and second pixels included in the image sensor (200) (e.g., first pixels and second pixels included in the same pixel group) may be implemented as the same color pixels, thereby eliminating interference between pixels that may occur when adjacent first pixels and second pixels are implemented as different color pixels and reducing crosstalk. Accordingly, while the image sensor (2200) is implemented as a hybrid sensor, the image sensing function and event sensing function of the image sensor (2200) may be improved, and the image quality of the image generated by the image sensor (2200) may be improved.

[0154] The working memory (2400) can store data used for the operation of the electronic device (2000). For example, the working memory (2400) can temporarily store packets or frames processed by the application processor (2100). The working memory (2400) can temporarily store a frame containing output data received from the image sensor (2200).

[0155] The working memory (2400) can be implemented as a volatile memory such as DRAM, SRMA, or a non-volatile resistive memory such as FeRAM, RRAM, or PRAM. The working memory (2400) can store programs and / or data that the application processor (2100) processes or executes.

[0156] The storage (2500) may be implemented as a non-volatile memory device such as NADN flash or resistive memory, and, for example, the storage (2500) may be provided as a memory card (MMC, eMMC, SD, micro SD), etc. The storage (2500) may store data and / or a program for an execution algorithm that controls the image processing operation of the image sensor (2200), and the data and / or the program may be loaded into the working memory (2400) when the image processing operation is performed. In an embodiment, the storage (1500) may store output image data generated from the image sensor (2200), such as corrected image data or post-processed image data.

[0157] The user interface (2600) can be implemented with various devices capable of receiving user input, such as a keyboard, a curtain key panel, a touch panel, a fingerprint sensor, and a microphone. The user interface (2600) can receive user input and provide a signal corresponding to the received user input to the application processor (2100).

[0158] The wireless transceiver (2700) may include a transceiver (2720), a modem (2710), and an antenna (2730).

[0159] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims.

Claims

Claim 1 An image sensor comprising a plurality of pixel groups, wherein at least one pixel group among the plurality of pixel groups includes a first pixel for generating image data and a second pixel for generating event data, and wherein the first pixel and the second pixel included in the same pixel group receive light signals of the same color; and a dynamic vision sensor (DVS) circuit that generates an event signal based on an electrical signal generated from the second pixel. Claim 2 An image sensor according to claim 1, comprising: a read-out circuit that generates image data based on first electrical signals output from the first pixel of the plurality of pixel groups; and an event detection circuit that generates event data based on second electrical signals output from the second pixel of the at least one pixel group. Claim 3 An image sensor according to claim 1, wherein the plurality of pixel groups includes a first pixel group, a second pixel group, a third pixel group, and a fourth pixel group, wherein the first pixel group, the second pixel group, and the fourth pixel group each include the first pixel and the second pixel, and the third pixel group includes the first pixel, wherein the first pixel and the second pixel included in the first pixel group receive a light signal of a first color, the first pixel and the second pixel included in the second pixel group receive a light signal of a second color, the first pixel included in the third pixel group receives a light signal of a third color, and the first pixel and the second pixel included in the fourth pixel group receive a light signal of the second color, wherein the first color, the second color, and the third color are different from each other and are one of red, green, and blue. Claim 4 An image sensor according to claim 1, wherein the plurality of pixel groups are formed in a first layer, and the DVS circuit connected to the pixel group including the second pixel among the plurality of pixel groups is formed in a second layer. Claim 5 An image sensor according to claim 1, wherein the at least one pixel group comprises a plurality of first pixels, and the plurality of first pixels share a first floating diffusion node. Claim 6 An image sensor according to claim 3, wherein a plurality of second pixels included in the first pixel group, the second pixel group, and the fourth pixel group share an event floating diffusion node. Claim 7 An image sensor according to claim 1, wherein at least two of the plurality of pixel groups each include the first pixel and the second pixel, and in the at least two pixel groups, at least two of the second pixels are positioned at the edge portion where the at least two pixel groups meet. Claim 8 An image sensor according to claim 3, wherein the plurality of first pixels included in the second pixel group share a second floating diffusion node, the plurality of first pixels included in the third pixel group share a third floating diffusion node, and the plurality of first pixels included in the fourth pixel group share a fourth floating diffusion node. Claim 9 An image sensor comprising a plurality of pixel groups, wherein one or more of the plurality of pixel groups include a pixel array comprising a first pixel and a second pixel; a dynamic vision sensor (DVS) circuit that generates an event signal based on a first electrical signal output from the second pixel; a pixel circuit that generates a pixel signal based on a second electrical signal output from the first pixel; a read-out circuit that generates image data based on the pixel signal; and an event detection circuit that receives the event signal and generates event data, wherein the first pixel group among the plurality of pixel groups includes N of the first pixels and M of the second pixels, where N and M are natural numbers, and the N of the first pixels and M of the second pixels receive a light signal of a first color and convert it into an electrical signal. Claim 10 An image sensor according to claim 9, characterized in that the first color is one of red, green, blue, cyan, yellow, and magenta.

Images