Semiconductor pattern image generation device, method and system

Abstract

A semiconductor pattern image generation device according to one embodiment is an artificial intelligence-based semiconductor pattern image generation device for generating a group of semiconductor pattern images to be input into a semiconductor process simulation by executing program code loaded into one or more memory devices through one or more processors, wherein the program code is executed to receive a patterning vulnerability and convert it into a first vector, receive a design condition and convert it into a second vector, and generate at least one pattern image satisfying both the patterning vulnerability and the design condition using the first vector and the second vector as inputs.

Description

Technology Field

[0001] The present invention relates to a semiconductor pattern image generation apparatus, method, and system, and more specifically, to a semiconductor pattern image generation apparatus, method, and system that generates a semiconductor pattern image by receiving design rules and patterning vulnerabilities as inputs. Background Technology

[0002] Conventional semiconductor pattern image generation methods involve engineers directly creating candidate semiconductor pattern images for semiconductor process simulation or obtaining them through rule-based methods.

[0003] In the case of direct production, the quality of the result varies significantly depending on the producer's expertise (reduced diversity), and the generation speed is inefficient (low diversity, high cost, and high fidelity). In the case of rule-based methods, the upper bound of diversity is determined by the complexity of the designed rules (middle diversity, middle cost, and low fidelity). Semiconductor pattern images generated using rule-based methods are highly likely to have low accuracy and fidelity.

[0004] In other words, the quality of the patterning candidate pool depends on the engineer's expertise, resulting in slow production speeds and high costs. Furthermore, there is a problem where the upward limit for the diversity of semiconductor pattern images produced varies depending on the complexity of the designed rules. The problem to be solved

[0005] One embodiment of the present invention aims to provide a semiconductor pattern image generation apparatus, method, and system that generates a semiconductor pattern image by receiving design rules and patterning vulnerabilities as inputs. means of solving the problem

[0006] Among the embodiments, the semiconductor pattern image generation device is an artificial intelligence-based semiconductor pattern image generation device for generating a group of semiconductor pattern images to be input into a semiconductor process simulation by executing program code loaded into one or more memory devices through one or more processors, wherein the program code is executed to receive a patterning vulnerability and convert it into a first vector, receive a design condition and convert it into a second vector, and generate at least one pattern image satisfying both the patterning vulnerability and the design condition using the first vector and the second vector as inputs.

[0007] Receiving the patterning vulnerability and converting it into a first vector may include receiving the patterning vulnerability represented by a first vulnerability score using a patterning vulnerability evaluation index including PVB (Process Variation Band) or NILS (Normalized Image Log Slope), and calculating a vector value corresponding to the received first vulnerability score.

[0008] Calculating a vector value corresponding to the received first vulnerability score may include quantizing the vulnerability score appearing as a continuous value to define a plurality of grades, defining a codebook containing a vector value corresponding to each of the plurality of grades, and determining the first vector corresponding to the first vulnerability score based on the codebook.

[0009] Defining multiple grades by quantizing the vulnerability score represented by the above continuous values ​​may include defining an unknown grade used when ignoring the received patterning vulnerability.

[0010] Receiving the above patterning vulnerability and converting it into a first vector may include simultaneously receiving a plurality of vulnerability scores, each presented using a plurality of patterning vulnerability evaluation indicators, as the plurality of patterning vulnerabilities.

[0011] Receiving the above design conditions and converting them into a second vector may include receiving the design conditions for each of the plurality of polygons included in the at least one pattern image, and generating the second vector by projecting the received design conditions to a predetermined dimension.

[0012] Generating at least one pattern image, each satisfying both the patterning vulnerability and the design condition, using the first vector and the second vector as inputs, may include generating a plurality of polygons each satisfying the design condition, and generating a plurality of patterns defined according to the arrangement of the plurality of polygons and reflecting the patterning vulnerability.

[0013] Generating at least one pattern image, each satisfying both the patterning vulnerability and the design conditions, using the first vector and the second vector as inputs, may include generating the at least one pattern image using an artificial intelligence-based image generation model.

[0014] Generating the at least one pattern image using the above artificial intelligence-based image generation model may include generating the at least one pattern image that satisfies both the patterning vulnerability and the design conditions in random noise using a diffusion model.

[0015] Among the embodiments, the semiconductor pattern image generation method is a semiconductor pattern image generation method performed by a computing device including a processor and a memory, wherein the processor may include the steps of receiving a patterning vulnerability and converting it into a first vector, the processor receiving a design condition and converting it into a second vector, and the processor generating at least one pattern image satisfying both the patterning vulnerability and the design condition using the first vector and the second vector as inputs.

[0016] The step of receiving the patterning vulnerability and converting it into a first vector may include the step of the processor receiving the patterning vulnerability represented by a first vulnerability score using a patterning vulnerability evaluation indicator including PVB (Process Variation Band) or NILS (Normalized Image Log Slope), and the step of the processor calculating a vector value corresponding to the received first vulnerability score.

[0017] The step of calculating a vector value corresponding to the first vulnerability score may include the step of the processor defining a plurality of grades by quantizing the vulnerability score appearing as a continuous value, the step of the processor defining a codebook containing a vector value corresponding to each of the plurality of grades, and the step of the processor determining the first vector corresponding to the first vulnerability score based on the codebook.

[0018] The step of defining multiple grades by quantizing vulnerability scores appearing as consecutive values ​​may include the step of defining an unknown grade used when the processor ignores the received patterning vulnerability.

[0019] The step of receiving the patterning vulnerability and converting it into a first vector may include the step of the processor simultaneously receiving a plurality of vulnerability scores, each presented using a plurality of patterning vulnerability evaluation indicators, as the plurality of patterning vulnerabilities.

[0020] The step of receiving the design conditions and converting them into a second vector may include the step of the processor receiving the design conditions for each of the plurality of polygons included in the at least one pattern image, and generating the second vector by projecting the received design conditions to a predetermined dimension.

[0021] The step of generating at least one pattern image, each satisfying both the patterning vulnerability and the design condition, using the first vector and the second vector as inputs, may include the step of the processor generating a plurality of polygons each satisfying the design condition and the step of the processor generating a plurality of patterns defined according to the arrangement of the plurality of polygons and reflecting the patterning vulnerability.

[0022] The step of generating at least one pattern image, each satisfying both the patterning vulnerability and the design conditions, using the first vector and the second vector as inputs, may include the step of the processor generating the at least one pattern image using an artificial intelligence-based image generation model.

[0023] The step of generating the at least one pattern image using the above artificial intelligence-based image generation model may include the step of the processor generating the at least one pattern image that satisfies both the patterning vulnerability and the design conditions in random noise using a diffusion model.

[0024] Among the embodiments, the semiconductor pattern image generation system includes a semiconductor pattern image generation device comprising an artificial intelligence model that generates a patterning candidate group including at least one pattern image satisfying both input design conditions and patterning vulnerability, and a simulator that performs process simulation using said patterning candidate group, and can adjust process variables using the results of said simulation.

[0025] The semiconductor pattern image generation device may include a patterning vulnerability embedding module that receives a patterning vulnerability and converts it into a first vector, a design condition embedding module that receives a design condition and converts it into a second vector, and an image generation module that generates at least one pattern image satisfying both the patterning vulnerability and the design condition, using the first vector and the second vector as inputs. Effects of the invention

[0026] A semiconductor pattern image generation apparatus, method, and system according to one embodiment of the present invention can generate various semiconductor pattern images as patterning candidate groups for semiconductor process simulation based on design conditions and patterning vulnerability for a plurality of polygons to solve the above-mentioned problem. Brief explanation of the drawing

[0027] FIG. 1 schematically shows a semiconductor pattern image generation system according to one embodiment of the present invention. FIG. 2 is a block diagram of a semiconductor pattern image generation device according to one embodiment of the present invention. FIG. 3 is a diagram illustrating the patterning vulnerability embedding module of FIG. 2 according to an embodiment of the present invention. FIG. 4 is a drawing for explaining the design condition embedding module of FIG. 2 according to an embodiment of the present invention. FIG. 5 is an exemplary diagram showing input and output according to an embodiment of the present invention. FIGS. 6a and 6b are block diagrams of a semiconductor pattern image generation device according to another embodiment of the present invention. FIG. 7 is a flowchart of a semiconductor pattern image generation method according to one embodiment of the present invention. FIG. 8 is a drawing for explaining a computing device according to an embodiment of the present invention. Specific details for implementing the invention

[0028] Embodiments of the present invention are described below with reference to the attached drawings so that those skilled in the art can easily implement them. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification are denoted by similar reference numerals.

[0029] Throughout the specification and claims, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. Such terms are used solely for the purpose of distinguishing one component from another.

[0030] Terms such as "...part," "...unit," and "module" as used in the specification may refer to a unit capable of processing at least one function or operation described in this specification, and may be implemented as hardware or a circuit, software, or a combination of hardware or a circuit and software.

[0031] In addition, at least some of the components or functions of the semiconductor pattern image generating device, method, and system according to the embodiments described below may be implemented as a program or software, and the program or software may be stored on a computer-readable medium.

[0032] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0033] FIG. 1 schematically shows a semiconductor pattern image generation system according to one embodiment of the present invention.

[0034] Referring to FIG. 1, a semiconductor pattern image generation system may include a semiconductor pattern image generation device (100) and a simulator (200).

[0035] A semiconductor pattern image generating device (100) can generate a patterning candidate group (40) including at least one pattern image (30) that satisfies both input design conditions and patterning vulnerability.

[0036] When a semiconductor pattern image generating device (100) inputs design conditions and patterning vulnerabilities, it can generate a patterning candidate group (40) that satisfies both design conditions and patterning vulnerabilities.

[0037] The simulator (200) receives the generated patterning candidate group (40) and can perform a semiconductor process simulation using the received patterning candidate group (40).

[0038] The simulator (200) outputs simulation results (50) through repeated semiconductor process simulations.

[0039] The semiconductor pattern image generation system adjusts process variables through feedback using the simulation results (50) obtained through the semiconductor pattern image generation device (100) and the simulator (200).

[0040] A semiconductor pattern image generation system can repeat semiconductor process simulations using adjusted process variables and determine the validity of the process.

[0041] FIG. 2 is a block diagram of a semiconductor pattern image generating device according to an embodiment of the present invention. FIG. 2 may be a block diagram of the semiconductor pattern image generating device (100) of FIG. 1.

[0042] A semiconductor pattern image generating device (100) according to one embodiment can execute program code or instructions loaded into one or more memory devices through one or more processors.

[0043] For example, the semiconductor pattern image generating device (100) may be implemented as a computing device (900) as described below in relation to FIG. 9. In this case, one or more processors may correspond to the processor (910) of the computing device (900), and one or more memory devices may correspond to the memory (930) of the computing device (900).

[0044] Program code or instructions can be executed by one or more processors to generate at least one pattern image satisfying both design conditions and patterning vulnerability as a patterning candidate input to a semiconductor process simulation. In this specification, the term "module" is used to logically distinguish these functions performed by the program code or instructions.

[0045] Referring to FIG. 2, the semiconductor pattern image generation device (100) may include a patterning vulnerability embedding module (110), a design condition embedding module (120), and an image generation module (130).

[0046] The patterning vulnerability embedding module (110) can receive the patterning vulnerability and convert it into a first vector.

[0047] Patterning vulnerability (10) is an evaluation metric that predicts whether the patterning of the actual process is valid through a designed process simulation.

[0048] That is, patterning vulnerability (10) can be an indicator for determining the success or failure of the simulation results. Patterning vulnerability (10) can be calculated through various indicators such as PVB (process variation band) and NILS (Normalized image log slope).

[0049] The patterning vulnerability embedding module (110) can receive a patterning vulnerability (10) calculated using multiple indicators.

[0050] Patterning vulnerability (10) can be represented as a weak score based on multiple indicators.

[0051] The patterning vulnerability embedding module (110) can receive a patterning vulnerability (10) of a real number and convert it into a vector value.

[0052] That is, the patterning vulnerability embedding module (110) receives a patterning vulnerability (10) represented by a vulnerability score based on a patterning vulnerability evaluation indicator including PVB or NILS, and can calculate a vector value corresponding to the received vulnerability score. For example, the vulnerability score may be 13.3.

[0053] The patterning vulnerability embedding module (110) can provide the first vector as input to the artificial intelligence model of the image generation module (130).

[0054] In one embodiment, the patterning vulnerability embedding module (110) can simultaneously receive a plurality of vulnerability scores, each presented using a plurality of patterning vulnerability evaluation indicators, as a plurality of patterning vulnerabilities.

[0055] That is, the patterning vulnerability embedding module (110) can receive a PVB-based first vulnerability score and a NILS-based second vulnerability score together.

[0056] The design condition embedding module (120) can receive a design condition (Design rule) and convert it into a second vector.

[0057] The design condition (20) is a rule regarding the arrangement and shape of the design polygon. The design condition (20) may mean the minimum conditions for patterning to be possible within the process.

[0058] The design conditions (20) may include the length, position, and spacing between polygons as criteria that polygons within the semiconductor pattern image must physically observe for the success or failure of the patterning.

[0059] The design condition embedding module (120) can convert the design conditions presented for each polygon into vector values.

[0060] The design condition embedding module (120) can provide the second vector as input to the artificial intelligence model of the image generation module (130).

[0061] When the image generation module (130) receives the first vector and the second vector as input, it can generate at least one pattern image (30) that satisfies both the patterning vulnerability and the design conditions.

[0062] The image generation module (130) may include various artificial intelligence-based image generation models. For example, the image generation module (130) may include diffusion models (DMs), Generative Adversarial Networks (GANs) models, Variational AutoEncoder (VAE) models, or Autoregressive models (Ams) models.

[0063] For example, the image generation module (130) can generate at least one pattern image that satisfies both the patterning vulnerability and design conditions in random noise using a diffusion model.

[0064] When the image generation module (130) receives a first vulnerability score and a second vulnerability score calculated according to different patterning vulnerability evaluation indicators, it can generate at least one pattern image that satisfies both the first vulnerability score and the second vulnerability score.

[0065] The image generation module (130) can generate multiple polygons, each satisfying design conditions. The image generation module (130) can generate multiple patterns defined according to the arrangement of the multiple polygons and reflecting patterning vulnerability.

[0066] That is, each of the multiple pattern images has a pattern satisfying patterning vulnerability and can include multiple polygons that satisfy design conditions.

[0067] FIG. 3 is a diagram illustrating the patterning vulnerability embedding module of FIG. 2 according to an embodiment of the present invention.

[0068] Referring to FIG. 3, the patterning vulnerability embedding module (110) may include a score quantization unit (111) and a score codebook (112).

[0069] The score quantization unit (111) can define multiple grades by quantizing the vulnerability score that appears as a continuous value.

[0070] The PVB-based vulnerability score can have a minimum score of 0 to a maximum score of 14. The score quantization unit (111) can quantize the vulnerability score from 0 to 14 to define a grade from 1 to 8.

[0071] For example, when a PVB-based vulnerability score of 13.3 is input, the score quantization unit (111) defines the patterning vulnerability as grade 8.

[0072] The score quantization unit (111) can define an unknown class used when ignoring received patterning vulnerabilities.

[0073] The score quantization unit (111) can define an unknown grade (here, grade 0) in addition to grades 1 through 9.

[0074] If the score quantization unit (111) does not input an indicator of patterning vulnerability into the image generation module (130), the patterning vulnerability can be determined as an unknown grade.

[0075] The score codebook (112) can define a codebook containing vector values ​​corresponding to each of the multiple grades.

[0076] For example, if PVB-based patterning vulnerability is received and vulnerability scores are defined as grades 0 to 8, the score codebook (112) can generate a codebook containing vector values ​​corresponding to each of grades 0 to 8.

[0077] The score codebook (112) can determine a first vector corresponding to a vulnerability score based on the generated codebook.

[0078] For example, if the input patterning vulnerability (10) is 13.3, the score quantization unit (111) assigns a class 8, and the score codebook (112) can determine a first vector corresponding to class 8 and provide it to the image generation module (130).

[0079] FIG. 4 is a drawing for explaining the design condition embedding module of FIG. 2 according to an embodiment of the present invention.

[0080] Referring to FIG. 4, the design condition embedding module (120) may include a design condition projector (121).

[0081] The design condition embedding module (120) receives design conditions for each of the multiple polygons included in the pattern image.

[0082] The design condition projector (121) can project the received design conditions into a predetermined dimension and generate a second vector.

[0083] In one embodiment, the design condition projector (121) can receive design conditions that have m samples and each are expressed in a d-dimensional space.

[0084] The design condition projector (121) is represented by the matrix W and can perform a transformation operation to map the input design conditions to a high-dimensional (or low-dimensional) feature space.

[0085] The design condition projector (121) can output a second vector in a new vector space represented in a new dimension (Gdim) through a conversion operation.

[0086] The design condition projector (121) can provide the second vector as input to the artificial intelligence model of the image generation module (130).

[0087] FIG. 5 is an exemplary diagram showing input and output according to an embodiment of the present invention.

[0088] In FIG. 5, the patterning vulnerability (11) is input as a PVB-based vulnerability score 13. The input design conditions (21) include separation distance, position, etc. for each polygon (POL1).

[0089] The generated multiple pattern images (31) satisfy the input patterning vulnerability (11), and the included polygon (POL2) satisfies the input design condition (21).

[0090] FIGS. 6a and 6b are block diagrams of a semiconductor pattern image generation device according to another embodiment of the present invention.

[0091] FIG. 6a is a block diagram according to one embodiment of a semiconductor pattern image generation device (100-1) in which only design conditions are input while ignoring patterning vulnerability.

[0092] In FIG. 6a, when only design conditions are input independently, the pattern image generating device (100-1) can use an unknown grade (61), for example, grade 0, as input to the patterning vulnerability embedding module (110).

[0093] FIG. 6b is a block diagram according to one embodiment of a semiconductor pattern image generation device (100-2) that generates multiple pattern images by ignoring design conditions and inputting only patterning vulnerability.

[0094] In FIG. 6b, when only patterning vulnerability is input independently, the semiconductor pattern image generation device (100-2) can use unknown information (62, unknown information), for example -1, which is predefined in the design condition embedding module (120) as input.

[0095] FIG. 7 is a flowchart of a semiconductor pattern image generation method according to an embodiment of the present invention. The semiconductor pattern image generation method of FIG. 7 can be performed through the semiconductor pattern image generation device (100) of FIG. 2.

[0096] In FIG. 7, the semiconductor pattern image generating device (100) can receive the patterning vulnerability of a specific score and convert it into a first vector for input to an artificial intelligence model (step S710).

[0097] A semiconductor pattern image generation device (100) can receive a patterning vulnerability represented by a first vulnerability score using a patterning vulnerability evaluation indicator including PVB (Process Variation Band) or NILS (Normalized Image Log Slope).

[0098] The semiconductor pattern image generating device (100) can calculate a vector value corresponding to the received first vulnerability score.

[0099] A semiconductor pattern image generating device (100) can define multiple grades by quantizing vulnerability scores that appear as continuous values.

[0100] In one embodiment, the semiconductor pattern image generating device (100) may define an unknown class used when ignoring the received patterning vulnerability.

[0101] The semiconductor pattern image generating device (100) can define a codebook containing vector values ​​corresponding to each of the multiple grades.

[0102] A semiconductor pattern image generating device (100) can determine a first vector corresponding to a first vulnerability score based on a codebook.

[0103] In one embodiment, the semiconductor pattern image generation device (100) can simultaneously receive a plurality of vulnerability scores, each presented using a plurality of patterning vulnerability evaluation indicators, as a plurality of patterning vulnerabilities.

[0104] A semiconductor pattern image generating device (100) can receive each design condition for at least one polygon and convert it into a second vector for input into an artificial intelligence model (step S720).

[0105] A semiconductor pattern image generating device (100) can receive design conditions for each of the plurality of polygons included in at least one pattern image.

[0106] The semiconductor pattern image generating device (100) can generate a second vector by projecting the received design conditions into a predetermined dimension.

[0107] A semiconductor pattern image generation device (100) inputs the first vector and the second vector into an artificial intelligence model and can generate at least one pattern image that satisfies both patterning vulnerability and design conditions (step S730).

[0108] A semiconductor pattern image generating device (100) can generate multiple polygons, each satisfying design conditions, and generate multiple patterns defined according to the arrangement of the multiple polygons and reflecting patterning vulnerability.

[0109] A semiconductor pattern image generating device (100) can generate at least one pattern image using an artificial intelligence-based image generation model.

[0110] For example, a semiconductor pattern image generating device (100) can generate at least one pattern image that satisfies both patterning vulnerability and design conditions in random noise using a diffusion model.

[0111] FIG. 8 is a drawing for explaining a computing device according to an embodiment of the present invention.

[0112] Referring to FIG. 8, a semiconductor pattern image generation device, method, and system according to embodiments can be implemented using a computing device (900).

[0113] The computing device (900) may include at least one of a processor (910), memory (930), user interface input device (940), user interface output device (950), and storage device (560) that communicate via a bus (920). The computing device (900) may also include a network interface (970) that is electrically connected to a network (90). The network interface (970) may transmit or receive signals to or from other entities via the network (90).

[0114] The processor (910) can be implemented in various types such as an MCU (Micro Controller Unit), AP (Application Processor), CPU (Central Processing Unit), GPU (Graphic Processing Unit), NPU (Neural Processing Unit), etc., and may be any semiconductor device that executes instructions stored in memory (930) or storage device (960). The processor (910) may be configured to implement the functions and methods described above in relation to FIGS. 1 to 7.

[0115] The memory (930) and storage device (960) may include various forms of volatile or non-volatile storage media. For example, the memory may include ROM (read-only memory) (931) and RAM (random access memory) (932). In this embodiment, the memory (930) may be located inside or outside the processor (910), and the memory (930) may be connected to the processor (910) through various known means.

[0116] In some embodiments, at least some configurations or functions of the semiconductor pattern image generating device, method and system according to the embodiments may be implemented as a program or software executed on a computing device (900), and the program or software may be stored on a computer-readable medium.

[0117] In some embodiments, at least some configurations or functions of the semiconductor pattern image generating device, method and system according to the embodiments may be implemented using hardware or circuits of the computing device (900), or may be implemented using separate hardware or circuits that can be electrically connected to the computing device (900).

[0118] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art to which the present invention belongs, utilizing the basic concept of the present invention as defined in the following claims, also fall within the scope of the present invention. Explanation of the symbols

[0119] 10: Patterning Vulnerability 20: Design Conditions 30: Pattern image 100: Semiconductor pattern image generation device 110: Patterning Vulnerability Embedding Module 120: Design Condition Embedding Module 130: Image generation module

Claims

Claim 1 An artificial intelligence-based semiconductor pattern image generation device for generating a group of semiconductor pattern images to be input into a semiconductor process simulation by executing program code loaded into one or more memory devices through one or more processors, wherein the program code is executed to receive a patterning vulnerability and convert it into a first vector, receive a design condition and convert it into a second vector, and generate at least one pattern image satisfying both the patterning vulnerability and the design condition using the first vector and the second vector as inputs. Claim 2 A semiconductor pattern image generation device according to claim 1, wherein receiving the patterning vulnerability and converting it into a first vector comprises receiving the patterning vulnerability represented by a first vulnerability score using a patterning vulnerability evaluation index including PVB (Process Variation Band) or NILS (Normalized Image Log Slope), and calculating a vector value corresponding to the received first vulnerability score. Claim 3 A semiconductor pattern image generating device according to claim 2, wherein calculating a vector value corresponding to the received first vulnerability score comprises quantizing the vulnerability score appearing as a continuous value to define a plurality of grades, defining a codebook containing a vector value corresponding to each of the plurality of grades, and determining the first vector corresponding to the first vulnerability score based on the codebook. Claim 4 A semiconductor pattern image generation device according to claim 3, wherein defining a plurality of grades by quantizing the vulnerability score appearing as a continuous value includes defining an unknown grade used when ignoring the received patterning vulnerability. Claim 5 A semiconductor pattern image generation device according to claim 1, wherein receiving the patterning vulnerability and converting it into a first vector includes simultaneously receiving a plurality of vulnerability scores, each presented using a plurality of patterning vulnerability evaluation indicators, as the plurality of patterning vulnerabilities. Claim 6 A semiconductor pattern image generating device according to claim 1, wherein receiving the design conditions and converting them into a second vector comprises receiving the design conditions for each of the plurality of polygons included in the at least one pattern image, and generating the second vector by projecting the received design conditions to a predetermined dimension. Claim 7 A semiconductor pattern image generating device according to claim 1, wherein, with the first vector and the second vector as inputs, generating at least one pattern image each satisfying both the patterning vulnerability and the design condition, comprises generating a plurality of polygons each satisfying the design condition and generating a plurality of patterns defined according to the arrangement of the plurality of polygons and reflecting the patterning vulnerability. Claim 8 A semiconductor pattern image generation device according to claim 1, wherein generating at least one pattern image, each satisfying both the patterning vulnerability and the design conditions, using the first vector and the second vector as inputs, comprises generating the at least one pattern image using an artificial intelligence-based image generation model. Claim 9 A semiconductor pattern image generation device according to claim 8, wherein generating the at least one pattern image using the artificial intelligence-based image generation model comprises generating the at least one pattern image satisfying both the patterning vulnerability and the design conditions in random noise using a diffusion model. Claim 10 A semiconductor pattern image generation method performed by a computing device including a processor and memory, wherein the processor comprises the steps of: receiving a patterning vulnerability and converting it into a first vector; receiving a design condition and converting it into a second vector; and the processor generating at least one pattern image satisfying both the patterning vulnerability and the design condition, using the first vector and the second vector as inputs. Claim 11 A semiconductor pattern image generation method according to claim 10, wherein the step of receiving the patterning vulnerability and converting it into a first vector comprises: the step of the processor receiving the patterning vulnerability represented by a first vulnerability score using a patterning vulnerability evaluation index including PVB (Process Variation Band) or NILS (Normalized Image Log Slope); and the step of the processor calculating a vector value corresponding to the received first vulnerability score. Claim 12 A semiconductor pattern image generation method according to claim 11, wherein the step of calculating a vector value corresponding to the first vulnerability score comprises: a step in which the processor quantizes the vulnerability score appearing as a continuous value to define a plurality of grades; a step in which the processor defines a codebook containing a vector value corresponding to each of the plurality of grades; and a step in which the processor determines the first vector corresponding to the first vulnerability score based on the codebook. Claim 13 A semiconductor pattern image generation method according to claim 12, wherein the step of defining a plurality of grades by quantizing vulnerability scores appearing as continuous values ​​includes the step of defining an unknown grade used when the processor ignores the received patterning vulnerability. Claim 14 A semiconductor pattern image generation method according to claim 10, wherein the step of receiving the patterning vulnerability and converting it into a first vector comprises the step of the processor simultaneously receiving a plurality of vulnerability scores, each presented using a plurality of patterning vulnerability evaluation indicators, as the plurality of patterning vulnerabilities. Claim 15 A semiconductor pattern image generation method according to claim 10, wherein the step of receiving the design conditions and converting them into a second vector comprises the step of the processor receiving the design conditions for each of the plurality of polygons included in the at least one pattern image, and generating the second vector by projecting the received design conditions into a predetermined dimension. Claim 16 A semiconductor pattern image generation method according to claim 10, wherein the step of generating at least one pattern image, each satisfying both the patterning vulnerability and the design condition, using the first vector and the second vector as inputs, comprises: the step of the processor generating a plurality of polygons each satisfying the design condition; and the step of the processor generating a plurality of patterns defined according to the arrangement of the plurality of polygons and reflecting the patterning vulnerability. Claim 17 A semiconductor pattern image generation method according to claim 10, wherein the step of generating at least one pattern image, each satisfying both the patterning vulnerability and the design conditions, using the first vector and the second vector as inputs, comprises the step of the processor generating the at least one pattern image using an artificial intelligence-based image generation model. Claim 18 A semiconductor pattern image generation method according to claim 17, wherein the step of generating at least one pattern image using the artificial intelligence-based image generation model comprises the step of the processor generating at least one pattern image satisfying both the patterning vulnerability and the design conditions in random noise using a diffusion model. Claim 19 A semiconductor pattern image generation device comprising an artificial intelligence model that generates a patterning candidate group including at least one pattern image satisfying both input design conditions and patterning vulnerability; and a semiconductor pattern image generation system comprising a simulator that performs process simulation using the patterning candidate group and adjusts process variables using the results of the simulation. Claim 20 In claim 19, the semiconductor pattern image generating device comprises: a patterning vulnerability embedding module that receives a patterning vulnerability and converts it into a first vector; a design condition embedding module that receives a design condition and converts it into a second vector; and an image generating module that takes the first vector and the second vector as inputs and generates at least one pattern image satisfying both the patterning vulnerability and the design condition, thereby forming a semiconductor pattern image generating system.

Images