Printed circuit board

Abstract

The present disclosure relates to a printed circuit board comprising: a glass layer; a first wiring portion disposed on the upper side of the glass layer; and a second wiring portion disposed on the upper side of the first wiring portion; wherein the first wiring portion comprises one or more inorganic insulating layers, one or more first wiring layers disposed on or within the one or more inorganic insulating layers, and one or more first wiring vias disposed on or within the one or more inorganic insulating layers, and wherein the second wiring portion comprises one or more first organic insulating layers, one or more second wiring layers disposed on or within the one or more first organic insulating layers, and one or more second wiring vias disposed on or within the one or more first organic insulating layers, and wherein the second wiring portion comprises a cavity penetrating at least a portion of the one or more first organic insulating layers.

Description

Technology Field

[0001] The present disclosure relates to a printed circuit board. Background Technology

[0003] With the recent surge in demand for high-performance computing and large-scale data processing, the server-centric semiconductor application market is expanding rapidly. In response, there is an increasing demand for large-area substrates for high-density and high-bandwidth processing, leading to continuous miniaturization and performance enhancement of substrates and packages. For example, as the demand for chiplets and heterogeneous integrated packages—which integrate multiple chips into a single package to implement distributed functions—increases, the importance of technologies for reducing fine wiring spacing, ensuring overall flatness of packages and substrates, and suppressing warping is emerging. However, the reality is that existing substrate technologies using organic-based copper clad laminates are showing limitations in terms of pitch reduction and warping control. The problem to be solved

[0005] One of the various objectives of the present disclosure is to provide a printed circuit board that is applicable to large-area products, enables miniaturization and high performance, and has a structure advantageous in terms of pitch reduction and warping control. means of solving the problem

[0007] One of the various solutions proposed through the present disclosure is to form an inorganic insulating layer and a fine wiring layer on a glass layer having excellent flatness, and to form an organic insulating layer and a general wiring layer thereon, wherein a cavity capable of being used as a mounting space for a semiconductor chip is formed in the organic insulating layer to provide a printed circuit board.

[0009] For example, a printed circuit board according to one example comprises: a glass layer; a first wiring portion disposed on the upper side of the glass layer; and a second wiring portion disposed on the upper side of the first wiring portion; wherein the first wiring portion comprises one or more inorganic insulating layers, one or more first wiring layers disposed on or within the one or more inorganic insulating layers, and one or more first wiring vias disposed on or within the one or more inorganic insulating layers, and the second wiring portion comprises one or more first organic insulating layers, one or more second wiring layers disposed on or within the one or more first organic insulating layers, and one or more second wiring vias disposed on or within the one or more first organic insulating layers, and may have a cavity penetrating at least a portion of the one or more first organic insulating layers.

[0011] For example, a printed circuit board according to one example comprises: a glass layer; a first substrate portion disposed on the upper side of the glass layer; and a second substrate portion disposed on the upper side of the first substrate portion and including a first region having a cavity on a plane and a second region surrounding the first region; wherein the first substrate portion comprises a first insulating body comprising an inorganic insulating material and one or more first conductive pattern layers disposed on or within the first insulating body, and the second wiring portion comprises a second insulating body comprising an organic insulating material and one or more second conductive pattern layers disposed on or within the second insulating body, and the one or more second conductive pattern layers may be disposed in the second region. Effects of the invention

[0013] As one of the various effects of the present disclosure, it is possible to provide a printed circuit board with a structure that is applicable to large-area products, enables miniaturization and high performance, and is advantageous in terms of pitch reduction and warping control. Brief explanation of the drawing

[0015] FIG. 1 is a schematic cross-sectional view of an example of a printed circuit board. FIG. 2 is a schematic plan view showing the top-view of the printed circuit board of FIG. 1. FIGS. 3a to 3f are process cross-sectional views schematically illustrating an example of manufacturing a printed circuit board. Figure 4 is a cross-sectional view schematically showing an example of a deformation of a printed circuit board. Figure 5 is a cross-sectional view schematically showing another modified example of a printed circuit board. FIG. 6 is a cross-sectional view schematically showing another modified example of a printed circuit board. Figure 7 is a cross-sectional view schematically showing another modified example of a printed circuit board. FIG. 8 is a cross-sectional view schematically showing another modified example of a printed circuit board. FIG. 9 is a cross-sectional view schematically showing another modified example of a printed circuit board. FIG. 10 is a cross-sectional view schematically showing another modified example of a printed circuit board. FIG. 11 is a schematic cross-sectional view of another example of a printed circuit board. FIG. 12 is a schematic plan view showing the top-view of the printed circuit board of FIG. 11. FIGS. 13a and FIGS. 13b are process cross-sectional views schematically illustrating another example of manufacturing a printed circuit board. FIG. 14 is a cross-sectional view schematically showing an example of a deformation of a printed circuit board. FIG. 15 is a cross-sectional view schematically showing another modified example of a printed circuit board. FIG. 16 is a cross-sectional view schematically showing another modified example of a printed circuit board. FIG. 17 is a cross-sectional view schematically showing another modified example of a printed circuit board. FIG. 18 is a cross-sectional view schematically showing another modified example of a printed circuit board. FIG. 19 is a cross-sectional view schematically showing another modified example of a printed circuit board. FIG. 20 is a cross-sectional view schematically showing another modified example of a printed circuit board. Specific details for implementing the invention

[0016] The present disclosure will be described below with reference to the attached drawings. In the drawings, the shapes and sizes of elements may be exaggerated or reduced for clearer explanation.

[0018] FIG. 1 is a schematic cross-sectional view of an example of a printed circuit board.

[0019] FIG. 2 is a schematic plan view showing the top-view of the printed circuit board of FIG. 1.

[0021] Referring to the drawings, a printed circuit board (100A) according to an example may include a glass layer (110), a first wiring section (120) disposed on the upper side of the glass layer (110), and a second wiring section (130) disposed on the upper side of the first wiring section (120). The first wiring section (120) may include one or more inorganic insulating layers (121), one or more first wiring layers (122) disposed on or within one or more inorganic insulating layers (121), and one or more first wiring vias (123) disposed on or within one or more inorganic insulating layers (121). The second wiring section (130) may include one or more first organic insulating layers (131), one or more second wiring layers (132) disposed on or within one or more organic insulating layers (131), and one or more second wiring vias (133) disposed on one or more first organic insulating layers (131). The second wiring section (130) may have a cavity (C) that penetrates at least a portion of one or more first organic insulating layers (131).

[0023] In this way, a printed circuit board (100A) according to an example may include a glass layer (110) which has superior flatness and is advantageous for bending control compared to an organic material-based copper clad laminate. Additionally, a first wiring section (120) may be formed on the glass layer (110), comprising one or more inorganic insulating layers (121), one or more first wiring layers (122), and one or more first wiring vias (123). In this case, by utilizing the flatness characteristics of the glass layer (110) and the thin film characteristics of one or more inorganic insulating layers (121), one or more first wiring layers (122) and one or more first wiring vias (123) may be formed as fine wiring and fine vias, respectively. Accordingly, a silicon interposer or interconnect bridge for die-to-die signal transmission can be replaced with the first wiring section (120), and the first wiring section (120) may also perform the role of other high-density wiring sections. In addition, the glass layer (110) may have a higher thermal conductivity than the organic substrate copper clad laminate, and thus heat dissipation may be improved.

[0025] Additionally, a printed circuit board (100A) according to an example may form a second wiring section (130) on a first wiring section (120) comprising one or more first organic insulating layers (131), one or more second wiring layers (132), and one or more second wiring vias (133). At this time, a cavity (C) penetrating at least a portion of one or more first organic insulating layers (131) may be formed in the second wiring section (130). In this case, a plurality of semiconductor chips (151, 152) may be mounted in the cavity (C) as described below. Accordingly, signal transmission paths or power transmission paths between the first wiring section (120) and the plurality of semiconductor chips (151, 152) can be minimized. Furthermore, even when mounting a plurality of semiconductor chips (151, 152), the overall thickness of the product can be reduced.

[0027] In addition, according to one example, a printed circuit board (100A) may have one or more second wiring layers (132) and one or more second wiring vias (133) disposed around a cavity (C). For example, the second wiring section (130) may have a first region (R1) having a cavity (C) on a plane and a second region (R2) surrounding the first region (R1), and one or more second wiring layers (132) and one or more second wiring vias (133) may be disposed in the second region (R2). In this case, since a rigid metal may be disposed around the cavity (C) where a plurality of semiconductor chips (151, 152) are disposed, warpage control and improvement may be easy. In addition, various functions may be added to the board by forming a capacitor pattern, an inductor pattern, a dummy pattern, etc., on the second wiring section (130). In addition, by forming many power wires in the second wiring section (130), the number of layers of the third wiring section (140), which will be described later, can be reduced. Also, through the second wiring section (130), the printed circuit board (100A) may be applied to a package-on-package (PoP) structure.

[0029] Meanwhile, one or more inorganic insulating layers (121) may each include one or more of silicon oxide films and silicon nitride films. However, they are not limited thereto, and as described below, various other inorganic insulating materials used as materials for inorganic insulating films in semiconductor processes may also be used. When one or more inorganic insulating layers (121) include such inorganic insulating materials, one or more inorganic insulating layers (121) may be formed as thinner films. For example, the thickness of at least one of the one or more inorganic insulating layers (121) may be thinner than the thickness of at least one of the one or more first organic insulating layers (131). Preferably, the thickness of each of the one or more inorganic insulating layers (121) may be thinner than the thickness of each of the one or more first organic insulating layers (131). In addition, the total thickness of one or more inorganic insulating layers (121) may be thinner than the total thickness of one or more first organic insulating layers (131). For example, the thickness of each of the one or more inorganic insulating layers (121), such as the height from the lower surface to the upper surface, may be 5 μm or less, but is not limited thereto. For example, at least some of the one or more inorganic insulating layers (121) can be easily formed as a thin film.

[0031] Additionally, at least one of the one or more first wiring layers (122) may include a relatively high-density wiring than at least one of the one or more second wiring layers (132). Preferably, each of the one or more first wiring layers (122) may include a relatively high-density wiring than each of the one or more second wiring layers (132). For example, the thickness of at least one of the one or more first wiring layers (122) may be thinner than the thickness of at least one of the one or more second wiring layers (132). Preferably, the thickness of each of the one or more first wiring layers (122) may be thinner than the thickness of each of the one or more second wiring layers (132). For example, each of the one or more first wiring layers (122) may include a plurality of line patterns, wherein the line width, spacing, and thickness of the plurality of line patterns may each be 3 μm or less, but are not limited thereto. For example, at least a portion of the one or more first wiring layers (122) may be easily formed as fine wiring.

[0033] Additionally, at least one of the one or more first wiring vias (123) may include a relatively high-density via compared to at least one of the one or more second wiring vias (133). Preferably, each of the one or more first wiring vias (123) may include a relatively high-density via compared to each of the one or more second wiring vias (133). For example, the thickness of at least one of the one or more first wiring vias (123) may be thinner than the thickness of at least one of the one or more second wiring vias (133). Preferably, the thickness of each of the one or more first wiring vias (123) may be thinner than the thickness of each of the one or more second wiring vias (133). For example, at least some of the one or more first wiring vias (123) may be easily formed as microvias.

[0035] Referring to the drawings, a printed circuit board (100A) according to an example may further include a third wiring section (140) disposed on the lower side of a glass layer (110) and a through-via (115) penetrating at least a portion of the glass layer (110). The third wiring section (140) may further include one or more second organic insulating layers (141), one or more third wiring layers (142) disposed respectively on or within one or more second organic insulating layers (141), and one or more third wiring vias (143) disposed respectively within one or more second organic insulating layers (141). The second and third wiring sections (130, 140) may have a symmetrical number of layers relative to each other, but are not limited thereto and may be asymmetrical. Here, the number of layers may be the number of layers of the first and second organic insulating layers (131, 141) and / or the second and third wiring layers (132, 142) included in each of the second and third wiring sections (130, 140).

[0037] For example, in a printed circuit board (100A) according to an example, first and second wiring sections (120, 130) and a third wiring section (140) may be arranged on the upper and lower sides, respectively, based on the glass layer (110), thereby enabling more diverse wiring designs. Additionally, warpage control may be easier. The through-via (115) may include a TGV (Through Glass Via) and may electrically connect the first and third wiring sections (120, 140) to each other. For example, one or more first and third wiring layers (122, 142) may be electrically connected to each other. Furthermore, the through-via (115) may have a reduced pitch compared to the through-via formed on the organic substrate copper clad laminate, thus enabling improved power integrity. Meanwhile, the glass layer (110) may be used as a core layer. For example, it may be a glass core.

[0039] Meanwhile, the lowest first wiring layer (122) among one or more first wiring layers (122) may be in direct contact with the upper surface of the glass layer (110). On the other hand, the uppermost third wiring layer (142) among one or more third wiring layers (142) may be spaced apart from the lower surface of the glass layer (110). At this time, the uppermost second organic insulating layer (141) among one or more second organic insulating layers (141) may be disposed between the lower surface of the glass layer (110) and the uppermost third wiring layer (142). For example, the lowest first wiring layer (122), which requires a relatively high-density wiring design, may be formed directly on the upper surface of the glass layer (110), which has excellent flatness. On the other hand, the uppermost third wiring layer (142), which is sufficient for a relatively low-density wiring design, may be formed on the lower surface of the uppermost second organic insulating layer (141) to ensure adhesion. In this regard, the upper surface of the through-via (115) may be connected in direct contact with at least a portion of the first wiring layer (122) of the lowest layer. On the other hand, the lower surface of the through-via (115) may be connected to at least a portion of the third wiring layer (142) of the uppermost layer through a third wiring via (143) that penetrates at least a portion of the second organic insulating layer (141) of the uppermost layer among one or more third wiring vias (143). In the present disclosure, one or more layers may be a single layer or multiple layers, and if it is a single layer, the uppermost layer and the lowermost layer may be the same, whereas if it is multiple layers, the uppermost layer and the lowermost layer may be distinct from each other.

[0041] Additionally, the thickness of at least one of the one or more inorganic insulating layers (121) may be thinner than the thickness of at least one of the one or more second organic insulating layers (141). Preferably, the thickness of each of the one or more inorganic insulating layers (121) may be thinner than the thickness of each of the one or more second organic insulating layers (141). Additionally, the total thickness of the one or more inorganic insulating layers (121) may be thinner than the total thickness of the one or more second organic insulating layers (141). Additionally, at least one of the one or more first wiring layers (122) may include a relatively high-density wiring than at least one of the one or more third wiring layers (142). Preferably, each of the one or more first wiring layers (122) may include a relatively high-density wiring than each of the one or more third wiring layers (142). For example, the thickness of at least one of the one or more first wiring layers (122) may be thinner than the thickness of at least one of the one or more third wiring layers (142). Preferably, the thickness of each of one or more first wiring layers (122) may be thinner than the thickness of each of one or more third wiring layers (142). Additionally, at least one of one or more first wiring vias (123) may include a relatively high-density via compared to at least one of one or more third wiring vias (143). Preferably, each of one or more first wiring vias (123) may include a relatively high-density via compared to each of one or more third wiring vias (143). For example, the thickness of at least one of one or more first wiring vias (123) may be thinner than the thickness of at least one of one or more third wiring vias (143). Preferably, the thickness of each of one or more first wiring vias (123) may be thinner than the thickness of each of one or more third wiring vias (143). In this case, the technical effects described above can be implemented more easily.

[0043] Referring to the drawings, a printed circuit board (100A) according to an example may include one or more first wiring layers (122), one or more second wiring layers (132), and one or more third wiring layers (142), each comprising a plurality of first wiring layers (122), a plurality of second wiring layers (132), and a plurality of third wiring layers (142). Additionally, one or more first wiring vias (123), one or more second wiring vias (133), and one or more third wiring vias (143) may each include a plurality of first wiring vias (123), a plurality of second wiring vias (133), and a plurality of third wiring vias (143). Additionally, one or more inorganic insulating layers (121) may be one inorganic insulating layer (121), and one or more organic first insulating layers (131) and one or more second insulating layers (141) may each include a plurality of first insulating layers (131) and a plurality of second insulating layers (141).

[0045] For example, a printed circuit board (100A) according to an example may have first to third wiring sections (120, 130, 140) each composed of multiple layers. In this case, a plurality of second wiring layers (132) and a plurality of third wiring layers (142) may each have a greater number of layers than a plurality of first wiring layers (122). For example, a plurality of first wiring layers (122) may be layers in which signal regions for die-to-die signal transmission, etc. are formed at high density, and a plurality of second and third wiring layers (132, 142) may be layers in which power regions, ground regions, dummy regions, etc. are formed, and thus there may be a relative difference in the number of layers. In this regard, the first wiring section (120) may include one inorganic insulating layer (121), whereas the second and third wiring sections (130, 140) may each include a plurality of first and second organic insulating layers (131, 141). However, the relationship of the number of layers of the first to third wiring sections (120, 130, 140) is not necessarily limited to this, and for example, the first to third wiring layers (122, 132, 142) and the first and second organic insulating layers (131, 141) do not necessarily have to be multiple layers. For example, at least one of the first and second organic insulating layers (131, 141) may be a single layer as needed. Also, at least one of the first to third wiring layers (122, 132, 142) may be a single layer as needed.

[0047] Meanwhile, the first to third wiring portions (120, 130, 140) may be referred to as the first to third substrate portions (120, 130, 140) depending on the purpose, function, effect, etc. of each component. Additionally, the first to third wiring layers (122, 132, 142) may be referred to as the first to third conductive pattern layers (122, 132, 142) depending on the purpose, function, effect, etc. of each component. Furthermore, the first to third wiring vias (123, 133, 143) may be referred to as the first to third conductive vias (123, 133, 143) depending on the purpose, function, effect, etc. of each component. For example, the terms used in this disclosure may be used interchangeably according to the structure, function, or common understanding in the general technical field of the components, and this should not be interpreted as limiting the scope of protection of the invention.

[0049] Referring to the drawings, a printed circuit board (100A) according to an example may further include a plurality of conductive bumps (135) that penetrate at least one of one or more first organic insulating layers (131), for example, at least a portion of the lowest layer of the plurality of first organic insulating layers (131). The plurality of conductive bumps (135) may be disposed in a first region (R1) of the second wiring section (130). For example, at least a portion of each of the plurality of conductive bumps (135) may be disposed within a second insulating body (131) provided through one or more first organic insulating layers (131) in the first region (R1). A cavity (C) may expose at least a portion of each of the plurality of conductive bumps (135) from one or more first organic insulating layers (131), for example, the plurality of first organic insulating layers (131). At this time, at least a portion of each of the plurality of semiconductor chips (151, 152) may be disposed within the cavity (C), and the plurality of semiconductor chips (151, 152) may each be connected to one or more of the plurality of conductive bumps (135).

[0051] For example, in a printed circuit board (100A) according to an example, a plurality of conductive bumps (135) may be formed in a first region (R1) of a second wiring section (130) and each connected to the uppermost first wiring layer (122) among one or more first wiring layers (122) of a first wiring section (120), and the plurality of conductive bumps (135) may be exposed through a cavity (C). In this case, a plurality of semiconductor chips (151, 152), each having at least a portion disposed within the cavity (C), may be more easily mounted through the exposed plurality of conductive bumps (135) and may also be more easily electrically connected to one or more first wiring layers (122) of the first wiring section (120). Meanwhile, a surface treatment layer (P) may be formed on the exposed upper surface of each of the plurality of conductive bumps (135). Additionally, a plurality of semiconductor chips (151, 152) may each be connected to a plurality of conductive bumps (135) through a plurality of first electrical connecting metals (155). In this case, the connection reliability between the plurality of semiconductor chips (151, 152) and the plurality of conductive bumps (135) can be further improved. If necessary, the plurality of conductive bumps (151, 152) may be fixed with underfill and / or molding material, but are not limited thereto.

[0053] Referring to the drawings, a printed circuit board (100A) according to one example may further include a solder resist layer (160) disposed below a third wiring section (140). The solder resist layer (160) may have a plurality of openings (h) that each expose at least a portion of the lowest third wiring layer (142) among one or more third wiring layers (142). A plurality of second electrical connecting metals (165) may be disposed on the plurality of openings (h) of the solder resist layer (160). A plurality of second electrical connecting metals (165) may each be connected to the lowest third wiring layer (142).

[0055] For example, a printed circuit board (100A) according to one example may have an electrical connection path for mounting on another board, such as a main board, on the lower side of the third wiring section (140). For example, a printed circuit board (100A) according to one example may be a Ball Grid Array (BGA) package board, but is not limited thereto.

[0057] Referring to the drawings, a printed circuit board (100A) according to an example may include one or more first organic insulating layers (131), and each of the first organic insulating layers (131) may include a photosensitive insulating material. For example, each of the first organic insulating layers (131) may include a PID (Photo Imageable Dielectric). Meanwhile, a cavity (C) may penetrate at least a portion of the first organic insulating layers (131), and in this case, among the first organic insulating layers (131), the inner surfaces providing the wall surface of the cavity (C) of the first organic insulating layers (131) through which the cavity (C) penetrates may have an interlayer step difference from each other.

[0059] For example, a printed circuit board (100A) according to an example may form a second wiring portion (130) based on a plurality of photosensitive organic insulating layers, and cavities (C) may be formed sequentially or stepwise in each of the photosensitive organic insulating layers. Accordingly, the walls of the partial cavities formed in each of the photosensitive organic insulating layers may have an interlayer step difference from each other. In addition, the width on the cross-section between these walls may become progressively smaller as it faces the bottom surface of the cavity (C). Cavities (C) of this structure can be formed more easily in the photosensitive organic insulating layers, and a plurality of semiconductor chips (151, 152) can be mounted more easily in cavities (C) of this structure.

[0061] Below, the components of the printed circuit board (100A) will be described in more detail with reference to the drawings.

[0063] The glass layer (110) may comprise glass that is an amorphous solid. The glass may comprise, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, it is not limited thereto, and alternative glass materials, such as fluorine glass, phosphate glass, chalcogen glass, etc., may also be used as materials. Additionally, other additives may be included to form glass having specific physical properties. The additives may include magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and / or antimony. Additionally, carbonates and / or oxides of these elements and other elements may be included. For example, calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda) may be included. The glass layer (110) may be a layer distinct from organic insulating materials such as glass fiber (glass fiber, glass cloth, glass fabric), etc., such as CCL (Copper Clad Laminate) and PPG (Prepreg). For example, the glass layer (110) may include a glass panel capable of large area, such as a glass plate. The glass layer (110) may be used as a glass core.

[0065] The through-via (115) may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The through-via (115) may perform various functions depending on the design. For example, it may include ground vias, power vias, signal vias, etc. The through-via (115) may have a substantially circular or elliptical shape in planar form, and may have a substantially columnar or hourglass shape in cross-section form, but is not limited thereto. The through-via (115) may be formed within a through hole penetrating between the upper and lower surfaces of the glass layer (110). For example, the through-via (115) may be a TGV (Through Glass Via). The through-via (115) may include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer and an electroplated layer (e.g., electrolytic copper) as a fill plating layer. However, it is not limited thereto, and may include an electroless plating layer (e.g., chemical copper) as a seed layer, or may include both a sputtered layer and an electroless plating layer. If necessary, the fill plating layer of the through-via (115) may be formed conformally, and a filler material may be filled between the fill plating layers. The upper and lower surfaces of the through-via (115) may be substantially coplanared with the upper and lower surfaces of the glass layer (110), respectively, but are not limited thereto. For example, the upper and lower surfaces of the through-via (115) may be recessed inwardly from the upper and lower surfaces of the glass layer (110), respectively. For example, the upper surface of the through-via (115) may be positioned lower than the upper surface of the glass layer (110), and the lower surface of the through-via (115) may be positioned higher than the lower surface of the glass layer (110). For example, a recess step may be formed between the upper and lower surfaces of the glass layer (110) and the upper and lower surfaces of the through-via (115), respectively.There may be multiple penetrating vias (115), and the above-described content may be applied independently to each penetrating via (115).

[0067] One or more inorganic insulating layers (121) may each include an inorganic insulating material. The inorganic insulating material may be, for example, silicon oxide or silicon nitride. For example, one or more inorganic insulating layers (121) may each include one or more of silicon oxide films and silicon nitride films. However, they are not limited thereto, and other inorganic insulating materials used as materials for inorganic insulating films in semiconductor processes may also be used. For example, one or more inorganic insulating layers (121) may each include silicon dioxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), boron nitride (BN), and / or silicon carbide (SiC), but are not limited thereto. In one example, one or more inorganic insulating layers (121) may be a single layer, but are not limited thereto. One or more inorganic insulating layers (121) may provide a first insulating body (121) to the first wiring portion (120). For example, one or more inorganic insulating layers (121) may collectively provide a single first insulating body (121).

[0069] One or more first wiring layers (122) may each include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. One or more first wiring layers (122) may each perform various functions according to the design. For example, they may include signal patterns, power patterns, ground patterns, etc. These patterns may each have various forms such as lines, planes, pads, etc. One or more first wiring layers (122) may mostly include signal patterns, but are not limited thereto. One or more first wiring layers (122) may each include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer and an electroplated layer (e.g., electrolytic copper) as a pattern layer. However, it is not limited thereto, and may include an electroless plating layer (e.g., chemical copper) as a seed layer, or may include both a sputter layer and an electroless plating layer. One or more first wiring layers (122) may provide relatively high-density wiring to the first insulating body (121).

[0071] One or more first wiring vias (123) may each include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. One or more first wiring vias (123) may each include a filled via that fills the via hole, but may also include a conformal via that is placed along the wall of the via hole. One or more first wiring vias (123) may each perform various functions depending on the design. For example, they may include ground vias, power vias, signal vias, etc. One or more first wiring vias (123) may mostly include signal vias. Each of the one or more first wiring vias (123) may include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer and an electroplated layer (e.g., electrolytic copper) as a pattern layer. However, they are not limited thereto, and may include an electroless plating layer (e.g., chemical copper) as a seed layer, or may include both a sputtered layer and an electroless plating layer. The one or more first wiring vias (123) may have a substantially tapered shape in cross-section, where the width of the upper portion is wider than the width of the lower portion. The one or more first wiring vias (123) may provide an electrical connection path to the first insulating body (121). For example, if the one or more first wiring layers (122) are multiple layers, the one or more first wiring vias (123) may be multiple first wiring vias (123), and the multiple first wiring vias (123) may electrically connect the multiple first wiring layers (122) to each other. If necessary, when one or more first wiring layers (122) are not formed on the upper surface of the glass layer (110), one or more first wiring layers (122) and through vias (115) may be electrically connected to each other.

[0073] One or more first organic insulating layers (131) may each include an organic insulating material. The organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material that includes an inorganic filler and / or an organic filler together with the resin. For example, one or more first organic insulating layers (131) may each include a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or a photosensitive insulating material such as PID (Photo Imageable Dielectric), but are not limited thereto. In one example, one or more first organic insulating layers (131) may each include a photosensitive insulating material such as PID (Photo Imageable Dielectric), but are not limited thereto. When one or more first organic insulating layers (131) are multiple layers, they may be separated by boundaries, but they may also be integrated without boundaries. If the interlayer boundaries of the first organic insulating layers (131) are unclear, the layers of the first organic insulating layers (131) can be distinguished through second wiring layers (132) formed on different layers. One or more first organic insulating layers (131) can provide a second insulating body (131) to the second wiring portion (130). For example, one or more first organic insulating layers (131) can collectively provide a single second insulating body (131).

[0075] The cavity (C) may penetrate at least a portion of one or more first organic insulating layers (131), for example, at least a portion of the first insulating body (131). For example, if one or more first organic insulating layers (131) are a plurality of first organic insulating layers (131), the cavity (C) may penetrate each of the remaining first organic insulating layers (131), excluding the lowest first organic insulating layer (131) among the plurality of first organic insulating layers (131), and the lowest first organic insulating layer (131) may provide the bottom surface of the cavity (C). The plurality of first organic insulating layers (131) may include a photosensitive organic insulating material, and in this case, the inner surfaces providing the wall surface of the cavity (C) of the remaining first organic insulating layers (131), excluding the lowest first organic insulating layer (131), may have an interlayer step difference with respect to each other, but are not limited thereto. When viewed from a top-view, the cavity (C) may have an approximate rectangular shape based on the outermost edge, and the four corners may each be approximately curved, but are not limited thereto.

[0077] One or more second wiring layers (132) may each include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. One or more second wiring layers (132) may each perform various functions according to the design. For example, they may include a signal pattern, a power pattern, a ground pattern, etc. Or, they may include a capacitor pattern, an inductor pattern, a dummy pattern, etc. These patterns may each have various forms such as a line, a plane, a pad, etc. One or more second wiring layers (132) may mostly include patterns other than signal patterns, but are not limited thereto. One or more second wiring layers (132) may each include an electroless plating layer (e.g., chemical copper) as a seed layer and an electroplating layer (e.g., electrolytic copper) as a pattern layer. However, it is not limited thereto, and may include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer, or may include both a sputtered layer and an electroless plating layer. One or more second wiring layers (132) may provide relatively low-density wiring to the second insulating body (131). Additionally, they may provide conductive patterns of various functions.

[0079] One or more second wiring vias (133) may each include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. One or more second wiring vias (133) may each include a filled via that fills the via hole, but may also include a conformal via that is placed along the wall of the via hole. One or more second wiring vias (133) may each perform various functions depending on the design. For example, they may include ground vias, power vias, signal vias, etc. Or, they may include vias for capacitors, vias for inductors, dummy vias, etc. One or more second wiring vias (133) may mostly include vias other than signal vias, but are not limited thereto. One or more second wiring vias (133) may each include an electroless plating layer (e.g., chemical copper) as a seed layer and an electrolytic plating layer (e.g., electrolytic copper) as a pattern layer. However, they are not limited thereto, and may include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer, or may include both a sputtered layer and an electroless plating layer. One or more second wiring vias (133) may have a substantially tapered shape in cross-section, where the width of the upper portion is wider than the width of the lower portion. For example, one or more first and second wiring vias (123, 133) may be tapered in substantially the same direction. One or more second wiring vias (133) may provide an electrical connection path to the second insulating body (131). For example, if one or more second wiring layers (132) are multiple layers, one or more second wiring vias (133) may be multiple second wiring vias (133).At this time, some of the plurality of second wiring vias (133) can electrically connect the plurality of first and second wiring layers (122, 132) to each other, and other parts can electrically connect the plurality of second wiring layers (132) to each other.

[0081] Each of the plurality of conductive bumps (135) may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Each of the plurality of conductive bumps (135) may be a metal post, for example, a copper post, but is not limited thereto. Each of the plurality of conductive bumps (135) may include a signal bump, a power bump, a ground bump, etc., and may mostly include a signal bump, but is not limited thereto. Each of the plurality of conductive bumps (135) may include an electroless plating layer (e.g., chemical copper) as a seed layer and an electroplating layer (e.g., electrolytic copper) as a pattern layer. However, it is not limited thereto, and the seed layer may include a sputtered layer (e.g., sputtered titanium / copper) or may include both a sputtered layer and an electroless plating layer. Each of the plurality of conductive bumps (135) may be embedded in the first organic insulating layer (131) of the lowest layer, and each upper surface or upper portion may be exposed through the cavity (C). The upper surface of each of the plurality of conductive bumps (135) may be substantially coplanar with the upper surface of the first organic insulating layer (131) of the lowest layer. However, it is not limited thereto, a portion of each of the plurality of conductive bumps (135) may protrude onto the upper surface of the first organic insulating layer (131) of the lowest layer.

[0083] A surface treatment layer (P) may be disposed on the exposed upper surface or on a portion of each of the plurality of conductive bumps (135). The surface treatment layer (P) may be composed of a single metal, such as copper (Cu), nickel (Ni), palladium (Pd), gold (Au), or tin (Sn), or a combination thereof, and these metals may be formed through methods such as plating, sputtering, deposition, or reflow. This surface treatment layer (P) can contribute to improving the reliability of the entire packaging process by providing functions such as controlling the formation of intermetallic compounds, minimizing electrical contact resistance, preventing oxidation, and improving wettability during the reflow process. For example, when the plurality of conductive bumps (135) each include a copper post, the surface treatment layer (P) may have a multilayer structure including a nickel layer, a copper layer, and a tin layer. For example, each metal post (135) having a surface treatment layer (P) formed thereon may consequently have a CNCS (Cu / Ni / Cu / Sn) bump structure, but is not limited thereto and may have other combinations of bump structures such as a CS (Cu / Sn) bump structure.

[0085] One or more second organic insulating layers (141) may each include an organic insulating material. The organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material that includes an inorganic filler and / or an organic filler together with the resin. For example, one or more second organic insulating layers (141) may each include a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or a photosensitive insulating material such as PID (Photo Imageable Dielectric), but are not limited thereto. In one example, one or more second organic insulating layers (141) may each include a photosensitive insulating material such as PID (Photo Imageable Dielectric), but are not limited thereto. When one or more second organic insulating layers (141) are multiple layers, they may be separated by boundaries, but they may also be integrated without boundaries. If the interlayer boundaries of the second organic insulating layers (141) are unclear, the layers of the second organic insulating layers (141) can be distinguished through the third wiring layers (142) formed on different layers. One or more second organic insulating layers (141) can provide a third insulating body (141) to the third wiring section (140). For example, one or more second organic insulating layers (141) can collectively provide a single third insulating body (141).

[0087] One or more third wiring layers (142) may each include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. One or more third wiring layers (142) may each perform various functions according to the design. For example, they may include signal patterns, power patterns, ground patterns, etc. One or more third wiring layers (142) may mostly include power patterns, but are not limited thereto. These patterns may each have various forms such as lines, planes, pads, etc. One or more third wiring layers (142) may each include an electroless plating layer (e.g., chemical copper) as a seed layer and an electroplating layer (e.g., electrolytic copper) as a pattern layer. However, it is not limited thereto, and may include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer, or may include both a sputtered layer and an electroless plating layer. One or more third wiring layers (142) may provide relatively low-density wiring to the third insulating body (141).

[0089] One or more third wiring vias (143) may each include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. One or more third wiring vias (143) may each include a filled via that fills the via hole, but may also include a conformal via that is placed along the wall of the via hole. One or more third wiring vias (143) may each perform various functions depending on the design. For example, they may include ground vias, power vias, signal vias, etc. One or more third wiring vias (143) may mostly include power vias, but are not limited thereto. One or more third wiring vias (143) may each include an electroless plating layer (e.g., chemical copper) as a seed layer and an electrolytic plating layer (e.g., electrolytic copper) as a pattern layer. However, they are not limited thereto, and may include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer, or may include both a sputtered layer and an electroless plating layer. One or more third wiring vias (143) may have a substantially tapered shape in cross-section, where the width of the lower portion is wider than the width of the upper portion. For example, one or more third wiring vias (143) may be tapered in a direction substantially opposite to one or more first and second wiring vias (123, 133). One or more third wiring vias (143) may provide an electrical connection path to the third insulating body (141). For example, if one or more third wiring layers (142) are multiple layers, one or more third wiring vias (143) may be multiple third wiring vias (143). In this case, some of the multiple third wiring vias (143) may electrically connect the through-via (115) and the multiple third wiring layers (142) to each other, and other parts may electrically connect the multiple third wiring layers (142) to each other.

[0091] Each of the multiple semiconductor chips (151, 152) may include an integrated circuit (IC) die in which hundreds to millions or more of components are integrated into a single chip. The integrated circuit may be a logic chip such as a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, an application processor (AP), an analog-to-digital converter, or an application-specific IC (ASIC). However, it is not limited to these, and it may be a memory chip such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, or high bandwidth memory (HBM), or it may be in the form of a system on chip (SoC) in which various functions are integrated into a single chip. For example, the first semiconductor chip (151) may be a logic chip such as a CPU or GPU, and the second semiconductor chip (152) may be a memory chip such as HBM, in which case a plurality of second semiconductor chips (152) may be arranged around the first semiconductor chip (151). Alternatively, the first semiconductor chip (151) may be an input / output die, and the second semiconductor chip (152) may be a chiplet of a logic chip such as a CPU or GPU and / or a memory chip such as HBM, in which case a plurality of second semiconductor chips (152) may be arranged around the first semiconductor chip (151). For example, a highly integrated package configuration may be possible.

[0093] Each of the plurality of first electrical connection metals (155) may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the plurality of first electrical connection metals (155) may include a copper bump. Alternatively, each of the plurality of first electrical connection metals (155) may include a solder bump. Alternatively, each of the plurality of first electrical connection metals (155) may include a combination of a copper bump and a solder bump. The plurality of first electrical connection metals (155) may be used for mounting a plurality of semiconductor chips (151, 152). For example, each of the plurality of first electrical connection metals (155) may be bonded to a plurality of conductive bumps (135), more specifically, to a surface treatment layer (P) formed on each of the plurality of conductive bumps (135).

[0095] The solder resist layer (160) may include a liquid or film-type solder resist. However, it is not limited thereto, and other types of insulating materials such as ABF may be used. A surface treatment layer and / or metal bumps may be formed as needed on each pattern exposed through a plurality of openings (h). Each pattern exposed through a plurality of openings (h) may be in the form of SMD (Solder Mask Defined) and / or NSMD (Non Solder Mask Defined), but is not limited thereto. The solder resist layer (160) can protect internal components of the printed circuit board (100A), for example, the third wiring section (140).

[0097] Each of the multiple second electrical connecting metals (165) may be formed from a low-melting-point metal, for example, solder such as tin (Sn)-aluminum (Al)-copper (Cu), but this is merely an example and the material is not specifically limited thereto. Each of the multiple second electrical connecting metals (165) may be a ball, a pin, etc. Each of the multiple second electrical connecting metals (165) may be formed as a multilayer or a single layer. When formed as a multilayer, it may include copper pillars and solder, and when formed as a single layer, it may include tin-silver solder, but is not limited thereto. The multiple second electrical connecting metals (165) may be used to mount the printed circuit board (100A) onto another board, such as a main board.

[0099] FIGS. 3a to 3f are process cross-sectional views schematically illustrating an example of manufacturing a printed circuit board.

[0101] Referring to FIG. 3a, a glass layer (110) can be prepared. The glass layer (110) may be in the form of a glass plate. Thus, it can be easily applied to a large-area substrate. The glass layer (110) may have a substantially rectangular shape in cross-section and a substantially square or rectangular shape in planar section, but is not limited thereto. Next, a through-via (115) can be formed in the glass layer (110). For example, a through-hole can be formed in the glass layer (110) by various methods such as laser processing, mechanical processing, or chemical processing, a seed layer can be formed on the wall of the through-hole, and a fill plating layer can be formed to fill at least a portion of the through-hole to form the through-via (115). The through-hole can be formed to penetrate between the upper and lower surfaces of the glass layer (110). The seed layer can be formed by sputtering with a material containing titanium and a material containing copper, and the fill plating layer can be formed by electroplating with a material containing copper, but is not limited thereto. The seed layer and the plating layer on the upper and lower surfaces of the glass layer (110) can be removed by etching and / or polishing. Multiple through-vias (115) may be formed in the glass layer (110).

[0103] Referring to FIG. 3b, a first wiring layer (122) can be formed on the upper surface of a glass layer (110). The first wiring layer (122) may include a line pattern having a fine pitch, a pad pattern covering the upper surface of a through-via (115), etc. These patterns can be formed using a photolithography process and a plating process of a dry film. The plating process may involve forming a seed layer by sputtering with a material containing titanium and a material containing copper, and forming a pattern layer by electroplating with a material containing copper, but is not limited thereto. Next, an inorganic insulating layer (121) can be formed on the upper surface of the glass layer (110). The inorganic insulating layer (121) can cover the first wiring layer (122) formed earlier. The inorganic insulating layer (121) can be formed using CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), etc., but is not limited thereto. The inorganic insulating layer (121) can be formed in the form of a thin film. Next, a first wiring via (123) penetrating the inorganic insulating layer (121) can be formed. Additionally, a first wiring layer (122) can be further formed on the upper surface of the inorganic insulating layer (121). The first wiring via (123) may include a via pattern having a fine pitch. The additionally formed first wiring layer (122) may include a line pattern having a fine pitch, a pad pattern covering the upper surface of the via pattern, etc. The first wiring via (123) can be formed by forming a via hole in the inorganic insulating layer (121) through an etching process and performing the plating process described above on the via hole. The additionally formed first wiring layer (122) can be formed using the photo process and plating process described above. Through a series of processes, the first wiring portion (120) can be formed.

[0105] Referring to FIG. 3c, a plurality of conductive bumps (135) can be formed on the additionally formed first wiring layer (122). For example, a plurality of conductive bumps (135) can be formed on each of the plurality of pad patterns arranged in the central area on the plane among the plurality of pad patterns of the first wiring layer (122) formed on the upper surface of the inorganic insulating layer (121). The plurality of conductive bumps (135) can be formed using a dry film photolithography process and a plating process. The plating process may involve forming a seed layer by performing electroless plating with a copper-containing material and forming a pattern layer on the seed layer by performing electrolytic plating with a copper-containing material, but is not limited thereto. If necessary, all or part of the surface treatment layer (P), which will be described later, may be formed on each of the plurality of conductive bumps (135) in advance. Depending on the material used, the surface treatment layer (P) may be formed through methods such as plating, sputtering, deposition, or reflow.

[0107] Referring to FIG. 3d, one or more first organic insulating layers (131), one or more second wiring layers (132), and one or more second wiring vias (133) can be formed on the upper surface of an inorganic insulating layer (121). Additionally, one or more second organic insulating layers (141), one or more third wiring layers (142), and one or more third wiring vias (143) can be formed on the lower surface of a glass layer (110). Preferably, each of these can be formed as a plurality of layers. For example, a build-up process can be performed on both sides based on the glass layer (110) and the first wiring portion (120). The build-up process may include stacking organic insulating layers, forming via holes in the organic insulating layers, and forming wiring vias and wiring layers on the via holes and organic insulating layers, respectively. The stacking of organic insulating layers may, for example, involve stacking a photosensitive insulating material. The formation of via holes may, for example, be performed by a photolithography process and an etching process. Wiring vias can be formed by a plating process including electroless plating and electrolytic plating. Wiring layers can also be formed by a plating process including electroless plating and electrolytic plating. This build-up process can be repeated on both sides based on the glass layer (110) and the first wiring section (120). For example, the build-up process can be repeated until a desired number of layers is reached. Through a series of processes, the second wiring section (130) and the third wiring section (140) can be formed. Meanwhile, in the case of the second wiring section (130), the second wiring layer (132) and the second wiring via (133) may not be formed in the central area corresponding to the area where a plurality of conductive bumps (135) are formed on a plane, and the second wiring layer (132) and the second wiring via (133) may be formed only in the surrounding area surrounding the central area. Meanwhile, in the case of the second wiring section (130), if necessary, a stopper layer including titanium (Ti), etc., can be formed on a plurality of conductive bumps (150) during the build-up process.For example, a stopper layer can be formed on a plurality of conductive bumps (150) in the central region of the aforementioned plane by a sputtering or plating process. The stopper layer may be a layer for forming a cavity (C) described later. Next, a solder resist layer (160) can be formed on the lower side of the third wiring portion (140). The solder resist layer (160) can be formed by stacking or coating a solder resist material.

[0109] Referring to FIG. 3e, a cavity (C) can be formed in the central region on the aforementioned plane of the second wiring portion (130). The cavity (C) can be formed by performing a photolithography process and an etching process on each of the first organic insulating layers (131) to form each sub-cavity step by step. The cavity (C) can be formed up to the aforementioned stopper layer. After forming the cavity (C), the stopper layer can be removed by etching or the like. Meanwhile, the aforementioned stopper layer may not be formed, in which case the stopper layer removal process may be unnecessary. When forming the cavity (C), at least a portion of each of the plurality of conductive bumps (135) may be exposed through the cavity (C). A surface treatment layer (P) may be formed on at least a portion of the exposed portion of each of the plurality of conductive bumps (135). Meanwhile, as described above, if a portion or all of the surface treatment layer (P) is formed in advance on each of the plurality of conductive bumps (135), a portion or all of each surface treatment layer (P) may be exposed through the cavity (C). If only a portion of each surface treatment layer (P) is formed in advance, the remaining portion of each surface treatment layer (P) can be formed after the cavity (C) is formed. Depending on the material used, the surface treatment layer (P) can be formed through methods such as plating, sputtering, deposition, or reflow. Next, a plurality of openings (h) can be formed in the solder resist layer (160) through a photo process, an etching process, or laser processing. Additionally, a plurality of second electrical connection metals (165) can be formed by attaching solder balls, etc., to each of the plurality of openings (h).

[0111] Referring to FIG. 3f, a plurality of semiconductor chips (151, 152) can be mounted in a cavity (C). Each of the plurality of semiconductor chips (151, 152) can be connected to a surface treatment layer (P) formed on each of the plurality of conductive bumps (135) using a plurality of first electrical connection metals (155). After mounting the plurality of semiconductor chips (151, 152), underfill and / or molding may be further performed. A printed circuit board (100A) according to the example described above can be manufactured through a series of processes, but the manufacturing process is not necessarily limited thereto. Other details may be substantially the same as those described in the printed circuit board (100A) according to the example described above.

[0113] Figure 4 is a cross-sectional view schematically showing an example of a deformation of a printed circuit board.

[0115] Referring to the drawings, the printed circuit board (100B) according to the modified example may have the first wiring section (120) formed in more layers than the printed circuit board (100A) according to the example described above. For example, the first wiring section (120) may include a plurality of inorganic insulating layers (121), a plurality of first wiring layers (122) each disposed on or within the plurality of inorganic insulating layers (121), and a plurality of first wiring vias (123) each disposed within the plurality of inorganic insulating layers (121). For example, high-density wiring may be formed in more layers, and in this case, more complex and diverse wiring designs may be possible. The plurality of inorganic insulating layers (121) may include the inorganic insulating material described above, and each layer may include substantially the same inorganic insulating material. In this case, the plurality of inorganic insulating layers (121) may have boundaries separated from each other, but may also be integrated without boundaries separated. If the interlayer boundaries of the plurality of inorganic insulating layers (121) are unclear, the layers of the plurality of inorganic insulating layers (121) can be distinguished through the plurality of first wiring layers (122) formed on different layers. The plurality of inorganic insulating layers (121) can collectively provide a single second insulating body (131). Other details may be substantially the same as those described in the printed circuit board (100A) according to the example above.

[0117] Figure 5 is a cross-sectional view schematically showing another modified example of a printed circuit board.

[0119] Referring to the drawings, a printed circuit board (100C) according to another variation example may include, in addition to the printed circuit board (100A) according to the example described above, one or more first wiring layers (122), such as the uppermost first wiring layer (122) among the plurality of first wiring layers (122), may include a plurality of conductive pads (125). Furthermore, the cavity (C) may expose at least a portion of each of the plurality of conductive pads (125) from one or more first organic insulating layers (131), such as a plurality of first organic insulating layers (131), such as a second insulating body (131). For example, the plurality of conductive bumps (135) described in the example described above may be omitted, and the cavity (C) may be formed more deeply. For example, the cavity (C) may penetrate from the upper surface of the second insulating body (131) to the lower surface, rather than penetrating a portion of the upper surface of the second insulating body (131) as in the example described above. A plurality of conductive pads (125) may be disposed in the first region (R1) described above. A surface treatment layer (P) may be disposed on at least a portion of the exposed portion of each of the plurality of conductive pads (125). A plurality of semiconductor chips (151, 152) may each be connected to one or more of the plurality of conductive pads (125). In this case, the process can be simplified further. In addition, since the cavity (C) can be formed deeply, the thickness of the product after mounting the plurality of semiconductor chips (151, 152) can be made thinner. Other details may be substantially the same as those described in the printed circuit board (100A) according to the example described above.

[0121] FIG. 6 is a cross-sectional view schematically showing another modified example of a printed circuit board.

[0123] Referring to the drawings, a printed circuit board (100D) according to another modified example may include, in the printed circuit board (100A) according to the above-described example, a first wiring portion (120) may include a plurality of inorganic insulating layers (121), a plurality of first wiring layers (122) each disposed on or within the plurality of inorganic insulating layers (121), and a plurality of first wiring vias (123) each disposed within the plurality of inorganic insulating layers (121). Additionally, the uppermost first wiring layer (122) among the plurality of first wiring layers (122) may include a plurality of conductive pads (125), and a cavity (C) may expose at least a portion of each of the plurality of conductive pads (125), and a surface treatment layer (P) may be disposed on at least a portion of each of the exposed portions of the plurality of conductive pads (125). Additionally, a plurality of semiconductor chips (151, 152) may each be connected to one or more of the plurality of conductive pads (125). For example, a printed circuit board (100D) according to another modified example may be a combination of a printed circuit board (100A) according to one example, a printed circuit board (100B) according to a modified example, and a printed circuit board (100C) according to another modified example. Other details may be substantially the same as those described above for the printed circuit board (100A) according to one example, the printed circuit board (100B) according to a modified example, and the printed circuit board (100C) according to another modified example.

[0125] Figure 7 is a cross-sectional view schematically showing another modified example of a printed circuit board.

[0127] Referring to the drawings, a printed circuit board (100E) according to another variation example may further include a frame (180) having a through-hole (H) and an insulating material (190) filling at least a portion of the through-hole (H) in the printed circuit board (100A) according to the example described above. A glass layer (110) may be disposed at least a portion within the through-hole (H), and the insulating material (190) may be disposed between the frame (180) and the glass layer (110). One or more inorganic insulating layers (121), such as a first insulating body (121), may cover the upper surface of the glass layer (110), the upper surface of the frame (180), and the upper surface of the insulating material (190), respectively. One or more second organic insulating layers (141), such as a third insulating body (141), may cover the lower surface of the glass layer (110), the lower surface of the frame (180), and the lower surface of the insulating material (190), respectively. The insulating material (190) may be formed by a separate filling process, and thus may have an interlayer boundary with the uppermost second organic insulating layer (141). However, it is not limited thereto, and the insulating material (190) may be formed from the uppermost second organic insulating layer (141), in which case they may be integrated without an interlayer boundary. The frame (180) may be used as a jig during the process, and thus may be more advantageous for process warpage control, etc. Additionally, a plurality of through-holes (H) may be formed in the large-area frame (180), and by using this, a plurality of printed circuit boards (100E) can be manufactured through the same process and then divided into a cutting process, thereby increasing productivity. The frame (180) may include various materials. For example, it may include organic insulating materials such as CCL (Copper Clad Laminate). Or, it may include inorganic insulating materials such as silicon or ceramic. Or, it may include metals such as copper (Cu). However, it is not limited thereto. The through-holes (H) may penetrate between the upper and lower surfaces of the frame (118).The insulating material (190) may include an organic insulating material substantially identical to the second organic insulating layer (141) of the uppermost layer, but is not limited thereto and may include a different organic insulating material. For example, various organic insulating materials that are easy to fill may be used as the material of the insulating material (190). Other details may be substantially the same as those described in the printed circuit board (100A) according to the example above.

[0129] FIG. 8 is a cross-sectional view schematically showing another modified example of a printed circuit board.

[0131] Referring to the drawings, a printed circuit board (100F) according to another modified example may further include a frame (180) having a through-hole (H) and an insulating material (190) filling at least a portion of the through-hole (H) in the printed circuit board (100A) according to the example described above. Additionally, the first wiring section (120) may include a plurality of inorganic insulating layers (121), a plurality of first wiring layers (122) each disposed on or within the plurality of inorganic insulating layers (121), and a plurality of first wiring vias (123) each disposed within the plurality of inorganic insulating layers (121). For example, a printed circuit board (100F) according to another modified example may be a combination of a printed circuit board (100B) according to a modified example and a printed circuit board (100E) according to another modified example with the printed circuit board (100A) according to the example. Other details may be substantially the same as described in the printed circuit board (100A) according to the example above, the printed circuit board (100B) according to a modified example, and the printed circuit board (100E) according to another modified example.

[0133] FIG. 9 is a cross-sectional view schematically showing another modified example of a printed circuit board.

[0135] Referring to the drawings, a printed circuit board (100G) according to another variation example may further include a frame (180) having a through-hole (H) and an insulating material (190) filling at least a portion of the through-hole (H) in the printed circuit board (100A) according to the example described above. Additionally, one or more first wiring layers (122), such as the uppermost first wiring layer (122) among the plurality of first wiring layers (122), may include a plurality of conductive pads (125), and a cavity (C) may expose at least a portion of each of the plurality of conductive pads (125), and a surface treatment layer (P) may be disposed on at least a portion of each of the exposed portions of the plurality of conductive pads (125). Additionally, a plurality of semiconductor chips (151, 152) may each be connected to one or more of the plurality of conductive pads (125). For example, a printed circuit board (100G) according to another variation may be a combination of a printed circuit board (100A) according to one example, a printed circuit board (100C) according to another variation, and a printed circuit board (100E) according to another variation. Other details may be substantially the same as those described above for the printed circuit board (100A) according to one example, the printed circuit board (100C) according to another variation, and the printed circuit board (100E) according to another variation.

[0137] FIG. 10 is a cross-sectional view schematically showing another modified example of a printed circuit board.

[0139] Referring to the drawings, a printed circuit board (100H) according to another modified example may further include a frame (180) having a through-hole (H) and an insulating material (190) filling at least a portion of the through-hole (H), in addition to the printed circuit board (100A) according to the example described above. Additionally, the first wiring section (120) may include a plurality of inorganic insulating layers (121), a plurality of first wiring layers (122) each disposed on or within the plurality of inorganic insulating layers (121), and a plurality of first wiring vias (123) each disposed within the plurality of inorganic insulating layers (121). Additionally, the uppermost first wiring layer (122) among the plurality of first wiring layers (122) may include a plurality of conductive pads (125), and the cavity (C) may expose at least a portion of each of the plurality of conductive pads (125), and a surface treatment layer (P) may be disposed on at least a portion of each of the exposed portions of the plurality of conductive pads (125). Additionally, a plurality of semiconductor chips (151, 152) may each be connected to one or more of the plurality of conductive pads (125). For example, a printed circuit board (100H) according to another modified example may be a combination of a printed circuit board (100A) according to one example, a printed circuit board (100B) according to a modified example, a printed circuit board (100C) according to a modified example, and a printed circuit board (100E) according to another modified example. Other details may be substantially the same as described in the printed circuit board (100A) according to the example above, the printed circuit board (100B) according to a modified example, the printed circuit board (100C) according to another modified example, and the printed circuit board (100E) according to another modified example.

[0141] FIG. 11 is a schematic cross-sectional view of another example of a printed circuit board.

[0142] FIG. 12 is a schematic plan view showing the top-view of the printed circuit board of FIG. 11.

[0144] Referring to the drawings, a printed circuit board (100I) according to another example may, in addition to the printed circuit board (100A) according to the above example, have one or more first organic insulating layers (131), such as a plurality of first organic insulating layers (131), each comprising a non-photosensitive insulating material. For example, one or more first organic insulating layers (131), such as a plurality of first organic insulating layers (131), may each comprise ABF (Ajinomoto Build-up Film). In this case, the wall surface of the cavity (C') formed in one or more first organic insulating layers (131), such as a plurality of first organic insulating layers (131), may not have an interlayer step.

[0146] For example, in a printed circuit board (100I) according to another example, in the case where one or more first organic insulating layers (131) comprise a plurality of first organic insulating layers (131), the inner surfaces providing the wall surfaces of the cavity (C') of the first organic insulating layers (131) through which the cavity (C') penetrates among the plurality of first organic insulating layers (131) can be connected to each other without a step between layers. For example, in a printed circuit board (100I) according to another example, the second wiring portion (130) can be formed based on a plurality of non-photosensitive organic insulating layers, and the cavity (C') can be formed continuously in each non-photosensitive organic insulating layer. Accordingly, the wall surfaces of the partial cavities formed in each non-photosensitive organic insulating layer can be connected to each other without a step between layers.

[0148] Meanwhile, the cavity (C') may have a substantially tapered shape in cross-section, where the width of the upper portion is wider than the width of the lower portion, but is not limited thereto and may have a substantially vertical shape if necessary. A cavity (C') with such a structure can be more easily formed in a non-photosensitive organic insulating layer, and likewise, a plurality of semiconductor chips (151, 152) can be more easily mounted in a cavity (C') with such a structure. Other details may be substantially the same as those described in the printed circuit board (100A) according to the example above.

[0150] FIGS. 13a and FIGS. 13b are process cross-sectional views schematically illustrating another example of manufacturing a printed circuit board.

[0152] Referring to the drawings, an intermediate structure prior to the formation of the cavity (C') can be formed through the process described with reference to FIGS. 3a to 3d, and then the cavity (C') can be formed in the central region on the aforementioned plane of the second wiring portion (130). The cavity (C') can be formed by performing laser processing, chemical etching, and / or plasma etching on one or more first organic insulating layers (131), such as a plurality of first organic insulating layers (131). The cavity (C') can be formed up to the aforementioned stopper layer. After forming the cavity (C'), the stopper layer can be removed by etching, etc. Meanwhile, the aforementioned stopper layer may not be formed, in which case the stopper layer removal process may be unnecessary. Next, a plurality of semiconductor chips (151, 152) can be mounted in the cavity (C'). A printed circuit board (100I) according to another example described above may be manufactured through a series of processes, but the manufacturing process is not necessarily limited thereto. Other details may be substantially the same as those described in the example of manufacturing the printed circuit board (100A) according to the example described above, the printed circuit board (100I) according to another example, and the example of manufacturing the printed circuit board (100A) according to the example.

[0154] FIG. 14 is a cross-sectional view schematically showing an example of a deformation of a printed circuit board.

[0156] Referring to the drawings, the printed circuit board (100J) according to a modified example may include, in the printed circuit board (100I) according to another example described above, a first wiring portion (120) may include a plurality of inorganic insulating layers (121), a plurality of first wiring layers (122) each disposed on or within the plurality of inorganic insulating layers (121), and a plurality of first wiring vias (123) each disposed within the plurality of inorganic insulating layers (121). Other details may be substantially the same as those described in the printed circuit board (100A) according to the example described above, the printed circuit board (100B) according to a modified example, and the printed circuit board (100I) according to another example.

[0158] FIG. 15 is a cross-sectional view schematically showing another modified example of a printed circuit board.

[0160] Referring to the drawings, a printed circuit board (100K) according to another variation example is a printed circuit board (100I) according to another example described above, wherein one or more first wiring layers (122), such as the uppermost first wiring layer (122) among the plurality of first wiring layers (122), may include a plurality of conductive pads (125), and a cavity (C') may expose at least a portion of each of the plurality of conductive pads (125), and a surface treatment layer (P) may be disposed on at least a portion of each of the exposed portions of the plurality of conductive pads (125). Additionally, a plurality of semiconductor chips (151, 152) may each be connected to one or more of the plurality of conductive pads (125). Other details may be substantially the same as those described in the printed circuit board (100A) according to the example above, the printed circuit board (100C) according to another variation example, and the printed circuit board (100I) according to another example.

[0162] FIG. 16 is a cross-sectional view schematically showing another modified example of a printed circuit board.

[0164] Referring to the drawings, a printed circuit board (100L) according to another variation example may include, in the printed circuit board (100I) according to another example described above, a first wiring section (120) may include a plurality of inorganic insulating layers (121), a plurality of first wiring layers (122) each disposed on or within the plurality of inorganic insulating layers (121), and a plurality of first wiring vias (123) each disposed within the plurality of inorganic insulating layers (121). Additionally, the uppermost first wiring layer (122) among the plurality of first wiring layers (122) may include a plurality of conductive pads (125), and a cavity (C') may expose at least a portion of each of the plurality of conductive pads (125), and a surface treatment layer (P) may be disposed on at least a portion of each of the exposed portions of the plurality of conductive pads (125). Additionally, a plurality of semiconductor chips (151, 152) may each be connected to one or more of a plurality of conductive pads (125). For example, a printed circuit board (100L) according to another modified example may be a combination of a printed circuit board (100I) according to another example, a printed circuit board (100J) according to a modified example, and a printed circuit board (100K) according to another modified example. Other details may be substantially the same as those described above for the printed circuit board (100A) according to the example, the printed circuit board (100B) according to the modified example, the printed circuit board (100C) according to another modified example, the printed circuit board (100I) according to another example, the printed circuit board (100J) according to the modified example, and the printed circuit board (100K) according to another modified example.

[0166] FIG. 17 is a cross-sectional view schematically showing another modified example of a printed circuit board.

[0168] Referring to the drawings, a printed circuit board (100M) according to another variation example may further include a frame (180) having a through-hole (H) and an insulating material (190) filling at least a portion of the through-hole (H), in addition to the printed circuit board (100I) according to another example described above. Other details may be substantially the same as those described in the printed circuit board (100A) according to the example described above, the printed circuit board (100E) according to another variation example, and the printed circuit board (100I) according to another example.

[0170] FIG. 18 is a cross-sectional view schematically showing another modified example of a printed circuit board.

[0172] Referring to the drawings, a printed circuit board (100N) according to another modified example may further include a frame (180) having a through-hole (H) and an insulating material (190) filling at least a portion of the through-hole (H), in addition to the printed circuit board (100I) according to another example described above. Additionally, the first wiring section (120) may include a plurality of inorganic insulating layers (121), a plurality of first wiring layers (122) each disposed on or within the plurality of inorganic insulating layers (121), and a plurality of first wiring vias (123) each disposed within the plurality of inorganic insulating layers (121). For example, a printed circuit board (100N) according to another modified example may be a combination of a printed circuit board (100J) according to a modified example and a printed circuit board (100M) according to another modified example, in addition to the printed circuit board (100I) according to another example. Other details may be substantially the same as those described in the printed circuit board (100A) according to the example above, the printed circuit board (100B) according to a modified example, the printed circuit board (100E) according to another modified example, the printed circuit board (100I) according to another example, the printed circuit board (100J) according to a modified example, and the printed circuit board (100M) according to another modified example.

[0174] FIG. 19 is a cross-sectional view schematically showing another modified example of a printed circuit board.

[0176] Referring to the drawings, a printed circuit board (100O) according to another variation example may further include a frame (180) having a through-hole (H) and an insulating material (190) filling at least a portion of the through-hole (H), in addition to the printed circuit board (100I) according to another example described above. Also, one or more first wiring layers (122), such as the uppermost first wiring layer (122) among the plurality of first wiring layers (122), may include a plurality of conductive pads (125), and a cavity (C') may expose at least a portion of each of the plurality of conductive pads (125), and a surface treatment layer (P) may be disposed on at least a portion of each of the exposed portions of the plurality of conductive pads (125). Additionally, a plurality of semiconductor chips (151, 152) may each be connected to one or more of the plurality of conductive pads (125). For example, a printed circuit board (100O) according to another variation may be a combination of a printed circuit board (100I) according to another example, a printed circuit board (100K) according to another variation, and a printed circuit board (100M) according to another variation. Other details may be substantially the same as those described above for the printed circuit board (100A) according to the example, the printed circuit board (100C) according to another variation, the printed circuit board (100E) according to another variation, the printed circuit board (100I) according to another example, the printed circuit board (100K) according to a variation, and the printed circuit board (100M) according to another variation.

[0178] FIG. 20 is a cross-sectional view schematically showing another modified example of a printed circuit board.

[0180] Referring to the drawings, a printed circuit board (100P) according to another modified example may further include a frame (180) having a through-hole (H) and an insulating material (190) filling at least a portion of the through-hole (H), in addition to the printed circuit board (100I) according to another example described above. Additionally, the first wiring section (120) may include a plurality of inorganic insulating layers (121), a plurality of first wiring layers (122) each disposed on or within the plurality of inorganic insulating layers (121), and a plurality of first wiring vias (123) each disposed within the plurality of inorganic insulating layers (121). Additionally, the uppermost first wiring layer (122) among the plurality of first wiring layers (122) may include a plurality of conductive pads (125), and the cavity (C') may expose at least a portion of each of the plurality of conductive pads (125), and a surface treatment layer (P) may be disposed on at least a portion of each of the exposed portions of the plurality of conductive pads (125). Additionally, a plurality of semiconductor chips (151, 152) may each be connected to one or more of the plurality of conductive pads (125). For example, a printed circuit board (100P) according to another modified example may be a combination of a printed circuit board (100I) according to another example, a printed circuit board (100J) according to a modified example, a printed circuit board (100K) according to a modified example, and a printed circuit board (100M) according to another modified example. Other details may be substantially the same as described in the printed circuit board (100A) according to the example above, the printed circuit board (100B) according to a modified example, the printed circuit board (100C) according to another modified example, the printed circuit board (100E) according to another modified example, the printed circuit board (100I) according to another example, the printed circuit board (100J) according to a modified example, the printed circuit board (100K) according to a modified example, and the printed circuit board (100M) according to another modified example.

[0182] In the present disclosure, thickness, width, length, pitch, depth, etc., can each be measured using a scanning microscope or an optical microscope based on a cross-section obtained by grinding or cutting a printed circuit board. The cross-section may be a vertical or horizontal cross-section, and each value can be measured based on the required cross-section. If the values ​​are not constant, the values ​​can be determined by the average value of values ​​measured at any five points. The width of the top and / or bottom of a via or cavity can be measured on a cross-section obtained by cutting the substrate in the thickness direction along the central axis of the via or cavity. The depth of the via or cavity can be measured as the distance from the top to the bottom of the via on a cross-section obtained by cutting the substrate in the thickness direction along the central axis of the via or cavity.

[0184] In the present disclosure, the expression "covering" may include not only cases of covering the entire area but also cases of covering at least a portion, and may include not only cases of direct covering but also cases of indirect covering. Additionally, the expression "filling" may include not only cases of filling completely but also cases of filling approximately, and may include, for example, cases where some voids or pores exist.

[0186] In the present disclosure, substantially, this can be determined by including process errors, positional deviations, and measurement errors occurring during the manufacturing process. For example, being substantially identical in line width, spacing, thickness, height, etc., may include not only cases where they are numerically identical but also cases where they have approximately similar values. Furthermore, having a substantially certain shape may include not only cases where they have a completely such shape but also cases where they have an approximately such shape. Additionally, being substantially coplanar may include not only cases where they are in a completely identical plane but also cases where they are in an approximately identical plane.

[0188] In the present disclosure, substantially identical materials may mean not only completely identical materials but also include materials of the same type. For example, the composition of the materials may be substantially identical, but their specific compositional ratios may differ slightly.

[0190] In the present disclosure, the meaning of "in cross-section" may refer to the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed in a side view. Additionally, the meaning of "in planar" may refer to the planar shape when the object is cut horizontally, or the planar shape when the object is viewed in a top view or bottom view.

[0192] In this disclosure, terms such as "lower side," "bottom," and "bottom surface" are used for convenience to refer to the downward direction based on the cross-section of the drawings, while terms such as "upper side," "top," and "top surface" are used to refer to the opposite direction. Additionally, terms such as "side" and "side surface" are used to refer to the direction perpendicular to the top and bottom surfaces. However, this definition of direction is merely for the convenience of explanation, and it should be understood that the scope of the patent claims is not specifically limited by such descriptions of direction, and the concepts of "up" and "down" may change at any time.

[0194] In this disclosure, the term "connected" encompasses not only direct connection but also indirect connection through an adhesive layer, etc. Furthermore, the term "electrically connected" encompasses both cases of physical connection and cases of non-connection. Additionally, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order or / or importance of said components. In some cases, without departing from the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0196] The expression "one example" as used in this disclosure does not imply identical embodiments, but is provided to emphasize distinct features of each. However, the examples presented above do not exclude the implementation of features of other examples. For example, even if a detail described in a particular example is not described in another example, it may be understood as a detail related to that other example, provided that there is no description in that other example that contradicts or conflicts with that detail.

[0198] The terms used in this disclosure are for illustrative purposes only and are not intended to limit the disclosure. Whereby, singular expressions include plural expressions unless the context clearly indicates otherwise. Explanation of the symbols

[0200] 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K, 100L, 100M, 100N, 100O, 100P: Printed circuit board 110: Glass layer 115: Penetrating Via 120: First wiring section (first circuit board section) 121: Inorganic insulating layer (first insulating body) 122: 1st wiring layer 123: 1st wiring via 125: Conductive pad 130: Second wiring section (second circuit board section) 131: First organic insulating layer (second insulating body) 132: Second wiring layer 133: 2nd wiring via 135: Challenging Bump 140: 3rd wiring section (3rd circuit board section) 141: Second organic insulating layer (third insulating body) 142: Third wiring layer 143: 3rd wiring via 151, 152: Semiconductor Chip 155: First electrical connecting metal 160: Solder resist layer 165: Second electrical connecting metal 180: Frame 190: Insulating material P: Surface treatment layer C, C': Cavity H: Penetration part h: opening R1: Zone 1 (Central Zone) R2: Second region (peripheral region)

Claims

Claim 1 A printed circuit board comprising: a glass layer; a first wiring portion disposed on the upper side of the glass layer; and a second wiring portion disposed on the upper side of the first wiring portion; wherein the first wiring portion comprises one or more inorganic insulating layers, one or more first wiring layers disposed respectively on or within the one or more inorganic insulating layers, and one or more first wiring vias disposed respectively within the one or more inorganic insulating layers; and the second wiring portion comprises one or more first organic insulating layers, one or more second wiring layers disposed respectively on or within the one or more first organic insulating layers, and one or more second wiring vias disposed respectively within the one or more first organic insulating layers, and having a cavity penetrating at least a portion of the one or more first organic insulating layers. Claim 2 A printed circuit board according to claim 1, wherein each of the one or more inorganic insulating layers comprises one or more of a silicon oxide film and a silicon nitride film. Claim 3 A printed circuit board according to claim 2, wherein the thickness of at least one of the one or more inorganic insulating layers is thinner than the thickness of at least one of the one or more first organic insulating layers. Claim 4 A printed circuit board according to claim 1, wherein at least one of the one or more first wiring layers comprises a relatively high-density wiring than at least one of the one or more second wiring layers. Claim 5 In claim 4, a printed circuit board in which the thickness of at least one of the one or more first wiring layers is thinner than the thickness of at least one of the one or more second wiring layers. Claim 6 A printed circuit board according to claim 1, further comprising: a third wiring portion disposed below the glass layer; and a through-via penetrating at least a portion of the glass layer, wherein the third wiring portion comprises one or more second organic insulating layers, one or more third wiring layers disposed respectively on or within the one or more second organic insulating layers, and one or more third wiring vias disposed respectively within the one or more second organic insulating layers. Claim 7 A printed circuit board according to claim 6, wherein the first wiring layer of the lowest layer among the one or more first wiring layers is in direct contact with the upper surface of the glass layer and the upper surface of the through-via, respectively, and between the lower surface of the glass layer and the third wiring layer of the uppermost layer among the one or more third wiring layers, the second organic insulating layer of the uppermost layer among the one or more second wiring layers is disposed, and the lower surface of the through-via is connected to at least a portion of the third wiring layer of the uppermost layer through a third wiring via that penetrates at least a portion of the second organic insulating layer of the uppermost layer among the one or more third wiring vias. Claim 8 In claim 6, the printed circuit board wherein the one or more first wiring layers, the one or more second wiring layers and the one or more third wiring layers each comprise a plurality of first wiring layers, a plurality of second wiring layers and a plurality of third wiring layers. Claim 9 In claim 8, the one or more inorganic insulating layers are a single inorganic insulating layer, and the one or more first organic insulating layers and the one or more second organic insulating layers each comprise a plurality of first organic insulating layers and a plurality of second organic insulating layers, a printed circuit board. Claim 10 In claim 8, the one or more inorganic insulating layers comprise a plurality of inorganic insulating layers, and the one or more first organic insulating layers and the one or more second organic insulating layers each comprise a plurality of first organic insulating layers and a plurality of second organic insulating layers, a printed circuit board. Claim 11 In claim 8, the one or more first wiring vias, the one or more second wiring vias, and the one or more third wiring vias each comprise a plurality of first wiring vias, a plurality of second wiring vias, and a plurality of third wiring vias, wherein the plurality of first wiring vias electrically connect the plurality of first wiring layers to each other, a portion of the plurality of second wiring vias electrically connects the plurality of first and second wiring layers to each other, another portion of the plurality of second wiring vias electrically connects the plurality of second wiring layers to each other, a portion of the plurality of third wiring vias electrically connects the through-vias and the plurality of third wiring layers to each other, and another portion of the plurality of third wiring vias electrically connects the plurality of third wiring layers to each other, a printed circuit board. Claim 12 A printed circuit board according to claim 6, further comprising: a frame having a penetration; and an insulating material filling at least a portion of the penetration; wherein the glass layer is disposed at least a portion within the penetration, the insulating material is disposed between the frame and the glass layer, the one or more inorganic insulating layers each cover the upper surface of the glass layer, the upper surface of the frame, and the upper surface of the insulating material, and the one or more second organic insulating layers each cover the lower surface of the glass layer, the lower surface of the frame, and the lower surface of the insulating material. Claim 13 A printed circuit board according to claim 1, wherein the second wiring portion further comprises a plurality of conductive bumps each penetrating at least a portion of at least one of the one or more first organic insulating layers, the cavity exposes at least a portion of each of the plurality of conductive bumps from the one or more first organic insulating layers, and a surface treatment layer is disposed on at least a portion of each of the exposed portions of the plurality of conductive bumps. Claim 14 A printed circuit board according to claim 13, further comprising a plurality of semiconductor chips, each having at least a portion disposed within the cavity and each connected to one or more of the plurality of conductive bumps. Claim 15 A printed circuit board according to claim 1, wherein the uppermost first wiring layer among the one or more first wiring layers comprises a plurality of conductive pads, the cavity exposes at least a portion of each of the plurality of conductive pads from the one or more first organic insulating layers, and a surface treatment layer is disposed on at least a portion of each of the plurality of conductive pads. Claim 16 A printed circuit board according to claim 15, further comprising a plurality of semiconductor chips, each having at least a portion disposed within the cavity and each connected to one or more of the plurality of conductive fibers. Claim 17 A printed circuit board according to claim 1, wherein the one or more first organic insulating layers comprise a plurality of first organic insulating layers, each of the plurality of first organic insulating layers comprises a photosensitive insulating material, the cavity penetrates at least a portion of the plurality of first organic insulating layers, and the inner surfaces of the first organic insulating layers through which the cavity penetrates have an interlayer step difference from each other. Claim 18 A printed circuit board according to claim 1, wherein the one or more first organic insulating layers comprise a plurality of first organic insulating layers, each of the plurality of first organic insulating layers comprises a non-photosensitive insulating material, the cavity penetrates at least a portion of the plurality of first organic insulating layers, and the inner surfaces of the first organic insulating layers through which the cavity penetrates are connected to each other without an interlayer step. Claim 19 A printed circuit board comprising: a glass layer; a first substrate portion disposed on the upper side of the glass layer; and a second substrate portion disposed on the upper side of the first substrate portion, comprising a first region having a cavity on a plane and a second region surrounding the first region; wherein the first substrate portion comprises a first insulating body comprising an inorganic insulating material and one or more first conductive pattern layers disposed respectively on or within the first insulating body, and the second wiring portion comprises a second insulating body comprising an organic insulating material and one or more second conductive pattern layers disposed respectively on or within the second insulating body, and wherein the one or more second conductive pattern layers are disposed in the second region. Claim 20 In claim 19, the one or more first conductive pattern layers each comprise a plurality of line patterns, wherein the plurality of line patterns each have a line width, spacing, and thickness of 3 μm or less, a printed circuit board. Claim 21 In claim 19, the second substrate portion further comprises a plurality of conductive bumps, each having at least a portion disposed within the second insulating body, wherein the plurality of conductive bumps are disposed in the first region, and the cavity penetrates a portion from the upper surface of the second insulating body and exposes at least a portion of each of the plurality of conductive bumps from the second insulating body, a printed circuit board. Claim 22 A printed circuit board according to claim 19, wherein the one or more first conductive pattern layers comprise a plurality of conductive pads, the plurality of conductive pads are disposed in the first region, the cavity penetrates from the upper surface to the lower surface of the second insulating body, and at least a portion of each of the plurality of conductive pads is exposed from the second insulating body. Claim 23 In claim 19, the one or more second conductive pattern layers comprise one or more of a capacitor pattern, an inductor pattern, and a dummy pattern, a printed circuit board. Claim 24 A printed circuit board according to claim 19, further comprising: a third substrate portion disposed below the glass layer; and a through-via penetrating at least a portion of the glass layer, wherein the third wiring portion comprises a third insulating body comprising an organic insulating material and one or more third conductive pattern layers disposed on or within the third insulating body. Claim 25 A printed circuit board according to claim 24, further comprising: a frame having a penetration; and an insulating material filling at least a portion of the penetration; wherein the glass layer is disposed at least a portion within the penetration, the insulating material is disposed between the frame and the glass layer, the first insulating body covers the upper surface of the glass layer, the upper surface of the frame, and the upper surface of the insulating material, respectively, and the third insulating body covers the lower surface of the glass layer, the lower surface of the frame, and the lower surface of the insulating material, respectively.

Images