A Strain Control Device of a Semiconductor Package, A Semiconductor Package including the Strain Control Device, and A Semiconductor Module including the Semiconductor Package

Abstract

The embodiments relate to a strain control device for a semiconductor package, a semiconductor package including the strain control device, and a semiconductor module including the semiconductor package. In an embodiment, the strain control device of a semiconductor package may include a body, a plurality of spaced first connection members disposed in a first region below the body, and a conductive paste layer disposed in a second region below the body.

Description

Technology Field

[0001] The present invention relates to a semiconductor package, and more specifically, to an apparatus for controlling strain and heat flow of a semiconductor package, a semiconductor package including the same, and a semiconductor module including said semiconductor package. Background Technology

[0002] As the performance and miniaturization of electrical and electronic products progress rapidly, multiple semiconductor devices are being densely packed into semiconductor packages. While this package structure offers the advantages of efficiently utilizing mounting area and enabling high-speed signal transmission, the heat generated by semiconductor devices and the resulting increase in strain are causing a decline in reliability. Consequently, heat and strain management technology at the package level is recognized as an important challenge.

[0003] Semiconductor packages are applied to various electronic devices such as smartphones, servers, network systems, computers, tablets, and automotive electronics. In particular, in high-performance computing environments like data centers, heat generated in semiconductor packages and the resulting reliability issues are recognized as critical technical challenges due to the increasing adoption of AI semiconductors. Accordingly, there is a demand for technology to properly manage heat in semiconductor packages and control the associated strain.

[0004] In particular, High Bandwidth Memory (HBM) features a multi-layered structure utilizing Through-Silicon Via (TSV), resulting in high power and heat densities and limited heat dissipation paths, making thermal management essential. When HBM is applied to personal electronic devices with small form factors, it may be deployed in a System-In-Package (SIP) form, combined with an Application Processor (AP) into a single package. In this case, since memory devices, which are relatively vulnerable to heat, are placed adjacent to logic chips within a confined space, there is a risk that heat generated by the logic chips will be transferred to the HBM if the heat flow is not properly controlled, thereby degrading the reliability of the memory devices. Therefore, to operate HBM stably in such environments, technology that effectively disperses and controls heat through the package structure is required.

[0005] For example, FIG. 1d is a cross-sectional view of a semiconductor package (10R4) according to the third comparative example.

[0006] A semiconductor package (10R4) according to the fourth comparative example may include a first semiconductor element (11) disposed on a first substrate (10) and a second semiconductor element (12) disposed on a conductive layer (14) on the first substrate (10).

[0007] The first substrate (10) may include at least one of a plurality of insulating layers, wiring layers, and via electrodes. The first semiconductor device (11) may be a semiconductor chip including active and / or passive devices, and for example, an integrated circuit (IC), an application processor (AP), a CPU, a GPU, a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an ASIC, or a combination thereof, such as a System on Chip (SoC), may be applied as the first semiconductor device (11).

[0008] Meanwhile, the second semiconductor device (12) may be a memory chip and may include various types of memory such as stack memory (e.g., HBM), DRAM, ROM, flash memory, etc.

[0009] According to the semiconductor package (10R4) of the fourth comparative example, heat generated from the first semiconductor device (11) may cause thermal stress to the adjacent second semiconductor device (12) during the process of being transferred to a heat sink or vapor chamber, thereby degrading reliability. Although this was not a major issue in the past, as the amount of heat generated by high-performance logic devices such as APs, ASICs, or SoCs has recently increased, the problem of thermal interference in which heat generated from logic devices affects adjacent memory devices has emerged, and thus the need for technology to properly control the heat flow within the package is increasing.

[0010] Furthermore, SiC-based power semiconductor modules are used in high-power environments such as hybrid and electric vehicles, and these modules are susceptible to junction degradation, heat concentration, and thermal runaway due to high temperatures and repetitive thermal cycling. Accordingly, thermal and strain control technologies are also critically required to ensure stable operation even under high-power driving conditions.

[0011] Various heat dissipation structures, such as heat sinks, heat plates, heat pipes, and vapor chambers, are utilized to improve the heat dissipation performance of semiconductor packages. However, even with these structures, reliability issues such as heat concentration, warpage, cracks, voids, and delamination can occur due to differences in the material properties of the junction layer placed in the heat transfer path, particularly in thermal conductivity and coefficient of thermal expansion (CTE).

[0012] FIG. 1a is a cross-sectional view of a semiconductor package (10R1) according to the first comparative example.

[0013] In the semiconductor package (10R1) of the first comparative example, a heat dissipation plate (40) in the form of a metal lid is disposed on the first electronic element (20a) to dissipate heat generated from the first electronic element (20a) in an upward direction, and the first electronic element (20a) and the heat dissipation plate (40) can be bonded by a first adhesive layer (30a) of a polymer-based material. Additionally, a heat sink (50) is disposed on the heat dissipation plate (40), and the heat dissipation plate (40) and the heat sink (50) can be bonded by a second adhesive layer (30b) of a polymer-based material.

[0014] However, the first adhesive layer (30a) and the second adhesive layer (30a) of the polymer-based material have relatively low thermal conductivity, so the heat generated from the first electronic device (20a) cannot be efficiently diffused and may be concentrated in a specific area, resulting in a problem of reduced heat dissipation efficiency. Accordingly, the semiconductor package (10R1) of the first comparative example had a problem in which the performance decreased to 30% or less as it lowered the driving power to lower the temperature itself as the temperature of the first electronic device (20a) increased.

[0015] FIG. 1b is a cross-sectional view of a semiconductor package (10R2) according to a second comparative example.

[0016] In the second comparative example, a metal TIM (Thermal Interface Material), etc., may be applied to the first metal adhesive layer (30M1) and the second metal adhesive layer (30M2) to improve heat transfer.

[0017] However, since there is a difference in the coefficient of thermal expansion between the heat dissipation plate (40) and the second electronic device (20b), or between the heat dissipation plate (40) and the heat sink (50), warpage may occur when the temperature of the second electronic device (20b) increases rapidly, and stress may be concentrated at the interface, and consequently, cracks or voids may occur in the metal adhesive layer, leading to delamination. For example, FIG. 1c is a photograph showing delamination (DP) occurring in a semiconductor package (10R2) according to the second comparative example.

[0019] Referring again to FIG. 1b, in the second comparative technique using a metal TIM (Thermal Interface material), when the temperature of the second electronic device (20b) increases rapidly, a relatively large strain may occur at an interface with a large difference in thermal expansion coefficients, such as the first edge region (ER1) of the first metal adhesive layer (30M1) or the second edge region (ER2) of the second metal adhesive layer (30M2), and if such stress concentration is repeated, there is a possibility of reliability problems such as delamination.

[0021] As such, high-performance semiconductor packages require structural technology capable of efficiently dissipating heat generated by electronic devices while simultaneously resolving strain and delamination issues caused by CTE mismatches between materials. The problem to be solved

[0022] One of the technical challenges of the embodiment is to solve the problem in conventional technology using TIM where, when the temperature of an electronic device increases rapidly, cracks or voids occur in the edge region of the adhesive layer due to differences in the coefficient of thermal expansion, leading to delamination.

[0023] In addition, one of the technical challenges of the embodiment is to provide a structure that efficiently transfers heat generated from the electronic device to the top while mitigating the technical contradiction of delamination occurring at the bonding interface due to the difference in thermal expansion coefficients between adjacent materials.

[0024] In addition, one of the technical challenges of the embodiment is to resolve the problem of reduced reliability caused by excessive thermal stress on memory devices such as HBM during the process of heat generated from logic chips, etc., being transferred to heat sinks or vapor chambers, by controlling the heat flow within the package.

[0025] In addition, improving the reliability of the power semiconductor module by mitigating strain concentration and junction degradation problems inside the package caused by repetitive thermal cycling under high temperature and high power conditions is also one of the technical challenges of the embodiment.

[0026] The technical problems of the present invention are not limited to those described above, and include various technical problems that can be understood by those skilled in the art through the following description of the invention and embodiments. means of solving the problem

[0028] A strain control device for a semiconductor package according to an embodiment may include a body (110), a plurality of spaced first connection members (112) disposed in a first lower region of the body (110); and a conductive paste layer (114) disposed in a second lower region of the body (110).

[0029] The conductive paste layer (114) may include one or more of a solder paste layer, a metal paste, or a metal TIM.

[0030] The first connecting member (112) may be placed in the outer or corner area of ​​the first region of the body (110), and the conductive paste layer (114) may be placed in the central area of ​​the body (110).

[0031] The conductive paste layer (114) may include a plurality of spaced-apart conductive paste layers, and may include a first conductive paste layer (114a) in a central region and a second conductive paste layer (114b), a third conductive paste layer (114c), or a fourth conductive paste layer (114d) and a fifth conductive paste layer (114e) disposed in an outer region spaced apart horizontally or vertically from it.

[0032] The first connecting member (112) may include a plurality of first connecting members (112) disposed in the corner area of ​​the body (110), and some may be disposed to overlap in a vertical direction with a conductive paste layer disposed in the outer area.

[0033] The first roughness (110R1) of the first region where the conductive paste layer (114) is formed may be greater than the second roughness (110R2) of the second region.

[0034] The above body (110) may include a body protrusion (110P) and an exposed portion (110B).

[0035] The first connecting member may include a metal ball (112B1) and a solder cover layer (112B2) surrounding the metal ball (112B1).

[0036] The first connecting member may include a metal pillar (112C1) and a second solder cover layer (112C2) surrounding the metal pillar (112C1).

[0037] Additionally, the embodiment further includes a heat flow control layer (150) disposed on the side of the body (110), and

[0038] The above heat flow control layer (150) may include a plating layer.

[0039] Additionally, the semiconductor package of the embodiment may include a first semiconductor element (211) disposed on a first package substrate (210a), a strain control device (101) disposed on the first semiconductor element (211), and a second semiconductor element (212) disposed spaced apart from the side of the first strain control device (101).

[0040] The strain control device (101) may include a strain control device of any one of the semiconductor packages.

[0041] In addition, the semiconductor module of the embodiment may include any one of the semiconductor packages.

[0042] The strain control device, semiconductor package, and semiconductor module according to the present embodiment can provide the following effects.

[0043] Even if the temperature of the electronic device increases rapidly, the first connecting member (112) is spaced apart so that the thermal expansion stress is dispersed, thereby suppressing cracks, voids, and peeling problems that occur in the edge region of the adhesive layer. In particular, when the first connecting member is a solder ball, the stress dispersion effect is increased by the spaced structure between the solder balls, thereby improving the heat dissipation efficiency and reliability of the joint.

[0044] In addition, according to the strain control device (101) of the embodiment, a conductive paste layer (114) having high thermal conductivity characteristics is placed in the central region considering the maximum strain generation area, and a connecting member (112) is placed in the outer / corner region where thermal stress is high, thereby securing thermal conductivity performance improved by about 400~500% compared to the front TIM structure of the comparative technology.

[0045] A strain control device (101) positioned to overlap with a first semiconductor device (211) intensively forms a heat flow (F1) in the upward direction, and a heat flow control layer (150) on the side suppresses a heat flow (F2) in the direction of a second semiconductor device (212), such as an HBM, thereby minimizing thermal damage to the memory device and improving reliability.

[0046] The uneven surface (110R) formed on the body of the second strain control device (102) can increase the contact area and adhesion with the upper heat dissipation device, thereby reducing the possibility of peeling and maximizing the performance of the upper heat dissipation path.

[0047] The technical effects of the embodiments are not limited to those described in this section and include those that can be understood through the description of the invention. Brief explanation of the drawing

[0049] FIG. 1a is a cross-sectional view of a semiconductor package (10R1) according to a first comparative example. FIG. 1b is a cross-sectional view of a semiconductor package (10R2) according to a second comparative example. FIG. 1c is a photograph of a delamination problem (DP) in a semiconductor package (10R3) according to the third comparative example. FIG. 1d is a cross-sectional view of a semiconductor package (10R4) according to the fourth comparative example. FIG. 2a is a cross-sectional view of a semiconductor package module (1000) according to an embodiment. FIG. 2b is a detailed drawing of a semiconductor package module (1000) according to the embodiment shown in FIG. 2a. FIG. 3a is a cross-sectional view of a first semiconductor package (210A) according to a first embodiment. FIG. 3b is a detailed drawing of a first semiconductor package (210A) according to the first embodiment shown in FIG. 3a. FIG. 4 is a detailed drawing of a first strain control device (101) according to an embodiment. FIG. 5 is a first example of the bottom surface of the first strain control device (101) of FIG. 4. FIG. 6 is a second example of the bottom surface of the first strain control device (101) of FIG. 4. Figure 7a shows stress distribution data in the heat dissipation block of the comparative technology. FIG. 7b shows stress distribution data in a strain control device (101) according to an embodiment. FIG. 8 is a cross-sectional view of a second strain control device (102) according to an embodiment. FIG. 9 is a cross-sectional view of a third strain control device (103) according to an embodiment. FIG. 10a is a bottom view example of the fourth strain control device (104). FIG. 10b is a cross-sectional view of the fourth strain control device (104) shown in FIG. 10a. FIG. 11a is a bottom view example of the fifth strain control device (105). FIG. 11b is a cross-sectional view of the fifth strain control device (105) shown in FIG. 11a. FIG. 12a is a cross-sectional view of a sixth strain control device (106) according to an embodiment. FIG. 12b is a cross-sectional view of the first-second connecting member (112B) in the sixth strain control device (106). FIG. 12c is a cross-sectional view of the first-third connecting member (112C) in the sixth strain control device (106). FIGS. 13a to 13c are exemplary diagrams of semiconductor packages according to the third to fifth embodiments. Specific details for implementing the invention

[0050] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. The suffixes 'module' and 'part' for components used in the following description are assigned or used interchangeably for the sake of ease of drafting the specification and do not inherently possess distinct meanings or roles. Furthermore, the attached drawings are intended to facilitate an easy understanding of the embodiments disclosed in this specification, and the technical concepts disclosed in this specification are not limited by the attached drawings. Additionally, when an element such as a layer, region, or substrate is referred to as existing 'on' another component, this includes existing directly on the other element or having other intermediate elements existing between them.

[0052] (Example)

[0053] FIG. 2a is a cross-sectional view of a semiconductor package module (1000) according to an embodiment, and FIG. 2b is a detailed drawing of a semiconductor package module (1000) according to an embodiment shown in FIG. 2a.

[0054] Referring to FIG. 2a, a semiconductor package module (1000) according to an embodiment may include one or more semiconductor packages (210, 220) and a heat dissipation device (230) disposed on a main board (205).

[0055] The product family to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package) and SIP (System In Package), but is not limited thereto.

[0056] The above main board (205) may be physically and / or electrically connected to other circuit components, and the semiconductor package mounted thereon may have various configurations.

[0057] The first semiconductor package (210) may include a single or multiple semiconductor elements (211, 212) disposed on the first package substrate (210a) and a strain control device (100) disposed to overlap with at least one of these semiconductor elements.

[0058] In the embodiment, the strain control device (100) may simultaneously perform a heat flow control function.

[0059] For example, the first semiconductor device (211) may be placed on the first package substrate (210a), and the second semiconductor device (212) may be placed spaced apart from the first semiconductor device (211). The strain control device (100) may be placed so as to overlap the first semiconductor device (211) in the vertical direction.

[0060] The first package substrate (210a) may include at least one of a plurality of insulating layers, wiring layers, and via electrodes, and may further include an interposer substrate (not shown) to mount a first semiconductor device (211) and a second semiconductor device (212) on the interposer substrate, but is not limited thereto.

[0061] The first semiconductor device (211) and the second semiconductor device (212) may include active devices and / or passive devices. For example, the active device may be an integrated circuit (IC) in which a plurality of devices are integrated, an application processor (AP), a CPU, a GPU, a digital signal processor, a processor for encryption, a microprocessor, a microcontroller, an ASIC, or a System on Chip (SoC).

[0062] In addition, memory chips can be stacked memory such as HBM, and can be implemented as various forms of memory such as DRAM and flash memory.

[0063] In the following description, the first semiconductor device (211) is described as a logic chip and the second semiconductor device (212) is described as a memory chip, but the embodiments are not limited thereto.

[0064] Additionally, the second semiconductor package (220) may include a single or multiple semiconductor elements (223a, 223b) disposed on the second package substrate (220a).

[0065] For example, the second semiconductor package (220) may include a third-1 semiconductor element (223a) and a third-2 semiconductor element (223b) spaced apart and disposed on the second package substrate (220a).

[0066] These semiconductor devices may also include active or passive components and can be implemented in various forms, such as logic chips or memory chips.

[0067] Next, the semiconductor package module (1000) according to the embodiment may include a heat dissipation device (230) disposed on the first semiconductor package (210) and the second semiconductor package (220). The heat dissipation device (230) may be a vapor chamber, but is not limited thereto.

[0068] According to an embodiment, when heat generated from the first semiconductor package (210) and the second semiconductor package (220) is transferred to the lower metal plate of the heat dissipation device (230), the working fluid can vaporize and absorb latent heat of vaporization, and then move toward the upper metal plate and condense into a liquid while releasing latent heat of vaporization. The condensed working fluid can be absorbed into a hollow trench structure and moved toward the lower metal plate.

[0070] Next, referring to FIG. 2b, the first package substrate (210a) in the first semiconductor package (210) can be mounted by the main board (205) and the first adhesive member (210b). The first adhesive member (210b) may be a solder ball, but is not limited thereto.

[0071] Additionally, in the second semiconductor package (220), the second package substrate (220a) may be mounted by a third adhesive member (220b). The third adhesive member (220b) may be a solder ball, but is not limited thereto.

[0072] The above third-1 semiconductor device (223a) and third-2 semiconductor device (223b) may be disposed within a second package body (225), and the second package body (225) may be bonded to a heat dissipation device (230) by a fourth adhesive layer (226). The second package body (225) may include at least one of a plurality of insulating layers, wiring layers, and via electrodes, but is not limited thereto.

[0073] The above-mentioned fourth adhesive layer (226) may be a metal adhesive layer containing a metal material, but is not limited thereto. For example, the above-mentioned fourth adhesive layer (226) may include a Sn alloy adhesive layer, an In alloy adhesive layer, an Al alloy adhesive layer, etc., but is not limited thereto.

[0074] The features of the first semiconductor package (210) will be described in detail later based on FIGS. 3a and 3b.

[0075] According to the semiconductor package of the embodiment, heat generated from semiconductor devices, etc., can be efficiently transferred to the upper side, while resolving the problem of technical contradiction in which delamination occurs at the junction due to the difference in thermal expansion coefficients between adjacent materials.

[0076] In addition, according to the embodiment, the problem of reduced reliability caused by the concentration of thermal stress on memory devices such as HBM during the process in which heat generated from logic chips, etc. is transferred to a heat sink or vapor chamber, can be solved through a heat flow control structure.

[0078] The technical features of the embodiment will be described in detail below with reference to FIGS. 3a and FIGS. 3b.

[0079] FIG. 3a is an enlarged view of a first region (A1) of a semiconductor package module (1000) according to the embodiment shown in FIG. 2b, and is a cross-sectional view of a first semiconductor package (210A) according to the first embodiment, FIG. 3b is a detailed drawing of the first semiconductor package (210A) according to the first embodiment shown in FIG. 3a. In the following description, 'first embodiment' may be abbreviated as 'embodiment'.

[0080] FIG. 4 is a detailed drawing of a first strain control device (101) according to an embodiment.

[0081] FIG. 5 is an example of a bottom view of the first strain control device (101) of FIG. 4, and FIG. 4 may be a cross-sectional view along the line A1-A1' of FIG. 5. FIG. 6 is also a second example of a bottom view of the first strain control device (101) of FIG. 4.

[0082] Referring to FIG. 3a, a first semiconductor package (210A) according to a first embodiment may include a single or multiple semiconductor elements (211, 212) disposed on a first package substrate (210a) and a first strain control device (101).

[0083] For example, the first semiconductor package (210A) of the first embodiment may include a first semiconductor element (211) disposed on a first package substrate (210a), a second semiconductor element (212) disposed spaced apart from the first semiconductor element (211), and a first strain control device (101).

[0084] The first semiconductor device (211) may be disposed in the first package body (213). The first package body (213) may include at least one of a plurality of insulating layers, wiring layers, and via electrodes, but is not limited thereto.

[0085] The first strain control device (101) may include a body (110), a plurality of spaced first connecting members (112) disposed in a first lower region of the body (110), and a conductive paste layer (114) disposed in a second lower region of the body (110). The body (110) may be referred to as a 'strain control body' or a 'heat flow control body'.

[0086] The conductive paste layer (114) may be a solder paste layer, Metal TIM, Ag paste, etc., but is not limited thereto.

[0087] The first connecting member (112) may include a conductive ball, for example, a solder ball, but is not limited thereto.

[0088] The first strain control device (101) may be arranged to overlap with the first semiconductor element (211) in the vertical direction, but is not limited thereto.

[0089] In addition, in the embodiment, the position of the first strain control device (101) is shown as being placed to the left of the second semiconductor element (212), but is not limited thereto, and the position of the first strain control device (101) may be changed according to the position of the first semiconductor element (211) and the position of the heat source in the first semiconductor element (211).

[0090] In addition, in the embodiment, the size of the first semiconductor device (211) is not limited to the size shown in FIG. 2a and FIG. 2b, and may be arranged large enough to occupy the entire first package body (213).

[0091] The second semiconductor device (212) may be disposed on a metal wiring layer (214) with a second connecting member (217) interposed therein, but is not limited thereto. The wiring layer (214) may be an RDL layer, but is not limited thereto.

[0092] The second connecting member (217) may include a conductive ball, for example, a solder ball, but is not limited thereto.

[0094] Next, FIG. 5 is a first example of the bottom surface of the first strain control device (101) of FIG. 4, and FIG. 6 is a second example of the bottom surface of the first strain control device (101) of FIG. 4.

[0095] First, referring to FIG. 5, the strain control device (101) of the embodiment may include a conductive paste layer (114) disposed in a first region of the body (110) and a first connecting member (112) disposed in a second region. For example, the conductive paste layer (114) may be a solder paste layer, Metal TIM, Ag paste, etc., but is not limited thereto. In addition, the first connecting member (112) may include a conductive ball, for example, a solder ball, but is not limited thereto.

[0096] For example, the strain control device (101) of the embodiment may include a conductive paste layer (114) disposed in a first region of the body (110) and a first connecting member (112) disposed in a second region outside the first region.

[0097] Referring to FIG. 3b and FIG. 4 together, the conductive paste layer (114) may be placed in the central region of the body (110), and the first connecting member (112) may be placed in the corner regions on both sides of the body (110).

[0099] FIG. 7a is stress distribution data in a heat dissipation block (10M) of the comparative technology, and FIG. 7b is stress distribution data in a strain control device (101) according to the embodiment.

[0100] Referring to FIG. 7a, in a heat dissipation block (10M) of a comparative technology using a metal TIM (Thermal Interface material), when the temperature of an electronic device adjacent to the heat dissipation block increases rapidly, a maximum strain occurs in the first edge region (ER1) of the TIM (30M3) or the second edge region (ER2) of the second metal adhesive layer (30M2) due to the difference in the coefficient of thermal expansion (CTE) between the TIM (30M3) and the Cu heat dissipation body (not shown). As a result, cracks or voids occur in the first edge region (ER1) or the second edge region (ER2) of the TIM (30M3), causing delamination.

[0102] On the other hand, referring to FIG. 7b, the strain control device (101) of the embodiment includes a conductive paste layer (114) disposed in a first region of the body (110) and a first connecting member (112) disposed in a second region outside the first region, thereby confirming that the maximum strain of the first to fourth edge regions (ER1, ER2, ER3, ER4) is reduced by about 50% to 60% compared to the comparative technology under operating conditions equivalent to the comparative technology. As a result, the problem of delamination caused by cracks or voids in the edge regions is prevented, and the bonding reliability is significantly improved.

[0103] For example, the strain control device (101) of the embodiment may have a first connecting member (112) containing a conductive ball placed in an outer area or corner area where maximum strain is concentrated, and a conductive paste layer (114) placed in a central area.

[0104] Accordingly, the spaced arrangement of connecting members disperses thermal expansion stress caused by CTE differences at the bonding interface and enhances compliance against local expansion and contraction compared to full-surface TIM bonding, thereby preventing the occurrence of voids or cracks.

[0105] For example, when the first connecting member (112) of the strain control device (101) is a solder ball, stress distribution is possible by the spacing between the balls, and by inducing the thermal expansion stress caused by heat generated from the first semiconductor device (211) into a multi-point distribution path, the prevention of thinning, heat dissipation efficiency, and bonding reliability are improved.

[0106] In addition, according to the embodiment, the conductive paste layer (114) placed in the second region enhances upward heat flow and suppresses lateral heat flow, thereby having a technical effect of increasing thermal conductivity by about 400 to 500% compared to the comparative technology.

[0107] Next, FIG. 6 is a second example of the bottom surface of the first strain control device (101) shown in FIG. 4.

[0108] Referring to FIG. 6, in the strain control device (101) of the embodiment, the conductive paste layer (114) may include a plurality of spaced conductive paste layers to relieve strain caused by thermal expansion.

[0109] For example, the conductive paste layer (114) may include a first conductive paste layer (114a) disposed in the central region of the body (110), and a second conductive paste layer (114b) or a third conductive paste layer (114c) disposed in the outer region spaced apart horizontally from the first conductive paste layer (114).

[0110] The strain control device (101) of the embodiment may include a plurality of first connecting members (112) disposed in the corner area of ​​the body (110).

[0111] In the embodiment, the first connecting member (112) placed in the corner area may be spaced apart in the horizontal direction and placed in a vertically overlapping manner with the second conductive paste layer (114b) or the third conductive paste layer (114c) placed in the outer area.

[0112] Additionally, the conductive paste layer (114) may include a third conductive paste layer (114c) or a fifth conductive paste layer (114e) disposed in an outer region spaced apart in a vertical direction from the first conductive paste layer (114).

[0113] In the embodiment, the first connecting member (112) placed in the corner area may be placed vertically overlapping with the third conductive paste layer (114c) or the fifth conductive paste layer (114e) placed in the outer area, spaced apart in the vertical direction.

[0114] Therefore, through the combination of the conductive paste layer (114) and the connecting member (112), a technical effect of dispersing and alleviating interfacial strain due to thermal expansion can be obtained.

[0116] Referring again to FIG. 3a, the upper portion of the second semiconductor device (212) and the strain control device (101) can be bonded to a heat dissipation device (230) via a second adhesive layer (216). The second adhesive layer (216) may be a metal adhesive layer containing a metal material, but is not limited thereto. For example, the second adhesive layer (216) may include a Sn alloy adhesive layer, an In alloy adhesive layer, an Al alloy adhesive layer, etc., but is not limited thereto.

[0117] Referring to FIG. 3a and FIG. 4, the first strain control device (101) may include a heat flow control layer (150) disposed on the side of the body (110).

[0118] Specifically, referring to FIG. 4, the heat flow control layer (150) may include a single or multiple heat flow control layers on one side of the body (110) in a direction adjacent to the second semiconductor device (212).

[0119] For example, the heat flow control layer (150) may include a first heat flow control layer (151) on one side of the body (110) in a direction adjacent to the second semiconductor device (212).

[0120] Additionally, the heat flow control layer (150) may further include a second heat flow control layer (152) disposed on the first heat flow control layer (151).

[0121] The thermal conductivity of the above heat flow control layer (150) may be lower than the thermal conductivity of the above body (110).

[0122] The embodiment may include a first heat flow control layer (151) and a second heat flow control layer (152) sequentially disposed on one side of the body (110), and the thermal conductivity of the second heat flow control layer (152) may be lower than the thermal conductivity of the first heat flow control layer (151), but is not limited thereto.

[0123] For example, the body (110) may include a Cu material, and the heat flow control layer (150) may include a Ni material.

[0124] The thermal conductivity of the body (110) made of Cu material may be approximately 401 W / (m·K), and the thermal conductivity of the heat flow control layer made of Ni material may be approximately 90.9 W / (m·K).

[0125] For example, the first heat flow control layer (151) may include a Ni plating layer, and the second heat flow control layer (152) may include a gold (Au) plating layer or a palladium (Pd) plating layer, but is not limited thereto. For example, the second heat flow control layer (152) may include an ENIG layer (Electroless Nickel Immersion Gold layer) or an ENEPIG layer (Electroless Nickel Electroless Palladium Immersion Gold layer) or an insulating coating material, but is not limited thereto. In the embodiment, the thermal conductivity of the heat flow control layer made of Au material may be about 318 W / (m·K), and the thermal conductivity of the heat flow control layer made of Pa material may be about 71 W / (m·K).

[0126] In addition, for example, the first heat flow control layer (151) may include an ENIG layer or an ENEPIG layer, and the second heat flow control layer (152) may include a Ni plating layer.

[0128] Accordingly, according to the embodiment, a heat flow control layer (150) with lower thermal conductivity can be provided on one side of the body (110) in a direction adjacent to the second semiconductor element (212), and there is a technical effect of reducing damage to the second semiconductor element (212) by increasing the flow of heat generated from the first semiconductor element (211) in the upward direction, which is the location of the heat dissipation device (230), and reducing the flow in the lateral direction.

[0129] In addition, in the embodiment, the body (110) may include Cu of rolled copper material. In the embodiment, since the body (110) is equipped with rolled copper material, the purity is higher compared to electrolytic copper material, resulting in higher thermal conductivity and improved heat dissipation efficiency. Additionally, rolled copper has a high density and high rigidity, which has the advantage of excellent rigidity design characteristics.

[0130] In addition, in the first strain control device (101) of the embodiment, one side of the body (110) may include an inclined surface (110S). The inclined surface (110S) of one side of the body (110) may be inclined such that the distance from the second semiconductor element (212) increases as it moves upward, and accordingly, there is an effect of causing less damage to the second semiconductor element (212) when heat generated from the first semiconductor element (211) flows to the heat dissipation device (230).

[0132] In addition, the center of the body (110) in the first strain control device (101) may have a first width (W1), and the upper side of the body (110) may have a second width (W2) smaller than the first width (W1).

[0133] For example, according to an embodiment, by controlling the first width (W1) on the lower side of the body (110) to be larger than the second width (W2) on the upper side, the contact area with the first semiconductor element (211) is expanded so that heat generated from the first semiconductor element (211) can efficiently move toward the heat dissipation device (230) in the upward direction, while having the effect of causing less heat damage to the second semiconductor element (212).

[0134] Additionally, the first strain control device (101) may have a lower protective layer (120) disposed on the lower part of the body (110), and may include a conductive paste layer (114) in the first region and a plurality of spaced-apart first connecting members (112) in the second region. The lower protective layer (120) may be a solder resist, but is not limited thereto.

[0136] Referring again to FIG. 3b, according to the embodiment, the problem of reduced reliability caused by damage to the second semiconductor device (212), such as HBM, during the process in which heat generated from the first semiconductor device (211), such as a logic chip, is transferred to a heat sink or vapor chamber, can be solved by controlling the flow of heat.

[0137] For example, according to an embodiment, by means of a first strain control device (101) arranged to overlap with the first semiconductor device (211) and the upper and lower sides, the first direction heat flow (F1) in the upper direction is maximized, and the second direction heat flow (F2) in the direction of the second semiconductor device (212), such as an HBM, in the side direction is minimized by a heat flow control layer (150), thereby minimizing thermal damage to the second semiconductor device (212), such as a memory device, and thus improving reliability, there is a technical effect.

[0138] For example, according to an embodiment, a heat flow control layer (150) with lower thermal conductivity may be provided on one side of the body (110) in a direction adjacent to the second semiconductor element (212), and accordingly, the heat flow generated from the first semiconductor element (211) is maximized in the first direction heat flow (F1) in the upper direction, which is the location of the heat dissipation device (230), and the heat flow (F2) in the second direction in the lateral direction is reduced, thereby providing a technical effect of reducing damage to the second semiconductor element (212).

[0139] In addition, by providing a composite layer of a plurality of heat flow control layers, such as a first heat flow control layer (151) and a second heat flow control layer (152), in which the heat flow control layer (150) has a lower thermal conductivity than the material of the body (110), the second heat flow (F2) in the side direction can be further reduced, and accordingly, the first heat flow (F1) in the upper direction can be maximized while minimizing damage to the second semiconductor device (212), thus providing a technical effect.

[0141] In addition, according to an embodiment, one side of the body (110) in the first strain control device (101) is configured to include an inclined surface (110S), and the second width (W2) of the upper side of the body (110) is configured to be smaller than the first width (W1) of the center, thereby increasing the distance from the second semiconductor device (212), so that the second direction heat flow (F2) in the direction of the second semiconductor device (212) can be minimized, and thereby there is a technical effect of minimizing thermal damage to the second semiconductor device (212), such as a memory device, and improving reliability.

[0142] In addition, according to an embodiment, the first strain control device (101) includes a plurality of spaced-apart first connection members (112) in the form of solder balls at the bottom of the body (110), thereby dispersing thermal expansion stress caused by heat generated from the first semiconductor device (211). Accordingly, the occurrence of delamination due to cracks or voids that may occur in the connection member made of Metal TIM material can be prevented, thereby improving heat dissipation efficiency and bonding reliability at the bonding portion.

[0143] In addition, according to the strain control device (101) of the embodiment, by placing a first connecting member (112) including a conductive ball in an outer area or corner area considering the maximum strain generation area and placing a conductive paste layer (114) in a central area, the first connecting member (112) disperses the thermal expansion stress caused by heat generated from the first semiconductor device (211), thereby preventing peeling caused by cracks or voids and improving heat dissipation efficiency and bonding reliability in the bonding part. In addition, according to the embodiment, there is a composite technical effect in which the thermal conductivity increases by about 400 to 500% compared to the comparative technology by the conductive paste layer (114) placed in a second area where relatively less strain occurs.

[0145] Next, FIG. 8 is a cross-sectional view of a second strain control device (102) according to an embodiment.

[0146] The second strain control device (102) may adopt the technical features of the first strain control device (101) described above, and the following description will focus on the main features of the second strain control device (102).

[0147] According to internal research, when forming a conductive paste layer (114) on the body (110), a problem was found in that the thickness of the conductive paste layer (114) was not uniform compared to the thickness of the first connecting member (112).

[0148] For example, the problem of non-uniformity relative to the thickness of the first connecting member (112) was studied as the conductive paste layer (114) clumps together due to surface tension in the liquid state.

[0149] According to the second strain control device (102) of the embodiment, the first roughness (110R1) of the first region where the conductive paste layer (114) is formed is controlled to be greater than the second roughness (110R2) of the second region where the first connecting member (112) is placed, thereby minimizing the clumping phenomenon of the conductive paste layer (114) and thus having the technical effect of uniformly controlling the thickness of the conductive paste layer (114).

[0150] For example, the first roughness (110R1) can be formed to be greater than the second roughness (110R2) in the second region by etching or plasma treatment in the first region where the conductive paste layer (114) is formed, but is not limited thereto.

[0151] Next, FIG. 9 is a cross-sectional view of a third strain control device (103) according to an embodiment.

[0152] The third strain control device (103) may adopt the technical features of the first strain control device (101) or the second strain control device (102) described above, and the following description will focus on the main features of the third strain control device (103).

[0153] The third strain control device (103) of the embodiment may include an uneven surface (110R) on the upper surface of the body (110) compared to the first strain control device (101).

[0154] In the third strain control device (103) of the embodiment, the roughness of the upper surface unevenness (110R) of the body (110) may be greater than the roughness of the inclined surface (110S) of one side of the body (110), but is not limited thereto.

[0155] Accordingly, by providing an uneven surface (110R) on the upper surface of the body (110) of the third strain control device (103), the adhesion between the third strain control device (103) and the heat dissipation device (230), such as a vapor chamber, is improved and the adhesion area is increased, thereby reducing the possibility of peeling and improving bonding reliability, and there is a technical effect of maximizing heat dissipation efficiency toward the first direction heat flow (F1) on the upper side.

[0157] Next, FIG. 10a is a bottom view example of the fourth strain control device (104), and FIG. 10b is a cross-sectional view along the line A2-A2' of the fourth strain control device (104) shown in FIG. 10a.

[0158] The fourth strain control device (104) may adopt the technical features of the first to third strain control devices (101, 102, 103) described above, and the following description will focus on the main features of the fourth strain control device (104).

[0160] The fourth strain control device (104) may include a body protrusion (110P) in a first region of the body (110) and a first conductive connecting member (112) disposed in a second region outside the first region. A plurality of body protrusions (110P) may be spaced apart and disposed on the body (110), but are not limited thereto.

[0161] According to the fourth strain control device (104) of the embodiment, a first connecting member (112) including a conductive ball is placed in an outer area or a corner area considering the maximum strain generation area, and a body protrusion (110P) is placed in a central area. Accordingly, heat dissipation efficiency can be further improved by the body protrusion (110P) in the central area, and thermal expansion stress can be dispersed by the first connecting member (112) placed in the outer area, thereby improving heat dissipation efficiency and bonding reliability.

[0163] Next, FIG. 11a is a bottom view example of the fifth strain control device (105), and FIG. 11b is a cross-sectional view along the line A3-A3' of the fifth strain control device (105) shown in FIG. 11a.

[0164] The fifth strain control device (105) may adopt the technical features of the first to fourth strain control devices (101, 102, 103, 104) described above, and the following description will focus on the main features of the fifth strain control device (105).

[0165] The fifth strain control device (105) may include an exposed portion (110B) in a first region of the body (110) and a first conductive connecting member (112) disposed in a second region outside the first region. A plurality of exposed portions (110B) may be spaced apart and disposed in the body (110), but are not limited thereto.

[0166] According to the fifth strain control device (105) of the embodiment, a first connecting member (112) including a conductive ball is placed in an outer area or corner area considering the maximum strain generation area, and an exposed portion (110B) is placed in a central area, etc. Accordingly, the thermal expansion stress is dispersed by the first connecting member (112) placed in the outer area, and at the same time, the stress due to bending of thermal expansion is further dispersed by the exposed portion (110B), thereby improving heat dissipation efficiency and bonding reliability.

[0168] Next, FIG. 12a is a cross-sectional view of a sixth strain control device (106) according to an embodiment, FIG. 12b is a cross-sectional view of a first-second connecting member (112B) in the sixth strain control device (106), and FIG. 12c is a cross-sectional view of a first-third connecting member (112C) in the sixth strain control device (106).

[0169] The sixth strain control device (106) may adopt the technical features of the first to fifth strain control devices (101, 102, 103, 104, 105) described above, and the following description will focus on the main features of the sixth strain control device (106).

[0170] First, referring to FIG. 12b, the first-second connecting member (112B) in the sixth strain control device (106) may include a Cu ball structure. For example, the first-second connecting member (112B) may include a metal ball (112B1) and a solder cover layer (112B2) surrounding the metal ball (112B1). The metal ball (112B1) may be a Cu ball, but is not limited thereto.

[0171] According to the 6th strain control device (106), the 1st-2nd connecting member (112B) includes a metal ball such as a Cu ball, thereby providing a technical effect of improved thermal conductivity and improved structural reliability.

[0172] Next, referring to FIG. 12c, the first-third connecting member (112C) in the sixth strain control device (106) may include a Cu Post structure. For example, the first-third connecting member (112C) may include a metal pillar (112C1) and a second solder cover layer (112C2) surrounding the metal pillar (112C1). The metal pillar (112C1) may be a Cu Post, but is not limited thereto.

[0173] According to the 6th strain control device (106), the height of the 1st-3rd connecting member (112C) can be controlled by including a metal pillar such as a Cu post, and there is a technical effect of improving thermal conductivity and structural reliability.

[0175] Next, FIGS. 13a to 13c are exemplary diagrams of semiconductor packages (210A3, 210A4, 210A5) according to the third to fifth embodiments.

[0176] The semiconductor packages (210A3, 210A4, 210A5) according to the third to fifth embodiments may adopt the technical features of the first semiconductor packages (210A, 210B) of the first to second embodiments described above, and the features of the semiconductor packages (210A3, 210A4, 210A5) according to the third to fifth embodiments will be described below.

[0177] Referring to FIG. 13a, semiconductor packages (210A3) according to the third embodiment may include a plurality of first semiconductor elements. For example, the semiconductor package (210A3) according to the third embodiment may include a first semiconductor element (211) disposed on a first package substrate (210a). Additionally, the semiconductor package (210A3) according to the third embodiment may include a second semiconductor element (212) disposed spaced apart from the first semiconductor element (211) and a strain control device (100).

[0178] The first semiconductor device (211) and the second semiconductor device (212) may include active and / or passive devices. For example, the active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions or more devices are integrated into a single chip. Additionally, the first semiconductor device (211) may be a logic chip such as an AP or SOC, and the second semiconductor device (212) may be a memory chip, but is not limited thereto.

[0179] In the third embodiment, the size of the first semiconductor device (211) may be larger than the size of the second semiconductor device (212), but is not limited thereto.

[0180] In the third embodiment, the strain control device (100) can control the flow of heat generated from the first semiconductor device (211) so that the heat generated from the first semiconductor device (211) does not flow toward the second semiconductor device (212) by rapidly and efficiently dissipating heat generated from the first semiconductor device (211) and controlling the flow of heat generated from the first semiconductor device (211) toward the strain control device (100), and the embodiment can arrange the heat flow control device (100) according to the main heat source that generates heat.

[0182] Next, referring to FIG. 13b, semiconductor packages (210A4) according to the fourth embodiment may include a plurality of second semiconductor elements. For example, the semiconductor package (210A4) according to the fourth embodiment may include a first-1 semiconductor element (211a) disposed on a first package substrate (210a) and a first-2 semiconductor element (211b). Additionally, the semiconductor package (210A4) according to the fourth embodiment may include a second-1 semiconductor element (212a), a second-2 semiconductor element (212b), and a strain control device (100) disposed spaced apart on the first-1 semiconductor element (211a) and the first-2 semiconductor element (211b). The strain control device (100) may be disposed between the second-1 semiconductor element (212a) and the second-2 semiconductor element (212b), but is not limited thereto.

[0184] Next, referring to FIG. 13c, semiconductor packages (210A5) according to the fifth embodiment may include a plurality of strain control devices (100). For example, the semiconductor package (210A5) according to the fifth embodiment may include a first-1 semiconductor element (211a) and a first-2 semiconductor element (211b) disposed on a first package substrate (210a). Additionally, the semiconductor package (210A5) according to the fifth embodiment may include a second-1 semiconductor element (212a), a second-2 semiconductor element (212b), and a strain control device (100) disposed spaced apart on the first-1 semiconductor element (211a) and the first-2 semiconductor element (211b). The strain control device (100) may include a first-1 strain control device (100a) and a first-2 strain control device (100b) disposed between a second-1 semiconductor device (212a) and a second-2 semiconductor device (212b), but is not limited thereto.

[0186] Although the present invention has been described above with reference to embodiments thereof, those skilled in the art will readily understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as described in the following claims.

Claims

Claim 1 A strain control device for a semiconductor package comprising: a body; a plurality of spaced first connection members disposed in a first lower region of the body; and a conductive paste layer disposed in a second lower region of the body. Claim 2 A strain control device for a semiconductor package according to claim 1, wherein the conductive paste layer comprises one or more of a solder paste layer, a metal paste, or a Metal TIM, and the first connecting member comprises a conductive ball. Claim 3 A strain control device for a semiconductor package according to claim 1, wherein the first connecting member is disposed in an outer region of the first region of the body. Claim 4 A strain control device for a semiconductor package according to paragraph 3, wherein the conductive paste layer is disposed in the central region of the body, and the first connecting member is disposed in the outer regions on both sides of the body. Claim 5 A strain control device for a semiconductor package according to claim 1, wherein the conductive paste layer comprises a plurality of spaced-apart conductive paste layers. Claim 6 A strain control device for a semiconductor package according to claim 5, wherein the conductive paste layer comprises a first conductive paste layer disposed in a central region of the body and a second conductive paste layer or a third conductive paste layer disposed in an outer region spaced apart horizontally from the first conductive paste layer. Claim 7 A strain control device for a semiconductor package according to claim 6, wherein the first connecting member comprises a plurality of first connecting members disposed in the corner region of the body, and at least one of the first connecting members is disposed in a vertically overlapping manner with the second conductive paste layer or the third conductive paste layer disposed in the outer region, spaced apart in the horizontal direction. Claim 8 A strain control device for a semiconductor package according to claim 7, wherein the conductive paste layer comprises a fourth conductive paste layer or a fifth conductive paste layer disposed in an outer region spaced vertically apart from the first conductive paste layer, and the first connecting member disposed in the corner region is disposed in an overlapping vertical direction with the third conductive paste layer or the fourth conductive paste layer disposed in an outer region spaced vertically apart. Claim 9 A strain control device for a semiconductor package according to claim 1, wherein the first roughness of the first region in which the conductive paste layer is formed is greater than the second roughness in the second region. Claim 10 A strain control device for a semiconductor package according to claim 1, wherein the body includes a body protrusion. Claim 11 A strain control device for a semiconductor package, wherein the body includes an exposed portion in claim 1. Claim 12 A strain control device for a semiconductor package according to claim 1, wherein the first connecting member comprises a metal ball and a solder cover layer surrounding the metal ball. Claim 13 A strain control device for a semiconductor package according to claim 1, wherein the first connecting member comprises a metal pillar and a second solder cover layer surrounding the metal pillar. Claim 14 A strain control device for a semiconductor package according to claim 1, further comprising a heat flow control layer disposed on the side of the body, wherein the heat flow control layer comprises a plating layer. Claim 15 A semiconductor package comprising: a first semiconductor device disposed on a first package substrate; a strain control device disposed on the first semiconductor device; and a second semiconductor device disposed spaced apart from the side of the first strain control device, wherein the strain control device comprises a strain control device of a semiconductor package according to claims 1 to 14. Claim 16 A semiconductor module including the semiconductor package of claim 15.

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