Memory devices with selectively coupled write assist circuit and methods for operating the same

Abstract

A memory circuit comprises: a first memory array including a plurality of first memory cells, wherein each of the plurality of first memory cells is configured to operate with a first supply voltage; a second memory array including a plurality of second memory cells, wherein each of the plurality of second memory cells is configured to operate with a second supply voltage, and the first supply voltage and the second supply voltage are different from each other; and a driver operably coupled to the plurality of first memory cells and the plurality of second memory cells, respectively, through a first access line and a second access line. The driver is configured to selectively provide a negative voltage on one of the first access line or the second access line based on an address signal.

Description

Technology Field

[0001] Cross-reference of related applications

[0002] This application claims priority and the benefit of U.S. Provisional Application No. 63 / 755,578 filed February 7, 2025, the full text of which is incorporated herein by reference for all purposes. Background Technology

[0003] Static Random Access Memory (SRAM) is a type of semiconductor memory used, for example, in computing applications that require high-speed data access. For instance, cache memory applications use SRAMs to store frequently accessed data, such as data accessed by a central processing unit.

[0004] The cell structure and architecture of SRAM enable high-speed data access. An SRAM cell includes, for example, a bistable flip-flop structure comprising four to eight transistors. An SRAM architecture may include one or more arrays of memory cells and support circuitry. Each SRAM array is arranged in rows and columns referred to as "word lines" and "bit lines," respectively. Support circuitry includes address and driver circuits for accessing each of the SRAM cells via the word lines and bit lines for various SRAM operations. Brief explanation of the drawing

[0005] The embodiments of the present disclosure are best understood from the description when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the art, the various features are not drawn to actual scale. In fact, the dimensions of the various features may be increased or decreased at will to clarify the discussion. FIG. 1 illustrates a block diagram of a memory device including a recording auxiliary circuit according to some embodiments. FIG. 2 illustrates a schematic diagram of one of the memory cells of the memory device of FIG. 1 according to some embodiments. FIG. 3 illustrates an exemplary schematic diagram of a portion of the memory device of FIG. 1 according to some embodiments. FIG. 4 illustrates a circuit diagram of a part of the memory device of FIG. 1 implemented based on the schematic diagram of FIG. 3 according to some embodiments. FIG. 5 illustrates another exemplary schematic diagram of a part of the memory device of FIG. 1 according to some embodiments. FIG. 6 illustrates another exemplary schematic diagram of a part of the memory device of FIG. 1 according to some embodiments. FIG. 7 illustrates exemplary waveforms of various signals while operating the memory device of FIG. 1 according to some embodiments of the present disclosure. FIG. 8 illustrates an exemplary schematic diagram of a recording auxiliary circuit of a memory device of FIG. 1 according to some embodiments of the present disclosure. FIG. 9 illustrates a cross-sectional view of an exemplary semiconductor device that may be part of an embodiment of the memory device of FIG. 1 according to some embodiments. FIG. 10 illustrates an exemplary flowchart of a method for fabricating a part of the memory device of FIG. 1 according to some embodiments. FIG. 11 illustrates an exemplary flowchart of a method for operating the memory device of FIG. 1 according to some embodiments. Specific details for implementing the invention

[0006] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. To simplify the disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Additionally, the disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplification and clarification, and such repetition itself does not affect the relationship between the various embodiments and / or configurations discussed.

[0007] Additionally, to describe the relationship between one element or feature and another element(s) or feature(s) as illustrated in the drawings, spatially relative terms such as "beneath," "below," "lower," "above," "upper," "top," and "bottom" may be used herein for convenience of explanation. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientations depicted in the drawings. The device may be oriented differently (rotated 90 degrees or in other orientations), and accordingly, the spatially relative descriptors used herein may be interpreted in the same way.

[0008] The following disclosure describes various aspects of memory devices or circuits, e.g., static random access memory (SRAM) devices. For example, the present disclosure describes different embodiments related to SRAM memory write operations. For convenience of explanation and to facilitate the description of different embodiments, specific SRAM circuit elements and control logic are disclosed. It should be understood that SRAM devices also include other circuit elements and control logic. These other circuit elements and control logic are within the spirit and scope of the present disclosure.

[0009] Typically, an SRAM device comprises an array of individual SRAM cells. Each SRAM cell can store a binary voltage value, which represents a logic data bit (e.g., "0" or "1"). One conventional configuration for an SRAM cell includes a pair of devices, such as cross-coupled inverters. According to complementary metal oxide semiconductor (CMOS) technology, each inverter typically includes a pull-up PFET (p-channel) transistor connected to a complementary pull-down NFET (n-channel) transistor. Inverters connected in a cross-coupled configuration act as latches to store data bits as long as power is supplied to the memory array. In a conventional 6-transistor (6T) cell, a pair of access transistors or pass gates (when activated by a word line) selectively couple the inverters to a pair of complementary bit lines. Other SRAM cell designs may include a different number of transistors, e.g., 4T, 8T, etc.

[0010] The design of SRAM cells has traditionally involved trade-offs between the read and write functions of the memory cell to maintain cell stability, read performance, and write performance. The transistors forming the cross-coupled latches tend to be weak enough to be overdriven during write operations, while also being strong enough to maintain data values ​​when driving bit lines during read operations. The access transistors connecting the cross-coupled cell nodes to the true and complement bit lines affect both the stability and performance of the cell. In 1-port SRAM cells, a single pair of access transistors is typically used for both read and write access to the cell. Gates are driven by digital values ​​to switch the transistors between the on and off states. Optimization of access for write operations affects the on-resistance (R) of the device. on ) will lead to a reduction. On the other hand, the optimization of the access transistor for the read operation isolates the cell from the bit line capacitance and R to prevent cell disturbance. on Induces an increase in.

[0011] One proposed approach to improve the write performance of SRAM devices is to use so-called "negative boosting" techniques to discharge bit lines to a voltage level below a nominal low supply rail value (e.g., ground). In other words, the corresponding bit line of an SRAM cell may exhibit a negative voltage when written. This bit line is typically discharged to a negative voltage through a write auxiliary circuit that typically includes a capacitor (sometimes referred to as a boost capacitor). In this way, the pass gates of the SRAM cell coupled to the discharged bit line see a resulting increase in both the gate-source voltage and the drain-source voltage. This negative boosting can enable an increase in margin of more than 3σ (in terms of expected device failure) compared to more conventional write techniques where the bit line is simply discharged to a value of the nominal low voltage rail (e.g., ground).

[0012] Despite the advantages of negative boosting, existing SRAM devices with negative boosting may still not be entirely satisfactory in certain aspects. For example, as transistor sizes continue to shrink progressively in advanced technology nodes, multiple memory banks are typically coupled to a write-auxiliary circuit, where some of the memory banks may operate at a relatively high supply voltage, while others may operate at a relatively low supply voltage in relation to power consumption. Generally, for example, memory banks selected to operate at a high supply voltage are configured for high-speed read / write operations, and for example, memory banks selected to operate at a low supply voltage are configured for data retention.

[0013] Under a configuration where the first memory bank (operating at a low supply voltage) is physically located closer to the write-assist circuit than the second memory bank (operating at a high supply voltage), to efficiently write the first memory bank to a negative bit line, the write-assist circuit typically provides a "deeper" negative voltage on the bit line to ensure that the first memory bank receives a sufficiently negative voltage on the bit line. As a non-limiting example where the high supply voltage and low supply voltage are approximately 1.1 V and 0.5 V, respectively, the write-assist circuit may apply a negative voltage of approximately 250 mV on the discharge bit line connected to both the distant first memory bank and the nearby second memory bank. Thus, the first memory bank can see a negative voltage of approximately 50 mV on its bit line, which allows the second memory bank to see a negative voltage close to 250 mV on its bit line. This is the V of the access transistors gs That V th Because it is too close to, the access transistors of the second memory bank are unintentionally turned on. As a result, the second memory bank may lose its ability to retain stored data to the disadvantage.

[0014] The present disclosure provides various embodiments of a memory circuit comprising a (record) driver capable of providing a negative voltage on a bit line, sometimes referred to as a negative bit line voltage. The memory circuit may comprise an SRAM device or circuit. The negative bit line voltage may be optionally coupled (or applied) to a first bit line of a first memory bank of the disclosed memory circuit selected to be an active memory bank, while the negative bit line voltage may be optionally isolated from a second bit line of a second memory bank of the disclosed memory circuit selected to be an inactive memory bank. For example, a memory circuit as disclosed herein may comprise a logic gate, at least a first multiplexer (e.g., a first transistor), and at least a second multiplexer (e.g., a second transistor). The first multiplexer is coupled between the record driver and the first bit line, and the second multiplexer is coupled between the record driver and the second bit line. Based on the received address signal, the logic gate may enable one of the first or second multiplexer while disabling the other of the first or second multiplexer. In some embodiments, the active memory bank may be configured to operate for high-speed read / write operations or at a relatively high supply voltage, and the inactive memory bank may be configured to operate for data retention or at a relatively low supply voltage. In some embodiments, the inactive memory bank (operating at a lower supply voltage) may be located physically closer to the write driver than the active memory bank (operating at a higher supply voltage). Under this arrangement, a first bit line coupling the write driver to the active memory bank may pass over the inactive memory bank by physically configuring the first bit line having a plurality of metal tracks within different metallization layers.

[0015] FIG. 1 illustrates a block diagram of an exemplary static random access memory (SRAM) device / circuit (100) having a write driver (110) including a write assist circuit according to various embodiments of the present disclosure. The SRAM device (100) may further include a row decoder (120), a word line driver (130), a bank decoder (140), a bank multiplexer circuit (150), and a memory array (180). The block diagram of FIG. 1 is provided for exemplary purposes and is simplified, and accordingly, the SRAM device (100) may include any of various other suitable components while remaining within the scope of the present disclosure.

[0016] The memory array (180) includes a plurality of memory cells (190). The memory cells (190) may be arranged as a plurality of memory banks, some of which may be configured as active memory banks and some of which may be configured as inactive memory banks, which will be discussed in more detail below. In the example illustrated in FIG. 1, the memory array (180) comprises "M" rows (e.g., ROW1 to ROW M ) and "N" columns (COL1 to COL N It has ). As a non-limiting example, M may be equal to 256, and thus, the memory array (180) may include a first memory bank having 128 rows and a second memory bank having 128 rows. Each of the memory cells (190) may be located at the intersection of a corresponding row among the rows and a corresponding column among the columns. Thus, notation "190 11 " refers to one of the memory cells (190) located in ROW1 and COL1, and is denoted as "190" MN "is ROW M and COL N It refers to another one of the memory cells (190) located in the area.

[0017] According to various embodiments of the present disclosure, based on an address (ADDR) signal, a bank decoder (140) may provide a bank select (SEL) signal to a bank multiplexer circuit (150). Using the SEL signal, the bank multiplexer circuit (150) may select at least one of the memory banks (of the memory array (180)) as an active memory bank and at least one of the memory banks (of the memory array (180)) as an inactive memory bank. The active memory bank may be powered by a relatively high supply voltage for high-speed write / read operations, and the inactive memory bank may be powered by a relatively low supply voltage to maintain previously written data. The memory cells (190) of the active memory bank selected by the bank multiplexer circuit (150) may be accessed (e.g., written) by a write driver (110). The recording auxiliary circuit of the recording driver (110) can provide a negative bit line voltage and apply it to one or more bit line pairs of the active memory bank. The bit line pairs are typically referred to as BL and BLB, where the notation "BL" refers to a bit line and the notation "BLB" refers to the complement of BL, which is sometimes referred to as a bit line bar.

[0018] On the other hand, memory cells (190) of an inactive memory bank selected by the bank multiplexer circuit (150) can be operablely isolated from the write driver (110) so that the bit line pairs of the inactive memory bank can be floated (e.g., after being pre-charged with a corresponding supply voltage). Before, simultaneously with, or after selecting an active memory bank, each of the memory cells (190) can be accessed using an ADDR signal, for example, for a read or write operation. Based on the ADDR signal, the row decoder (120) [connects] the word line driver (130) (e.g., a plurality of word line drivers (1301–130)M A row of memory cells in an active memory bank (e.g., ROW1 to ROW2) to be accessed via the corresponding word line driver) M You can choose one of them.

[0019] The memory cell (190) may have any of the various circuit topologies. For example, the memory cell (190) may have a "6T" circuit topology. FIG. 2 illustrates an exemplary 6T circuit topology for the memory cell (190). The 6T circuit topology includes n-channel metal-oxide-semiconductor (NMOS) pass gate devices (220 and 230), NMOS pull-down devices (240 and 250), and p-channel metal-oxide-semiconductor (PMOS) pull-up devices (260 and 270). The voltage from the word line driver (130) controls (e.g., turn on / off) the NMOS devices (220 and 230) through the word line (WL) to transfer voltage from the bit line pair (BL and BLB) to the bistable flip-flop structure formed by the NMOS devices (240 and 250) and the PMOS devices (260 and 270). The NMOS device (240) and the PMOS device (260) form a first inverter, and the NMOS device (250) and the PMOS device (270) form a second inverter, and the first and second inverters are cross-coupled to form an operable flip-flop structure. The voltage applied to the bit line pair (BL and BLB) can be used for a write operation.

[0020] For example, when the voltage applied to the word line (WL) (or to the gate terminals of the NMOS pass gate devices (220 and 230)) is at a sufficient voltage level, the logic value of BL and the logic value of BLB can be transmitted to the bistable flip-flop structure. As a non-limiting example, when the NMOS pass gate devices (220 and 230) are turned on, a '1' or logic high value (e.g., power supply voltage (CVDD) such as 0.4 V, 0.5 V, 0.6 V, 0.7 V, 1.0 V, 1.1 V, 1.2 V, 1.8 V, 2.4 V, 3.3 V, 5 V, or any combination thereof) is provided to the bit line bar (BLB), and a '0' or logic low value (e.g., ground or 0 V) ​​is provided to the bit line (BL). In this case, the logic low value of BL and the logic high value of BLB can be transmitted to the internal nodes (X and Y) of the bistable flip-flop structure, respectively. As a result, these logic values ​​are written (or programmed) within the bistable flip-flop structure.

[0021] FIG. 3 illustrates an exemplary schematic diagram of a part of an SRAM device (100) (Fig. 1) according to some embodiments of the present disclosure, and FIG. 4 illustrates a circuit diagram constructed based on the schematic diagram of FIG. 3. In the examples of FIG. 3 and FIG. 4, two memory banks, for example, 180A and 180B, are included within the memory array (180), one of which may be selected as an active memory bank and the other of which may be selected as an inactive memory bank. For example, the memory array (180) may contain 256 rows (or 256 word lines), wherein a memory bank (180A) having 128 rows is selected as an active memory bank (e.g., operating at about 1.1 V CVDD), and a memory bank (180B) having 128 rows is selected as an inactive memory bank (e.g., operating at about 0.5 V CVDD).

[0022] In some embodiments, the write assist circuit of the write driver (110) may provide a vBL signal to the memory array (180). For example, the write driver (110) may optionally provide the vBL signal as a negative bit line voltage for an active memory bank (e.g., 180A) based on an ADDR signal. The write assist circuit of the write driver (110) may include one or more boost capacitors to provide this negative vBL signal, which will be discussed below in relation to FIG. 8. The negative vBL signal may be applied to at least one bit line (BL) (e.g., 340) coupled to a plurality of memory cells (190) of the active memory bank (180A) through the multiplexer (320) of the bank multiplexer circuit (150). The multiplexer (320) (e.g., implemented as an NMOS device) may be turned on by an SEL signal generated by the logic gate (310) of the bank decoder (140). For example, the logic gate (310) may include a NOR gate having a first input portion configured to receive an ADDR signal, a second input portion configured to receive a control (YMUXB) signal, and an output portion configured to generate an SEL signal by NORing the ADDR signal and the YMUXB signal. The multiplexer (320) has a gate terminal connected to the output portion of the logic gate (310), a first source / drain terminal connected to a record driver (110), and a second source / drain terminal connected to a bit line (BL) (340).

[0023] Although not illustrated, while a negative vBL signal is applied to the bit line (BL) (340), the corresponding bit line bar (BLB) of the same column may be floated (e.g., maintained at a pre-charged voltage level). This may apply when a logic low value and a logic high value are programmed within internal nodes X and Y, respectively (Fig. 2). In other cases where a logic high value and a logic low value are programmed within internal nodes X and Y, respectively, a negative vBL signal may be applied to the corresponding bit line (BLB), and the bit line BL (340) is floated.

[0024] At the same time as the recording driver (110) is coupled to the bit line (BL) (340) through the turned-on multiplexer (320), the negative vBL signal can be isolated from the bit line (BL) (e.g., 350) coupled to a plurality of memory cells (190) of the inactive memory bank (180B). The bit line (BL) (350) can be isolated from the driver (110) by turning off the multiplexer (330) of the bank multiplexer circuit (150). The multiplexer (330) (e.g., implemented as another NMOS device) can be turned off by an SEL signal. For example, the multiplexer (330) has a gate terminal connected to the output of the logic gate (310), a first source / drain terminal connected to the recording driver (110), and a second source / drain terminal connected to the bit line (BL) (350). Although not illustrated, the corresponding bit line bar (BLB) of the same column may also be isolated from the recording driver (110). In this way, the bit line pair (BL (350) and BLB) may be floated or maintained at a pre-charged voltage level.

[0025] In the exemplary example of FIG. 3, when the memory array (180) has 256 rows, the ADDR signal may be provided or input as 8 bits, e.g., ADDR[7:0]. One of these 8 bits may be used to identify whether the corresponding memory bank is configured as an active memory bank. For example, when a specific column of the memory array (180) is selected, the YMUXB signal may be provided as an inverse pulse (i.e., when a specific column is selected, the YMUXB signal is pulled down to logic 0). Additionally, when logic 0 is provided to ADDR[7] and logic 1 is provided to ADDR[6], the logic gate (310) may perform a NOR operation on the ADDR signal and the YMUXB signal to output a SEL signal containing a first bit of logic 1 and a second bit of logic 0. The first bit can be received by the gate terminal of the multiplexer (320), and the second bit can be received by the gate terminal of the multiplexer (330). Thus, the multiplexer (320) is turned on and the multiplexer (330) is turned off, thereby causing the recording driver (110) to be coupled to the bit line (BL) (340) and uncoupled from the bit line (BL) (350).

[0026] In some embodiments, the memory bank (180A) may be located physically further from the recording driver (110) than the memory bank (180B). As such, the bit line (BL) (340) may be formed across a plurality of metallization layers to pass over the memory bank (180A). As a non-limiting example, the memory cells of both memory banks (180A-B) may be formed along the main surface of the substrate and may sometimes be referred to as part of a front-end-of-line (FEOL) network. The bit line (BL) (350) may be formed based on at least one first metal track placed within a first metallization layer (e.g., M0 layer) among a plurality of metallization layers placed over the main substrate surface and may sometimes be referred to as part of a back-end-of-line (BEOL) network. The bit line (BL) (340) can be formed based on at least a second metal track disposed within a second metal layer (e.g., M2 layer) higher among a plurality of metal layers, a third metal track disposed within a first metal layer (M0 layer), and one or more via structures connecting the second metal track to the third metal track.

[0027] Next, referring to FIG. 4 (in conjunction with FIG. 3), two memory cells, e.g., 190A1, 190A2, 190B1, and 190B2, are exemplified within each of the memory banks (180A and 180B). Continuing the above example, where memory bank (180A) and memory bank (180B) are selected as the active bank and inactive bank, respectively, and a logic low value is applied to the bit line (BL) (350), a negative bit line voltage of approximately 100 mV may be applied to the bit line (350) (e.g., by the write driver (110)), while the BLB (340') and bit line pair (BL (350) and BLB (350')) (of the active memory bank (180A)) are floated (e.g., remain at a pre-charged voltage level of approximately 1.1 V). In this way, the memory cell (190A1) closer to the recording driver (110) can see the vBL signal present on the corresponding portion of the bit line (BL) (340) at about 100 mV, and the memory cell (190A2) further from the recording driver (110) can see the vBL signal present on the corresponding portion of the bit line (BL) (340) at about 50 mV (for example, due to IR drop and / or leakage of pass gate devices placed between the memory cell (190A2) and the recording driver (110).

[0028] If the corresponding portions of the bit line (340) each indicate a negative bit line voltage, the logic row value within the X node of each memory cell (190A1 and 190A2) can be programmed more efficiently. On the other hand, each memory cell (190B1 and 190B2) sees the corresponding portion of the bit line (BL) (350) maintained at about 1.1 V (pre-charged voltage level). Since the inactive memory bank (180B) is powered by a CVDD of about 0.5 V, the X of each memory cell (190B1 and 190B2) is latched at about 0.5 V. If a negative bit line voltage is not applied on the bit line (350), the memory cells (190B1 and 190B2) can accordingly safely retain the previously stored data.

[0029] FIG. 5 illustrates an exemplary schematic diagram of a portion of an SRAM device (100) (Fig. 1) according to some embodiments of the present disclosure. In the example of FIG. 5, three memory banks, e.g., 180A, 180B, and 180C, are included within the memory array (180), one of which may be selected as an active memory bank and the other two of which may each be selected as inactive memory banks. For example, the memory array (180) may contain 256 rows (or 256 word lines), wherein a memory bank (180A) having 128 rows is selected as an active memory bank (e.g., operating at about 1.1 V CVDD), and a memory bank (180B) having 64 rows and a memory bank (180C) having 64 rows are each selected as inactive memory banks (e.g., operating at about 0.5 V CVDD).

[0030] Similar to the schematic diagram of FIG. 3, the bank decoder (140) also includes a NOR gate (310) that NORs the received ADDR signal and the MUXB signal to provide an SEL signal to the bank multiplexer circuit (150). In FIG. 5, the bank multiplexer circuit (150) includes three multiplexers (510, 520, and 530) respectively coupled between the record driver (110) and the corresponding memory bank (or its bit line (BL)). Each of the multiplexers (510 to 530) may be implemented as an NMOS device, and its gate terminal is configured to receive an SEL signal. Additionally, the multiplexer (510) may have first and second source / drain terminals respectively connected to the record driver (110) and the bit line (BL) (540) of the memory bank (180A); The multiplexer (520) may have first and second source / drain terminals connected to the bit lines (BL) (550) of the recording driver (110) and the memory bank (180B), respectively; and the multiplexer (530) may have first and second source / drain terminals connected to the bit lines (BL) (550) of the recording driver (110) and the memory bank (180C), respectively.

[0031] In some embodiments, the memory bank (180A) may be located physically further from the recording driver (110) than the memory banks (180B and 180C), and the memory bank (180B) may be located physically further from the recording driver (110) than the memory bank (180C). As such, the bit line (BL) (540) may be formed across a plurality of metallized layers to pass over the memory banks (180B-C), and the bit line (BL) (550) may also be formed across a plurality of metallized layers to pass over the memory bank (180C).

[0032] As a non-limiting example, memory cells of all memory banks (180A-C) may be formed along the main surface of the substrate. A bit line (BL) (560) may be formed based on at least one first metal track disposed within a first metallization layer (e.g., M0 layer) among a plurality of metallization layers disposed on the main substrate surface. A bit line (BL) (550) may be formed based on at least a second metal track disposed within a higher second metallization layer (e.g., M2 layer) among the plurality of metallization layers, a third metal track disposed within the first metallization layer (M0 layer), and one or more via structures connecting the second metal track to the third metal track. The bit line (BL) (550) can be formed based on at least a fourth metal track disposed within a third metal layer (e.g., M4 layer) higher among the plurality of metal layers, a fifth metal track disposed within a first metal layer (M0 layer), and one or more via structures connecting the fourth metal track to the fifth metal track.

[0033] FIG. 6 illustrates an exemplary schematic diagram of a portion of an SRAM device (100) (Fig. 1) according to some embodiments of the present disclosure. In the example of FIG. 5, four memory banks, e.g., 180A, 180B, 180C, and 180D, are included within the memory array (180), one of which may be selected as an active memory bank and the other three of which may each be selected as inactive memory banks. For example, the memory array (180) may contain 256 rows (or 256 word lines), wherein a memory bank (180C) having 64 rows is selected as an active memory bank (e.g., operating at about 1.1 V CVDD), and memory banks (180A, 180B, and 180D) having 64 rows are each selected as inactive memory banks (e.g., operating at about 0.5 V CVDD).

[0034] Similar to the schematic diagram of FIG. 3, the bank decoder (140) also includes a NOR gate (310) that NORs the received ADDR signal and the MUXB signal to provide an SEL signal to the bank multiplexer circuit (150). In FIG. 6, the bank multiplexer circuit (150) includes four multiplexers (610, 620, 630, and 640) each coupled between the record driver (110) and the corresponding memory bank (or its bit line (BL)). Each of the multiplexers (610 to 640) may be implemented as an NMOS device, and its gate terminal is configured to receive an SEL signal. Additionally, the multiplexer (610) may have first and second source / drain terminals connected to the record driver (110) and the bit line (BL) (650) of the memory bank (180A), respectively; The multiplexer (620) may have first and second source / drain terminals connected to bit lines (BL) (660) of the recording driver (110) and memory bank (180B), respectively; the multiplexer (630) may have first and second source / drain terminals connected to bit lines (BL) (670) of the recording driver (110) and memory bank (180C), respectively; and the multiplexer (640) may have first and second source / drain terminals connected to bit lines (BL) (680) of the recording driver (110) and memory bank (180D), respectively.

[0035] In some embodiments, memory bank (180A) may be located physically further from the recording driver (110) than memory banks (180B-D), memory bank (180B) may be located physically further from the recording driver (110) than memory banks (180C-D), and memory bank (180C) may be located physically further from the recording driver (110) than memory bank (180D). Thus, bit line (BL) (650) may be formed across a plurality of metallized layers to pass over memory banks (180B-D), bit line (BL) (660) may also be formed across a plurality of metallized layers to pass over memory banks (180C-D), and bit line (BL) (670) may also be formed across a plurality of metallized layers to pass over memory bank (180D).

[0036] As a non-limiting example, memory cells of all memory banks (180A-D) may be formed along the main surface of the substrate. A bit line (BL) (680) may be formed based on at least one first metal track disposed within a first metallization layer (e.g., layer M0) among a plurality of metallization layers disposed on the main substrate surface. A bit line (BL) (670) may be formed based on at least a second metal track disposed within a higher second metallization layer (e.g., layer M2) among the plurality of metallization layers, a third metal track disposed within the first metallization layer (layer M0), and one or more via structures connecting the second metal track to the third metal track. A bit line (BL) (680) may be formed based on at least a fourth metal track disposed within a higher third metal layer (e.g., M4 layer) among a plurality of metal layers, a fifth metal track disposed within a first metal layer (M0 layer), and one or more via structures connecting the fourth metal track to the fifth metal track. A bit line (BL) (650) may be formed based on at least a sixth metal track disposed within a higher fourth metal layer (e.g., M6 layer) among a plurality of metal layers, a seventh metal track disposed within a first metal layer (M0 layer), and one or more via structures connecting the sixth metal track to the seventh metal track.

[0037] FIG. 7 illustrates exemplary waveforms of the aforementioned vBL signal and one bit of the ADDR signal, respectively, according to some embodiments of the present disclosure. The bit of the ADDR signal may be configured to indicate whether the corresponding memory bank is configured as an active memory bank (e.g., to be written). For example, when the bit of the ADDR signal is provided as a logic 1, the corresponding memory bank is configured as an inactive memory bank, so that vBL is provided at a pre-charged voltage level (e.g., about 1.1 V); and when the bit of the ADDR signal is provided as a logic 0, the corresponding memory bank is configured as an active memory bank, so that vBL is provided at a negative voltage level (e.g., about 100 mV).

[0038] FIG. 8 illustrates an exemplary circuit diagram of the aforementioned recording assist circuit (hereinafter, "recording assist circuit (800)") of a recording driver (110) according to some embodiments of the present disclosure. Generally, the recording assist circuit (800) may optionally provide a negative voltage to the vBL signal. The circuit diagram of FIG. 8 should be understood as simplified for exemplary purposes. Accordingly, the recording assist circuit (800) may include any of various other suitable components while remaining within the scope of the present disclosure.

[0039] As illustrated, the record auxiliary circuit (800) includes an NMOS device (810) (functioning as a switch) and a boost capacitor (820). The NMOS device (810) is coupled between ground and node A, and the boost capacitor (820) is coupled between node B, which is connected to the gate terminal of the NMOS device (810), and node A. A bit line boost enable control signal (801) at node B may be provided from a logic circuit (830) which may be configured to receive a record enable signal (803) (e.g., a logic inverse for a YMUXB signal). The logic circuit (830) may include a plurality of delay elements connected in series with one or more inverters that provide a delay to the record enable signal (803). Accordingly, the record enable signal (803) may be delayed and inverted to provide a boost signal (805) at node B. Before the record enable signal (803) becomes high (at the start of the record operation / period), the boost signal (805) is high, which turns on the NMOS device (810) and charges the boost capacitor (820). When the boost signal (805) is high, Node A is also connected to ground through the NMOS device (810). After a delay, the boost signal (805) becomes low, which turns off the NMOS device (810) and, at the same time, causes a discharge from the boost capacitor (820), which drives Node A from ground (low) to a negative value. Then, this negative voltage is provided as a vBL signal and is provided to the active memory bank as discussed above.

[0040] FIG. 9 illustrates a cross-sectional view of a semiconductor device (900) that may be implemented as at least part of an SRAM device (100). For example, the semiconductor device (900) may include various components configured as a recording auxiliary circuit of a recording driver (110). The cross-sectional view of FIG. 9 is cut along the length direction of the channels of a plurality of transistors of the semiconductor device (900), each implemented as a gate-all-around field-effect-transistor (GAA FET) device. However, it should be understood that the transistors of the semiconductor device (900) may be implemented as any of various other transistor structures (e.g., FinFET, planar FET, or other nanostructure transistors, etc.) while remaining within the scope of the present disclosure.

[0041] On the front side of the substrate (surrounded by a dotted line as it was removed when forming the rear interconnect structures), the semiconductor device (900) comprises an active region (902) having portions formed as channels (904) and portions formed as source / drain structures (906). In various embodiments, the channels (904) may each comprise one or more nanostructures (e.g., nanosheets, nanowires) spaced perpendicularly apart from each other, and the source / drain structures (906) may each comprise one or more epitaxial structures. The semiconductor device (900) comprises a plurality of active (e.g., metal) gate structures (908) each surrounding the nanostructures of the corresponding channels (904). On a source / drain structure (906), the semiconductor device (900) comprises a plurality of source / drain interconnect structures (sometimes referred to as MDs) (910), some of which are coupled with contact via structures (sometimes referred to as VDs) (912) formed thereon. On a gate structure (908), the semiconductor device (900) comprises a plurality of gate via structures (sometimes referred to as VGs) (914).

[0042] VD (912) can bond MD (910) to a first metal track (916) in a first front-side metallization layer (M0 layer). The metal track (916) is sometimes referred to as the M0 track (916). VG (914) can bond a gate structure (908) to a second M0 track (918). On the M0 tracks (916 and 918) (and various other metal tracks in the M0 layer), the semiconductor device (900) includes a plurality of via structures (sometimes referred to as V0s) (920 and 922) for bonding the M0 tracks (916 and 918) to each metal track (sometimes referred to as M1 tracks) (924 and 926) in a next front-side metallization layer (M1 layer) located further away from the substrate. Additionally, on the M1 tracks (924 and 926) (and various other metal tracks within the M1 layer), the semiconductor device (900) includes a plurality of via structures (sometimes referred to as V1s) (928 and 930) for coupling the M1 tracks (924 and 926) to each metal track (sometimes referred to as M2 tracks) (932 and 934) within the next front metallization layer (M2 layer) located further away from the substrate. Although three front metallization layers are illustrated, it should be understood that the semiconductor device (900) may include any number of front metallization layers.

[0043] According to various embodiments, metal tracks formed across these front metallization layers may be configured to electrically couple different components of the SRAM device (100) (to route signals and / or transmit power). Using the schematic diagram of FIG. 3 as a representative example, a bit line (BL) (340) passing over a memory bank (180B) may be formed by at least one M0 track and one M2 track. In another example, a bit line (350) may be formed by at least one M0 track. According to some embodiments of the present disclosure, at least one of the channels (904) may form an NMOS device (810) of the write auxiliary circuit (800) together with a corresponding gate structure among the gate structures (908) surrounding the channel and together with a pair of corresponding source / drain structures (906). The M0 tracks (916 and 918) may form one of a plurality of parallel-connected sub-capacitors of the boost capacitor (820). The M0 tracks (916, 918) can each function as terminals of these sub-capacitors.

[0044] FIG. 10 illustrates a flowchart of an exemplary method (1000) for forming or manufacturing a semiconductor device according to some embodiments. Some of the operations of the method (1000) are at least some of the SRAM device (100) discussed above, for example, memory cells (190) of different memory banks (180A-B), a write driver (110), and bit lines (BLs) (340-350) that combine the write driver (110) to memory banks (180A-B) (Figs. 3 and 4), memory cells (190) of different memory banks (180A-C), a write driver (110), and bit lines (BLs) (540-560) that combine the write driver (110) to memory banks (180A-C) (Fig. 5), or bits that combine memory cells (190) of different memory banks (180A-D), a write driver (110), and the write driver (110) to memory banks (180A-D). It can be configured to form lines (BLs) (650-680) (Fig. 6). It is understood that additional operations may be performed before, during, and / or after the method (1000) illustrated in Fig. 10.

[0045] For example, the method (1000) begins with an operation (1010) of providing a substrate comprising a first region, a second region, and a third region. The method (1000) proceeds to an operation (1020) of forming channel layers and sacrificial layers that are alternately stacked up and down on the substrate. The method (1000) proceeds to an operation (1030) of defining a plurality of first semiconductor pins each comprising a first portion of each of the channel layers and sacrificial layers, a plurality of second semiconductor pins each comprising a second portion of each of the channel layers and sacrificial layers, and a plurality of third semiconductor pins each comprising a third portion of each of the channel layers and sacrificial layers. In some embodiments, the first semiconductor pins may be placed in the first region, the second semiconductor pins may be placed in the second region, and the third semiconductor pins may be placed in the third region.

[0046] The method (1000) proceeds to an operation (1040) of forming a plurality of first source / drain structures within each of the first semiconductor pins, a plurality of second source / drain structures within each of the second semiconductor pins, and a plurality of third source / drain structures within each of the third semiconductor pins. The method (1000) may proceed to an operation (1050) of forming a plurality of first active (e.g., metal) gate structures across the first semiconductor pins, a plurality of second active (e.g., metal) gate structures across the second semiconductor pins, and a plurality of third active (e.g., metal) gate structures across the third semiconductor pins. The first active gate structures can replace the remaining portions of the sacrificial layers in the first semiconductor pins to surround the remaining portions of the channel layers in the first semiconductor pins, the second active gate structures can replace the remaining portions of the sacrificial layers in the second semiconductor pins to surround the remaining portions of the channel layers in the second semiconductor pins, and the third active gate structures can replace the remaining portions of the sacrificial layers in the third semiconductor pins to surround the remaining portions of the channel layers in the third semiconductor pins.

[0047] In some embodiments, the first semiconductor pins, the first source / drain structures, and the first active gate structures may operably form the first memory cells of the first memory bank; the second semiconductor pins, the second source / drain structures, and the second active gate structures may operably form the second memory cells of the second memory bank; and the third semiconductor pins, the third source / drain structures, and the third active gate structures may operably form the record driver. Additionally, the first region may be located between the second region and the third region, and accordingly, the first memory bank within the first region may sometimes be referred to as the near bank (with respect to the record driver), and the second memory bank within the second region may sometimes be referred to as the far bank (with respect to the record driver).

[0048] The method (1000) proceeds to an operation (1060) of forming at least a first metal track in a first metallization layer configured to combine a recording driver with a first memory bank, and at least a second metal track in a second higher metallization layer configured to combine a recording driver with a second memory bank, and a third metal track in the first metallization layer. In some embodiments, the first metal track may be operable as one of a plurality of first bit lines of the first memory bank, and the second and third metal tracks may be operable as one of a plurality of second bit lines of the first memory bank.

[0049] FIG. 11 illustrates a flowchart of an exemplary method (1100) for operating a memory device according to some embodiments. For example, at least some of the operations of the method (1100) may be configured to selectively combine a write assist circuit capable of providing a negative bit line voltage with one or more of the various memory banks of the memory array, while decouple the negative bit line voltage from other memory banks. It should be noted that the method (1100) is merely an example and is not intended to limit the scope of the disclosure. Accordingly, additional operations may be provided before, during, and / or thereafter of the method (1100) illustrated in FIG. 11, and some other operations may be described only briefly herein.

[0050] The method (1100) begins with an operation (1110) of receiving an address signal indicating that the first memory array is an inactive memory bank and the second memory array is an active memory bank. In some embodiments, the inactive memory bank is configured to operate at a lower supply voltage, and the active memory bank is configured to operate at a higher supply voltage. Using the embodiment illustrated in FIG. 3 as a representative example, the bank decoder (140) may receive an ADDR signal comprising one or more bits, each configured to indicate whether the corresponding memory bank is configured as an active bank or as an inactive bank. Based on the ADDR signal, memory bank (180A) may be indicated as an active memory bank, and memory bank (180B) may be indicated as an inactive memory bank. According to some embodiments, the active memory bank is configured to perform read / write operations, while the inactive memory bank is configured to retain previously written data.

[0051] The method (1100) continues to an operation (1120) of providing a select signal based on an address signal to disable the first multiplexer and enable the second multiplexer. Continuing with the above example, the bank decoder (140) may provide an SEL signal to control (e.g., enable) a multiplexer (320) that selectively couples the write driver (110) to the memory bank (180A) and a multiplexer (330) that selectively couples the write driver (110) to the memory bank (180B) based on the ADDR signal. The SEL signal may include first and second bits, and the first and second bits are logically inverse of each other. When the first bit is provided at logic 1 (when the second bit is provided at logic 0), the multiplexer (320) is enabled and the multiplexer (330) is disabled.

[0052] The method (1100) continues with the operation (1130) of uncouple the driver from the inactive memory bank through a first multiplexer that is disabled to float the first bit line of the inactive memory bank, while coupling the driver to the active memory bank through a second multiplexer that is enabled to provide a negative voltage on the second bit line of the active memory bank. Continuing from the example above, when the multiplexer (320) is enabled and the multiplexer (330) is disabled, the recording driver (110) can be configured to provide a negative bit line voltage and coupled to the memory bank (180A) through the enabled multiplexer (320). When the recording driver (110) is configured to provide a negative bit line voltage, the recording driver (110) can simultaneously be uncoupled from the memory bank (180B) through the disabled multiplexer (330).

[0053] In one aspect of the present disclosure, a memory circuit is disclosed. The memory circuit comprises: a first memory array comprising a plurality of first memory cells, each of the plurality of first memory cells is configured to operate with a first supply voltage; a second memory array comprising a plurality of second memory cells, each of the plurality of second memory cells is configured to operate with a second supply voltage, wherein the first supply voltage and the second supply voltage are different from each other; and a driver operably coupled to the plurality of first memory cells and the plurality of second memory cells, respectively, through a first access line and a second access line. The driver is configured to selectively provide a negative voltage on one of the first access line or the second access line based on an address signal.

[0054] In another aspect of the present disclosure, a memory circuit is disclosed. The memory circuit comprises: a first memory array comprising a plurality of first memory cells coupled to each other via a first bit line; a second memory array comprising a plurality of second memory cells coupled to each other via a second bit line; and a driver operably coupled to the first memory cells via the first bit line and to the second memory cells via the second bit line, wherein the first memory array and the second memory array are each physically positioned along a lateral direction with respect to the driver. The driver is configured to be uncoupled from the first bit line when the first memory array is configured as an inactive memory bank based on an address signal; and to apply a negative voltage on the second bit line when the second memory array is configured as an active memory bank based on an address signal.

[0055] In another aspect of the present disclosure, a method for operating a memory circuit is disclosed. The method comprises receiving an address signal indicating that a first memory array is an inactive memory bank and a second memory array is an active memory bank, wherein the inactive memory bank is configured to operate at a lower supply voltage and the active memory bank is configured to operate at a higher supply voltage. The method comprises providing a selection signal based on the address signal to disable a first multiplexer and enable a second multiplexer. The method comprises uncouple a driver from the inactive memory bank through the disabled first multiplexer to float a first bit line of the inactive memory bank, while coupling a driver to the active memory bank through the enabled second multiplexer to provide a negative voltage on a second bit line of the active memory bank.

[0056] As used herein, the terms “about” and “approximately” generally refer to a predetermined amount of value that may vary based on a specific technical node associated with the target semiconductor device. Based on a specific technical node, the term “about” may refer to a predetermined amount of value that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0057] The foregoing outlines the features of various embodiments to enable those skilled in the art to better understand the aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages as the embodiments introduced herein. Furthermore, those skilled in the art should recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that those skilled in the art may make various changes, substitutions, and replacements without departing from the spirit and scope of the present disclosure.

[0058] Examples

[0059] Example 1. As a memory circuit,

[0060] A first memory array comprising a plurality of first memory cells - each of the plurality of first memory cells is configured to operate with a first supply voltage -;

[0061] A second memory array comprising a plurality of second memory cells - each of the plurality of second memory cells is configured to operate with a second supply voltage, wherein the first supply voltage and the second supply voltage are different from each other -; and

[0062] A driver operably coupled to the plurality of first memory cells and the plurality of second memory cells, respectively, through a first access line and a second access line.

[0063] Includes;

[0064] A memory circuit configured such that the driver is configured to selectively provide a negative voltage on either the first access line or the second access line based on an address signal.

[0065] Example 2. In Example 1,

[0066] A memory circuit in which the first memory cells and the second memory cells each include a static random access memory (SRAM) cell.

[0067] Example 3. In Example 1,

[0068] The above driver is a memory circuit located along the lateral direction to one of the first or second memory arrays, which is physically closer to the other of the first or second memory arrays.

[0069] Example 4. In Example 1,

[0070] A memory circuit configured such that the driver is discoupled from the second access line through a second transistor that is turned off by the address signal, and applies the negative voltage on the first access line through a first transistor that is turned on by the address signal.

[0071] Example 5. In Example 1,

[0072] A memory circuit in which the first memory array is interposed between the driver and the second memory array along the lateral direction, wherein the first access line is formed by at least a first metal track physically extending along the lateral direction, and the second access line is formed by at least a second metal track and a third metal track both physically extending along the lateral direction.

[0073] Example 6. In Example 5,

[0074] A memory circuit in which the first metal track and the third metal track are formed within a first metallization layer, and the second metal track is formed within a higher second metallization layer.

[0075] Example 7. In Example 6,

[0076] A memory circuit in which both the first metal track and the second metal track extend across the first memory array.

[0077] Example 8. In Example 1,

[0078] A memory circuit wherein the first memory array is configured as an active memory bank based on the address signal, so that the first access line receives the negative voltage, while the second memory array is configured as an inactive memory bank based on the address signal, so that the second access line is floated.

[0079] Example 9. In Example 1,

[0080] A logic gate configured to provide a selection signal based on the above address signal—the address signal indicates whether to select the second memory array as an active memory bank—;

[0081] A first transistor configured to uncouple the driver from the first access line based on the above selection signal; and

[0082] A second transistor configured to couple the driver to the second access line based on the above selection signal.

[0083] A memory circuit that further includes

[0084] Example 10. In Example 9,

[0085] A memory circuit in which the above logic gate is configured to perform a NOR operation on the above address signal and control signal.

[0086] Example 11. In Example 9,

[0087] A memory circuit in which the first transistor and the second transistor are alternately turned on based on the address signal.

[0088] Example 12. As a memory circuit,

[0089] A first memory array comprising a plurality of first memory cells combined with each other through a first bit line;

[0090] A second memory array comprising a plurality of second memory cells combined with each other through a second bit line; and

[0091] A driver operably coupled to the first memory cells via the first bit line and to the second memory cells via the second bit line - the first memory array and the second memory array are each physically positioned along the lateral direction with respect to the driver -

[0092] Includes;

[0093] The above driver is:

[0094] When the first memory array is configured as an inactive memory bank based on an address signal, it is decoupled from the first bit line;

[0095] When the second memory array is configured as an active memory bank based on the address signal, a negative voltage is applied to the second bit line.

[0096] A memory circuit that is composed of.

[0097] Example 13. In Example 12,

[0098] The above driver is a memory circuit located along the lateral direction to one of the first or second memory arrays, which is physically closer to the other of the first or second memory arrays.

[0099] Example 14. In Example 12,

[0100] A memory circuit in which the first memory array is interposed between the driver and the second memory array along the lateral direction, wherein the first bit line is formed by at least a first metal track physically extending along the lateral direction, and the second bit line is formed by at least a second metal track and a third metal track both physically extending along the lateral direction.

[0101] Example 15. In Example 14,

[0102] A memory circuit in which the first metal track and the third metal track are formed within a first metallization layer, and the second metal track is formed within a higher second metallization layer.

[0103] Example 16. In Example 15,

[0104] A memory circuit in which both the first metal track and the second metal track extend across the first memory array.

[0105] Example 17. In Example 12,

[0106] A logic gate configured to provide a selection signal based on the above address signal;

[0107] A first transistor selectively coupled between the driver and the first bit line based on the above selection signal; and

[0108] A second transistor selectively coupled between the driver and the second bit line based on the above selection signal.

[0109] A memory circuit that further includes

[0110] Example 18. A method for operating a memory circuit, wherein

[0111] A step of receiving an address signal indicating that the first memory array is an inactive memory bank and the second memory array is an active memory bank - said inactive memory bank is configured to operate at a lower supply voltage and said active memory bank is configured to operate at a higher supply voltage -;

[0112] A step of providing a selection signal based on the address signal to disable the first multiplexer and enable the second multiplexer; and

[0113] A step of uncouple a driver from the inactive memory bank through the deactivated first multiplexer to float a first bit line of the inactive memory bank, while coupling the driver to the active memory bank through the activated second multiplexer to provide a negative voltage on a second bit line of the active memory bank.

[0114] A method for operating a memory circuit including

[0115] Example 19. In Example 18,

[0116] A method for operating a memory circuit, wherein the first memory array is physically located along the lateral direction between the second memory bank and the driver.

[0117] Example 20. In Example 19,

[0118] A method for operating a memory circuit, wherein the first bit line is formed by at least a first metal track physically extending along the lateral direction, and the second bit line is formed by at least a second metal track and a third metal track both physically extending along the lateral direction, and the first metal track and the third metal track are formed within a first metallization layer, and the second metal track is formed within a higher second metallization layer.

Claims

Claim 1 A memory circuit comprising: a first memory array including a plurality of first memory cells, wherein each of the plurality of first memory cells is configured to operate with a first supply voltage; a second memory array including a plurality of second memory cells, wherein each of the plurality of second memory cells is configured to operate with a second supply voltage, wherein the first supply voltage and the second supply voltage are different from each other; and a driver operably coupled to the plurality of first memory cells and the plurality of second memory cells, respectively, through a first access line and a second access line; wherein the driver is configured to selectively provide a negative voltage on one of the first access line or the second access line based on an address signal. Claim 2 A memory circuit according to claim 1, wherein the first memory cells and the second memory cells each include a static random access memory (SRAM) cell. Claim 3 A memory circuit according to claim 1, wherein the driver is located along the lateral direction to one of the first or second memory arrays, which is physically closer than the other of the first or second memory arrays. Claim 4 A memory circuit according to claim 1, wherein the driver is configured to apply the negative voltage on the first access line through a first transistor turned on by the address signal, while being discoupled from the second access line through a second transistor turned off by the address signal. Claim 5 A memory circuit according to claim 1, wherein the first memory array is interposed between the driver and the second memory array along the lateral direction, the first access line is formed by at least a first metal track physically extending along the lateral direction, and the second access line is formed by at least a second metal track and a third metal track, both physically extending along the lateral direction. Claim 6 A memory circuit according to claim 5, wherein the first metal track and the third metal track are formed within the first metallization layer, and the second metal track is formed within the second metallization layer. Claim 7 A memory circuit according to claim 1, wherein the first memory array is configured as an active memory bank based on the address signal, so that the first access line receives the negative voltage, while the second memory array is configured as an inactive memory bank based on the address signal, so that the second access line is floating. Claim 8 A memory circuit according to claim 1, further comprising: a logic gate configured to provide a selection signal based on the address signal, wherein the address signal indicates whether to select the second memory array as an active memory bank; a first transistor configured to uncouple the driver from the first access line based on the selection signal; and a second transistor configured to couple the driver to the second access line based on the selection signal. Claim 9 A memory circuit comprising: a first memory array including a plurality of first memory cells coupled to each other through a first bit line; a second memory array including a plurality of second memory cells coupled to each other through a second bit line; and a driver operably coupled to the first memory cells through the first bit line and to the second memory cells through the second bit line, wherein the first memory array and the second memory array are each physically positioned along a lateral direction with respect to the driver; and the driver comprises: When the first memory array is configured as an inactive memory bank based on an address signal, it is decoupled from the first bit line; When the second memory array is configured as an active memory bank based on the address signal, a negative voltage is applied to the second bit line. A memory circuit that is composed of. Claim 10 A method for operating a memory circuit, comprising: receiving an address signal indicating that a first memory array is an inactive memory bank and a second memory array is an active memory bank—wherein the inactive memory bank is configured to operate at a lower supply voltage and the active memory bank is configured to operate at a higher supply voltage—; providing a selection signal based on the address signal to disable a first multiplexer and enable a second multiplexer; and uncouple a driver from the inactive memory bank through the disabled first multiplexer to float a first bit line of the inactive memory bank, while coupling the driver to the active memory bank through the enabled second multiplexer to provide a negative voltage on a second bit line of the active memory bank.

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