Method of forming a gate stack including a dielectric layer

Abstract

A method for forming a gate stack comprises the steps of providing a substrate, optionally forming an interface layer, forming a dielectric layer, and optionally forming a dipole layer, wherein the dielectric layer comprises at least one of hafnium, zirconium, and oxygen, and silicon or aluminum.

Description

Technology Field

[0001] The present disclosure generally relates to a method for forming an electronic device. More specifically, examples are described regarding a method for forming a gate stack suitable for use in a transistor, as well as a structure including the gate stack and a substrate processing apparatus for forming the gate stack including a dielectric layer. Background Technology

[0002] The speed and density of integrated circuits have been significantly improved due to the scaling of semiconductor devices. However, the scaling of semiconductor devices has presented challenges. For example, during the formation of field-effect transistors such as metal oxide field-effect transistors, it has been a challenge to form a gate stack having a dielectric layer that maintains a relatively high dielectric constant (high dielectric constant material) while maintaining a relatively low equivalent oxide thickness (EOT) or capacitance equivalent thickness (CET) and leakage current.

[0003] High dielectric constant materials can exhibit desirable electrical characteristics for the function of a gate stack. However, current high dielectric constant materials may not exhibit the desired dielectric constant while maintaining other desired electrical characteristics, such as a high band gap, to allow for relatively low EOT or CET in the gate stack. Therefore, there is a need for improved methods and improved dielectric layers for forming dielectric layers and gate stacks that can be formed with accuracy and precision while maintaining desirable characteristics.

[0004] Any discussion, including the discussion of the problems and solutions presented in this section, is incorporated into this disclosure solely for the purpose of providing context for the present disclosure. Such discussion should not be construed as an acknowledgment that any or all information was known at the time the present invention was made or otherwise constitutes prior art.

[0005] The content of the present invention is provided to introduce selected concepts in a simplified form. These concepts are described in more detail below in the detailed description of exemplary embodiments of the present disclosure. The content of the present invention is not intended to essentially identify the principal or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0006] Various embodiments described herein provide a method for forming a gate stack and a method for forming a dielectric layer on a gate stack. The method disclosed herein provides a gate stack having a dielectric layer having desired characteristics, such as a high dielectric constant (e.g., greater than 12) and a high band gap (e.g., greater than about 5 eV, greater than about 6 eV, or greater than 8 eV), for use in a gate stack having a relatively low CET (e.g., less than 16 angstroms or less than 14 angstroms).

[0007] According to one or more embodiments, a method for forming a gate stack is provided, comprising the step of forming a dielectric layer. An exemplary method comprises the step of providing a substrate to a reaction chamber. An exemplary method continues to the step of forming a dielectric layer by a periodic deposition process. In some embodiments, the periodic deposition method is an atomic layer deposition (ALD) method. In an exemplary method, the step of forming a dielectric layer comprises pulsed a hafnium precursor a plurality of times, pulsed a zirconium precursor at least once, pulsed an addition precursor at least once, and pulsed an oxygen reactant. In some embodiments, the addition precursor comprises a silicon precursor. In some embodiments, the addition precursor comprises an aluminum precursor.

[0008] In some embodiments, an interface layer is formed on the surface of a substrate. The interface layer may be formed, for example, by a periodic deposition process or by oxidation of the surface of the substrate. In some embodiments, the interface layer comprises a semiconductor oxide such as silicon oxide. In some embodiments, the interface layer comprises SiO2 or crystalline SiO2. In some embodiments, the interface layer has a thickness of about 2 to 10 Angstroms, or about 2 to 7 Angstroms.

[0009] In some embodiments, the dielectric layer is formed (e.g., directly) on the interface layer. In some embodiments, the dielectric layer is formed (e.g., directly) on the dipole layer. The dielectric layer may comprise hafnium, zirconium, silicon, and oxygen. In some embodiments, the dielectric layer may further comprise aluminum. In some embodiments, the dielectric layer may comprise hafnium, zirconium, aluminum, and oxygen. In some embodiments, the dielectric layer comprises zirconium-doped hafnium silicon oxide, zirconium-doped hafnium aluminum oxide, or zirconium-doped hafnium silicate. In some embodiments, the dielectric layer may comprise a plurality of sublayers. The dielectric layer may comprise a sublayer of hafnium oxide, silicon oxide, aluminum oxide, and / or zirconium oxide. In some embodiments, a sublayer comprising silicon oxide and / or aluminum oxide and a sublayer comprising zirconium oxide are separated by at least one sublayer comprising hafnium oxide. In some embodiments, the dielectric layer comprises a first hafnium oxide sublayer, a silicon oxide sublayer or an aluminum oxide sublayer, a second hafnium oxide sublayer, and a zirconium oxide sublayer, wherein the silicon oxide sublayer or the aluminum oxide sublayer and the zirconium oxide sublayer do not come into direct contact with each other. The dielectric layer may include a hafnium oxide sublayer between each zirconium oxide sublayer and the silicon oxide sublayer or the aluminum oxide sublayer.

[0010] In some embodiments, the dielectric layer is a bilayer or comprises a bilayer and comprises a first sublayer and a second sublayer. In some embodiments, the first sublayer comprises hafnium silicate, hafnium silicon oxide, or hafnium aluminum oxide. In some embodiments, the first sublayer is disposed (e.g., directly) on an interface layer. In some embodiments, the first sublayer is disposed (e.g., directly) on a dipole layer. In some embodiments, the second sublayer comprises zirconium oxide, zirconium silicon oxide, zirconium aluminum oxide, or zirconium silicate. In some embodiments, the second sublayer is disposed (e.g., directly) on the first sublayer.

[0011] In some embodiments, during the formation of the dielectric layer, the hafnium precursor is pulsed at least once between each pulse of the zirconium precursor and each pulse of the addition precursor. In some embodiments, the step of forming the dielectric layer includes performing one or more first cycles. In some embodiments, the first cycle comprises, in order, pulse the hafnium precursor for a first period, pulse the addition precursor, pulse the hafnium precursor for a second period, and pulse the zirconium precursor. In some embodiments, the zirconium precursor is not pulsed before the second period in each first cycle. In some embodiments, the addition precursor is not pulsed before the first period or after the second period in each first cycle.

[0012] In some embodiments, during the formation of the dielectric layer, the ratio of the number of pulses of the addition precursor to the number of pulses of the zirconium precursor in the first cycle is in the range of about 2.5:1 to about 4:1, or about 2.7:1 to about 3.5:1, or about 2.9:1 to about 3.2:1. In the first cycle, the ratio of the number of pulses of the hafnium precursor to the number of pulses of the zirconium precursor may be in the range of about 1.5:1 to about 2.5:1, or about 1.7:1 to about 2.3:1, or about 1.9:1 to about 2.1:1. In the first cycle, the ratio of the number of pulses of the addition precursor to the number of pulses of the hafnium precursor may be in the range of about 1.25:1 to 1.75:1, or about 1.4:1 to about 1.6:1.

[0013] In some embodiments, during the formation of the dielectric layer, the ratio of the number of pulses of the hafnium precursor to the number of pulses of the zirconium precursor is about 30:1 to about 7:1, or about 20:1 to about 10:1.

[0014] The precursor and reactant may be any suitable precursor or reactant. In some embodiments, the hafnium precursor comprises a hafnium halide or an organometallic hafnium precursor. In some embodiments, the zirconium precursor comprises a zirconium halide or an organometallic zirconium precursor. In some embodiments, the silicon precursor comprises a silane, a chlorosilane, an organosilane, a heterosilane, or a silicon halide. In some embodiments, the aluminum precursor comprises triethylaluminum (TEA), trimethylaluminum (TMA), dimethylaluminum hydride (DMAH), and aluminum chloride. In some embodiments, the oxygen reactant comprises one or more of H2O, O2, O3, H2O2, NO, NO2, and N2O in any combination.

[0015] In some embodiments, the dielectric layer has a thickness of about 15 Angstroms to about 25 Angstroms, or about 16 Angstroms to about 20 Angstroms, or about 12 Angstroms to about 16 Angstroms. In some embodiments, the dielectric layer has a dielectric constant greater than about 12, or about 12 to 30, or about 12 to 24, or about 12 to 15, or about 18 to 22.

[0016] In some embodiments, the method includes the step of forming a dipole layer. In some embodiments, the dipole layer comprises a metal oxide, a metal nitride, or a metal oxynitride. In some embodiments, the dipole layer comprises lanthanum, aluminum, yttrium, scandium, and / or gallium. In some embodiments, the dipole layer comprises lanthanum oxide, aluminum oxide, yttrium oxide, scandium oxide, or gallium oxide. In some embodiments, the dipole layer may be formed (e.g., directly) on a dielectric layer. In some embodiments, the dipole layer is disposed directly on a second sublayer of the dielectric layer. In some embodiments, the dielectric layer may be formed (e.g., directly) on the dipole layer, and the dipole layer may be formed (e.g., directly) on an interface layer. In some embodiments, the dipole layer may be formed between sublayers of the dielectric layer.

[0017] According to additional examples of the present disclosure, the element is formed using a method as described herein and / or includes a structure.

[0018] According to a further exemplary embodiment of the present disclosure, a system is provided to perform a method as described herein and / or to form a structure.

[0019] According to various additional embodiments of the present disclosure, a method for forming a gate stack is provided, the method comprising: providing a substrate having a surface including an interface layer to a reaction chamber; and forming a dielectric layer on the interface layer by an atomic layer deposition process, wherein the step of forming the dielectric layer comprises pulsed a hafnium precursor a plurality of times, pulsed a zirconium precursor at least once, pulsed an addition precursor at least once, and pulsed an oxygen reactant, wherein the addition precursor comprises a silicon precursor or an aluminum precursor, and the hafnium precursor is pulsed at least once between each pulse of the zirconium precursor and each pulse of the addition precursor.

[0020] In some embodiments, the dielectric layer comprises a plurality of sublayers including a first sublayer comprising hafnium oxide, a second sublayer comprising silicon oxide or aluminum oxide, a third sublayer comprising hafnium oxide, and a fourth sublayer comprising zirconium oxide, wherein the second sublayer and the fourth sublayer do not come into direct contact with each other.

[0021] In some embodiments, the step of forming a dielectric layer includes performing a plurality of first cycles, wherein the first cycles include, in order, pulse a hafnium precursor for a first period, pulse an additive precursor, pulse a hafnium precursor for a second period, and pulse a zirconium precursor.

[0022] In some embodiments, the zirconium precursor is not pulsed before the second period, and the addition precursor is not pulsed before the first period or after the second period in the first cycle.

[0023] In some embodiments, the ratio of the number of pulses of the additive precursor to the number of pulses of the zirconium precursor in the first cycle is in the range of about 2.5:1 to about 4:1.

[0024] In some embodiments, the ratio of the number of pulses of hafnium precursor to the number of pulses of zirconium precursor in the first cycle is in the range of about 1.5:1 to about 2.5:1.

[0025] In some embodiments, the ratio of the number of pulses of the additive precursor to the number of pulses of the hafnium precursor in the first cycle is in the range of about 1.25:1 to 1.75:1.

[0026] In some embodiments, the method further includes the step of forming a dipole layer directly on a dielectric layer.

[0027] In some embodiments, the dipole layer comprises lanthanum oxide, aluminum oxide, yttrium oxide, scandium oxide, or gallium oxide.

[0028] In some embodiments, the method further includes the step of forming a dipole layer directly on the interface layer.

[0029] In some embodiments, the ratio of oxygen atoms to the sum of hafnium, zirconium, aluminum, and silicon atoms is in the range of about 1.6:1 to about 2.5:1.

[0030] In some embodiments, the additive precursor includes a silicon precursor.

[0031] According to various additional embodiments of the present disclosure, a method for forming a gate stack is provided, the method comprising: providing a substrate having a surface including an interface layer to a reaction chamber; and forming a dielectric layer on the interface layer by an atomic layer deposition process, wherein the dielectric layer comprises a first sublayer comprising hafnium silicate, hafnium silicon oxide, or hafnium aluminum oxide disposed directly on the interface layer, and a second sublayer comprising zirconium oxide, zirconium silicon oxide, or zirconium silicate disposed directly on the first sublayer.

[0032] In some embodiments, the method further comprises the step of forming a dipole layer directly on a second sublayer, wherein the dipole layer comprises lanthanum oxide, aluminum oxide, yttrium oxide, scandium oxide, or gallium oxide.

[0033] In some embodiments, the dielectric layer has a thickness of about 15 Angstroms to about 25 Angstroms.

[0034] In some embodiments, the interface layer comprises silicon oxide.

[0035] In some embodiments, the dielectric layer has a dielectric constant in the range of about 12 to about 30.

[0036] These and other embodiments will be readily apparent to those skilled in the art from the following detailed description of specific embodiments with reference to the accompanying drawings; the invention is not limited to any specific embodiment(s) disclosed. Brief explanation of the drawing

[0037] FIG. 1 illustrates a method for forming a gate stack according to one or more embodiments of the present disclosure; FIG. 2 illustrates a method for forming a dielectric layer according to one or more embodiments of the present disclosure; FIG. 3 illustrates another method for forming a dielectric layer according to one or more embodiments of the present disclosure; FIG. 4 illustrates another method for forming a dielectric layer according to one or more embodiments of the present disclosure; FIG. 5 illustrates an example of a substrate processing apparatus according to one or more examples of the present disclosure; FIG. 6 illustrates an example of a structure capable of forming a part of an element according to one or more examples of the present disclosure; FIG. 7 illustrates another example of a structure capable of forming a part of an element according to one or more examples of the present disclosure; FIG. 8 illustrates another example of a structure capable of forming a part of an element according to one or more examples of the present disclosure; FIG. 9 illustrates another example of a structure capable of forming a part of an element according to one or more examples of the present disclosure; FIG. 10 illustrates another example of a structure capable of forming a part of an element according to one or more examples of the present disclosure; It will be understood that the elements of the drawings are depicted in a simplified and clear manner and are not necessarily depicted in proportion. For example, to aid in understanding the embodiments illustrated in this disclosure, the dimensions of some components in the drawings may be exaggerated compared to other components. Specific details for implementing the invention

[0038] The description of exemplary embodiments of methods, structures, elements, and systems provided below is merely illustrative and intended only for illustrative purposes, and is not intended to limit the scope or claims of this disclosure. Furthermore, citing multiple embodiments describing features is not intended to exclude other embodiments having additional features or other embodiments including other combinations of specified features. For example, various embodiments are presented as exemplary embodiments and may be cited in dependent claims. Unless otherwise noted, exemplary embodiments or their components may be combined or applied separately.

[0039] As used herein, the term “and / or” includes any and all combinations of one or more of the associated enumerated items. Unless otherwise indicated, an expression such as “at least one of” following an enumeration of elements modifies the entire enumeration of elements and does not necessarily modify the individual elements of the enumeration.

[0040] As used herein, the singular forms "one," "one," and "the above" are intended to include the plural forms unless the context indicates otherwise.

[0041] As used herein, the term “substrate” may refer to any underlying material or materials that can be used to form a device, circuit, or film, or upon which a device, circuit, or film can be formed. The substrate may comprise a bulk material such as silicon (e.g., single-crystal silicon), other Group IV materials such as germanium, or compound semiconductor materials such as Group III-V or Group II-VI semiconductors, and may comprise one or more layers placed on or beneath the bulk material. For example, the substrate may comprise silicon or silicon germanium.

[0042] In some embodiments, “film” refers to a layer extending in a direction perpendicular to the thickness direction. In some embodiments, “layer” refers to a material having a specific thickness formed on a surface, or may be a synonym for a film or a non-film structure. A film or layer may consist of a single film or layer or multiple films or layers having specific properties, and the boundary between adjacent films or layers may be clear or not, and may be constructed or not constructed based on physical, chemical, and / or any other properties, the formation process and sequence, and / or the function or purpose of adjacent films or layers. A layer or film may or may not be continuous. Additionally, a single film or layer may be formed using one or more deposition cycles.

[0043] As used herein, the term “structure” may refer to a partially or completely manufactured device structure. For example, the structure may be or include a substrate having one or more layers and / or features formed thereon.

[0044] As used herein, terms including elements followed by "precursors" may refer to compounds including the mentioned elements.

[0045] As used herein, the term "placed on" may refer to two membranes in direct contact with each other.

[0046] As used herein, the terms “periodic deposition process” or “cyclic deposition process” refer to a vapor deposition process, wherein deposition cycles, typically a plurality of consecutive deposition cycles, are performed in a process chamber. The periodic deposition process may include, for example, periodic chemical vapor deposition (CCVD) and / or atomic layer deposition (ALD) processes.

[0047] In this disclosure, any two numeric values ​​of a variable may constitute an executable range of the variable, and any indicated range may include or exclude endpoints. Additionally, any value of an indicated variable may refer to an exact value or an approximate value (regardless of whether "approximate" is indicated), may include an equivalent, and may refer to an average, median, representative, majority, etc. For example, a value of a variable may include + / - 20%, or + / - 10%, or + / - 5%, or + / - 1%, or + / - 0% of the value of the enumerated variable. Also, in this disclosure, the terms "comprising," "including," "consisting of," and "having" may independently refer to "ordinarily or approximately including," "comprising," "essentially made of," or "made of" in some embodiments. In this disclosure, any defined meaning is not necessarily excluded from the ordinary and customary meaning in some embodiments.

[0048] In some embodiments, the term "dielectric" or "dielectric material" may refer to a material having a dielectric constant greater than 1, or greater than 2, or greater than 3.9, or greater than 10.

[0049] FIG. 1 illustrates a method (100) for forming a gate stack according to an exemplary embodiment of the present disclosure. The method (100) comprises the steps of providing a substrate to a reaction chamber (step (110)), optionally forming an interface layer (step (120)), forming a dielectric layer (step (130)), optionally forming a dipole layer (step (140)), and forming a gate electrode (step (150)).

[0050] During step (110), the substrate is provided into the reaction space within the reaction chamber. According to an example of the present disclosure, the reaction chamber may form part of a chemical vapor deposition (CVD) reactor, such as a chemical vapor deposition (CVD) reactor or an atomic layer deposition (ALD) reactor. Various steps of the method described herein may be performed within a single reaction chamber or within multiple reaction chambers, such as the reaction chamber of a cluster tool.

[0051] During step (110), the substrate may be at a desired temperature and / or pressure suitable for subsequent steps, or the reaction space may be at a desired pressure. For example, the temperature within the reaction space (e.g., the substrate or substrate support, or the environment) may be about 0°C to about 500°C, or about 250°C to about 425°C. For example, the pressure within the reaction space may be less than 760 Torr, or about 1 Torr to 500 Torr, or about 1 Torr to about 100 Torr.

[0052] In some embodiments, the surface of the substrate includes an interface layer. In some embodiments, the interface layer is disposed directly on a semiconductor material such as silicon, single-crystal silicon, other Group IV materials, such as germanium, or compound semiconductor materials, such as silicon-germanium, Group III-V or Group II-VI semiconductors.

[0053] If the surface of the substrate does not include an interface layer, the method (100) includes the step (120) of forming an interface layer on the substrate. The interface layer may be formed by any suitable method. In some embodiments, the interface layer is formed by a (e.g., periodic) deposition process or by oxidation of a semiconductor material. In some embodiments, the interface layer comprises silicon oxide. In some embodiments, the interface layer comprises SiO2. In some embodiments, the interface layer comprises crystalline SiO2. In some embodiments, the interface layer has a thickness of about 2 to 10 Angstroms, or about 2 to 7 Angstroms.

[0054] The method (100) continues to the step of forming a dielectric layer (step (130)). During step (130), the substrate may be at a desired temperature and / or the reaction space may be at a desired pressure. For example, the temperature inside the reaction chamber (e.g., the substrate or substrate support) may be about 200°C to about 500°C, or about 250°C to about 425°C. The pressure inside the reaction chamber may be controlled. For example, the pressure inside the reaction space may be less than 760 Torr, or about 1 Torr to 100 Torr. In some embodiments, the dielectric layer is formed directly on the interface layer. In some embodiments, the step of forming the dielectric material includes a periodic deposition process such as an atomic layer deposition (ALD) process or a periodic CVD process.

[0055] In some embodiments, the dielectric layer has a thickness of about 15 Angstroms to about 25 Angstroms, or about 16 Angstroms to about 20 Angstroms. In some embodiments, the dielectric layer has a dielectric constant greater than about 12, or about 12 to 30, or about 12 to 24, or about 12 to 15, or about 18 to 22.

[0056] In some embodiments, the dielectric layer comprises hafnium, zirconium, silicon, and oxygen. In some embodiments, the dielectric layer comprises Hfx Zr y A z It comprises O2, wherein x, y, and z are in the range of 0 to about 1, and the sum of x, y, and z is in the range of about 0.8 to 1.2, or about 0.9 to 1.1, and A is aluminum, silicon, or a combination of aluminum and silicon. In some embodiments, the dielectric layer comprises a tetragonal crystal structure.

[0057] In some embodiments, the dielectric layer comprises zirconium-doped hafnium silicon oxide, zirconium-doped hafnium silicate, or zirconium-doped hafnium aluminum oxide. In some embodiments, the dielectric material comprises hafnium silicon oxide, hafnium silicate, or hafnium aluminum oxide, wherein a plurality of hafnium atoms in its crystal structure are substituted with zirconium. In some embodiments, the dielectric layer may comprise a plurality of sublayers. In some embodiments, the dielectric layer may comprise one or more sublayers of hafnium oxide, silicon oxide, aluminum oxide, and / or zirconium oxide. In some embodiments, a sublayer comprising silicon oxide or aluminum oxide and a sublayer comprising zirconium oxide are separated by at least one sublayer comprising hafnium oxide. In some embodiments, the dielectric layer comprises a first hafnium oxide sublayer, a silicon oxide sublayer or an aluminum oxide sublayer, a second hafnium oxide sublayer, and a zirconium oxide sublayer, wherein the silicon oxide sublayer or the aluminum oxide sublayer and the zirconium oxide sublayer do not come into direct contact with each other. The dielectric layer may include a hafnium oxide sublayer between each zirconium oxide sublayer and the silicon oxide sublayer or the aluminum oxide sublayer.

[0058] In some embodiments, the dielectric layer comprises a first sublayer and a second sublayer. In some embodiments, the first sublayer comprises hafnium silicate, hafnium silicon oxide, or hafnium aluminum oxide. In some embodiments, the first sublayer is disposed directly on the interface layer. In some embodiments, the second sublayer comprises zirconium oxide, zirconium silicon oxide, or zirconium silicate. In some embodiments, the second sublayer is disposed directly on the first sublayer. In some embodiments, the dielectric layer consists of a first sublayer and a second sublayer.

[0059] FIG. 2 illustrates a method (200) that may be suitable for step (130) of FIG. 1. The method (200) may produce a dielectric layer comprising zirconium-doped hafnium silicon oxide, zirconium-doped hafnium silicate, or zirconium-doped hafnium aluminum oxide. The method (200) may produce a dielectric layer comprising hafnium silicon oxide, hafnium silicate, or hafnium aluminum oxide, wherein about 5 to 10 atomic percent of the hafnium in the hafnium silicon oxide, hafnium silicate, or hafnium aluminum oxide is substituted with zirconium. The method (200) comprises the steps of pulses a hafnium precursor or a zirconium precursor (sub-step (210)), pulses an oxygen reactant (sub-step (220)), pulses an additive precursor including an aluminum precursor or a silicon precursor (sub-step (230)), optionally performs one or more purging steps (loop (240)), and optionally repeats the steps one or more times (loop (250)). The sub-steps (210 to 240) of the method (200) may be performed in any order. Each sub-step (210 to 240) of the method (200) may be performed one or more times. In some embodiments, purging (240) is performed after any or all of the steps (210 to 230) of pulses of a hafnium precursor or zirconium precursor (substep (210)), pulses of an oxygen reactant (substep (220)), and pulses of an additive precursor (substep (230)). In some embodiments, pulses of the oxygen reactant (substep (220)) are performed after pulses of the hafnium precursor or zirconium precursor (substep (210)), or pulses of the additive precursor (substep (230)). In some embodiments, the ratio of the number of pulses of the hafnium precursor to the number of pulses of the zirconium precursor during the formation of the dielectric layer is about 30:1 to about 7:1, or about 20:1 to about 10:1.In some embodiments, the ratio of the number of hafnium atoms to zirconium atoms in the dielectric layer is about 20:1 to about 10:1, or about 30:1 to about 7:1, or about 20:1 to about 10:1. In some embodiments, sub-steps (210 to 240) constitute a first process cycle. In some embodiments, the first process cycle is repeated a plurality of times. In some embodiments where a plurality of first process cycles are performed, a plurality of first process cycles including a step of pulsed a zirconium precursor to a plurality of first process cycles including a step of pulsed a hafnium precursor is about 1:10 to about 1:20. In some embodiments, the dielectric layer formed by the method (200) is Hf. x Zr y A z It has the compositional formula of O2, where x, y, and z are 0 to about 1, the sum of x, y, and z is in the range of about 0.8 to 1.2, x is about 10 to 20 times greater than y, and A is aluminum, silicon, or a combination of aluminum and silicon. In some embodiments, z is in the range of about 0.05 to about 0.2, or about 0.06 to about 0.14.

[0060] It is believed that, without being bound by theory, replacing about 5 to 10 percent of hafnium with zirconium while forming hafnium silicate, hafnium silicon oxide, or hafnium aluminum oxide can increase the dielectric constant to greater than 12 while maintaining a high band gap (e.g., greater than 5 eV or greater than 6 eV) and keeping the CET of the gate stack less than about 16 angstroms or less than about 14 angstroms.

[0061] FIG. 3 illustrates another method (300) that may be suitable for step (130) of FIG. 1. The method (300) may produce a dielectric layer comprising zirconium-doped hafnium silicon oxide, zirconium-doped hafnium silicate, or zirconium-doped hafnium aluminum oxide, wherein zirconium and silicon or aluminum are separated as by hafnium. The method (300) comprises the steps of pulse a hafnium precursor during a first period (310), pulse an additive precursor including a silicon precursor or an aluminum precursor (320), pulse a hafnium precursor during a second period (330), pulse a zirconium precursor (340), pulse an oxygen reactant (350), optionally perform a purge, and optionally repeat the sub-steps (310 to 360) one or a plurality of times (loop (370)). In some embodiments, the method (300) comprises sub-steps (310 to 340) performed one or more times and in any order, wherein at least one pulse of the hafnium precursor is between the pulse of the zirconium precursor and the pulse of the addition precursor. In some embodiments, the step of pulsed the oxygen reactant is performed after one or more of the sub-steps (310 to 340). In some embodiments, the step of pulsed the oxygen reactant is performed after one or more of the sub-steps (310 to 340) and before another of the sub-steps (310 to 340) is performed. In some embodiments, purge (360) is performed after any or all of the sub-steps (310 to 350). In some embodiments, the sub-steps (310 to 360) constitute a deposition cycle. In some embodiments, the deposition cycle is repeated one or more times (loop (370)).

[0062] In some embodiments, the ratio of the number of pulses of the additive precursor to the number of pulses of the zirconium precursor in the first cycle is in the range of about 2.5:1 to about 4:1, or about 2.7:1 to about 3.5:1, or about 2.9:1 to about 3.2:1. In some embodiments, the ratio of the number of pulses of the hafnium precursor to the number of pulses of the zirconium precursor in the first cycle is in the range of about 1.5:1 to about 2.5:1, or about 1.7:1 to about 2.3:1, or about 1.9:1 to about 2.1:1. In some embodiments, the ratio of the number of pulses of the additive precursor to the number of pulses of the hafnium precursor in the first cycle is in the range of about 1.25:1 to 1.75:1, or about 1.4:1 to about 1.6:1.

[0063] In some embodiments, the step of forming a dielectric layer includes performing one or more first cycles. In some embodiments, the first cycle includes, in order, pulses a hafnium precursor for a first period, pulses an additive precursor, pulses a hafnium precursor for a second period, and pulses a zirconium precursor. In some embodiments, the zirconium precursor is not pulsed before the second period in each first cycle. In some embodiments, the additive precursor is not pulsed before the first period or after the second period in each first cycle. In some embodiments, the first cycle includes pulses a hafnium precursor exactly once during a first period, pulses an additive precursor exactly three times, pulses a hafnium precursor exactly once during a second period, and pulses a zirconium precursor exactly once.

[0064] Without being bound by theory, the presence of a zirconium-silicon or zirconium-aluminum interface, or the presence of a zirconium silicate, zirconium silicon oxide, or zirconium aluminum oxide sublayer, is believed to lower the dielectric constant of the dielectric layer. To prevent the formation of a zirconium-silicon interface or a zirconium silicate, zirconium silicon oxide, or zirconium aluminum oxide sublayer, the pulse of the zirconium precursor can be separated from the pulse of the addition precursor by the pulse of the hafnium precursor. In this case, hafnium or hafnium oxide prevents the formation of a zirconium silicate, zirconium silicon oxide, or zirconium aluminum oxide sublayer. In an embodiment in which the hafnium precursor is pulsed at least once between each pulse of the zirconium precursor and each pulse of the addition precursor, a gate structure having a dielectric layer having a dielectric constant greater than 12 and a gate stack CET of less than about 16 A or less than about 14 A is obtained.

[0065] FIG. 4 illustrates another method (400) that may be suitable for step (130) of FIG. 1. The method (400) may be used to form a dielectric layer comprising a first sublayer and a second sublayer. In some embodiments, the first sublayer comprises hafnium silicate, hafnium silicon oxide, or hafnium aluminum oxide. In some embodiments, the second sublayer comprises zirconium oxide, zirconium silicon oxide, or zirconium silicate. The method (400) comprises the steps of pulse a hafnium precursor (sub-step (410)), pulse an additive precursor containing a silicon precursor or a hafnium precursor (sub-step (420)), pulse an oxygen reactant (sub-step (430)), optionally perform a purge (sub-step (440)), optionally repeat the sub-steps (410 to 440) one or more times (loop (450)), pulse a zirconium precursor (sub-step (460)), pulse an oxygen reactant (sub-step (470)), optionally pulse an additive precursor containing a silicon precursor or an aluminum precursor (sub-step (480)), optionally perform a purge (sub-step (490)), and optionally repeat the sub-steps (460 to 490) one or more times (loop (495)).

[0066] In some embodiments, sub-steps (410 to 440) may be performed one or more times and in any order. In some embodiments, the step of pulsed oxygen reactants (sub-step (430)) is performed after one or more of sub-steps (410 and 420). In some embodiments, the step of pulsed oxygen reactants (sub-step (430)) is performed after one or more of sub-steps (410 and 420) and before the other of sub-steps (410 and 420) is performed. In some embodiments, purging (sub-step (440)) is performed after any or all of sub-steps (410 to 430). In some embodiments, sub-steps (410 to 450) form a first sub-layer. In some embodiments, sub-steps (410 to 440) constitute a first sub-layer deposition cycle. In some embodiments, the first sublayer deposition cycle is repeated once or multiple times (loop (450)).

[0067] In some embodiments, sub-steps (460 to 490) may be performed one or more times and in any order. In some embodiments, the step of pulsed oxygen reactants (sub-step (470)) is performed after one or more of sub-steps (460 and 480). In some embodiments, the step of pulsed oxygen reactants (sub-step (470)) is performed after one or more of sub-steps (460 and 480) and before the other of sub-steps (460 and 480) is performed. In some embodiments, purging (sub-step (490)) is performed after any or all of sub-steps (460 to 480). In some embodiments, sub-steps (460 to 495) form a second sub-layer. In some embodiments, sub-steps (460 to 490) constitute a second sub-layer deposition cycle. In some embodiments, the second sublayer deposition cycle is repeated once or multiple times (loop (495)).

[0068] In some embodiments, the first sublayer is disposed directly on the interface layer. In some embodiments, the first sublayer is disposed directly on the dipole layer. In some embodiments, the second sublayer is disposed directly on the first sublayer. In some embodiments, the dielectric layer consists of the first sublayer and the second sublayer. In some embodiments, the first sublayer has a thickness of about 10 to 22 Angstroms, or about 15 to about 22 Angstroms. In some embodiments, the second sublayer has a thickness of about 3 to about 10 Angstroms, or about 3 to 7 Angstroms.

[0069] Without being bound by theory, the method (400) is believed to be able to form a dielectric layer that maintains a high band gap of hafnium silicon oxide, hafnium silicate, or hafnium aluminum oxide forming an interface layer, while increasing the dielectric constant of the dielectric layer with zirconium silicon oxide, zirconium silicate, or zirconium oxide. The method (400) is believed to be able to form a dielectric layer having a dielectric constant greater than 12 (e.g., 12 to 30, or 12 to 24, or 12 to 15, or 18 to 22).

[0070] In some embodiments of step (130) comprising some embodiments of the method (200, 300, and 400), the hafnium precursor comprises a hafnium halide or a metal-organic hafnium precursor. In some embodiments of step (130) comprising some embodiments of the method (200, 300, and 400), the zirconium precursor comprises a zirconium halide or a metal-organic zirconium precursor. For example, the hafnium precursor may be or may comprise hafnium chloride or tetrakis(dimethylamino)hafnium, and the zirconium precursor may be or may comprise zirconium chloride. In some embodiments of step (130) comprising some embodiments of the method (200, 300, and 400), the silicon precursor comprises a silane, a chlorosilane, an organic silane, a heterosilane, or silicon tetrachloride. In some embodiments, the aluminum precursor comprises triethylaluminum (TEA), trimethylaluminum (TMA), dimethylaluminum hydride (DMAH), or aluminum chloride. In some embodiments of step (130), comprising some embodiments of the method (200, 300, and 400), the oxygen reactant comprises any combination of H2O, O2, O3, H2O2, NO, NO2, or N2O.

[0071] Returning to FIG. 1, the method (100) continues to the step of forming a dipole layer (step (140)). In some embodiments, the step of forming a dipole layer (step (140)) is performed before the step of forming a dielectric layer (step (130)). In some embodiments, the step of forming a dipole layer (step (140)) is performed after the step of forming a dielectric layer (step (130)). In some embodiments, the step of forming a dipole layer is performed during the step of forming a dielectric layer (step (130)) (e.g., between individual sub-steps of the method (200, 300, or 400)). In some embodiments, the dipole layer is formed directly on the dielectric layer. In an embodiment where the dielectric layer comprises a second sub-layer comprising zirconium oxide, zirconium silicon oxide, or zirconium silicate, the dipole layer is disposed directly on the second sub-layer. In some embodiments, the dipole layer is formed directly on the interface layer. In some embodiments, the dipole layer is formed between the sublayers of the dielectric layer. The dipole layer may be formed by any suitable method including a periodic deposition process. In some embodiments, the dipole layer comprises a metal oxide, a metal nitride, or a metal oxynitride. In some embodiments, the dipole layer comprises lanthanum, aluminum, yttrium, scandium, or gallium. In some embodiments, the dipole layer comprises lanthanum oxide, aluminum oxide, yttrium oxide, scandium oxide, or gallium oxide.

[0072] The method (100) continues to the step of forming a gate electrode (step (150)). As used herein, the step of forming a gate electrode may include the step of forming an additional layer on the gate stack. Step (150) may include any deposition, etching, annealing, etc. to complete the gate stack. In some embodiments, the gate electrode comprises a metal nitride such as TiN or TaN. In some embodiments, the gate electrode comprises a conductive layer. In some embodiments, the step of forming a gate electrode (step (150)) comprises the step of forming a layer comprising a metal or metal nitride layer such as TiN directly on a dipole layer. In some embodiments, the step of forming a gate electrode (step (150)) comprises the step of forming a layer comprising TiN directly on a dielectric layer.

[0073] Various steps of the method described herein may be performed within a single reaction chamber or within multiple reaction chambers, such as the reaction chambers of a cluster tool. In some embodiments, the method (100) may be performed in a single reaction space. In some embodiments, one or more sub-steps of the method (100) may be performed in different reaction spaces or different reaction chambers.

[0074] Additionally, the carrier and / or inert gas may flow jointly throughout the entire method (100, 200, 300, 400) or during any of the sub-steps of the method (100, 200, 300, or 400). For example, the carrier and / or inert gas may be one or more of helium, argon, or nitrogen.

[0075] FIG. 5 illustrates an example of a substrate processing apparatus (500) according to one or more examples of the present disclosure. The apparatus (500) may be used to perform a method as described herein and / or to form a part of a structure or element as described herein.

[0076] In the illustrated example, the device (500) includes one or more reaction chambers (502), a hafnium precursor gas source (504), a zirconium precursor gas source (506), an additive precursor gas source (508), an oxygen reactant gas source (510), an exhaust source (522), and a controller (512).

[0077] The reaction chamber (502) may include any suitable reaction chamber, such as an atomic layer deposition (ALD) or chemical vapor deposition (CVD) reaction chamber.

[0078] The hafnium precursor gas source (504) may comprise a container and one or more hafnium precursors described herein, either alone or mixed with one or more carrier gases (e.g., inert). The zirconium precursor gas source (506) may comprise a container and one or more zirconium precursors as described herein, either alone or mixed with one or more carrier gases (e.g., inert). The additive precursor gas source (508) may comprise a container and one or more silicon or aluminum precursors as described herein, either alone or mixed with one or more carrier gases. The oxygen reactant gas source (510) may comprise one or more oxygen reactant gases as described herein. Although shown as four gas sources (504 to 510), the apparatus (500) may comprise any suitable number of gas sources. Gas supply sources (504 to 510) can be connected to the reaction chamber (502) through lines (514 to 520), each of which may include a flow controller, a valve, and a heater, etc.

[0079] The exhaust source (522) may include one or more vacuum pumps.

[0080] The controller (512) includes electronic circuits and software for selectively operating valves, manifolds, heaters, pumps, and other components included in the device (500). These circuits and components operate to introduce precursors, reactants, and gases from respective sources (504 to 510). The controller (512) may control the timing of the gas pulse sequence, the temperature of the substrate and / or reaction chamber, the pressure within the reaction chamber, and various other operations to provide suitable operation of the device (500). The controller (512) may include control software that electrically or pneumatically controls valves for controlling the flow of precursors, reactants, and purge gas into and out of the reaction chamber (502). The controller (512) may include software or hardware components, such as modules like FPGAs or ASICs that perform specific tasks. The modules may advantageously be configured to reside in an addressable storage medium of the control system and may be configured to execute one or more processes or methods as described herein.

[0081] Different configurations of the device (500) are possible, including different numbers and types of precursor and reactant sources and purge gas sources. Additionally, it will be understood that there are multiple arrangements of valves, conduits, precursor sources, and purge gas sources that can be used to achieve the purpose of selectively supplying gas into the reaction chamber (502). Furthermore, while the system is schematically depicted, many components have been omitted for the sake of simplification of the example, such components may include, for example, various valves, manifolds, purifiers, heaters, vessels, vents, and / or bypasses.

[0082] During the operation of the device (500), a substrate, such as a semiconductor wafer (not shown), is transferred, for example, from a substrate handling system to a reaction chamber (502). Once the substrate(s) are transferred to the reaction chamber (502), one or more gases, such as a precursor, a reactant, a carrier gas, and / or a purge gas, are introduced into the reaction chamber (502) from gas sources (504 to 510).

[0083] FIG. 6 illustrates a part (600) of a structure / device according to a further example of the present disclosure. The device or structure (600) comprises a substrate (610), an interface layer (620), a dielectric layer (630), a dipole layer (640), and one or more additional layers (650). In some embodiments, the device or structure (600) is a gate stack or at least a part of a gate stack. The interface layer (620) may be formed by a method described in the present disclosure. In some embodiments, the interface layer (620) comprises silicon oxide. The interface layer (620) may have a thickness of about 2 to 10 angstroms, or about 2 to 7 angstroms. The dielectric layer (630) may be formed by a method described in the present disclosure. In some embodiments, the dielectric layer (630) comprises hafnium, zirconium, silicon, and oxygen. In some embodiments, the dielectric layer (630) comprises hafnium, zirconium, aluminum, and oxygen. In some embodiments, the dielectric layer (630) comprises hafnium, zirconium, silicon, aluminum, and oxygen. In some embodiments, the dielectric layer (630) comprises zirconium-doped hafnium silicon oxide, zirconium-doped hafnium silicate, or zirconium-doped hafnium aluminum oxide. In some embodiments, the dielectric layer (630) may comprise a sublayer of hafnium oxide, silicon oxide, aluminum oxide, and zirconium oxide. In some embodiments, a sublayer comprising silicon oxide or aluminum oxide and a sublayer comprising zirconium oxide are separated by at least one sublayer of hafnium oxide. In some embodiments, the dielectric layer (630) has a thickness of about 15 Angstroms and about 25 Angstroms, or about 16 Angstroms to about 20 Angstroms. In some embodiments, the dielectric layer (630) has a dielectric constant greater than about 12, or about 12 to 30, or about 12 to 24, or about 12 to 15, or about 18 to 22.In some embodiments, the dielectric layer (630) is disposed directly on the interface layer (620). The dipole layer (640) may be formed by the method described in this disclosure. In some embodiments, the dipole layer (640) comprises a metal nitride, a metal oxynitride, or a metal oxide, such as lanthanum oxide, yttrium oxide, aluminum oxide, scandium oxide, or gallium oxide. The dipole layer (640) may have a thickness of less than 50 angstroms, or about 5 angstroms to 30 angstroms. In some embodiments, the dipole layer (640) is deposited directly on the dielectric layer (630). The additional layer (650) may include any other layer in forming the gate electrode, barrier or liner layer, and the gate stack. In some embodiments, the additional layer (650) may include TiN.

[0084] FIG. 7 illustrates a part (700) of a structure / device according to an additional example of the present disclosure. The device (700) is substantially identical to the device (600) except that the dielectric layer (730) comprises a first sublayer (730a) and a second sublayer (730b). The first sublayer (730a) is disposed directly on the interface layer (720). The second sublayer (730b) is disposed directly on the first sublayer (730a). The dipole layer (740) is disposed directly on the second sublayer (730b). The first sublayer (730a) comprises hafnium silicate, hafnium silicon oxide, or hafnium aluminum oxide. The second sublayer (730b) comprises zirconium oxide, zirconium silicon oxide, or zirconium silicate. The first sublayer (730a) may have a thickness of about 10 to 22 Angstroms, or about 15 to 22 Angstroms. The second sublayer (730b) may have a thickness of about 3 to 10 Angstroms, or about 3 to 7 Angstroms.

[0085] FIG. 8 shows a part (800) of a structure / device according to an additional example of the present disclosure. The device (800) is substantially identical to the device (600) except that a dipole layer (640) is disposed between an interface layer (620) and a dielectric layer (630).

[0086] FIG. 9 shows a part (900) of a structure / device according to an additional example of the present disclosure. The device (900) is substantially identical to the device (700) except that a dipole layer (740) is disposed between an interface layer (720) and a first sublayer (730a) of a dielectric layer (730).

[0087] FIG. 10 shows a part (1000) of a structure / device according to an additional example of the present disclosure. The device (1000) is substantially identical to the device (600) except that a dipole layer (640) is disposed as a layer between a lower layer (1030a) and a lower layer (1030b) of a dielectric layer. The lower layers (1030a and 1030b) may be any lower layer of the dielectric layer as described herein.

[0088] The exemplary embodiments of the foregoing disclosure do not limit the scope of the invention, for these embodiments are merely examples of embodiments of the invention as defined by the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of the invention. In fact, in addition to what is shown and described herein, various variations of the disclosure, such as alternative useful combinations of the described elements, may become apparent from the description to those skilled in the art. Such variations and embodiments are also intended to be within the scope of the appended claims.

Claims

Claim 1 A method for forming a gate stack, the method comprising: providing a substrate having a surface including an interface layer to a reaction chamber; and forming a dielectric layer on the interface layer by an atomic layer deposition process, wherein the step of forming the dielectric layer comprises pulses a hafnium precursor a plurality of times, pulses a zirconium precursor at least once, pulses an additive precursor at least once, and pulses an oxygen reactant, wherein the additive precursor comprises a silicon precursor or an aluminum precursor, and the hafnium precursor is pulsed at least once between each pulse of the zirconium precursor and each pulse of the additive precursor. Claim 2 A method according to claim 1, wherein the dielectric layer comprises a plurality of sublayers including a first sublayer comprising hafnium oxide, a second sublayer comprising silicon oxide or aluminum oxide, a third sublayer comprising hafnium oxide, and a fourth sublayer comprising zirconium oxide, wherein the second sublayer and the fourth sublayer do not come into direct contact with each other. Claim 3 A method according to claim 1, wherein the step of forming the dielectric layer comprises the step of performing a plurality of first cycles, wherein the first cycle comprises, in order, the step of pulsed the hafnium precursor for a first period, the step of pulsed the addition precursor, the step of pulsed the hafnium precursor for a second period, and the step of pulsed the zirconium precursor. Claim 4 A method according to paragraph 3, wherein the zirconium precursor is not pulsed before the second period, and the addition precursor is not pulsed before the first period or after the second period in the first cycle. Claim 5 A method according to claim 3, wherein the ratio of the number of pulses of the additive precursor to the number of pulses of the zirconium precursor in the first cycle is in the range of about 2.5:1 to about 4:

1. Claim 6 A method according to claim 3, wherein the ratio of the number of pulses of the hafnium precursor to the number of pulses of the zirconium precursor in the first cycle is in the range of about 1.5:1 to about 2.5:

1. Claim 7 A method according to claim 3, wherein the ratio of the number of pulses of the additive precursor to the number of pulses of the hafnium precursor in the first cycle is in the range of about 1.25:1 to 1.75:

1. Claim 8 A method according to claim 1, further comprising the step of forming a dipole layer directly on the dielectric layer. Claim 9 In claim 8, the method wherein the dipole layer comprises lanthanum oxide, aluminum oxide, yttrium oxide, scandium oxide, or gallium oxide. Claim 10 A method according to claim 1, further comprising the step of forming a dipole layer directly on the interface layer. Claim 11 A method according to claim 1, wherein the ratio of oxygen atoms to the sum of hafnium, zirconium, aluminum, and silicon atoms is in the range of about 1.6:1 to about 2.5:

1. Claim 12 A method according to claim 1, wherein the additive precursor comprises a silicon precursor. Claim 13 A method for forming a gate stack, the method comprising: providing a substrate having a surface including an interface layer to a reaction chamber; and forming a dielectric layer on the interface layer by an atomic layer deposition process, wherein the dielectric layer comprises a first sublayer comprising hafnium silicate, hafnium silicon oxide, or hafnium aluminum oxide disposed directly on the interface layer, and a second sublayer comprising zirconium oxide, zirconium silicon oxide, or zirconium silicate disposed directly on the first sublayer. Claim 14 A method according to claim 13, further comprising the step of forming a dipole layer directly on the second sublayer, wherein the dipole layer comprises lanthanum oxide, aluminum oxide, yttrium oxide, scandium oxide, or gallium oxide. Claim 15 In claim 13, the method wherein the dielectric layer has a thickness of about 15 Angstroms to about 25 Angstroms. Claim 16 In claim 13, the method wherein the interface layer comprises silicon oxide. Claim 17 In claim 13, the method wherein the dielectric layer has a dielectric constant in the range of about 12 to about 30. Claim 18 A method for forming a gate stack, the method comprising: providing a substrate having a surface including an interface layer to a reaction chamber; and forming a dielectric layer on the interface layer by an atomic layer deposition process, wherein the step of forming the dielectric layer comprises pulses a hafnium precursor a plurality of times, pulses a zirconium precursor at least once, pulses an addition precursor at least once, and pulses an oxygen reactant, wherein the addition precursor comprises a silicon precursor or an aluminum precursor, and the dielectric layer comprises zirconium-doped hafnium silicon oxide, zirconium-doped hafnium silicate, or zirconium-doped hafnium aluminum oxide, and the ratio of the number of pulses of the hafnium precursor to the number of pulses of the zirconium precursor during the formation of the dielectric layer is about 30:1 to about 7:

1. Claim 19 In paragraph 18, the method wherein the additive precursor comprises a silicon precursor. Claim 20 A method according to claim 18, further comprising the step of forming a dipole layer directly on the dielectric layer.

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