Data converter based on semiconductor devices

Abstract

The present invention is a data converter based on a semiconductor device. The data converter according to the present invention is configured to correspond one-to-one with K bits constituting a digital code and comprises K bit processing units sequentially connected in a pipeline form. Each bit processing unit comprises: a signal generation module including a semiconductor device having a threshold voltage or conductance set according to the position of the bit; a signal transmission module that outputs one of a bit-level input voltage and a bit-level residual voltage according to an output selection signal; a signal conversion module that converts the bit-level residual voltage into a binary signal and outputs it; and a mode selection module configured to operate as either an ADC or a DAC by controlling a signal path according to an operation mode selection signal. Since the data converter according to the present invention enables low power consumption and high-speed operation, it can be particularly advantageously applied to sensor interfaces, artificial intelligence accelerators, neuromorphic systems, and in-memory computing environments.

Description

Technology Field

[0001] The present invention relates to a data converter, and more specifically, to a data converter based on semiconductor devices configured by arranging semiconductor devices having different threshold voltages in a pipeline form, which can be implemented in a small area and operated at low power, and can be used in various applications including neuromorphic systems to improve performance. Background Technology

[0002] An Analog-to-Digital Converter (ADC) is an electronic device that converts analog signals into digital signals. Signals detected by sensors in the natural world, such as temperature and voltage, are analog signals. An ADC circuit converts these analog signals into digital signals that can be processed by electronic devices, such as computers and control units, and outputs them. Recently, with the widespread commercialization of advanced electronic devices such as IoT and neuromorphic systems, the demand for ADCs with low power consumption and small area characteristics is increasing. In response to this demand, ADCs with various structures are being developed.

[0003] U.S. Patent Publication No. 2009-0091483 discloses a Flash ADC structure as one of the ADC types. FIG. 1 is a structural diagram illustrating a Flash ADC scheme. As shown in FIG. 1, the Flash ADC is 2 KAn ADC operation is performed to convert an analog signal into a digital signal using a comparator bank consisting of several comparators. The comparators of the Flash ADC receive a reference voltage corresponding to a reference value and an analog voltage to be distinguished as inputs. The comparators then compare the magnitudes of the two input voltages and output the result as a digital code. Flash ADCs with this structure continue to be widely used in applications requiring high speed and low latency.

[0004] However, conventional Flash ADCs with the aforementioned structure use a large number of comparators, resulting in high power consumption during operation. Consequently, conventional Flash ADCs are difficult to use in low-power applications. Furthermore, because conventional Flash ADCs use a large number of comparators, they require a large chip area. For this reason, ADCs with the aforementioned structure are difficult to use in small-scale applications.

[0005] Furthermore, the resolution of conventional Flash ADCs is limited by the number of comparators used. Therefore, increasing the resolution of Flash ADCs requires increasing the number of comparators; this leads to problems such as increased circuit complexity, higher manufacturing costs, and increased power consumption.

[0006] As such, when the number of bits increases, the device area and power consumption of an ADC having the aforementioned structure increase exponentially, and it is difficult to use in applications requiring high resolution.

[0007] U.S. Patent No. 7965218 discloses a Successive Approximation Register (SAR) ADC structure. FIG. 2 is a structural diagram illustrating a SAR ADC scheme according to the prior art. As shown in FIG. 2, the SAR ADC performs ADC operations by utilizing a single comparator, a DAC, a logic circuit, a register, etc. Generally, bits are determined sequentially starting from the Most Significant Bit (MSB). The SAR ADC uses a single comparator, and the DAC uses multiple capacitors of different sizes and controls the output value of the DAC using the charge sharing principle. The results of bit determination up to that point are stored in the register, and based on the results, the DAC adjusts the reference voltage of the comparator through the logic circuit. By repeating the aforementioned process, bit values ​​are determined from the MSB to the Least Significant Bit (LSB).

[0008] Although the SAR ADC with the aforementioned structure provides high resolution, it still suffers from the problem of requiring a large circuit area and high power consumption. Prior art literature

[0009] U.S. Patent Publication No. US 2009 / 0091483, U.S. Registered Patent Publication No. US 7965218, Korean Patent Publication No. 10-2023-0020295, Korean Patent Publication No. 10-2023-0018972 The problem to be solved

[0010] To solve the aforementioned problems, the present invention aims to provide a data converter that can be used in various systems, including neuromorphic networks, as well as significantly reducing circuit area and power consumption by configuring it to perform analog-to-digital conversion and digital-to-analog conversion operations using a structure in which memory elements having different threshold voltages are connected in a pipeline form. means of solving the problem

[0011] To achieve the aforementioned technical objectives, a pipeline-type data converter according to the first aspect of the present invention is a data converter based on a semiconductor device that converts an analog signal into a digital code composed of K bits (where K is a natural number) or converts a digital code into an analog signal, and comprises K bit processing units sequentially connected in a pipeline form, configured to correspond one-to-one with the K bits constituting the digital code. Each bit processing unit includes a semiconductor device having a threshold voltage or conductance set according to the position of the corresponding bit within the digital code, and a bit-level input voltage is applied to the semiconductor device, and the bit-level input voltage (B_IN) and the threshold voltage (V) of the memory device th A signal generation module configured to generate a bit level residual voltage (B_RES) determined according to the relationship of ); and a signal transmission module configured to include one or more switching elements and output either the bit level input voltage and the bit level residual voltage of the signal generation module as a bit level output voltage according to an output selection signal; wherein the bit level input voltage of a bit processing unit (MSB bit processing unit) that processes the most significant bit of a digital code is a preset starting voltage or an analog signal to be converted, and the bit level input voltages of the remaining bit processing units are bit level output voltages of the signal transmission module included in the bit processing unit of the previous stage.

[0012] A pipeline-type data converter according to the first sun having the aforementioned features is a Digital-to-Analog Converter (DAC) that converts a digital code into an analog signal, and the bit-level input voltage of the bit processing unit that processes the most significant bit of the digital code is a preset starting voltage, and the signal transmission module of each bit processing unit is provided with the code of the corresponding bit within the digital code or the inverted code of said code as an output selection signal, and the bit-level output voltage of the signal transmission module of the bit processing unit that processes the least significant bit of the digital code forms an analog signal corresponding to the digital code.

[0013] A pipeline-type data converter according to the first sun having the aforementioned features is an Analog-to-Digital Converter (ADC) that converts an analog signal into a digital code, and each bit processing unit further comprises a signal conversion module configured to convert a bit-level residual voltage (B_RES) output from a signal generation module into a binary signal and output it; wherein the bit-level input voltage of the bit processing unit processing the most significant bit of the digital code is an analog signal, and the signal conversion module of each bit processing unit is configured to output the code of the corresponding bit within the digital code and provide it to a signal transmission module as an output selection signal.

[0014] A pipeline-type data converter according to the first sun having the aforementioned features is a converter capable of selectively operating as either an ADC or a DAC, and each bit processing unit further comprises: a signal conversion module configured to convert a bit-level residual voltage output from a signal generation module into a binary signal and output it; and a mode selection module disposed between the signal conversion module and the signal transmission module, receiving an operation mode selection signal and controlling a signal path according to the input operation mode selection signal so that the converter operates as either an ADC or a DAC; wherein the mode selection module is preferably configured such that when an analog-to-digital conversion mode is selected, the output signal of the signal conversion module for the analog signal to be converted is provided to the signal transmission module as an output selection signal, and when a digital-to-analog conversion mode is selected, the code of the corresponding bit of the digital code to be converted is provided to the signal transmission module as an output selection signal.

[0015] In a pipeline-type data converter according to the first aspect having the aforementioned features, each bit processing unit preferably further comprises a stabilization module disposed between the output terminal and the ground terminal of a signal generation module, the stabilization module being composed of a device or circuit that provides a constant current to a signal generation module.

[0016] In a pipeline-type data converter according to the first aspect having the aforementioned features, the signal generation module of the bit processing unit is preferably composed of a semiconductor device having non-volatile memory characteristics capable of varying a threshold voltage or conductance, or is composed of one of a flash memory device, a resistance change memory device, a phase change memory device, a ferroelectric memory device, a magnetoresistance memory device, or a FET (Field Effect Transistor).

[0017] In a pipeline-type data converter according to the first sun having the aforementioned features, the signal conversion module of the bit processing unit is preferably composed of one of an inverter circuit, a buffer circuit, and a sense amplifier having a preset switching voltage.

[0018] In a pipeline-type data converter according to the first sun having the aforementioned features, the signal transmission module comprises: a first switching element configured to output a bit-level residual voltage of a signal generation module as a bit-level output voltage; a second switching element configured to output a bit-level input voltage of a bit processing unit as a bit-level output voltage; and a selection circuit configured to drive one of the first switching element and the second switching element according to an output selection signal; and the output selection signal of the selection circuit is preferably either a code of a corresponding bit in a digital code or a binary signal converted from the bit-level residual voltage of the signal generation module.

[0019] In a pipeline-type data converter according to the first sun having the aforementioned features, it is more preferable that the first and second switching elements of the signal transmission module are composed of either a transmission gate (TG) or a simple single-pass gate (Single Pass Gate).

[0020] In a pipeline-type data converter according to the first sun having the aforementioned features, the mode selection module is preferably configured to include one of a digital multiplexer, an analog multiplexer, and a tri-state buffer, or is configured as a combination of multiple NAND gate elements.

[0021] A pipeline-type data converter according to the first aspect having the aforementioned features preferably further comprises a threshold voltage adjustment module for adjusting or resetting the threshold voltage of memory elements included in the signal generation modules of the bit processing units.

[0022] To achieve the aforementioned technical objectives, a pipeline-type data converter according to a second aspect of the present invention comprises: a plurality of conversion stages sequentially connected in a pipeline form, configured to convert an analog signal into a digital code composed of K bits (where K is a natural number) based on a semiconductor device, and configured to convert a stage input voltage into a digital code to generate a partial digital code; and an output code generation module configured to generate a final digital code corresponding to an analog signal based on the partial digital codes output from the plurality of conversion stages. Each conversion stage comprises: a signal generation module configured to convert a stage input voltage into a digital code to generate a partial digital code using semiconductor devices having different threshold voltages or conductances; and a signal transmission module configured to generate a stage output voltage based on the stage input voltage and the digital conversion result of the signal generation module. The stage input voltage of the first conversion stage is an analog signal to be converted, and the stage input voltages of the remaining conversion stages are stage output voltages generated from the previous conversion stage.

[0023] In a pipeline-type data converter according to the second sun having the aforementioned features, the partial digital code generated by the signal generation module of each conversion stage is a thermometer code, and each conversion stage preferably further includes a code conversion module configured to convert the partial digital code in the form of a thermometer code generated from the signal generation module into a binary code and output it.

[0024] Furthermore, in a pipeline-type data converter according to the second aspect having the aforementioned features, it is more preferable that the output code generation module is configured to generate a final digital code based on binary codes output from code conversion modules included in a plurality of conversion stages.

[0025] In a pipeline-type data converter according to the second sun having the aforementioned features, it is preferable that the stage output voltage is a residual voltage in which the stage input voltage is not converted by a partial digital code in a signal generation module included in the conversion stage.

[0026] In a pipeline-type data converter according to the second aspect having the aforementioned features, the signal generation module included in the conversion stage comprises a plurality of semiconductor devices having different threshold voltages or conductances, a stage level voltage is applied to the plurality of semiconductor devices, and the plurality of semiconductor devices are each configured to generate binary values ​​based on the relationship between the stage level voltage and the threshold voltage, and the signal generation module is preferably configured to generate a partial digital code based on the binary values ​​generated by the plurality of semiconductor devices.

[0027] In a pipeline-type data converter according to the second aspect having the aforementioned features, the signal generation module included in the conversion stage is preferably composed of a semiconductor device having non-volatile memory characteristics capable of varying the threshold voltage or conductance, or is composed of one of a flash memory device, a resistance change memory device, a phase change memory device, a ferroelectric memory device, a magnetoresistance memory device, or a FET (Field Effect Transistor).

[0028] In a pipeline-type data converter according to the second sun having the aforementioned features, the signal transmission module included in the conversion stage preferably includes one of a digital multiplexer, an analog multiplexer, and a tri-state buffer, which selects one of a plurality of input channels by a selection signal and provides it as a single output channel.

[0029] In a pipeline-type data converter according to the second sun having the aforementioned features, the selection signal is a partial digital code based on the digital conversion result of a signal generation module, and the signals input to a plurality of input channels each include voltages output from a plurality of semiconductor devices included in the signal generation module and a stage input voltage, and it is more preferable that the output channel is configured to detect a residual voltage that the stage input voltage was not converted by the partial digital code based on the selection signal and output it as a stage output voltage.

[0030] A sequential approximation (SAR) type data converter according to a third aspect of the present invention for achieving the aforementioned technical problem comprises: a sequential approximation (SAR) type data converter based on a semiconductor device that converts an analog input signal into a digital code composed of K bits (where K is a natural number), and comprises a plurality of semiconductor devices arranged to correspond to each bit of the digital code and having different threshold voltages, wherein an input signal is applied to one selected among the plurality of semiconductor devices and configured to generate a bit-level output voltage for the input signal based on the relationship between the input signal and the threshold voltage; a signal conversion module configured to convert the bit-level output voltage output from the signal generation module into a binary signal and output a binary value for the corresponding bit of the digital code; and a SAR register configured to store the binary value output from the signal conversion module at the corresponding bit position of the digital code. The system includes a SAR control unit configured to generate a control signal for sequentially selecting semiconductor devices included in a signal generation module based on a bit value stored in a SAR register according to a preset sequential approximation logic; and is characterized in that the signal generation module sequentially generates bit-level output voltages for the input signal by sequentially applying an input signal to the semiconductor devices included in the signal generation module according to the control signal of the SAR control unit.

[0031] In a data converter of a sequential approximation method according to the third aspect having the aforementioned features, semiconductor devices included in a signal generation module are connected in parallel, and according to a control signal of a SAR control unit, an input signal is applied only to a selected semiconductor device and a turn-off signal is applied to the remaining unselected semiconductor devices, so that a bit level output voltage of the signal generation module is generated based on the relationship between the threshold voltage of the selected semiconductor device and the applied input signal.

[0032] In a data converter of a sequential approximation method according to the third aspect having the aforementioned features, semiconductor devices included in a signal generation module are connected in series to form a string structure, and according to a control signal of a SAR control unit, an input signal is applied to a selected semiconductor device and a pass voltage is applied to the remaining unselected semiconductor devices, and a bit-level output voltage of the signal generation module is generated based on the relationship between the threshold voltage of the selected semiconductor device and the applied input signal.

[0033] A data converter of a sequential approximation method according to a third sun having the aforementioned features preferably further comprises a stabilization module disposed between the output terminal and the ground terminal of a signal generation module, wherein the data converter comprises elements configured to provide a constant current to semiconductor elements included in a signal generation module.

[0034] In a data converter of a sequential approximation method according to the third aspect having the aforementioned features, the semiconductor devices included in the signal generation module are preferably composed of semiconductor devices having non-volatile memory characteristics capable of varying threshold voltage or conductance, or are composed of one of a flash memory device, a resistance change memory device, a phase change memory device, a ferroelectric memory device, a magnetoresistance memory device, a field effect transistor (FET), or a ferroelectric tunnel junction (FTJ).

[0035] In a data converter of a sequential approximation method according to the third sun having the aforementioned features, the signal conversion module is preferably composed of one of an inverter circuit having a preset switching voltage, a buffer circuit, and a sense amplifier.

[0036] In a data converter of a sequential approximation method according to a third aspect having the aforementioned features, the signal generation module preferably further includes a plurality of selection elements connected in a one-to-one correspondence with each of the plurality of semiconductor elements.

[0037] In a data converter of a sequential approximation method according to the third aspect having the aforementioned features, the SAR control unit applies an input signal to a plurality of semiconductor elements included in a signal generation module and sequentially activates selected elements connected to selected semiconductor elements according to a control signal, thereby allowing the signal generation module to sequentially output bit-level output voltages for the input signal.

[0038] In a data converter of a sequential approximation method according to the third aspect having the aforementioned features, the selection element of the signal generation module is preferably composed of a transmission gate (TG) or a switching element. Effects of the invention

[0039] The data converter according to the present invention having the aforementioned configuration has a threshold voltage or conductance control structure based on a non-volatile memory device, thereby allowing it to be naturally combined with the analog computation characteristics required in-memory computing and neuromorphic systems. Accordingly, the structure according to the present invention can be effectively applied to next-generation artificial intelligence and neuromorphic computing systems.

[0040] In addition, the data converter according to the present invention can precisely set the threshold voltage corresponding to each bit because the semiconductor devices included in the signal generation module have non-volatile memory characteristics capable of varying the threshold voltage or conductance. Through this, the linearity and accuracy of the analog output voltage corresponding to the digital code can be improved.

[0041] Meanwhile, the data converter according to the first, second, third, and fourth embodiments of the present invention has a structure in which K bit processing units are sequentially connected in a pipeline form, so that the operation of each bit processing unit proceeds stepwise based on a clock signal. Accordingly, the total conversion delay time is reduced, making high-speed digital-to-analog conversion possible.

[0042] In addition, in the data converter according to the first, second, third, and fourth embodiments of the present invention, each bit processing unit generates a bit-level residual voltage based on the difference between the threshold voltage of a semiconductor device and the bit-level input voltage, so analog conversion can be performed without using a conventional weighted resistor network or a large-scale capacitor array. Accordingly, the circuit structure is simplified and the implementation complexity is reduced.

[0043] In addition, the data converter according to the first and third embodiments of the present invention adopts a structure that sets the input voltage of the MSB bit processing unit as the start voltage (IN), thereby allowing the reference offset of the final output voltage (DACOUT) to be circuitously adjusted. Accordingly, it is possible to accommodate various output voltage ranges while maintaining the same circuit structure.

[0044] In addition, in the data converter according to the first, second, third, and fourth embodiments of the present invention, the signal transmission module selectively transmits only one of the bit-level input voltage or the bit-level residual voltage according to the digital code, thereby suppressing unnecessary current consumption. Accordingly, the power consumption of the entire system can be reduced.

[0045] Furthermore, the structure of the data converter according to the first, second, third, and fourth embodiments of the present invention can be implemented as a DAC structure that converts a digital code into an analog signal, and can also be extended and applied as an analog-to-digital converter (ADC) structure using the same threshold voltage-based comparison and residual transfer principles. Accordingly, both a DAC and an ADC can be implemented based on a single basic architecture.

[0046] In particular, the data converter according to the fourth embodiment of the present invention enables high-resolution digital conversion that exceeds the resolution limit achievable in a single conversion step by converting an analog input signal into a digital signal stepwise in a plurality of conversion steps. Furthermore, since the approximate magnitude of the input signal is determined in the initial conversion step and finer voltage changes are converted based on residual voltage in subsequent conversion steps, precise digital representation from the upper bit to the lower bit is possible overall.

[0047] In addition, the data converter according to the fourth embodiment of the present invention implements resolution by distributing it into multiple stages, thereby allowing the circuit size of each conversion stage to be relatively simplified. Accordingly, the circuit area is reduced, the difficulty of design is alleviated, and the integration density in large-scale integrated circuits can be improved.

[0048] Meanwhile, the data converter according to the 5th, 6th, and 7th embodiments of the present invention generates a bit-level output voltage based on the relationship between the threshold voltage of a semiconductor device and the magnitude of an input signal, so that the voltage comparison operation is performed immediately based on the physical characteristics of the semiconductor device. Accordingly, high-speed analog-to-digital conversion is possible compared to conventional computation-based comparison methods.

[0049] Furthermore, since the data converter according to the 5th, 6th, and 7th embodiments of the present invention generates a bit-level output voltage based on the relationship between the threshold voltage of the semiconductor device and the magnitude of the input signal, the comparison operation is performed directly by the physical characteristics of the semiconductor device. Accordingly, high-speed sequential approximation conversion is possible without using a separate high-speed comparator.

[0050] Furthermore, the data converter according to the 5th, 6th, and 7th embodiments of the present invention can program and erase the threshold voltages of semiconductor devices, thereby compensating for characteristic variations due to process deviations, temperature changes, or aging. Additionally, by adjusting the threshold voltage distribution, the resolution characteristics or non-linear characteristics of the ADC can be controlled design-wise.

[0051] In addition, the data converter according to the 5th, 6th, and 7th embodiments of the present invention maintains the basic structure of the SAR register and SAR control unit, while replacing the comparator and DAC functions with a semiconductor device-based signal generation module, thereby allowing the existing SAR ADC design assets to be utilized as is.

[0052] In addition, the data converter according to the 5th, 6th, and 7th embodiments of the present invention facilitates resolution expansion by increasing the number of semiconductor devices included in the signal generation module, and can support various resolutions and operating modes by changing the SAR control logic. Due to the structural features described above, the data converter according to the present invention can be particularly advantageously applied to sensor interfaces, artificial intelligence accelerators, neuromorphic systems, and in-memory computing environments that require low power consumption and high-speed operation. Brief explanation of the drawing

[0053] Figure 1 is a structural diagram illustrating a Flash ADC Scheme according to conventional technology. Figure 2 is a structural diagram illustrating a SAR ADC scheme according to conventional technology. FIG. 3 is a circuit diagram illustrating the structure of a data converter according to a first embodiment of the present invention. FIG. 4 is a circuit diagram illustrating a data converter according to a second embodiment of the present invention. FIG. 5 is a circuit diagram illustrating another embodiment of a signal transmission module in a data converter according to a second embodiment of the present invention. FIG. 6 is a circuit diagram illustrating the structure of a data converter according to a third embodiment of the present invention. FIG. 7 is a circuit diagram illustrating a data converter according to a fourth embodiment of the present invention. FIG. 8 is a circuit diagram illustrating an example of a signal generation module (600) included in each conversion stage in a data converter according to the fourth embodiment of the present invention. Figure 9 is a circuit diagram illustrating a SAR-type data converter according to conventional technology. FIG. 10 is a circuit diagram illustrating a data converter based on SAR logic according to the fifth embodiment of the present invention. FIG. 11 is a circuit diagram illustrating a sequential approximation type data converter according to the 6th embodiment of the present invention. FIG. 12 is a circuit diagram illustrating a sequential approximation type data converter according to the seventh embodiment of the present invention. Specific details for implementing the invention

[0054] A data converter based on semiconductor devices according to the present invention is characterized by utilizing a structure in which semiconductor devices having different threshold voltages are sequentially arranged in a pipeline form. The data converter according to the present invention converts an input analog signal into a digital code and outputs it, and the digital-to-analog converter according to the present invention converts an input digital code into an analog signal and outputs it. Furthermore, the data converter according to the present invention may be configured to selectively operate as either an ADC or a DAC by including an operation mode selection function. Herein, the digital code is composed of a binary code consisting of K bits (where K is a natural number). Hereinafter, the structure and operation of a data converter according to preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Meanwhile, for convenience of explanation, this specification focuses on the case where the semiconductor device is composed of an NMOS-based device. However, this is merely illustrative, and the technical concept of the present invention is not limited thereto. That is, the semiconductor device is not limited to an NMOS-based device but can be implemented with a transistor structure of various polarities, including a PMOS-based device.

[0056] < 1st Example >

[0057] Hereinafter, the structure and operation of a pipeline-type data converter according to the first embodiment of the present invention will be described in detail with reference to the attached drawings. The data converter according to the first embodiment of the present invention is a digital-to-analog converter and is characterized by converting a digital code into an analog voltage signal and outputting it based on semiconductor devices sequentially connected in a pipeline form. Here, the digital code is composed of a binary code consisting of K bits (where K is a natural number). Meanwhile, for convenience of explanation, this specification focuses on the case where the semiconductor device is composed of an NMOS-based device. However, this is merely illustrative, and the technical concept of the present invention is not limited thereto. That is, the semiconductor device is not limited to an NMOS-based device but can be implemented with a transistor structure of various polarities, including a PMOS-based device.

[0058] FIG. 3 is a circuit diagram illustrating the structure of a digital-to-analog converter according to a first embodiment of the present invention. Referring to FIG. 3, the digital-to-analog converter (3) according to the first embodiment of the present invention comprises K bit processing units (30-1, 30-2, …, 30-k) connected in a pipeline form. The K bit processing units (30-1, 30-2, …, 30-k) are each configured to correspond one-to-one with K bits constituting a digital code and are connected sequentially in a pipeline form. Each bit processing unit comprises a signal generation module (300) and a signal transmission module (310), and may further comprise a stabilization module (320).

[0059] The bit level input voltage (B_IN[1]) of the bit processing unit (MSB bit processing unit; 30-1) that processes the most significant bit of the digital code is set to a preset starting voltage (IN). Then, the bit level input voltages (B_IN[2], B_IN[3], …, B_IN[k]) of the remaining bit processing units (30-2, 30-3, …, 30-k) excluding the MSB bit processing unit are sequentially transmitted with bit level output voltages (B_OUT[1], B_OUT[2], …, B_OUT[k-1]) from the signal transmission module included in the bit processing unit of the previous stage. Additionally, the bit level output voltage (B_OUT[k]) output from the signal transmission module of the bit processing unit (LSB bit processing unit; 30-k) that processes the least significant bit of the digital code is an analog signal corresponding to the digital code to be converted, and forms the output voltage (DACOUT) of the digital-to-analog converter.

[0060] At this time, the bit-level input voltage of the MSB bit processing unit is sequentially transmitted to each bit processing unit with respect to the start voltage (IN), either reduced by or maintained by the threshold voltage of the semiconductor device included in the signal generation module according to the digital code (Code[1:k]), and finally, a bit-level output voltage (B_OUT[k]) is generated. Accordingly, the digital-to-analog converter according to the first embodiment of the present invention can adjust the offset of the final output voltage (DACOUT) using the start voltage (IN). Meanwhile, if the semiconductor device is implemented as a PMOS-based memory device, it is sequentially transmitted to each bit processing unit with a state increased by or maintained by the threshold voltage of the semiconductor device, and finally, a bit-level output voltage can be generated.

[0061] K bit processing units (30-1, 30-2, …, 30-k) are each configured to correspond one-to-one with the K bits constituting the digital code. The signal generation modules (300) of the K bit processing units (30-1, 30-2, …, 30-k) each include semiconductor devices (M[1], M[2], …, M[k]). The semiconductor devices (M[1], M[2], …, M[k]) included in the bit processing units each have a threshold voltage (V) determined according to the position of the corresponding bit within the digital code. th1 , V th2 , … , V thk The gate electrode of the semiconductor device of the signal generation module (300) can be configured to receive a bit level input voltage and generate a bit level residual voltage (B_RES[1], B_RES[2], … , B_RES[k]) determined according to the relationship between the bit level input voltage and the threshold voltage of the semiconductor device. Here, the bit level residual voltage (B_RES) can be defined as the difference between the bit level input voltage and the threshold voltage.

[0062] The semiconductor devices (M[1], M[2], … , M[k]) included in the signal generation modules (300) may be composed of semiconductor devices having non-volatile memory characteristics capable of varying threshold voltage or conductance, or may be composed of one of a flash memory device, a resistance change memory device, a phase change memory device, a ferroelectric memory device, a magnetoresistance memory device, or a FET (Field Effect Transistor). Additionally, the first semiconductor device (M1) may be composed of a two-terminal device such as an RRAM, PRAM, or FJT (Ferroelectric Tunnel Junction). A detailed description of various methods for varying the threshold voltage or conductance of the first semiconductor device will be provided later.

[0063] The threshold voltage (V) of the semiconductor device included in the signal generation module (300) having the above-described configuration thThe operating state of the signal generation module (300), i.e., the current driving capability, is determined by the relationship between the bit level input voltage (B_IN) applied to the gate terminal and the signal generation module (300). Specifically, when the bit level input voltage applied to the semiconductor device included in the signal generation module (300) is greater than the threshold voltage, the device of the signal generation module (300) is turned on and outputs a bit level residual voltage (B_RES). On the other hand, when the bit level input voltage applied to the semiconductor device included in the signal generation module (300) is less than the threshold voltage, the semiconductor device of the signal generation module (300) is turned off.

[0064] The signal transmission module (310) may be configured to include one or more switching elements to output either a bit level input voltage (B_IN) and a bit level residual voltage (B_RES) of the signal generation module according to the code of the corresponding bit (Code[1], Code[2], …, Code[k]) in the digital code.

[0065] The signal transmission module (310) may include a first switching element (312), a second switching element (314), and a selection circuit (316). The first switching element (312) (NP1) may be positioned between the output terminal of the signal generation module and the output terminal of the bit processing unit, and configured to output the bit level residual voltage (B_RES) of the signal generation module to the output terminal of the bit processing unit. The second switching element (314) (NP2) may be positioned between the input terminal and the output terminal of the bit processing unit, and configured to output the bit level input voltage (B_IN) of the bit processing unit to the output terminal of the bit processing unit.

[0066] The selection circuit (316) may be configured to selectively drive one of the first switching element and the second switching element according to the output selection signal. At this time, the signal transmission module (310) of each bit processing unit receives the code of the corresponding bit within the digital code and uses it as the output selection signal. Accordingly, the output selection signal input to the signal transmission module (310) of each bit processing unit may consist of the value of the corresponding bit within the digital code (Code[1:k]) to be converted.

[0067] The selection circuits (316) of the signal transmission modules (310) of the K bit processing units can be implemented as an inverter element (INV). An output selection signal is applied to the gate electrode of the first switching element (312) and to the input of the inverter element included in the selection circuit (316), and the output of the inverter element can be configured to be applied to the gate electrode of the second switching element (314). Accordingly, the output selection signal is applied to the gate electrode of the first switching element (312), and the inverted signal of the output selection signal is applied to the gate electrode of the second switching element (314), so that either the first switching element or the second switching element is selectively driven.

[0068] The first switching element (312) and the second switching element (314) of the signal transmission module (310) may be configured as either a transmission gate (TG) or a simple single-pass gate. The first switching element and the second switching element are selected and driven mutually exclusively according to an output selection signal. Specifically, when the output selection signal code (Code[1]) is '1', the first switching element (312) is driven in the ON state, and the second switching element (314) is maintained in the OFF state. Accordingly, a bit level residual voltage (B_RES) can be applied to the output terminal of the bit processing unit by the driving of the first switching element. On the other hand, when the output selection signal code (Code[1]) is '0', the first switching element (312) is maintained in the OFF state, and the second switching element (314) is driven in the ON state. Accordingly, by driving the second switching element, a bit level input voltage (B_IN) can be applied to the output terminal of the bit processing unit.

[0069] The stabilization module (320) is composed of elements capable of providing a constant current to the signal generation module and can be placed between the output terminal and the ground terminal of the signal generation module. The stabilization module (320) can be composed of a single MOSFET element, a plurality of sequentially connected MOSFET elements, a transmission gate element, a resistor, or a non-volatile memory element. If the stabilization module is composed of a single transistor, the Rout can be increased to improve stabilization.

[0070] As described above, the semiconductor devices (M[1], M[2], …, M[k]) included in the signal generation module (300) are composed of devices capable of varying the threshold voltage or conductance, and depending on the type of device, the threshold voltage or conductance may be fixedly set during the design phase or varied in various ways during the driving phase using non-volatile memory characteristics. Accordingly, the semiconductor devices (M[1], M[2], …, M[k]) included in the signal generation module (300) may be implemented as 1) devices having non-volatile memory characteristics capable of varying the threshold voltage or conductance, or 2) semiconductor devices that fix the threshold voltage or conductance by adjusting the coupling ratio, etc., during the design phase.

[0071] Semiconductor devices having non-volatile memory characteristics that can be used as a signal generation module (300) include flash memory devices, resistance change memory devices, phase change memory devices, ferroelectric memory devices, magnetoresistance memory devices, etc. Below, a method for adjusting the threshold voltage or conductance for each device that can constitute the semiconductor device of the signal generation module (300) is described in detail.

[0072] Flash memory devices can control threshold voltage or conductance by injecting electrons or holes into the gate insulating layer by applying a voltage pulse. The electrons or holes injected into the gate insulating layer affect the channel. Utilizing this characteristic, in the case of n-channel flash memory devices, the threshold voltage of the device can be controlled by raising the threshold voltage by injecting electrons or lowering the threshold voltage by injecting holes.

[0073] A resistance change memory device is composed of a metal-insulator-metal structure, and can change conductance by inducing a change in resistance in the intermediate insulating layer by applying a voltage pulse. At this time, a voltage pulse can be applied in a direction that increases the conductance or in a direction that decreases the conductance.

[0074] Ferroelectric memory devices can change threshold voltage or conductance by applying voltage pulses to a ferroelectric insulating film to form an electric field within the film. In the case of field-effect transistors that utilize a ferroelectric insulating film as a gate insulating film, the electric field can be formed in a direction that increases conductance in the ferroelectric insulating film, or the electric field can be controlled in a direction that decreases conductance. Ferroelectric tunnel junction devices can control conductance by adjusting the carrier tunneling probability through the direction and strength of the electric field in the ferroelectric insulating film.

[0075] A magnetoresistive memory device is composed of a fixed layer, an insulating film, and a free layer, and both the fixed layer and the free layer are magnetic. The magnetization direction of the fixed layer is fixed, while the magnetization direction of the free layer can be changed. In this case, when current is applied to the magnetoresistive memory device in the direction from the fixed layer to the free layer, the magnetization direction of the free layer becomes the same as that of the fixed layer, and the conductance increases. On the other hand, when current is applied to the magnetoresistive memory device in the direction opposite to that from the fixed layer to the free layer, the magnetization direction of the free layer becomes different from that of the fixed layer, and the conductance decreases. In this way, the conductance of the magnetoresistive memory device can be controlled using current.

[0076] When the signal generation module (300) is composed of a semiconductor device having a gate electrode or a control gate electrode, the threshold voltage of each device can be adjusted during the device and surrounding wiring design (physical layout) stage. As an example of a method for this, when designing the device, the physical layout is adjusted to have components that act as a floating gate and a control gate, and the threshold voltage or conductance can be set by adjusting the coupling ratio between these gates. In addition, when the device does not have a floating gate or a charge storage layer, the threshold voltage or conductance can be set by adjusting the coupling between the gate and the surrounding metal wiring.

[0077] When designing the components that constitute the signal generation module (300), if the physical layout is adjusted to have components that act as floating gates and control gates, the coupling ratio in which the voltage of the control gate is transmitted to the floating gate varies depending on the spacing or area ratio between the two gates. Through this, even semiconductor devices without memory functions can have their threshold voltage or conductance set to various desired values.

[0078] In the case of a semiconductor device that is not equipped with a floating gate, the threshold voltage can be controlled by adjusting the coupling ratio between the gate electrode and the surrounding electrode. In this case, the gate electrode is designed to act as a floating gate, and the surrounding electrode acts as a control gate. Here, the threshold voltage or conductance can be changed by adjusting the coupling ratio between the floating gate and the control gate.

[0079] When implementing the signal generation module (300) with FET devices without memory functions or devices having non-volatile memory characteristics, it is desirable to increase precision by reducing the variation of the threshold voltage through methods such as making the gate area larger than the minimum size, including dummy devices, or applying a common centroid technique. Here, the gate area determines the length and width of the channel formed in the device.

[0080] When the signal generation module (300) is implemented as a two-terminal device among the aforementioned devices, the operation of the device can be controlled by connecting an additional switch device. Here, the two-terminal device may be one of RRAM, PCRAM, FTJ, MTJ, and as an example of the additional switch device, a MOSFET device including a gate terminal may be used.

[0081] When the signal generation module (300) is implemented as a device having non-volatile memory characteristics, a threshold voltage adjustment module may be further provided. The threshold voltage adjustment module may be configured to adjust or reset the threshold voltage of the semiconductor devices included in the signal generation modules of the bit processing units. By using the threshold voltage adjustment module, the threshold voltage or conductance of the semiconductor devices included in the signal generation module may be varied according to the bit position and resolution of each signal generation module (300) constituting the converter.

[0082] The threshold voltage adjustment module can control digital-to-analog conversion operations by adjusting the threshold voltage or conductance of a semiconductor device included in the signal generation module (300). The threshold voltage adjustment module can basically be composed of a pulse generator and can operate by applying a pulse to a non-volatile memory device constituting the signal generation module (300) to change the memory state.

[0084] <2nd Example>

[0085] Hereinafter, the structure and operation of a pipeline-type data converter according to a second embodiment of the present invention will be described in detail with reference to the attached drawings. The data converter according to the second embodiment of the present invention is an analog-to-digital converter and is characterized by converting an analog signal into a digital code and outputting it based on semiconductor devices sequentially connected in a pipeline form. Here, the digital code is composed of a binary code consisting of K bits (where K is a natural number).

[0086] FIG. 4 is a circuit diagram illustrating an analog-to-digital converter according to a second embodiment of the present invention. Referring to FIG. 4, the analog-to-digital converter (4) according to the second embodiment of the present invention comprises K bit processing units (40-1, 40-2, …, 40-k) connected in a pipeline form. The K bit processing units (40-1, 40-2, …, 40-k) are configured to correspond one-to-one with the K bits constituting a digital code and are connected sequentially in a pipeline form. Each bit processing unit comprises a signal generation module (400), a signal transmission module (410), and a signal conversion module (405), and may further comprise a stabilization module (420).

[0087] The bit level input voltage (B_IN[1]) of the bit processing unit (MSB bit processing unit; 40-1) that processes the most significant bit of the digital code is applied with the analog signal voltage (IN) to be converted. The bit level input voltages (B_IN[2], B_IN[3], …, B_IN[k]) of the remaining bit processing units (40-2, 40-3, …, 40-k) excluding the MSB bit processing unit are sequentially transmitted with bit level output voltages (B_OUT[1], B_OUT[2], …, B_OUT[k-1]) output from the signal transmission module included in the bit processing unit of the previous stage. In addition, the input signals input to the signal transmission modules of the K bit processing units (40-2, 40-3, …, 40-k) are each the codes of the corresponding bits within the digital code (OUT[1], OUT[2], …, OUT[k]), and the digital code for the analog signal is completed by combining the codes of each bit. At this time, OUT[1] forms the MSB of the digital code, and OUT[k] forms the LSB of the digital code.

[0088] The signal generation module (400) has a threshold voltage (V) set according to the position of the corresponding bit in the digital code. th It includes a semiconductor device (M) having ) or conductance. The signal generation module (400) may be configured to generate a bit-level residual voltage (B_RES[1], B_RES[2], … , B_RES[k]) in which a bit-level input voltage (B_IN) is applied to the gate electrode of the semiconductor device and the bit-level input voltage and the threshold voltage of the semiconductor device are determined according to the relationship. Since the structure and operation of the semiconductor device (M[1], M[2], … , M[k]) included in the signal generation modules (400) are substantially the same as the structure and operation of the semiconductor device of the signal generation module according to the first embodiment, a redundant description thereof is omitted.

[0089] The signal conversion module (405) is connected to the output terminal of the signal generation module and can be configured to convert the bit-level residual voltage output from the signal generation module into a binary signal and output the code of the corresponding bit (OUT[1], OUT[2], …, OUT[k]) within the digital code. Meanwhile, the signal conversion module (405) is configured to provide the output code of the bit to the signal transmission module.

[0090] The signal conversion module (405) is a device having a preset switching voltage and can be composed of one of an inverter circuit, a buffer circuit, or a sense amplifier, and the sense amplifier can be driven in a differential manner. The input terminal of the signal conversion module (405) is connected to the bit line of a semiconductor device included in the signal generation module (400) and is configured to output a binary value determined according to the switching voltage. Meanwhile, if the signal conversion module (405) is configured as an inverter circuit, the performance of the analog-to-digital converter can be improved by changing the number or structure of the inverter, or by adjusting the channel width and channel length of the MOSFET used in the inverter.

[0091] The signal transmission module (410) may be configured to include one or more switching elements to output either a bit-level input voltage (B_IN) or a bit-level residual voltage (B_RES) according to an output selection signal. The signal transmission module (410) may include a first switching element (412), a second switching element (414), and a selection circuit (416). Since the structure and operation of the signal transmission module (410), the first switching element (412), the second switching element (414), and the selection circuit (416) are substantially the same as the structure and operation of the signal transmission module according to the first embodiment, a redundant description thereof is omitted. However, unlike the first embodiment, the output selection signal input to the signal transmission module (410) may be composed of a code of a corresponding bit (OUT[1], OUT[2], …, OUT[k]) within the digital code output from the signal conversion module (405).

[0092] Accordingly, when the code (OUT) applied as the output selection signal is '1', the first switching element (412) is driven in the ON state, and the second switching element (414) is maintained in the OFF state. As a result, a bit level residual voltage (B_RES) can be applied to the output terminal of the bit processing unit by driving the first switching element. On the other hand, when the code (OUT) applied as the output selection signal is '0', the first switching element (412) is maintained in the OFF state, and the second switching element (414) is driven in the ON state. As a result, a bit level input voltage (B_IN) can be applied to the output terminal of the bit processing unit by driving the second switching element.

[0093] FIG. 5 is a circuit diagram illustrating another embodiment of a signal conversion module and a signal transmission module in an analog-to-digital converter according to a second embodiment of the present invention. Referring to FIG. 5, the signal conversion module (405) may be configured in the same manner as in the first embodiment, but may be configured to provide a first and a second output selection signal, respectively. Here, the first output selection signal may be composed of a code of corresponding bits within a digital code, and the second output selection signal may be composed of an inverted code for the first output selection signal. Meanwhile, the signal transmission module (470) may be configured to provide the first and second output selection signals provided from the signal conversion module to a first and a second switching element, respectively. The embodiment illustrated in FIG. 5 may operate substantially the same as the embodiment illustrated in FIG. 4.

[0094] The structure and operation of the stabilization module (420) are substantially identical to the structure and operation of the stabilization module according to the first embodiment, so a redundant description thereof is omitted. Meanwhile, the ADC according to the second embodiment of the present invention may further include a threshold voltage adjustment module. The structure and operation of the threshold voltage adjustment module are also substantially identical to the structure and operation of the threshold voltage adjustment module according to the first embodiment, so a redundant description thereof is omitted.

[0096] <Third Example>

[0097] Hereinafter, the structure and operation of a pipeline-type data converter according to the third embodiment of the present invention will be described in detail with reference to the attached drawings. The data converter according to the third embodiment of the present invention is characterized by being configured to select one of an operation mode between an ADC and a DAC based on semiconductor devices connected sequentially in a pipeline form. Accordingly, when the analog-to-digital conversion mode is selected, it operates as an ADC (Analog-to-Digital Converter) that converts an analog signal into a digital code and outputs it. Meanwhile, when the digital-to-analog conversion mode is selected, it operates as a DAC (Digital-to-Analog Converter) that converts a digital code into an analog signal and outputs it. Here, the digital code is composed of a binary code consisting of K bits (where K is a natural number).

[0098] FIG. 6 is a circuit diagram illustrating the structure of a converter according to a third embodiment of the present invention. Referring to FIG. 6, the converter (5) according to the third embodiment of the present invention comprises K bit processing units (50-1, 50-2, …, 50-k) connected in a pipeline form. The K bit processing units (50-1, 50-2, …, 50-k) are configured to correspond one-to-one with each of the K bits constituting a digital code and are connected sequentially in a pipeline form. Each bit processing unit comprises a signal generation module (500), a signal conversion module (505), a signal transmission module (510), and a mode selection module (530), and may further comprise a stabilization module (520).

[0099] The signal generation modules (500) each included in the K bit processing units (50-1, 50-2, …, 50-k) each include a semiconductor device (M[1], M[2], …, M[k]). Each semiconductor device (M[1], M[2], …, M[k]) has a threshold voltage (V) set according to the position of the corresponding bit of the digital code.th1 , V th2 , … , V thk It is configured to have ) or conductance. The signal generation module (500) can be configured to receive a bit level input voltage (B_IN[1], B_IN[2], … , B_IN[k]) as a gate electrode of a semiconductor device, and to generate and output a bit level residual voltage (B_RES[1], B_RES[2], … , B_RES[k]) determined according to the relationship between the bit level input voltage and the threshold voltage of the semiconductor device. Here, the bit level residual voltage can be defined as the difference value between the bit level input voltage and the corresponding threshold voltage.

[0100] The structure and operation of the semiconductor elements (M[1], M[2], … , M[k]) of the signal generation module (500) are substantially the same as those of the semiconductor elements of the signal generation module according to the first and second embodiments, so a redundant description thereof is omitted.

[0101] The bit level input voltage (B_IN[1]) of the bit processing unit (MSB bit processing unit; 50-1) that processes the most significant bit of the digital code is a preset starting voltage or an analog signal voltage (IN) that is the target of conversion. And, the bit level input voltages (B_IN[2], B_IN[3], …, B_IN[k]) of the remaining bit processing units (50-2, 50-3, …, 50-k) excluding the MSB bit processing unit are the bit level output voltages (B_OUT[1], B_OUT[2], …, B_OUT[k-1]) of the signal transmission module of the bit processing unit of the previous stage.

[0102] In the analog-to-digital conversion mode, the bit level input voltage (B_IN[1]) of the MSB bit processing unit (50-1) is applied with the analog signal (IN) to be converted, and K bit processing units can each output a code (ADCOUT[1], ADCOUT[2], …, ADCOUT[k]) of the corresponding bit within the digital code. The data converter according to the present embodiment can synthesize the codes output from the K bit processing units to complete a digital code (ADCOUT[1:k]) for the analog signal. Here, ADCOUT[1] forms the MSB of the digital code, and ADCOUT[k] forms the LSB of the digital code.

[0103] Meanwhile, in the digital-to-analog conversion mode, the bit level input voltage (B_IN[1]) of the MSB bit processing unit (50-1) is a preset starting voltage (IN), and the last bit processing unit (50-k) can output an analog signal (DACOUT).

[0104] The signal conversion module (505) is connected to the output terminal of the signal generation module and can be configured to convert the bit-level residual voltage (B_RES) output from the signal generation module into a binary signal and output it as a code (ADCOUT) of the corresponding bit of the digital code. Meanwhile, the signal conversion module (505) is configured to provide the code of the corresponding bit of the digital code (ADCOUT[1], ADCOUT[2], …, ADCOUT[k]) to the mode selection module (530). Since the configuration and operation of the signal conversion module (505) are substantially the same as the configuration and operation of the signal conversion module of the second embodiment, a redundant description thereof is omitted.

[0105] The signal transmission module (510) may be configured to include one or more switching elements to output either a bit level input voltage (B_IN) or a bit level residual voltage (B_RES) according to an output selection signal. The signal transmission module (510) may include a first switching element (512), a second switching element (514), and a selection circuit (516). Since the configuration and operation of the signal transmission module (510), the first switching element (512), the second switching element (514), and the selection circuit (516) are substantially the same as those of the signal transmission module according to the first and second embodiments, a redundant description thereof is omitted. However, unlike the first and second embodiments, the output selection signal input to the signal transmission module (510) is a signal output from the mode selection module (530). Accordingly, in the analog-to-digital conversion mode, the output selection signal can be composed of the codes of the corresponding bits of the digital code output from the signal conversion module (ADCOUT[1], ADCOUT[2], … , ADCOUT[k]). Meanwhile, in the digital-to-analog conversion mode, the output selection signal can be composed of the codes of the corresponding bits of the digital code to be converted (Code[1], Code[2], … , Code[k]).

[0106] Accordingly, when the signal applied as the output selection signal (Code[1:k] or ADCOUT[1:k]) is '1', the first switching element (512) is turned ON and the second switching element (514) is turned OFF. As a result, a bit-level residual voltage can be applied to the output terminal of the bit processing unit by driving the first switching element. And, when the signal applied as the output selection signal (Code[1:k] or ADCOUT[1:k]) is '0', the first switching element (512) is turned OFF and the second switching element (514) is turned ON. As a result, a bit-level input voltage can be applied to the output terminal of the bit processing unit by driving the second switching element.

[0107] Since the configuration and operation of the stabilization module (520) are substantially the same as the configuration and operation of the stabilization module according to the first and second embodiments, a redundant description thereof is omitted. Meanwhile, the converter according to the third embodiment of the present invention may further include a threshold voltage control module. Since the configuration and operation of the threshold voltage control module are also substantially the same as the configuration and operation of the threshold voltage control module according to the first and second embodiments, a redundant description thereof is omitted.

[0108] The mode selection module (530) is configured to provide an output selection signal to the signal transmission module according to the operation mode selection signal and is positioned between the signal conversion module and the signal transmission module. The operation mode selection signal is composed of a signal for selecting either an analog-to-digital conversion mode or a digital-to-analog conversion mode.

[0109] The mode selection module (530) includes a first input signal path, a second input signal path, and a multiplexer. The first input signal path consists of circuits configured to provide the output of a signal conversion module to the multiplexer in an analog-to-digital conversion mode. The second input signal path consists of circuits configured to provide the code of the corresponding bit of the digital code to be converted to the multiplexer in a digital-to-analog conversion mode. The multiplexer is configured to select one of the input signals and provide it to a signal transmission module. The aforementioned multiplexer may be configured as a digital multiplexer, an analog multiplexer, or a tri-state buffer, or may be configured by combining a plurality of NAND gate elements.

[0110] A mode selection module (530) having the above-described structure receives an operation mode selection signal and controls a signal path, thereby configuring the converter to operate in either an analog-to-digital conversion mode or a digital-to-analog conversion mode. Specifically, in the analog-to-digital conversion mode, the mode selection module provides the output signal of the signal conversion module to the signal transmission module as an output selection signal. On the other hand, in the digital-to-analog conversion mode, the mode selection module provides the code of the corresponding bit of the digital code to the signal transmission module as an output selection signal.

[0111] Hereinafter, the operation of a data converter according to the third embodiment of the present invention having the aforementioned configuration will be specifically described.

[0112] First, when operating in digital-to-analog conversion mode, a DAC selection signal and a digital code (Code[1:k]) are input to the mode selection module of each bit processing unit, and a preset starting voltage (IN) is applied to the bit level input voltage (B_IN[1]) of the MSB bit processing unit. Accordingly, each bit processing unit provides the code (Code[1], Code[2], …, Code[k]) of the corresponding bit of the digital code as an output selection signal of the signal transmission module. Then, the signal transmission module outputs either the bit level input voltage (B_IN) or the bit level residual voltage (B_RES) of the signal generation module according to the output selection signal. Thus, the bit level output voltage (B_OUT[k]) of the signal transmission module of the LSB bit processing unit (50-k) of the converter forms an analog signal corresponding to the digital code to be converted as the output voltage (DACOUT) of the DAC.

[0113] Meanwhile, when operating in analog-to-digital conversion mode, an ADC selection signal is input to the mode selection module of each bit processing unit, and the analog signal (IN) to be converted is applied to the bit level input voltage (B_IN[1]) of the MSB bit processing unit. Accordingly, the signal generation module and the signal conversion module of each bit processing unit convert the bit level residual voltage (B_RES) into a binary signal and output the code of the corresponding bit of the digital code (ADCOUT[1], ADCOUT[2], …, ADCOUT[k]). Then, the mode selection module provides the code of the corresponding bit of the digital code (ADCOUT[1], ADCOUT[2], …, ADCOUT[k]) as an output selection signal to the signal transmission module. Thus, the signal conversion modules of each bit processing unit of the converter output the code of the corresponding bit of the digital code (ADCOUT[1:k]), and these form a digital code for the analog signal to be converted.

[0115] <Fourth Example>

[0116] Hereinafter, the structure and operation of a pipeline-type data converter based on a semiconductor device according to the fourth embodiment of the present invention will be described in detail with reference to the attached drawings. The data converter according to the fourth embodiment of the present invention is an analog-to-digital converter and, based on semiconductor devices sequentially connected in a pipeline form, converts an analog signal into a digital code and outputs it. In particular, the analog-to-digital converter according to the fourth embodiment of the present invention is characterized by efficiently achieving high resolution by converting an analog input signal into a digital code stepwise through a plurality of conversion steps. Here, the digital code is composed of a binary code consisting of K bits (where K is a natural number).

[0117] FIG. 7 is a circuit diagram illustrating an analog-to-digital converter according to a fourth embodiment of the present invention. Referring to FIG. 7, the analog-to-digital converter (6) according to the fourth embodiment of the present invention comprises M conversion stages (60-1, 60-2, …, 60-M) connected in a pipeline form and an output code generation module (62). The analog-to-digital converter (6) according to the fourth embodiment of the present invention is configured to divide K bits constituting a digital code into M bit groups in order. Furthermore, the M conversion stages (60-1, 60-2, …, 60-M) are configured to correspond one-to-one with each of the M bit groups and are connected sequentially in a pipeline form. Each conversion stage (60-1, 60-2, …, 60-M) is configured to generate a binary code by digitally converting the stage input voltage (S_IN) by including a signal generation module (600), a signal transmission module (610), and a code conversion module (620). The output code generation module (62) generates the analog signal (V) based on the partial digital code output from the plurality of conversion stages. IN It is configured to generate a final digital code (ADC_OUT[1:K]) corresponding to ).

[0118] For convenience of explanation, this specification describes, by way of example, a case where M conversion stages each process N bits. In this case, the converter according to the present embodiment can provide a resolution of M*N bits. However, this is merely an example for illustrative purposes, and the M conversion stages may each be configured to process a different number of bits. For example, if the M conversion stages each process N[1], N[2], …, N[M] bits, the total resolution of the converter is It will be the bit.

[0119] The signal generation module (600) included in the conversion stage includes semiconductor devices having different threshold voltages or conductances. Accordingly, the signal generation module is configured to generate a partial digital code by digitally converting the stage input voltage (S_IN) using a plurality of semiconductor devices. The partial digital code generated by the signal generation module can be generated in the form of a thermometer code.

[0120] A signal transmission module (610) included in the conversion stage is configured to generate a stage output voltage (S_OUT) based on the stage input voltage and the digital conversion result of the signal generation module. A code conversion module (620) included in the conversion stage is configured to convert a partial digital code (OUT[1:N]) in the form of a thermometer code generated by the signal generation module into a binary code (ADC_OUT[(K / M+1):(2K / M)]) and output it.

[0121] The stage input voltage (S_IN[1]) of the first conversion stage (60-1) is the analog signal (V) to be converted. IN ) is applied. Meanwhile, the stage output voltages (S_OUT[1], S_OUT[2], …, S_OUT[M-1]) generated in the previous stage are sequentially applied to the stage input voltages (S_IN[2], S_IN[3], …, S_IN[M]) of the remaining conversion stages (60-2 to 60-M) excluding the first conversion stage.

[0122] Meanwhile, each conversion stage may further include a signal amplification module (not shown). The signal amplification module is positioned at the output terminal of the signal transmission module (610) and configured to amplify the residual voltage output from the signal transmission module and then provide the amplified residual voltage to the next conversion stage. By this configuration, the resolution requirements for the next conversion stages can be relaxed.

[0123] In addition, the plurality of conversion stages constituting the analog-to-digital converter according to the fourth embodiment do not all need to be composed of analog-to-digital converters of the same structure. At least some of the conversion stages may be configured to improve the overall conversion precision by processing the residual voltage using a CMOS-based analog-to-digital converter such as a flash ADC or a SAR ADC.

[0124] Hereinafter, the structure and operation of the signal generation module (600) will be described in more detail with reference to FIG. 8. FIG. 8 is a circuit diagram illustrating an example of a signal generation module (600) included in each conversion stage in an analog-to-digital converter according to the fourth embodiment of the present invention. Referring to FIG. 8, the signal generation module (600) of the analog-to-digital converter (6) according to the fourth embodiment of the present invention includes a plurality of semiconductor devices having different threshold voltages or conductances, and is configured to generate a partial digital code based on the voltage output from the semiconductor devices. Meanwhile, for convenience of explanation, this embodiment focuses on the case where the semiconductor device is composed of an NMOS-based device. However, this is merely illustrative, and the technical concept of the present invention is not limited thereto. That is, the semiconductor device is not limited to an NMOS-based device, but can also be implemented with a transistor structure of various polarities, including a PMOS-based device.

[0125] A plurality of semiconductor devices included in the signal generation module (600) are each to which a stage input voltage, which is the target of conversion, is applied. The plurality of semiconductor devices of the signal generation module (600) are each to which the stage input voltage (S_IN) and the threshold voltage (V) of the corresponding semiconductor device are applied. th It is configured to generate a binary value for the output voltage generated based on the relationship between ). Specifically, when the stage input voltage applied to the gate electrode of the semiconductor device is greater than the threshold voltage, the output terminal of the semiconductor device is configured to generate a binary value for the output voltage generated based on the relationship between the stage input voltage (S_IN) and the threshold voltage (V th It is charged with a voltage corresponding to the difference, and accordingly, '1' is output through a buffer circuit (Buff) connected to the semiconductor device. On the other hand, if the stage input voltage applied to the gate electrode of the semiconductor device is less than the threshold voltage, the semiconductor device cannot be turned on, and accordingly, '0' is output through a buffer circuit (Buff) connected to the semiconductor device.

[0126] Meanwhile, the semiconductor devices included in the signal generation module included in the conversion stage may be composed of semiconductor devices having non-volatile memory characteristics capable of varying threshold voltage or conductance, or may be composed of one of a flash memory device, a resistance change memory device, a phase change memory device, a ferroelectric memory device, a magnetoresistance memory device, or a FET (Field Effect Transistor).

[0127] Meanwhile, the signal transmission modules (610) of the conversion stages are each configured to output a stage output voltage (S_OUT). The stage output voltage (S_OUT) may be formed as a residual voltage in which the stage input voltage was not converted into a partial digital code at the corresponding conversion stage.

[0128] The signal transmission module (610) included in the conversion stage may include one of a digital multiplexer, an analog multiplexer, or a tri-state buffer that selects one of a plurality of input channels by a selection signal and provides it as a single output channel. The selection signal of the signal transmission module may use a binary code provided from the code conversion module (620). The binary code is generated by converting a partial digital code having the form of a thermometer code generated as a result of digital conversion by the signal generation module (600).

[0129] The signals input to the multiple input channels of the signal transmission module may each include voltages output from multiple semiconductor devices included in the signal generation module and stage input voltages. The output channel of the signal transmission module may be configured to detect a residual voltage that was not converted into a partial digital code from the stage input voltage based on a selection signal, and to output it as the stage output voltage.

[0130] The analog-to-digital converter according to the present embodiment can efficiently achieve high resolution by converting an analog input signal into a digital signal stepwise over a plurality of conversion steps. Specifically, in the first conversion step, a digital conversion having a relatively large quantization interval is performed on the analog input signal to rapidly determine the approximate magnitude or upper bit information of the input signal. Subsequently, the remaining analog signal component that is not converted by the digital conversion result generated in the first conversion step, i.e., the residual voltage, is generated, and the residual voltage is transferred to the next conversion step.

[0131] In the subsequent transformation steps, the residual voltage generated in the previous transformation step is used as input to perform a digital transformation with a smaller quantization interval than the previous step, thereby progressively converting finer voltage information contained in the analog input signal into digital. In this way, each transformation step is configured to perform progressively finer digital transformations based on the digital transformation result determined in the previous step, and the partial digital codes generated in each step are assigned to correspond to different bit weights. As a result, the combination of these partial digital codes generates a high-resolution digital code that is, overall, equivalent to a high-resolution transformation performed in a single step.

[0132] Accordingly, according to the fourth embodiment of the present invention, compared to the case where an analog input signal is converted to high resolution in a single step, the resolution can be effectively improved without increasing the circuit size and power consumption. In particular, since the upper bit is rapidly determined in the initial conversion step and the lower bit is precisely determined based on the residual voltage in the subsequent conversion step, analog-to-digital conversion that simultaneously satisfies high-speed operation and high resolution is possible.

[0133] In this way, the analog-to-digital converter according to the fourth embodiment of the present invention can improve overall resolution by converting an analog input signal into digital form step by step in a plurality of conversion steps, wherein the upper bits are converted roughly in the initial step and the lower bits are converted in detail based on the residual voltage in subsequent conversion steps.

[0134] The analog-to-digital converter according to the fourth embodiment of the present invention is based on the basic structure of the pipeline-type analog-to-digital converter according to the second embodiment described above. The analog-to-digital converter according to the second embodiment is configured such that K bit processing units each determine one bit, thereby providing a total resolution of K bits. On the other hand, the analog-to-digital converter according to the fourth embodiment is characterized by generalizing the structure of the second embodiment so that each conversion step is configured to determine a plurality of bits.

[0136] <5th Example>

[0137] FIG. 9 is a circuit diagram illustrating an analog-to-digital converter of the SAR method according to the prior art. Referring to FIG. 9, the analog-to-digital converter of the SAR (Successive Approximation Register) method according to the prior art includes a comparator (64), a digital-to-analog converter (DAC; 62), a SAR register (67), and a SAR control unit (69) to convert an input analog signal into a digital code. However, in the prior art SAR ADC, the comparator and the DAC are often implemented as relatively complex analog circuits composed of operational amplifiers, capacitor arrays, resistor networks, etc. Accordingly, problems such as increased circuit area, increased power consumption, and performance degradation due to process miniaturization may occur.

[0138] To improve this, the data converter according to the fifth embodiment of the present invention is an analog-to-digital converter based on SAR logic. The data converter based on SAR logic according to the present embodiment implements the functions of a comparator and a DAC in a structure using semiconductor devices having different threshold voltages or conductances. Specifically, the semiconductor devices are arranged to correspond to each bit position of a digital code, a threshold voltage corresponding to the bit position is set, and a bit-level output signal is configured to be determined according to the relationship between the input analog signal and the threshold voltage.

[0139] Hereinafter, the structure and operation of a pipeline-type sequential approximation data converter according to the fifth embodiment of the present invention will be described in detail with reference to the attached drawings. The sequential approximation data converter according to the fifth embodiment of the present invention is an analog-to-digital converter and is characterized by converting an analog signal into a digital code and outputting it based on semiconductor devices sequentially connected in a pipeline form with SAR logic. Here, the digital code is composed of a binary code consisting of K bits (where K is a natural number).

[0140] FIG. 10 is a circuit diagram illustrating an analog-to-digital converter based on SAR logic according to a fifth embodiment of the present invention. Referring to FIG. 10, the analog-to-digital converter (7) according to a fifth embodiment of the present invention comprises a signal generation module (70), a signal conversion module (75), a SAR register (77), and a SAR control unit (79), and may further comprise a stabilization module (72).

[0141] The signal generation module (70) is (2 k -1) semiconductor devices (M[1], M[2], … , M[2 k It may include (2) included in the signal generation module (70). k -1) semiconductor devices are power supply voltage (VDD It is connected in parallel between the signal generation module (70) and the signal conversion module (75). An input signal is applied to one of the selected semiconductor elements included in the signal generation module (70), and it can be configured to generate a bit-level output voltage for the input signal based on the relationship between the input signal and the threshold voltage.

[0142] Meanwhile, (2 included in the signal generation module (70) k -1) Each of the semiconductor devices receives control signals (IN[1], IN[2], … , IN[2] provided by the SAR control unit (79) k -1]) is configured to be applied. The SAR control unit (79) selects one of the semiconductor devices included in the signal generation module according to preset SAR logic. Specifically, the SAR control unit (79) applies an input signal only to the selected semiconductor device and applies a turn-off voltage to the remaining semiconductor devices through control signals. As a result, based on the relationship between the threshold voltage of the selected semiconductor device and the applied input signal, the signal generation module (70) generates and outputs a bit-level output voltage.

[0143] (2 included in the signal generation module (70) k -1) semiconductor devices each have different threshold voltages (V th) or conductance. Accordingly, the semiconductor devices included in the signal generation module may be composed of semiconductor devices having non-volatile memory characteristics capable of varying the threshold voltage or conductance, or may be composed of one of a flash memory device, a resistance change memory device, a phase change memory device, a ferroelectric memory device, a magnetoresistance memory device, a field effect transistor (FET), or a ferroelectric tunnel junction (FTJ). Since various methods for varying the threshold voltage or conductance of the semiconductor device are substantially the same as the methods described in the first embodiment, a redundant description thereof is omitted.

[0144] The signal conversion module (75) is configured to convert the bit level output voltage output from the signal generation module (70) into a binary signal and output the code of the corresponding bit within the digital code. The signal conversion module (75) is a device having a preset switching voltage and can be configured as one of an inverter circuit, a buffer circuit, or a sense amplifier, and the sense amplifier can be driven in a differential manner. Meanwhile, when the signal conversion module (75) is configured as an inverter circuit or a buffer circuit, the analog-to-digital conversion performance can be improved by changing the number or structure of the inverters or by adjusting the channel width and channel length of the MOSFETs used in the inverters.

[0145] The stabilization module (72) is composed of elements capable of providing a constant current to the signal generation module and can be placed between the output terminal and the ground terminal of the signal generation module. The stabilization module (320) can be composed of one of a single MOSFET element, a plurality of sequentially connected MOSFET elements, a transmission gate element, a resistor, and a non-volatile memory element.

[0146] The SAR register (77) is a storage circuit for storing and maintaining each bit of a digital code generated during a sequential approximation analog-to-digital conversion process, and may be configured to include a plurality of bit storage elements or a plurality of bit storage circuits. The SAR register (77) stores a binary signal output from a signal conversion module in bit units, and the stored bit values ​​may be maintained or updated according to the control of the SAR control unit. Accordingly, the SAR register stores the binary signal output from the signal conversion module at each bit position of the digital code and can sequentially record and maintain the bit values ​​according to the control of the SAR control unit.

[0147] The SAR control unit (79) may be configured to include one or more of a digital logic circuit, a flip-flop, a latch, a decoder, or a state machine. The SAR control unit (79) is a control circuit that generates and applies a plurality of control signals so that a sequential approximation analog-to-digital conversion is performed in hardware.

[0148] Specifically, the SAR control unit can control the semiconductor devices included in the signal generation module to be selectively driven according to corresponding bit positions within the digital code by sequentially generating a bit control signal and a control signal for selecting a semiconductor device in synchronization with the clock signal. To this end, the SAR control unit (79) determines the semiconductor device selected in the next step by referring to the bit value stored in the SAR register according to a preset sequential approximation logic, and generates control signals for applying an input signal to the selected semiconductor device. Additionally, the SAR control unit (79) applies an input voltage (V) to the selected semiconductor device according to the control signal. IN It is configured to provide ) and to provide a turn-off voltage to the remaining unselected semiconductor devices.

[0149] By such control operation, the SAR control unit (79) sequentially applies input signals to semiconductor devices included in the signal generation module, thereby controlling the signal generation module to sequentially generate bit-level output voltages for the input signals.

[0150] Hereinafter, the operation of an analog-to-digital converter of a sequential approximation method according to the fifth embodiment having the structure described above will be explained.

[0151] First, the SAR control unit selects a semiconductor device having a threshold voltage corresponding to the median value of the entire range of the digital code according to preset sequential approximation logic in order to determine the most significant bit (MSB) of the digital code. Accordingly, the SAR control unit applies an input signal to the selected semiconductor device through control signals and applies a turn-off voltage to the remaining semiconductor devices that are not selected.

[0152] At this time, if the input signal is greater than the threshold voltage of the selected semiconductor device, the semiconductor device is switched to a Turn ON state and outputs a bit-level output voltage corresponding to the difference between the input signal and the threshold voltage. On the other hand, if the input signal is not greater than the threshold voltage of the selected semiconductor device, the semiconductor device remains in a Turn OFF state, and the bit-level output voltage has a value of 0.

[0153] The signal conversion module receives the bit-level output voltage output from the signal generation module, outputs a logic value '1' if the bit-level output voltage exceeds a preset switching voltage, and outputs a logic value '0' if it does not exceed the switching voltage. The binary value output from the signal conversion module is stored and maintained in the SAR register.

[0154] Meanwhile, the SAR control unit determines the bit position to be processed in the next step by referring to the bit value stored in the SAR register and generates a control signal to select a semiconductor device corresponding thereto. Subsequently, the SAR control unit applies an input signal to the semiconductor device selected according to the control signal and repeats the process of generating and determining a bit-level output voltage in the same manner as above.

[0155] Through this sequential bit determination process, the digital code corresponding to the input analog signal is determined sequentially from the most significant bit to the least significant bit.

[0156] Hereinafter, an exemplary method for programming and erasing threshold voltages for a plurality of semiconductor devices included in a signal generation module in an analog-to-digital converter of a sequential approximation method according to the fifth embodiment will be described.

[0157] Multiple semiconductor devices included in the signal generation module (M[1:2 k -1]) can be configured as a NOR-type array structure in which the source terminals are commonly connected. In this case, the drain terminals of each semiconductor device may be connected to each other or may be individually separated. In both cases where the drain terminals are connected or separated, a logic value '0' is applied to the drain node and the source node during a program or erase operation, and the gate electrode (IN[1:2 k -1]) can perform programming or erasing operations of the threshold voltage by selectively applying a programming voltage or an erase voltage.

[0158] Additionally, it is possible to maintain the drain node in a floating state and apply a logic value '0' only to the source node while electrically connecting the source node or the source node and the body. In this case as well, the threshold voltage of each semiconductor device can be programmed or erased depending on the voltage applied to the gate electrode. At this time, the logic value '0' voltage applied to the source terminal may be applied through a common ground node (N) or provided through a separate voltage application path.

[0159] In this way, the converter according to the present embodiment can flexibly program and erase the threshold voltage of semiconductor devices included in the signal generation module using a NOR type array structure.

[0161] <6th Example>

[0162] The sequential approximation type data converter according to the sixth embodiment of the present invention is an analog-to-digital converter. The sequential approximation type data converter according to the sixth embodiment of the present invention is similar to the data converter according to the fifth embodiment described above, except that a plurality of semiconductor elements included in the signal generation module each further comprises selection elements. Hereinafter, the structure and operation of the pipeline-type sequential approximation type analog-to-digital converter according to the sixth embodiment of the present invention will be described in detail with reference to the attached drawings.

[0163] FIG. 11 is a circuit diagram illustrating a sequential approximation analog-to-digital converter according to the sixth embodiment of the present invention. Referring to FIG. 11, the analog-to-digital converter (8) according to the sixth embodiment of the present invention comprises a signal generation module (80), a signal conversion module (85), a SAR register (87), and a SAR control unit (89), and may further comprise a stabilization module (82). However, in the analog-to-digital converter according to the sixth embodiment, the configuration and operation of the signal conversion module (85), the SAR register (87), and the stabilization module (82) are substantially the same as those of the signal conversion module (75), the SAR register (77), and the stabilization module (72) of the fifth embodiment, so a redundant description thereof is omitted.

[0164] The signal generation module (80) is (2 k -1) semiconductor devices (M[1:2 k -1])(800) and selection elements(SELM[1:2 k -1])(810) may be included. (2 included in the signal generation module (80). k -1) semiconductor devices are power supply voltage (V DD It is connected in parallel between the signal conversion module (75). In addition, (2 included in the signal generation module (80) k -1) Select elements (810) are each connected in series in a one-to-one correspondence with semiconductor elements.

[0165] (2 included in the signal generation module (80) k -1) semiconductor devices (M[1:2 k The configuration and operation of -1])(800) are substantially identical to the semiconductor devices of the fifth embodiment, so a redundant description thereof is omitted.

[0166] (2 included in the signal generation module (80) k -1) selection elements (SELM[1:2 k-1])(810) may be composed of a transmission gate (TG) or a switching element. The selection elements (810) are configured such that, according to the control signal of the SAR control unit, only the selection element connected to the selected semiconductor element is activated.

[0167] The SAR control unit (89) according to the present embodiment inputs an input voltage (V) to all semiconductor devices (800) included in the signal generation module. IN Apply ), select a semiconductor device according to preset sequential approximation logic, and control signals (SEL[1], SEL[2], … , SEL[2 ) for activating a selected device connected to the selected semiconductor device. k -1]) is generated and output. Accordingly, (2 included in the signal generation module (80) k -1) selection elements (SELM[1:2 k -1])(810) are each control signals (SEL[1], SEL[2], … , SEL[2 k It can be selectively activated in response to -1]).

[0168] Hereinafter, the operation of a sequential approximation analog-to-digital converter according to the sixth embodiment of the present invention having the aforementioned configuration will be described.

[0169] First, the SAR control unit selects a semiconductor device having a threshold voltage corresponding to the median value of the entire range of the digital code according to preset sequential approximation logic to determine the most significant bit (MSB) of the digital code. Accordingly, the input signal (V) is applied to the gate electrodes of all semiconductor devices included in the signal generation module. IN ) applies and activates the selected device connected to the selected semiconductor device.

[0170] At this time, if the input signal is greater than the threshold voltage of the semiconductor device connected to the activated selector, the semiconductor device is switched to a Turn ON state and outputs a bit-level output voltage corresponding to the difference between the input signal and the threshold voltage. On the other hand, if the input signal is not greater than the threshold voltage of the semiconductor device connected to the activated selector, the semiconductor device remains in a Turn OFF state, and the bit-level output voltage has a value of 0. Thus, the converter according to the present embodiment is characterized by a structure that selectively activates a semiconductor device using a selector.

[0171] The signal conversion module receives the bit-level output voltage output from the signal generation module, outputs a logic value '1' if the bit-level output voltage exceeds a preset switching voltage, and outputs a logic value '0' if it does not exceed the switching voltage. The binary value output from the signal conversion module is stored and maintained in the SAR register.

[0172] Meanwhile, the SAR control unit refers to the bit value stored in the SAR register to determine the bit position to be processed in the next step and generates a control signal to select the corresponding semiconductor device. Subsequently, according to the control signal, the selected device connected to the selected semiconductor device is activated, and the process of generating and determining the bit-level output voltage is repeated in the same manner as above.

[0173] Through this sequential bit determination process, the digital code corresponding to the input analog signal is determined sequentially from the most significant bit to the least significant bit.

[0174] Hereinafter, in an analog-to-digital converter of a sequential approximation method according to the 6th embodiment, a method for programming and erasing threshold voltages for a plurality of semiconductor devices included in a signal generation module is described exemplarily.

[0175] In cases where there are select elements connected to each semiconductor element included in the signal generation module, program inhibition for unselected semiconductor elements can be performed using a channel self-boosting method. Specifically, by applying a general logic '1' to the drain terminal and gate electrode of the select elements (SEL[1:k]) and applying a high voltage only to the gate electrode (IN) of the semiconductor elements, the channel potential of the unselected semiconductor elements can be boosted to inhibit programming. At this time, a logic value '0' is applied to the source terminal of the semiconductor elements (M[1:k]), and a logic value '0' is applied to the drain terminal of the select element SEL[x] corresponding to the semiconductor element M[x] that is the target of programming.

[0176] In addition, a programming method using hot carrier injection is also possible. In this case, a high voltage is applied to the gate electrode (IN) of the semiconductor devices, and a logic value '0' is applied to the source terminal or body of the semiconductor device M[x] that is the target of programming. Furthermore, by applying a voltage to induce hot carrier injection to the drain terminal of the semiconductor device M[x] and applying a logic value '0' to the drain terminal of the remaining semiconductor devices (M[1:2k-1]) that are not the target of programming, the threshold voltage programming operation can be performed only for the selected semiconductor devices.

[0177] In this way, the converter according to the present embodiment can precisely program and erase the threshold voltages of semiconductor devices included in the signal generation module by selectively applying a channel self-boosting method using a selection element or a hot carrier injection method.

[0178] The analog-to-digital converter according to the sixth embodiment of the present invention adopts a structure that selectively activates semiconductor devices through a selection element, thereby facilitating circuit expansion as the number of semiconductor devices increases and allowing for relatively simple changes in resolution (K-bit) or structural modifications.

[0179] In addition, the analog-to-digital converter according to the sixth embodiment of the present invention can suppress unnecessary current flow in non-selected semiconductor devices by adopting a structure that activates only the selected semiconductor device among a plurality of semiconductor devices using a selection element. Accordingly, the total power consumption during the sequential approximation conversion process can be effectively reduced.

[0180] In addition, in the analog-to-digital converter according to the sixth embodiment of the present invention, the input signal is applied commonly to the gate electrodes of all semiconductor devices included in the signal generation module, and only the semiconductor device that actually operates is determined by the selection element. As a result, the input signal application path is simplified, and the design of the control signal of the SAR control unit can be made easier.

[0181] In particular, the analog-to-digital converter according to the 5th and 6th embodiments of the present invention has a structure in which semiconductor devices of the signal generation module are arranged in parallel, thereby reducing wiring complexity and improving layout efficiency compared to a serial stacking structure. Accordingly, the total circuit area can be effectively reduced.

[0183] <7th Example>

[0184] The sequential approximation type data converter according to the seventh embodiment of the present invention is an analog-to-digital converter. The data converter according to this embodiment is similar to the data converter according to the fifth embodiment described above, except that a plurality of semiconductor elements included in a signal generation module are connected in series to form a NAND string shape. Hereinafter, the structure and operation of the pipeline-type sequential approximation type data converter according to the seventh embodiment of the present invention will be described in detail with reference to the attached drawings.

[0185] FIG. 12 is a circuit diagram illustrating a sequential approximation analog-to-digital converter according to the seventh embodiment of the present invention. Referring to FIG. 12, the analog-to-digital converter (9) according to the seventh embodiment of the present invention comprises a signal generation module (90), a signal conversion module (95), a SAR register (97), and a SAR control unit (99), and may further comprise a stabilization module (92). However, in the analog-to-digital converter according to the ninth embodiment, the configuration and operation of the signal conversion module (95), SAR register (97), SAR control unit (99), and stabilization module (92) are substantially the same as those of the signal conversion module (75), SAR register (77), SAR control unit (79), and stabilization module (72) of the fifth embodiment, so a redundant description thereof is omitted.

[0186] The signal generation module (90) is (2 k -1) semiconductor devices (M[1], M[2], … , M[2 k It may include (2) included in the signal generation module (90). k -1) semiconductor devices are power supply voltage (V DDIt is connected in series between the ) and the signal conversion module (95) and arranged in a NAND string shape. Accordingly, an input signal is applied to one selected semiconductor device among those included in the signal generation module (90), and a pass voltage is applied to the remaining unselected semiconductor devices, thereby enabling the generation of a bit-level output voltage for the input signal based on the relationship between the input signal and the threshold voltage. (2 included in the signal generation module (90) k -1) The configuration and operation of the semiconductor devices are substantially the same as those of the semiconductor devices of the fifth embodiment, so a redundant description thereof is omitted.

[0187] Meanwhile, a drain select line (DSL) (92) and a source select line (SSL) (93) may be further placed at both ends of a string in which semiconductor devices included in a signal generation module are connected in series. The DSL and SSL devices may be used to perform selection control on a string basis, or to perform program and erase operations of the semiconductor devices.

[0188] The SAR register (97) is a storage circuit for storing and maintaining each bit of a digital code generated during a sequential approximation analog-to-digital conversion process, and may be configured to include a plurality of bit storage elements. Since the structure and operation of the SAR register (97) according to the present embodiment are substantially the same as those of the SAR register according to the fifth embodiment, a redundant description thereof is omitted.

[0189] The SAR control unit (99) may be configured to include one or more of a digital logic circuit, a flip-flop, a latch, a decoder, or a state machine. The SAR control unit (99) is a control circuit that generates and applies a plurality of control signals so that a sequential approximation analog-to-digital conversion is performed in hardware.

[0190] Specifically, the SAR control unit can control the semiconductor devices included in the signal generation module to be selectively driven according to corresponding bit positions within the digital code by sequentially generating a bit control signal and a control signal for selecting a semiconductor device in synchronization with the clock signal. To this end, the SAR control unit (99) determines the semiconductor device selected in the next step by referring to the bit value stored in the SAR register according to a preset sequential approximation logic, and generates control signals for applying an input signal to the selected semiconductor device. Additionally, the SAR control unit (99) applies an input voltage (V) to the selected semiconductor device according to the control signal. IN It is configured to provide ) and the remaining unselected semiconductor devices to provide a pass voltage.

[0191] By such control operation, the SAR control unit (99) sequentially applies input signals to semiconductor devices included in the signal generation module, thereby controlling the signal generation module to sequentially generate bit-level output voltages for the input signals.

[0192] Hereinafter, an exemplary method for programming and erasing a threshold voltage on the x-th semiconductor device (M[x]) among a plurality of semiconductor devices included in a signal generation module in an analog-to-digital converter of a sequential approximation method according to the 7th embodiment will be described.

[0193] First, for the program operation, a logic value '0' is applied to the drain terminal of the DSL device, and a general logic '1' is applied to the gate electrode of the DSL device. A pass voltage is applied to the gate electrodes of the semiconductor devices other than the selected semiconductor device M[x]. Additionally, a pass voltage is applied to the gate electrode of the SSL device, and a logic value '0' is applied to the source terminal of the SSL device. At this time, the '0' voltage applied to the source terminal may be applied through a common ground node (N) or provided through a separate voltage application path. Under these conditions, a program electric field is formed in the selected semiconductor device M[x], and the program operation is performed so that the threshold voltage of the semiconductor device changes.

[0194] Meanwhile, in the case of an erase operation, an erase voltage is applied to the substrate to erase the entire string, and a logic value '0' is applied to the gate electrodes of all semiconductor devices included in the string. Accordingly, the semiconductor devices of the entire string can be erased collectively. In addition, the entire string erase method is not limited to the method of erasing, and it is also possible to selectively erase semiconductor devices in 1-bit units by utilizing the Gate Induced Drain Leakage (GIDL) phenomenon occurring in SSL devices or DSL devices.

[0195] Accordingly, the converter according to the present embodiment can flexibly program and erase the threshold voltages of semiconductor devices included in the signal generation module on a string unit or an individual device unit by utilizing DSL devices and SSL devices. That is, the converter according to the present embodiment enables selective control on a string unit basis through DSL devices and SSL devices placed at both ends of the string, and can perform programming and erase operations of semiconductor devices using this. Accordingly, it becomes possible to pre-set or correct the threshold voltages of the semiconductor devices of the signal generation module.

[0196] Conventional SAR logic converters operate sequentially in bit units, so there is a problem in that the number of circuits that are simultaneously activated during the entire conversion process is limited. In contrast, the analog-to-digital converter according to the 7th embodiment of the present invention can suppress unnecessary dynamic power consumption and realize low-power operation by combining a NAND string-based signal generation module with a conventional SAR structure.

[0197] In addition, the NAND string structure, DSL / SSL configuration, and program / erase method applied to the analog-to-digital converter according to the 7th embodiment of the present invention have high similarity to the structure and operating principles widely used in existing NAND flash memory processes. Accordingly, it can be implemented by utilizing existing semiconductor manufacturing processes without the development of a separate new process.

[0198] In addition, the analog-to-digital converter according to the seventh embodiment of the present invention can significantly improve the device placement density compared to a parallel array structure by configuring the semiconductor devices of the signal generation module into a serially connected NAND string structure. Accordingly, the total circuit area can be effectively reduced while achieving the same resolution.

[0199] In addition, the analog-to-digital converter according to the seventh embodiment of the present invention adopts a structure in which an input signal is applied to selected semiconductor devices and a pass voltage is applied to unselected semiconductor devices, thereby eliminating the need to form complex selection wiring for each individual device. Accordingly, the control signal structure of the SAR control unit is simplified and wiring complexity is reduced.

[0200] Although the present invention has been described above with reference to preferred embodiments, this is merely illustrative and does not limit the invention. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the invention. Furthermore, differences related to such modifications and applications should be interpreted as being included within the scope of the invention as defined in the appended claims. Explanation of the symbols

[0201] 3 : Digital-to-Analog Converter 1, 2, 4, 7, 8, 9 : Analog-to-Digital Converter 5 : Converter 30, 40, 50: Bit processing unit 300, 400, 500, 70, 80, 90: Signal generation module 310, 410, 520: Signal transmission module 320, 420, 520: Stability Module 405, 505, 75, 85, 95: Signal conversion module 530: Mode Selection Module 77, 87, 97: SAR Registers 79, 89, 99: SAR control unit

Claims

Claim 1 A data converter based on a semiconductor device for converting an analog signal into a digital code composed of K bits (where K is a natural number) or converting a digital code into an analog signal, comprising K bit processing units sequentially connected in a pipeline form and configured to correspond one-to-one with the K bits constituting the digital code, wherein each bit processing unit includes a semiconductor device having a threshold voltage or conductance set according to the position of the corresponding bit in the digital code, wherein a bit level input voltage is applied to the semiconductor device, and the bit level input voltage (B_IN) and the threshold voltage (V) of the memory device th A pipeline-type data converter comprising: a signal generation module configured to generate a bit-level residual voltage (B_RES) determined according to the relationship of; and a signal transmission module configured to include one or more switching elements and output either the bit-level input voltage and the bit-level residual voltage of the signal generation module as a bit-level output voltage according to an output selection signal; wherein the bit-level input voltage of a bit processing unit (MSB bit processing unit) that processes the most significant bit of a digital code is a preset start voltage or an analog signal to be converted, and the bit-level input voltages of the remaining bit processing units are bit-level output voltages of the signal transmission module included in the bit processing unit of the previous stage. Claim 2 A pipeline-type data converter according to claim 1, wherein the data converter is a Digital-to-Analog Converter (DAC) that converts a digital code into an analog signal, the bit-level input voltage of a bit processing unit that processes the most significant bit of a digital code is a preset starting voltage, the signal transmission module of each bit processing unit is provided with the code of the corresponding bit in the digital code or the inverted code of said code as the output selection signal, and the bit-level output voltage of the signal transmission module of the bit processing unit that processes the least significant bit of the digital code forms an analog signal corresponding to the digital code. Claim 3 A pipeline-type data converter according to claim 1, wherein the data converter is an Analog-to-Digital Converter (ADC) that converts an analog signal into a digital code, and each bit processing unit further comprises a signal conversion module configured to convert and output a bit-level residual voltage (B_RES) output from the signal generation module into a binary signal, wherein the bit-level input voltage of the bit processing unit processing the most significant bit of the digital code is an analog signal, and the signal conversion module of each bit processing unit is configured to output a code of the corresponding bit in the digital code and provide it to the signal transmission module as the output selection signal. Claim 4 A pipeline-type data converter according to claim 1, wherein the data converter is a converter capable of selectively operating as either an ADC or a DAC, and each bit processing unit comprises: a signal conversion module configured to convert and output a bit-level residual voltage output from the signal generation module into a binary signal; and a mode selection module disposed between the signal conversion module and the signal transmission module, receiving an operation mode selection signal and controlling a signal path according to the input operation mode selection signal so that the converter operates as either an ADC or a DAC; wherein the mode selection module is configured such that when an analog-to-digital conversion mode is selected, the output signal of the signal conversion module for the analog signal to be converted is provided to the signal transmission module as an output selection signal, and when a digital-to-analog conversion mode is selected, the code of the corresponding bit of the digital code to be converted is provided to the signal transmission module as an output selection signal. Claim 5 A pipeline-type data converter according to claim 1, characterized in that each bit processing unit further comprises a stabilization module disposed between the output terminal and the ground terminal of the signal generation module, the stabilization module being composed of a device or circuit that provides a constant current to the signal generation module. Claim 6 A pipeline-type data converter according to claim 1, wherein the signal generation module of the bit processing unit is composed of a semiconductor device having non-volatile memory characteristics capable of varying a threshold voltage or conductance, or is composed of one of a flash memory device, a resistance change memory device, a phase change memory device, a ferroelectric memory device, a magnetoresistance memory device, or a FET (Field Effect Transistor). Claim 7 A pipeline-type data converter according to claim 3, wherein the signal conversion module of the bit processing unit is composed of one of an inverter circuit having a preset switching voltage, a buffer circuit, and a sense amplifier. Claim 8 A pipeline-type data converter according to claim 1, wherein the signal transmission module comprises: a first switching element configured to output a bit-level residual voltage of the signal generation module as a bit-level output voltage; a second switching element configured to output a bit-level input voltage of the bit processing unit as a bit-level output voltage; and a selection circuit configured to drive one of the first switching element and the second switching element according to the output selection signal, wherein the output selection signal of the selection circuit is either a code of a corresponding bit of a digital code or a binary signal converted from the bit-level residual voltage of the signal generation module. Claim 9 A pipeline-type data converter according to claim 8, characterized in that the first and second switching elements of the signal transmission module are composed of either a transmission gate (TG) or a simple single pass gate (Single Pass Gate). Claim 10 A pipeline-type data converter according to claim 4, wherein the mode selection module is configured to include one of a digital multiplexer, an analog multiplexer, and a tri-state buffer, or is configured as a combination of multiple NAND gate devices. Claim 11 A pipeline-type data converter according to claim 1, further comprising a threshold voltage adjustment module for adjusting or resetting the threshold voltage of memory elements included in the signal generation modules of the bit processing units. Claim 12 A data converter based on a semiconductor device that converts an analog signal into a digital code composed of K bits (where K is a natural number), comprising: a plurality of conversion stages sequentially connected in a pipeline form, configured to convert a stage input voltage into a digital code to generate a partial digital code; and an output code generation module configured to generate a final digital code corresponding to the analog signal based on the partial digital codes output from the plurality of conversion stages; wherein each conversion stage comprises: a signal generation module configured to convert the stage input voltage into a digital code to generate the partial digital code using semiconductor devices having different threshold voltages or conductances; and a signal transmission module configured to generate a stage output voltage based on the stage input voltage and the digital conversion result of the signal generation module; wherein the stage input voltage of the first conversion stage is the analog signal to be converted, and the stage input voltages of the remaining conversion stages are the stage output voltages generated from the previous conversion stage. Claim 13 A pipeline-type data converter according to claim 12, wherein the partial digital code generated by the signal generation module of each conversion stage is composed of a thermometer code, and each conversion stage further includes a code conversion module configured to convert and output the partial digital code in the form of a thermometer code generated from the signal generation module into a binary code, and wherein the output code generation module is configured to generate the final digital code based on the binary codes output from the code conversion modules included in the plurality of conversion stages. Claim 14 A pipeline-type data converter according to claim 12, characterized in that the stage output voltage is a residual voltage that the stage input voltage was not converted by the partial digital code in the signal generation module included in the conversion stage. Claim 15 A pipeline-type data converter according to claim 12, wherein the signal generation module included in the conversion stage comprises a plurality of semiconductor devices having different threshold voltages or conductances, wherein the stage level voltage is applied to the plurality of semiconductor devices, wherein the plurality of semiconductor devices are each configured to generate a binary value based on the relationship between the stage level voltage and the threshold voltage, and wherein the signal generation module is configured to generate the partial digital code based on the binary values ​​each generated by the plurality of semiconductor devices. Claim 16 A pipeline-type data converter according to claim 12, wherein the signal generation module included in the conversion stage is composed of a semiconductor device having non-volatile memory characteristics capable of varying a threshold voltage or conductance, or is composed of one of a flash memory device, a resistance change memory device, a phase change memory device, a ferroelectric memory device, a magnetoresistance memory device, or a FET (Field Effect Transistor). Claim 17 A pipeline-type data converter according to claim 12, wherein the signal transmission module included in the conversion stage includes one of a digital multiplexer, an analog multiplexer, and a tri-state buffer that selects one of a plurality of input channels by a selection signal and provides it as a single output channel, wherein the selection signal is a partial digital code based on the digital conversion result of the signal generation module, and the signals input to the plurality of input channels each include voltages output from a plurality of semiconductor devices included in the signal generation module and the stage input voltage, and the output channel is configured to detect a residual voltage that the stage input voltage was not converted by the partial digital code based on the selection signal and output it as the stage output voltage. Claim 18 A sequential approximation (SAR) data converter based on semiconductor devices that converts an input analog signal into a digital code composed of K bits (where K is a natural number), comprising: a plurality of semiconductor devices arranged to correspond to each bit of the digital code and having different threshold voltages, wherein an input signal is applied to one selected of the semiconductor devices and the signal generation module is configured to generate a bit-level output voltage for the input signal based on the relationship between the input signal and the threshold voltage; a signal conversion module configured to convert the bit-level output voltage output from the signal generation module into a binary signal and output a binary value for the corresponding bit of the digital code; and a SAR register configured to store the binary value output from the signal conversion module at the corresponding bit position of the digital code. A sequential approximation type data converter comprising: a SAR control unit configured to generate a control signal for sequentially selecting semiconductor devices included in the signal generation module based on a bit value stored in the SAR register according to a preset sequential approximation logic; and wherein the signal generation module sequentially generates bit-level output voltages for the input signal by sequentially applying an input signal to the semiconductor devices included in the signal generation module according to the control signal of the SAR control unit. Claim 19 A sequential approximation type data converter according to claim 18, wherein semiconductor devices included in the signal generation module are connected in parallel, and according to the control signal of the SAR control unit, an input signal is applied only to the selected semiconductor device and a turn-off signal is applied to the remaining unselected semiconductor devices, and a bit-level output voltage of the signal generation module is generated based on the relationship between the threshold voltage of the selected semiconductor device and the applied input signal. Claim 20 A sequential approximation type data converter according to claim 18, wherein semiconductor devices included in the signal generation module are connected in series to form a string structure, and according to a control signal of the SAR control unit, an input signal is applied to a selected semiconductor device and a pass voltage is applied to the remaining unselected semiconductor devices, and a bit-level output voltage of the signal generation module is generated based on the relationship between the threshold voltage of the selected semiconductor device and the applied input signal. Claim 21 In claim 18, the sequential approximation type data converter further comprises a stabilization module disposed between the output terminal and the ground terminal of the signal generation module, wherein the sequential approximation type data converter comprises elements configured to provide a constant current to semiconductor elements included in the signal generation module. Claim 22 A sequential approximation type data converter according to claim 18, wherein the semiconductor devices included in the signal generation module are composed of semiconductor devices having non-volatile memory characteristics capable of varying threshold voltage or conductance, or are composed of one of a flash memory device, a resistance change memory device, a phase change memory device, a ferroelectric memory device, a magnetoresistance memory device, a field effect transistor (FET), or a ferroelectric tunnel junction (FTJ). Claim 23 A sequential approximation type data converter according to claim 18, wherein the signal conversion module is composed of one of an inverter circuit having a preset switching voltage, a buffer circuit, and a sense amplifier. Claim 24 A sequential approximation type data converter according to claim 18, wherein the signal generation module further comprises a plurality of selection elements connected in a one-to-one correspondence with each of the plurality of semiconductor elements. Claim 25 A sequential approximation type data converter according to claim 24, wherein the SAR control unit applies an input signal to a plurality of semiconductor elements included in the signal generation module and sequentially activates selected elements connected to semiconductor elements selected according to the control signal, thereby causing the signal generation module to sequentially output bit-level output voltages for the input signal. Claim 26 A sequential approximation type data converter according to claim 24, characterized in that the selection element of the signal generation module is composed of a transmission gate (TG) or a switching element.

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