Data converter based on semiconductor devices

Abstract

The present invention relates to a dynamic analog-to-digital converter. The dynamic ADC comprises N bit processing units configured to correspond one-to-one with each of the N bits constituting a digital code, and configured to receive an input signal and a reference signal to generate and output a code for the corresponding bit. Each bit processing unit comprises: a signal generation module configured to receive the input signal, which includes a first semiconductor device having a first threshold voltage set according to a corresponding bit position within the digital code; a comparison module configured to receive the reference signal, which includes a second semiconductor device having a second threshold voltage; a latch module configured to regenerate the potential of an internal node according to the result of the operation of the first and second semiconductor devices based on the input signal and the first threshold voltage, and the reference signal and the second threshold voltage; and a signal conversion module configured to convert the output voltage of the latch module into a binary signal and output it.

Description

Technology Field

[0001] The present invention relates to a data converter, and more specifically, to a data converter based on semiconductor devices, characterized by being configured based on semiconductor devices having different threshold voltages, so that it can be implemented in a small area and operated at low power, and can be used in various applications including neuromorphic systems to improve performance. Background Technology

[0002] An Analog-to-Digital Converter (ADC) is an electronic device that converts analog signals into digital signals. Signals detected by sensors in the natural world, such as temperature and voltage, are analog signals. An ADC circuit converts these analog signals into digital signals that can be processed by electronic devices, such as computers and control units, and outputs them. Recently, with the widespread commercialization of advanced electronic devices such as IoT and neuromorphic systems, the demand for ADCs with low power consumption and small area characteristics is increasing. In response to this demand, ADCs with various structures are being developed.

[0003] U.S. Patent Publication No. 2009-0091483 discloses a Flash ADC structure as one of the ADC types. FIG. 1 is a structural diagram illustrating a Flash ADC scheme. As shown in FIG. 1, the Flash ADC is 2 KAn ADC operation is performed to convert an analog signal into a digital signal using a comparator bank consisting of several comparators. The comparators of the Flash ADC receive a reference voltage corresponding to a reference value and an analog voltage to be distinguished as inputs. The comparators then compare the magnitudes of the two input voltages and output the result as a digital code. Flash ADCs with this structure continue to be widely used in applications requiring high speed and low latency.

[0004] However, conventional Flash ADCs with the aforementioned structure use a large number of comparators, resulting in high power consumption during operation. Consequently, conventional Flash ADCs are difficult to use in low-power applications. Furthermore, because conventional Flash ADCs use a large number of comparators, they require a large chip area. For this reason, ADCs with the aforementioned structure are difficult to use in small-scale applications.

[0005] Furthermore, the resolution of conventional Flash ADCs is limited by the number of comparators used. Therefore, increasing the resolution of Flash ADCs requires increasing the number of comparators; this leads to problems such as increased circuit complexity, higher manufacturing costs, and increased power consumption.

[0006] As such, when the number of bits increases, the device area and power consumption of an ADC having the aforementioned structure increase exponentially, and it is difficult to use in applications requiring high resolution.

[0007] U.S. Patent No. 7965218 discloses a Successive Approximation Register (SAR) ADC structure. FIG. 2 is a structural diagram illustrating a SAR ADC scheme according to the prior art. As shown in FIG. 2, the SAR ADC performs ADC operations by utilizing a single comparator, a DAC, a logic circuit, a register, etc. Generally, bits are determined sequentially starting from the Most Significant Bit (MSB). The SAR ADC uses a single comparator, and the DAC uses multiple capacitors of different sizes and controls the output value of the DAC using the charge sharing principle. The results of bit determination up to that point are stored in the register, and based on the results, the DAC adjusts the reference voltage of the comparator through the logic circuit. By repeating the aforementioned process, bit values ​​are determined from the MSB to the Least Significant Bit (LSB).

[0008] Although the SAR ADC with the aforementioned structure provides high resolution, it still suffers from the problem of requiring a large circuit area and high power consumption. Prior art literature

[0009] U.S. Patent Publication No. US 2009 / 0091483, U.S. Registered Patent Publication No. US 7965218, Korean Patent Publication No. 10-2023-0020295, Korean Patent Publication No. 10-2023-0018972 The problem to be solved

[0010] To solve the aforementioned problems, the present invention aims to provide a data converter configured to convert an analog signal into a digital code using semiconductor devices capable of varying a threshold voltage or conductance and a latch circuit module.

[0011] In addition, another objective of the present invention is to provide a data converter configured to convert an analog signal into a digital code using steep switching devices capable of varying a threshold voltage or conductance. means of solving the problem

[0012] To achieve the aforementioned technical objectives, a data converter according to the first aspect of the present invention comprises: an analog-to-digital converter that converts an input analog signal into a digital code composed of N bits (wherein N is a natural number), and comprises: a reference signal input unit configured to provide a preset reference signal; and N bit processing units configured to correspond one-to-one with each of the N bits constituting the digital code, and configured to receive the input signal and the reference signal to generate and output a code for the corresponding bit. Each bit processing unit comprises: a signal generation module configured to receive an input signal, including a first semiconductor device having a first threshold voltage set according to a corresponding bit position within the digital code; a comparison module configured to receive a reference signal, including a second semiconductor device having a second threshold voltage characteristic; and a latch module configured to regenerate the potential of an internal node according to the input signal, the first threshold voltage, the reference signal, and the operation result of the first and second semiconductor devices according to the second threshold voltage. The invention is characterized by having a signal conversion module configured such that an input node is connected to an output node of a latch module, and the output voltage of the latch module is converted into a binary signal and output.

[0013] In a data converter according to the first sun having the aforementioned features, each bit processing unit is preferably configured such that the output state of the latch module is determined according to the relative magnitude of the difference between the input signal and the first threshold voltage and the difference between the reference signal and the second threshold voltage, and accordingly, the output signal of the signal conversion module is determined to be either a logic value '1' or '0'.

[0014] In a data converter according to the first aspect having the aforementioned features, each bit processing unit preferably further comprises a charging module configured to initialize the output node of the latch module to a pre-charged state prior to the latch operation of the latch module.

[0015] In a data converter according to the first aspect having the aforementioned features, the first semiconductor device of the signal generation module of each bit processing unit is preferably composed of a semiconductor device having non-volatile memory characteristics capable of varying a threshold voltage or conductance, or is composed of one of a flash memory device, a resistance change memory device, a phase change memory device, a ferroelectric memory device, a magnetoresistance memory device, or a field-effect transistor (FET).

[0016] In a data converter according to the first sun having the aforementioned features, the second semiconductor device of the comparison module of each bit processing unit is preferably composed of one of a field-effect transistor (FET) capable of generating a constant current and a resistor, or is composed of the same device as the first semiconductor device.

[0017] In a data converter according to the first sun having the aforementioned features, it is preferable that the latch module of each bit processing unit is composed of two cross-coupled inverters, two NMOS transistors with gates and drains connected to each other, or two PMOS transistors with gates and drains connected to each other.

[0018] In a data converter according to the first sun having the aforementioned features, the signal conversion module of the bit processing unit is preferably composed of one of an inverter circuit, a buffer circuit, and a sense amplifier having a preset switching voltage.

[0019] In a data converter according to the first sun having the aforementioned features, it is preferable that the first threshold voltages of the first semiconductor devices included in the N bit processing units are linearly mapped at a constant interval according to the position of the corresponding bit.

[0020] In a data converter according to the first sun having the aforementioned features, it is preferable that the first threshold voltages of the first semiconductor devices included in the N bit processing units are non-linearly mapped using a non-linear activation function according to the position of the corresponding bit.

[0021] In a data converter according to the first sun having the aforementioned features, it is preferable that the N binary signals output from each of the N bit processing units constitute a thermometer code.

[0022] In a data converter according to the first aspect having the aforementioned features, the data converter further comprises a thermometer-to-binary encoder configured to convert a thermometer code into a binary code, wherein the thermometer-to-binary encoder is connected to the N bit processing units, receives a thermometer code from the N bit processing units, converts the thermometer code into a binary code, and outputs the result.

[0023] To achieve the aforementioned technical objective, a data converter according to the second aspect of the present invention comprises an ADC that converts one or more analog signals, which are input signals, into a digital code composed of N bits (where N is a natural number), and N bit processing units configured to correspond one-to-one with each of the N bits constituting the digital code, and configured to receive one or more input signals, generate a code of the corresponding bits, and output it.

[0024] And, each bit processing unit comprises: a signal generation module configured to include one or more steep switching devices having a threshold voltage set according to the position of a corresponding bit in a digital code, wherein the one or more input signals are each applied to the control electrodes of the steep switching devices; a signal conversion module configured such that an input node is connected to an output node of the signal generation module, the voltage of the input node changes according to the operation result of the signal generation module, and the converted voltage of the input node is converted into a binary signal and output; and a pre-charging module connected to a power supply voltage and configured to pre-charge the input node of the signal conversion module according to a pre-charging signal.

[0025] In a data converter according to the second aspect having the aforementioned features, the rapid switching element included in the signal generation module of each bit processing unit is preferably composed of one of a Flash-gated thyristor and a thyristor having a memory function.

[0026] In a data converter according to the second sun having the aforementioned features, the signal conversion module is preferably composed of one of an inverter circuit, a buffer circuit, and a sense amplifier having a preset switching voltage.

[0027] In a data converter according to the second sun having the aforementioned features, each bit processing unit is preferably configured such that, after applying a pre-charging signal to the pre-charging module to pre-charge the input node of the signal conversion module, when an input signal is applied to the rapid switching element, the potential of the output node of the rapid switching element changes based on the relationship between the input signal and the threshold voltage, and the output code of the signal conversion module is determined according to the change in potential of the output node of the rapid switching element.

[0028] In a data converter according to the second aspect having the aforementioned features, a plurality of rapid switching elements included in the signal generation module of each bit processing unit are connected in parallel with each other, and a plurality of rapid switching elements included in one bit processing unit are each provided with a plurality of input signals simultaneously, and the signal conversion module of the bit processing unit is configured to output a bit value corresponding to the input signal that has the greatest influence on the potential change of the input node among the plurality of input signals, and it is preferable that the analog-to-digital converter outputs a digital code corresponding to the result of a Max Pooling operation of the plurality of input signals.

[0029] In a data converter according to the second sun having the aforementioned features, the threshold voltages of the rapid switching elements of the N bit processing units can be linearly mapped at regular intervals according to the position of the corresponding bit.

[0030] In a data converter according to the second sun having the aforementioned features, the threshold voltages of the rapid switching elements of the N bit processing units can be non-linearly mapped using a non-linear activation function according to the position of the corresponding bit.

[0031] In a data converter according to the second sun having the aforementioned features, it is preferable that the N binary signals output from each of the signal conversion modules of the N bit processing units constitute a thermometer code.

[0032] In a data converter according to the second aspect having the aforementioned features, the data converter further comprises a thermometer-to-binary encoder configured to convert a thermometer code into a binary code, wherein the thermometer-to-binary encoder is preferably connected to the N bit processing units, receives a thermometer code from the N bit processing units, converts the thermometer code into a binary code, and outputs the result. Effects of the invention

[0033] The data converter according to the present invention performs analog-to-digital conversion using a latch circuit or rapid switching elements based on memory elements having different threshold voltages, thereby simplifying the circuit configuration compared to existing structures that require multiple comparators or complex analog circuits. Accordingly, the total circuit area can be effectively reduced.

[0034] Furthermore, the data converter according to the present invention operates in a dynamic manner and has a structure in which charging and discharging occur only when necessary. In addition, by applying a latch-based discrimination mechanism utilizing rapid switching characteristics, static current consumption can be minimized, thereby significantly reducing power consumption compared to conventional static analog-to-digital converters.

[0035] Furthermore, the data converter according to the present invention can rapidly amplify and distinguish minute voltage differences of an input signal by utilizing latch-based regeneration operation or the threshold characteristics of a rapid switching element. Accordingly, high-speed analog-to-digital conversion is possible, making it suitable for applications requiring high-speed signal processing.

[0036] In addition, the data converter according to the present invention can implement thermometer code generation, Max Pooling, and non-linear activation characteristics at the analog signal stage through threshold voltage mapping or a parallel-connected rapid-switching element structure. Accordingly, the computational burden in the digital domain can be reduced and the computational efficiency of the entire system can be improved.

[0037] In addition, the data converter according to the present invention simultaneously provides the advantages of reduced circuit area, reduced power consumption, and computational integration in the analog domain, so it can be effectively applied to neuromorphic networks, artificial intelligence accelerators, sensor interfaces, and in-memory computing systems that require low-power operation. Brief explanation of the drawing

[0038] Figure 1 is a structural diagram illustrating a Flash ADC Scheme according to conventional technology. Figure 2 is a structural diagram illustrating a SAR ADC scheme according to conventional technology. FIG. 3 is a configuration diagram showing the overall structure of a data converter according to the first embodiment of the present invention. FIG. 4 is a circuit diagram illustrating the structure of the Nth bit processing unit (30-N) in a data converter according to the first embodiment of the present invention. FIG. 5 is a configuration diagram showing the overall structure of a data converter according to a second embodiment of the present invention. FIG. 6 is a flowchart illustrating the operation of a bit processing unit in a data converter according to a second embodiment of the present invention. FIG. 7 is a graph illustrating the ADC operation in the case where the threshold voltages of rapid switching elements are linearly mapped in a data converter according to the second embodiment of the present invention. FIG. 8 is a graph illustrating the ADC operation in the case where the threshold voltages of rapid switching elements are non-linearly mapped in a data converter according to a second embodiment of the present invention. FIG. 9 is a configuration diagram showing the overall structure of a data converter according to a third embodiment of the present invention. FIG. 10 is a diagram showing a thermometer code generated by seven bit processing units performing Max Pooling on four input signals in a data converter according to a third embodiment of the present invention. Specific details for implementing the invention

[0039] A data converter according to the present invention is characterized by sequentially arranging unit cells composed of Latch modules based on memory elements having different threshold voltages or rapid switching elements having different threshold voltages to convert an analog signal into a digital code. The data converter according to the present invention converts an input analog signal into a digital code composed of N bits (where N is a natural number) having binary values ​​and outputs it. Herein, the digital code may be composed of a thermometer code consisting of N bits (where N is a natural number). Hereinafter, the structure and operation of data converters according to preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0041] < 1st Example >

[0042] Hereinafter, the structure and operation of a data converter according to a first embodiment of the present invention will be described in detail with reference to the attached drawings. The data converter according to the first embodiment of the present invention is a Dynamic ADC and is characterized by using a Latch circuit module having semiconductor devices having different threshold voltages or conductances. Here, the digital code is composed of a Thermometer Code consisting of N bits (where N is a natural number).

[0043] FIG. 3 is a schematic diagram illustrating the overall configuration of a dynamic analog-to-digital converter according to a first embodiment of the present invention. Referring to FIG. 3, the dynamic analog-to-digital converter (3) according to the first embodiment of the present invention includes a reference signal input unit (32) and N bit processing units (Cell[1:N] ; 30-1, 30-2, … , 30-N). The reference signal input unit (32) has a preset reference signal (V Ref It is configured to provide ) to bit processing units. N bit processing units (Cell[1:N] ; 30-1, 30-2, … , 30-N) are configured to correspond one-to-one with each of the N bits constituting the digital code. The N bit processing units (30-1, 30-2, … , 30-N) are input signals (V IN ) and reference signal (V Ref It receives ) and generates and outputs a code for the corresponding bit. A dynamic analog-to-digital converter having the above configuration can generate and provide a digital code composed of a thermometer code based on N binary signals output from each of the N bit processing units.

[0044] In a dynamic analog-to-digital converter according to the first embodiment of the present invention, each bit processing unit (Cell[1:N]) has a power supply voltage (V) for circuit operation. DD It is connected to ) and ground potential (GND), and the input signal (V) to be convertedIN ) and reference signal (V Ref It is configured to receive ) in common. Each bit processing unit (Cell[1:N]) has different threshold voltages (V th Each semiconductor device having [1:N]) is provided, and a comparison result is output based on the relative relationship between a threshold voltage, an input signal, and a reference signal. In particular, the dynamic analog-to-digital converter according to the present embodiment may be configured such that the threshold voltages of the semiconductor devices included in the bit processing units are sequentially mapped according to the bit position. As a result, the dynamic analog-to-digital converter according to the present embodiment generates a thermometer code, and the generated thermometer code can be used for digital conversion.

[0045] FIG. 4 is a circuit diagram illustrating the structure of the Nth bit processing unit (Cell[N]; 30-N) in a dynamic analog-to-digital converter according to the first embodiment of the present invention. Hereinafter, the structure and operation of the bit processing unit will be described in detail with reference to FIG. 4. Although the circuit of FIG. 4 is implemented based on NMOS devices, it can also be implemented based on PMOS devices or as a hybrid structure combining NMOS devices and PMOS devices. The dynamic analog-to-digital converter according to the first embodiment of the present invention uses a latch-based amplification mechanism, thereby enabling rapid identification of input signals, which is more advantageous for analog-to-digital conversion applications requiring high-speed operation.

[0046] Referring to FIG. 4, the bit processing unit (30-N) includes a signal generation module (300), a comparison module (310), a latch module (320), and a signal conversion module (330). Meanwhile, the bit processing unit (30) may further include a pre-charging module (340, 342). Additionally, the bit processing unit (30) may further include a threshold voltage adjustment module (not shown). Additionally, the bit processing unit (30) may further include a leakage blocking module (not shown).

[0047] The signal generation module (300) has a threshold voltage (V) determined according to the position (N) of the corresponding bit in the digital code. th It includes a first semiconductor device (M1) having [N]). Input signal (V IN ) can be configured to be applied to the gate electrode of the first semiconductor device (M1). In the dynamic analog-to-digital converter according to the present invention, the first semiconductor devices (M1) of the signal generation modules (300) are set so that the threshold voltage is sequentially increased at regular intervals according to the position of the corresponding bit, and accordingly, the analog signal, which is the input signal, can be converted into a thermometer code.

[0048] In the data converter according to the present embodiment, the threshold voltages of the first semiconductor devices of the N bit processing units may be linearly mapped at regular intervals according to the position of the corresponding bit, or may be non-linearly mapped using a non-linear activation function according to the position of the corresponding bit.

[0049] The first semiconductor device (M1) may be composed of a semiconductor device having non-volatile memory characteristics capable of varying a threshold voltage or conductance, or may be composed of one of a flash memory device, a resistance change memory device, a phase change memory device, a ferroelectric memory device, a magnetoresistance memory device, or a FET (Field Effect Transistor). Additionally, the first semiconductor device (M1) may be composed of a two-terminal device such as an RRAM, a PRAM, or a FJT (Ferroelectric Tunnel Junction). Various methods for varying the threshold voltage or conductance of the first semiconductor device will be described later.

[0050] The comparison module (310) includes a second semiconductor device (M2). Reference signal (V Ref ) is configured to be applied to the gate electrode of the second semiconductor device. The second semiconductor device (M2) may be configured as either a FET or a resistor configured to generate a constant current.

[0051] The latch module (320) is a latch circuit configured to detect the state of an internal node corresponding to an input voltage according to the operation of the first semiconductor device and the second semiconductor device, and then rapidly determine the potential of the internal node through a regeneration operation for the potential of the internal nodes. The latch module (320) may be composed of two cross-coupled inverters, two NMOS transistors with gates and drains connected to each other, or two PMOS transistors with gates and drains connected to each other. Additionally, the latch module (320) is not limited to these structures and may be implemented in various modified structures capable of performing a latch operation.

[0052] The signal conversion module (330) is configured to detect a voltage change formed by the latch module, convert it into a binary signal, and output a code (OUT[N]) of the corresponding bit among the digital codes. The signal conversion module (330) may be composed of an inverter circuit, a buffer circuit, or a sense amplifier. Accordingly, the signal conversion module (330) operates to generate a binary code by determining the input voltage based on a preset switching voltage.

[0053] The pre-charging module (340, 342) is composed of a charging element and connected to the nodes of the latch module, configured to pre-charge each node of the latch module to an initial state before latch operation. One of a PMOS transistor, an NMOS transistor, a resistor, or a transmission gate may be used as the charging element.

[0054] Meanwhile, the first semiconductor device (M1) of the signal generation module (300) is composed of a device capable of setting a threshold voltage or conductance to an arbitrary value as described above. Accordingly, the first semiconductor device (M1) of the signal generation module (300) can be implemented as 1) a semiconductor device having non-volatile memory characteristics capable of varying the threshold voltage or conductance, or 2) a semiconductor device capable of setting a fixed threshold voltage or conductance by adjusting the coupling ratio, etc., during the design stage. Accordingly, depending on the type of device, the threshold voltage or conductance of the first semiconductor device (M1) of the signal generation module (300) can be set fixedly during the design stage or varied in various ways during the driving stage by utilizing non-volatile memory characteristics. Below, a method for adjusting the threshold voltage or conductance for each device capable of constituting the first semiconductor device (M1) will be described in detail.

[0055] As described above, the device having non-volatile memory characteristics that can be used as the first semiconductor device (M1) of the signal generation module (300) includes a flash memory device, a resistance change memory device, a phase change memory device, a ferroelectric memory device, a magnetoresistance memory device, etc. Meanwhile, the dynamic analog-to-digital converter according to the present invention may further include a threshold voltage adjustment module to vary the threshold voltage or conductance of the first semiconductor device (M1) having non-volatile memory characteristics.

[0056] Flash memory devices can control threshold voltage or conductance by injecting electrons or holes into the gate insulating layer by applying a voltage pulse. The electrons or holes injected into the gate insulating layer affect the channel. Utilizing this characteristic, in the case of n-channel flash memory devices, the threshold voltage of the device can be controlled by raising the threshold voltage by injecting electrons or lowering the threshold voltage by injecting holes.

[0057] A resistance change memory device is composed of a metal-insulator-metal structure, and can change conductance by inducing a change in resistance in the intermediate insulating layer by applying a voltage pulse. At this time, a voltage pulse can be applied in a direction that increases the conductance or in a direction that decreases the conductance.

[0058] Ferroelectric memory devices can change threshold voltage or conductance by applying voltage pulses to a ferroelectric insulating film to form an electric field within the film. In the case of field-effect transistors that utilize a ferroelectric insulating film as a gate insulating film, the electric field can be formed in a direction that increases conductance in the ferroelectric insulating film, or the electric field can be controlled in a direction that decreases conductance. Ferroelectric tunnel junction devices can control conductance by adjusting the carrier tunneling probability through the direction and strength of the electric field in the ferroelectric insulating film.

[0059] A magnetoresistive memory device is composed of a fixed layer, an insulating film, and a free layer, and both the fixed layer and the free layer are magnetic. The magnetization direction of the fixed layer is fixed, while the magnetization direction of the free layer can be changed. In this case, when current is applied to the magnetoresistive memory device in the direction from the fixed layer to the free layer, the magnetization direction of the free layer becomes the same as that of the fixed layer, and the conductance increases. On the other hand, when current is applied to the magnetoresistive memory device in the direction opposite to that from the fixed layer to the free layer, the magnetization direction of the free layer becomes different from that of the fixed layer, and the conductance decreases. In this way, the conductance of the magnetoresistive memory device can be controlled using current.

[0060] In the case where the first semiconductor device (M1) of the signal generation module (300) is composed of a semiconductor device having a gate electrode or a control gate electrode, the threshold voltage of each device can be adjusted during the device and peripheral wiring design (physical layout) stage. As an example of a method for this, when designing the device, if the physical layout is adjusted to have components acting as a floating gate and a control gate, the threshold voltage or conductance can be set by adjusting the coupling ratio between these gates. Additionally, in the case of a device that does not have a floating gate or a charge storage layer, the threshold voltage or conductance can be set by adjusting the coupling between the gate and the peripheral metal wiring.

[0061] When designing the first semiconductor device (M1) of the signal generation module (300) by adjusting the physical layout to have components that act as a floating gate and a control gate, the coupling ratio in which the voltage of the control gate is transmitted to the floating gate varies depending on the spacing or area ratio between the two gates. Through this, even semiconductor devices without memory functions can have their threshold voltage or conductance set to various desired values.

[0062] In the case of semiconductor devices without a floating gate, the threshold voltage can be controlled by adjusting the coupling ratio between the gate electrode and the surrounding electrode. In this case, the gate electrode is designed to act as a floating gate, and the surrounding electrode acts as a control gate. Here, the threshold voltage or conductance can be changed by adjusting the coupling ratio between the floating gate and the control gate.

[0063] When the first semiconductor device (M1) of the signal generation module (300) is implemented as a device having non-volatile memory characteristics, an additional threshold voltage adjustment module may be provided. By using the threshold voltage adjustment module, the threshold voltage or conductance can be varied according to the corresponding bit position and resolution of each bit processing unit constituting the analog-to-digital converter.

[0064] The threshold voltage adjustment module can control the operation of the analog-to-digital converter by raising or lowering the threshold voltage or conductance of the first semiconductor device (M1) of the signal generation module (300). The threshold voltage adjustment module may be composed of a pulse generator and operates by changing the memory state by applying a pulse to the first semiconductor device. To program or erase the threshold voltage of the first semiconductor device (M1), a Program / Erase voltage may be applied to the gate terminal, and a '0' voltage may be applied to the source, body, or both. Meanwhile, if Program and Erase are not desired, an Inhibition voltage may be applied to the source, body, gate, or multiple of these nodes, or they may be made floating.

[0065] Meanwhile, the bit processing unit of the present invention may further include a leakage blocking module. The leakage blocking module may be electrically connected to and positioned with each of the signal generation module and the comparison module. The leakage blocking module may be composed of a semiconductor device having a polarity complementary to that of the pre-charging module. For example, if the pre-charging module is composed of a PMOS transistor, the leakage blocking module may be composed of an NMOS transistor. Additionally, by applying the same control signal to the gate electrode of the leakage blocking module and the gate electrode of the pre-charging module, it may be configured to effectively block leakage current that may occur while the node is pre-charged by the pre-charging module.

[0066] The dynamic analog-to-digital converter (3) according to the first embodiment having the above-described configuration operates based on the principle of rapidly amplifying the minute difference between the input signal and the reference voltage by utilizing the rapid feedback effect of the latch module, and thereby rapidly discharging the potential of a specific node. Specifically, the difference (V) between the input signal applied to the first semiconductor device (M1) and the first threshold voltage IN -V th,M1 [N]) is the difference between the reference signal applied to the second semiconductor device (M2) and the second threshold voltage (V Ref -V th,M2 When the difference between the input signal and the first threshold voltage is greater than [N], the input node of the signal conversion module is rapidly discharged, and accordingly, the output signal (OUT[N]) is determined to be '1' through the inverter included in the signal conversion module. On the other hand, when the difference between the input signal and the first threshold voltage is not greater than the difference between the reference signal and the second threshold voltage, the input node of the signal conversion module maintains a pre-charged state, and accordingly, the output signal (OUT[N]) is determined to be '0' through the inverter included in the signal conversion module. As such, the converter according to the first embodiment enables rapid signal determination through high-speed regeneration operation using a latch structure, making it suitable for analog-to-digital conversion applications requiring high-speed operation.

[0067] Meanwhile, the dynamic analog-to-digital converter according to the present embodiment may further comprise a thermometer-to-binary encoder configured to convert a thermometer code into a binary code. The thermometer-to-binary encoder may be connected to the output terminals of N bit processing units, receive a thermometer code from the N bit processing units, and be configured to convert the thermometer code into a binary code and output it.

[0068] The dynamic analog-to-digital converter according to the first embodiment of the present invention, having the aforementioned configuration, can perform analog-to-digital conversion operations with a single module structure, making it applicable in the field of in-memory computing. Furthermore, since the dynamic analog-to-digital converter according to the first embodiment of the present invention operates in a dynamic manner, it can reduce power consumption compared to a static in-memory ADC. Therefore, the dynamic analog-to-digital converter according to the first embodiment of the present invention can be usefully utilized in sensor systems and artificial intelligence applications that require low-power operation.

[0070] < 2nd Example >

[0071] Hereinafter, the structure and operation of a data converter according to a second embodiment of the present invention will be described in detail with reference to the attached drawings. The data converter according to the second embodiment of the present invention is a dynamic analog-to-digital converter and is characterized by being configured using steep switching devices having different threshold voltages. Here, the digital code is composed of a thermometer code consisting of N bits (where N is a natural number).

[0072] FIG. 5 is a configuration diagram illustrating a data converter according to a second embodiment of the present invention in its entirety. Referring to FIG. 5, the data converter according to the second embodiment of the present invention comprises a dynamic analog-to-digital converter (5). The dynamic analog-to-digital converter (5) includes N bit processing units (50-1, 50-2, …, 50-N). The dynamic analog-to-digital converter according to the present embodiment having the above configuration can generate a digital code composed of a thermometer code based on N binary signals output from each of the N bit processing units.

[0073] N bit processing units (50-1, 50-2, …, 50-N) are configured to correspond one-to-one with each of the N bits constituting the digital code. And, the N bit processing units (50-1, 50-2, …, 50-N) are pre-charging signals (V pre ) and input signal (V IN It is configured to receive ) in common and output the binary signals of the corresponding bits (OUT[1], OUT[2], … , OUT[N]) respectively. Here, the input signal (V in ) is an analog signal to be converted. Each bit processing unit includes a signal generation module (500), a pre-charge module (510), and a signal conversion module (520). Meanwhile, each bit processing unit may further include a threshold voltage adjustment module (not shown).

[0074] The signal generation module (500) has a threshold voltage (V) set according to the position (1~N) of the corresponding bit in the digital code. th It includes a Steep Switching Device (PF) having ). In this specification, “Steep Switching Device” means a device in which the output state is rapidly switched in response to a small change in an input signal. Input signal (V in ) is applied to the control gate electrode of the rapid switching element.

[0075] The rapid switching element included in the signal generation module may be composed of a “semiconductor device capable of causing positive feedback or latch phenomena.” Semiconductor devices capable of causing positive feedback or latch phenomena may include a Flash-gated thyristor with charge storage memory and a thyristor with memory function based on a ferroelectric material. In this case, the devices may use both n-channel and p-channels and may include 3-terminal or 4-terminal devices. Additionally, the rapid switching element of the signal generation module may also be composed of 2-terminal switching devices such as RRAM, PRAM, and FTJ (Ferroelectric Tunnel Junction). However, the more super-steep the characteristics of the rapid switching element used in the signal generation module are, the more ideally the Max Pooling operation can be implemented.

[0076] The threshold voltages of the rapid switching elements included in the N bit processing units can be linearly mapped at regular intervals according to the position of the corresponding bit, or non-linearly mapped using a non-linear activation function according to the position of the corresponding bit.

[0077] The threshold voltage adjustment module may be configured to vary the threshold voltage or conductance of a plurality of rapid switching elements included in the signal generation module according to the bit position and resolution corresponding to the bit processing unit. Since the structure and operation of the threshold voltage adjustment module of this embodiment are identical to those of the first embodiment, redundant descriptions are omitted. Meanwhile, since the method for adjusting the threshold voltage or conductance of the rapid switching elements according to this embodiment is identical to that described in the first embodiment, redundant descriptions are omitted.

[0078] The pre-charging module (510) is a module for pre-charging the input node (Node 1) of the signal conversion module and may be composed of a switching element connected between the driving power supply and the input node (Node 1) of the signal conversion module. The switching element constituting the pre-charging module (510) may be composed of a single MOSFET element, a plurality of sequentially connected MOSFET elements, a transmission gate element, or a non-volatile memory element. During the initial operation of the dynamic analog-to-digital converter according to the present embodiment, a pulse-shaped pre-charging signal (V) is applied to the switching element of the pre-charging module. pre By applying ), the input node of the signal conversion module is driven by the driving voltage (V DD It can be pre-charged with ).

[0079] The signal conversion module (520) is configured to convert the voltage of the input node into a binary signal and output a binary signal (OUT) of the corresponding bit within the digital code. The signal conversion module may be composed of an inverter circuit, a buffer circuit, or a sense amplifier. Accordingly, the signal conversion module operates to generate a binary signal by determining the voltage input to the signal conversion module based on a preset switching voltage.

[0080] The input node of the signal conversion module (520) is connected to the output terminal of the pre-charging module (510) and the anode terminal of the rapid switching element (PF) included in the signal generation module (500). Accordingly, the input node of the signal conversion module can be pre-charged by the pre-charging module and rapidly discharged by the switching operation of the rapid switching element. Through the charging and discharging operations of the input node of the signal conversion module, the signal conversion module is configured to generate and output a binary signal corresponding to the input signal.

[0081] Hereinafter, the operation of the bit processing unit of a dynamic analog-to-digital converter according to a second embodiment of the present invention having the aforementioned configuration will be explained. FIG. 6 is a flowchart illustrating the operation of the bit processing unit in a dynamic analog-to-digital converter according to a second embodiment of the present invention.

[0082] Referring to FIG. 6, first, a pre-charging signal (V) to the gate electrode of a switching element included in the pre-charging module pre By driving the switching element by applying ), the input node (Node 1) of the signal conversion module connected to the output terminal of the pre-charging module is pre-charged (step 600).

[0083] Next, an input signal (V) to the control gate terminal of the rapid switching element. IN ) is applied (step 610). At this time, the input signal (V IN ) is the analog signal to be converted.

[0084] Subsequently, based on the relationship between the threshold voltage of the rapid switching element and the input signal, the input node (Node 1) of the signal conversion module remains in a discharged or pre-charged state (step 620). Specifically, the input signal (V IN When ) is greater than the threshold voltage of the rapid switching element ( V IN > V th ), the rapid switching element is turned on to discharge the input node (Node 1) of the signal conversion module. On the other hand, the input signal (V IN When ) is not greater than the threshold voltage of the rapid switching element ( V IN < V th ), the rapid switching element remains in a turned-off state, and accordingly, the input node (Node 1) of the signal conversion module remains in a pre-charged state.

[0085] Next, the signal conversion module outputs a digital thermometer code according to the potential state of the input node (Node 1) (step 630). That is, if the input node (Node 1) of the signal conversion module is discharged, the output of the inverter included in the signal conversion module is determined to be '1'. On the other hand, if the input node (Node 1) of the signal conversion module remains in a pre-charged state, the output of the inverter of the signal conversion module is determined to be '0'. The output of the inverter of the signal conversion module forms one bit of the digital thermometer code.

[0086] FIG. 7 is a graph illustrating the operation of an ADC in a dynamic analog-to-digital converter according to a second embodiment of the present invention when the threshold voltages of rapid switching elements are linearly mapped. FIG. 7 (a) is a graph illustrating the state in which the threshold voltages of rapid switching elements are linearly mapped at regular intervals according to corresponding bits, and (b) is a graph illustrating the thermometer code output as the input voltage is converted according to the linearly mapped threshold voltages. Through FIG. 7, it can be confirmed that when the threshold voltages of rapid switching elements are linearly mapped according to corresponding bits, the analog-to-digital conversion operation is also performed linearly.

[0087] FIG. 8 is a graph illustrating the operation of an ADC in a dynamic analog-to-digital converter according to a second embodiment of the present invention when the threshold voltages of rapid switching elements are non-linearly mapped. FIG. 8 (a) is a graph illustrating the state in which the threshold voltages of rapid switching elements are non-linearly mapped according to a corresponding bit, and (b) is a graph illustrating the thermometer code output as the input voltage is converted based on the non-linearly mapped threshold voltages. Through FIG. 8, it can be confirmed that when the threshold voltages of rapid switching elements are non-linearly mapped according to a corresponding bit, it is possible to perform non-linear activation characteristics such as a sigmoid function or a tanh function while simultaneously performing an analog-to-digital conversion operation.

[0088] Through FIGS. 7 and 8, it can be seen that the dynamic analog-to-digital converter according to the second embodiment of the present invention can control the distribution and growth characteristics of the thermometer code by adjusting the interval of the threshold voltages of the rapid switching elements.

[0089] Meanwhile, the dynamic analog-to-digital converter according to the present embodiment may further comprise a thermometer-to-binary encoder configured to convert a thermometer code into a binary code. The thermometer-to-binary encoder may be connected to the output terminals of N bit processing units, receive a thermometer code from the N bit processing units, and be configured to convert the thermometer code into a binary code and output it.

[0091] <3rd Example>

[0092] Hereinafter, the structure and operation of a data converter according to a third embodiment of the present invention will be described in detail with reference to the attached drawings. The data converter according to the third embodiment of the present invention is a dynamic analog-to-digital converter and is characterized by being configured to enable max pooling using step switching devices having different threshold voltages. Here, the digital code is composed of a thermometer code consisting of N bits (where N is a natural number).

[0093] FIG. 9 is a configuration diagram illustrating a data converter according to a third embodiment of the present invention in its entirety. Referring to FIG. 9, the data converter according to the third embodiment of the present invention comprises a dynamic analog-to-digital converter (6). The dynamic analog-to-digital converter (6) includes N bit processing units (60-1, 60-2, … , 60-N) and a signal input unit (62).

[0094] The signal input section (62) is a plurality of input signals (V) to be converted. IN1, V IN2, V IN3, V IN4 ) is configured to be provided in common to N bit processing units (60-1, 60-2, … , 60-N).

[0095] N bit processing units (60-1, 60-2, … , 60-N) are configured to correspond one-to-one with each of the N bits constituting the digital code. And, the N bit processing units (60-1, 60-2, … , 60-N) are pre-charging signals (V pre ) and multiple input signals (V IN1, V IN2, V IN3, V IN4 It is configured to receive ) in common and output the corresponding bit codes by performing Max Pooling operations on multiple input signals. Here, multiple input signals (V IN1, VIN2, V IN3, V IN4 ) are multiple analog signals to be converted and Max Pooled.

[0096] Each bit processing unit (60) includes a plurality of signal generation modules (600, 601, 602, 603), a pre-charging module (610), and a signal conversion module (620). Meanwhile, each bit processing unit may further include a threshold voltage adjustment module (not shown). The dynamic analog-to-digital converter according to the present embodiment having the above-described configuration outputs a plurality of input signals from the bit processing units by performing Max Pooling operations on a bit-by-bit basis, and can generate a digital code composed of a thermometer code that is Max Pooled based on N codes output from the bit processing units.

[0097] The signal generation module (600, 601, 602, 603) includes a plurality of steep switching devices (PF) having a threshold voltage (Vth) determined according to the position of a corresponding bit in a digital code, and the steep switching devices included in the signal generation module (600, 601, 602, 603) are connected in parallel with each other. Since the structure and operation of the steep switching device of the present embodiment are identical to those of the second embodiment, a redundant description is omitted. The threshold voltages of the steep switching devices included in the N bit processing units may be linearly mapped at regular intervals according to the position of the corresponding bit, or may be non-linearly mapped using a non-linear activation function according to the position of the corresponding bit.

[0098] The pre-charging module (610) is a module for pre-charging the input node (Node 1) of the signal conversion module, and may be composed of a switching element connected between the driving voltage and the input node (Node 1) of the signal conversion module. During the initial operation of the ADC according to the present embodiment, a pulse-shaped pre-charging signal (V) to the switching element of the pre-charging module pre By applying ), the input node of the signal conversion module is driven by the driving voltage (V DD It can be pre-charged using ). Since the structure and operation of the pre-charging module (610) of this embodiment are identical to those of the second embodiment, a redundant description is omitted.

[0099] The signal conversion module (520) is configured to convert the voltage of the input node into a binary signal and output a binary signal (OUT) of the corresponding bit within the digital code. Accordingly, the signal conversion module operates to generate a binary signal by determining the voltage input to the signal conversion module based on a preset switching voltage. Since the structure and operation of the signal conversion module (620) of this embodiment are identical to those of the second embodiment, a redundant description is omitted.

[0100] The input node of the signal conversion module (620) is connected to the output terminal of the pre-charge module (610) and the anode terminal of the rapid switching elements (PF) included in the signal generation modules (600, 601, 602, 603). Accordingly, the input node of the signal conversion module can be pre-charged by the pre-charge module and rapidly discharged by the switching operation of the rapid switching elements. Through the charging and discharging operations of the input node of the signal conversion module, the signal conversion module is configured to generate and output a binary signal corresponding to the input signal.

[0101] The threshold voltage adjustment module is configured to vary the threshold voltage or conductance of a plurality of rapid switching elements included in the signal generation module according to the bit position and resolution corresponding to the bit processing unit. Since the structure and operation of the threshold voltage adjustment module of this embodiment are identical to those of the second embodiment, a redundant description is omitted. Meanwhile, since the method for adjusting the threshold voltage or conductance of the rapid switching elements according to this embodiment is identical to that described in the second embodiment, a redundant description is omitted.

[0102] Hereinafter, the operation of the bit processing unit of the dynamic analog-to-digital converter according to the third embodiment of the present invention having the aforementioned configuration will be explained.

[0103] First, a precharging signal (V) to the gate electrode of the switching element included in the pre-charging module pre By applying ) to drive the switching element, the input node (Node 1) of the signal conversion module connected to the output terminal of the pre-charging module is pre-charged.

[0104] Next, input signals (V) are respectively input to the control gate terminals of a plurality of rapid switching elements (600, 601, 602, 603) included in the signal generation module. IN1, V IN2, V IN3, V IN4 ) is applied. At this time, the input signals (V IN1, V IN2, V IN3, V IN4 ) are multiple analog signals to be converted and subjected to Max Pooling operations.

[0105] Subsequently, based on the relationship between the threshold voltage of the rapid switching element and multiple input signals, the input node (Node 1) of the signal conversion module maintains a discharged or pre-charged state. Specifically, multiple input signals (V IN1, V IN2, V IN3, V IN4If one or more of ) is greater than the threshold voltage of the rapid switching element, one or more of the rapid switching elements are turned on, and the input node (Node 1) of the signal conversion module is discharged. On the other hand, multiple input signals (V IN1, V IN2, V IN3, V IN4 When ) are not all greater than the threshold voltage of the rapid switching elements, the rapid switching elements all remain turned off, and accordingly, the input node (Node 1) of the signal conversion module remains in a pre-charged state.

[0106] Next, a digital thermometer code is output according to the potential state of the input node (Node 1) of the signal conversion module. That is, if the input node (Node 1) of the signal conversion module is discharged, the output of the inverter included in the signal conversion module is determined to be '1'. On the other hand, if the input node (Node 1) of the signal conversion module maintains a pre-charged state, the output of the inverter of the signal conversion module is determined to be '0'. The output of the inverter of the signal conversion module forms one bit of the digital thermometer code. Accordingly, when a plurality of input signals are input, the Nth bit processing unit of the converter according to the present embodiment outputs a binary signal (OUT[N]) that has undergone Max Pooling operation as follows.

[0107] OUT[N] = '1' , if max( V IN1, V IN2, V IN3, V IN4 ) > V th

[0108] OUT[N] = '0' , if max( V IN1, V IN2, V IN3, V IN4 ) < V th

[0109] FIG. 10 is a diagram showing a thermometer code generated by seven bit processing units performing Max Pooling on four input signals in a dynamic analog-to-digital converter according to a third embodiment of the present invention. Referring to FIG. 10, a plurality of input signals (V IN1, V IN2, V IN3, V IN4 The values ​​are 0.37V, 0.48V, 0.66V, and 0.51V, respectively. Also, the threshold voltages of the seven bit processing units are set to 0V, 0.1V, 0.2V, 0.3V, 0.4V, 0.5V, and 0.6V, respectively. In this case, the Dynamic ADC according to the present embodiment performs Max Pooling operations on a plurality of input signals to output the thermometer code “1111111”.

[0110] The dynamic analog-to-digital converter according to the present embodiment can perform a Max Pooling operation on multiple input signals during the analog-to-digital conversion process by configuring the signal generation module with a plurality of rapid switching elements connected in parallel. Specifically, if any of the signals input to the plurality of rapid switching elements connected in parallel exceed a corresponding threshold voltage, the input node of the signal conversion module is discharged, and as a result, a digital thermometer code corresponding to the largest input signal is output.

[0111] Meanwhile, the dynamic analog-to-digital converter according to the present embodiment may further comprise a thermometer-to-binary encoder configured to convert a thermometer code into a binary code. The thermometer-to-binary encoder may be connected to the output terminals of N bit processing units, receive a thermometer code from the N bit processing units, and be configured to convert the thermometer code into a binary code and output it.

[0112] As such, the dynamic analog-to-digital converter according to the present embodiment is configured so that the largest input signal dominates the circuit operation, thereby enabling effective implementation of Max Pooling operations at the analog signal stage prior to conversion into a digital code. Accordingly, since there is no need to perform separate Pooling operations in the digital domain, computational overhead can be reduced and overall computational efficiency improved. Therefore, the dynamic analog-to-digital converter according to the present embodiment can be usefully applied in machine learning and neuromorphic computing environments where Pooling operations are frequently required.

[0113] Although the present invention has been described above with reference to preferred embodiments, this is merely illustrative and does not limit the invention. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the invention. Furthermore, differences related to such modifications and applications should be interpreted as being included within the scope of the invention as defined in the appended claims. Explanation of the symbols

[0114] 3, 5, 6: Dynamic analog-to-digital converter 32: Reference signal input section 30, 50, 60: Bit processing unit 300, 500, 600, 601, 602, 603: Signal generation module 310 : Comparison Module 320 : Latch Module 340, 342, 510, 610: Pre-charge module 520, 620: Signal conversion module

Claims

Claim 1 An analog-to-digital converter for converting an input analog signal into a digital code composed of N bits (where N is a natural number), comprising: a reference signal input unit configured to provide a preset reference signal; and N bit processing units configured to correspond one-to-one with each of the N bits constituting the digital code, and configured to receive the input signal and the reference signal to generate and output a code for the corresponding bit; wherein each bit processing unit comprises: a signal generation module configured to receive the input signal, comprising a first semiconductor device having a first threshold voltage set according to a corresponding bit position within the digital code; a comparison module configured to receive the reference signal, comprising a second semiconductor device having a second threshold voltage characteristic; and a latch module configured to regenerate the potential of an internal node according to the operation results of the first and second semiconductor devices based on the input signal, the first threshold voltage, the reference signal, and the second threshold voltage. A data converter characterized by having a signal conversion module configured such that an input node is connected to an output node of the latch module and converts the output voltage of the latch module into a binary signal and outputs it. Claim 2 A data converter according to claim 1, wherein each bit processing unit is configured such that the output state of the latch module is determined according to the relative magnitude of the difference between the input signal and the first threshold voltage and the difference between the reference signal and the second threshold voltage, and accordingly, the output signal of the signal conversion module is determined to be either a logic value '1' or '0'. Claim 3 A data converter according to claim 1, wherein each bit processing unit further comprises a charging module configured to initialize the output node of the latch module to a pre-charged state prior to the latch operation of the latch module. Claim 4 A data converter according to claim 1, wherein the first semiconductor device of the signal generation module of each bit processing unit is composed of a semiconductor device having non-volatile memory characteristics capable of varying a threshold voltage or conductance, or is composed of one of a flash memory device, a resistance change memory device, a phase change memory device, a ferroelectric memory device, a magnetoresistance memory device, or a field-effect transistor (FET). Claim 5 A data converter according to claim 1, wherein the second semiconductor device of the comparison module of each bit processing unit is composed of one of a field-effect transistor (FET) capable of generating a constant current and a resistor, or is composed of the same device as the first semiconductor device. Claim 6 A data converter according to claim 1, wherein the latch module of each bit processing unit is composed of two cross-coupled inverters, two NMOS transistors with gates and drains connected to each other, or two PMOS transistors with gates and drains connected to each other. Claim 7 A data converter according to claim 1, wherein the signal conversion module of the bit processing unit is composed of one of an inverter circuit having a preset switching voltage, a buffer circuit, and a sense amplifier. Claim 8 A data converter according to claim 1, characterized in that the first threshold voltages of the first semiconductor devices included in the N bit processing units are linearly mapped at constant intervals according to the position of the corresponding bit. Claim 9 A data converter according to claim 1, characterized in that the first threshold voltages of the first semiconductor devices included in the N bit processing units are non-linearly mapped using a non-linear activation function according to the position of the corresponding bit. Claim 10 A data converter according to claim 1, characterized in that the N binary signals output from each of the N bit processing units constitute a thermometer code. Claim 11 The data converter according to claim 1 further comprises a thermometer-to-binary encoder configured to convert a thermometer code into a binary code, wherein the thermometer-to-binary encoder is connected to the N bit processing units, receives a thermometer code from the N bit processing units, converts the thermometer code into a binary code, and outputs the result. Claim 12 A data converter comprising: an ADC that converts one or more analog signals, which are input signals, into a digital code composed of N bits (where N is a natural number); N bit processing units configured to correspond one-to-one with each of the N bits constituting the digital code, and configured to receive the one or more input signals and generate and output a code for the corresponding bits; wherein each bit processing unit includes one or more steep switching devices having a threshold voltage set according to the position of the corresponding bit within the digital code, and the one or more input signals are each applied to the control electrodes of the steep switching devices; a signal conversion module configured such that an input node is connected to an output node of the signal generation module, the voltage of the input node changes according to the operation result of the signal generation module, and the converted voltage of the input node is converted into a binary signal and output; and a pre-charging module connected to a power supply voltage and configured to pre-charge the input node of the signal conversion module according to a pre-charging signal. Claim 13 A data converter according to claim 12, characterized in that the rapid switching element included in the signal generation module of each bit processing unit is composed of one of a flash-gated thyristor and a thyristor having a memory function. Claim 14 A data converter according to claim 12, wherein the signal conversion module is characterized by being composed of one of an inverter circuit having a preset switching voltage, a buffer circuit, and a sense amplifier. Claim 15 A data converter according to claim 12, wherein each bit processing unit is configured such that, after applying a pre-charging signal to the pre-charging module to pre-charge the input node of the signal conversion module, when an input signal is applied to the rapid switching element, the potential of the output node of the rapid switching element changes based on the relationship between the input signal and the threshold voltage, and the output code of the signal conversion module is determined according to the change in potential of the output node of the rapid switching element. Claim 16 A data converter according to claim 12, wherein a plurality of rapid switching elements included in the signal generation module of each bit processing unit are connected in parallel with each other, and a plurality of rapid switching elements included in one bit processing unit are each provided with a plurality of input signals simultaneously, and the signal conversion module of the bit processing unit is configured to output a bit value corresponding to the input signal that has the greatest influence on the potential change of the input node among the plurality of input signals, and the analog-to-digital converter outputs a digital code corresponding to the result of a Max Pooling operation of the plurality of input signals. Claim 17 A data converter according to claim 12, characterized in that the threshold voltages of the rapid switching elements of the N bit processing units are linearly mapped at constant intervals according to the position of the corresponding bit. Claim 18 A data converter according to claim 12, characterized in that the threshold voltages of the rapid switching elements of the N bit processing units are non-linearly mapped using a non-linear activation function according to the position of the corresponding bit. Claim 19 A data converter according to claim 12, characterized in that the N binary signals output from each of the signal conversion modules of the N bit processing units constitute a thermometer code. Claim 20 In claim 12, the data converter further comprises a thermometer-to-binary encoder configured to convert a thermometer code into a binary code, wherein the thermometer-to-binary encoder is connected to the N bit processing units, receives a thermometer code from the N bit processing units, converts the thermometer code into a binary code, and outputs the result.

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