Touch display device and gate driving circuit

Abstract

The embodiments of the present specification relate to a touch display device and a gate driving circuit, and more specifically, by providing a touch display device comprising two or more signal lines that transmit clock signals having the same frequency and different phases, input nodes into which clock signals transmitted through the two or more signal lines are input, and an output node that outputs one of the clock signals input to the input nodes, a touch display device and a gate driving circuit with improved touch sensing accuracy and improved display quality can be provided.

Description

Technology Field

[0001] The embodiments of this specification relate to a touch display device and a gate driving circuit. Background Technology

[0002] As the information society develops, the demand for display devices that display images is increasing, and various types of display devices, such as liquid crystal displays and organic light-emitting diode displays, are being utilized.

[0003] In order to provide a wider range of functions to the user, such a display device may provide a function that recognizes a user's touch on the display panel and performs input processing based on the recognized touch.

[0004] For example, a touch-recognition display device includes a plurality of touch electrodes disposed on or embedded in a display panel, and can detect whether a user touches the display panel and the touch coordinates by driving these touch electrodes.

[0005] Here, the display panel may include wiring for image display and wiring for touch sensing, as it displays an image and provides a touch sensing function. In some cases, the wiring for image display and the wiring for touch sensing may be placed adjacent to each other; however, since both wirings transmit signals of similar frequencies, signal interference may occur between the two wirings.

[0006] Consequently, there are issues with degraded display quality and reduced touch sensing accuracy in specific areas. The problem to be solved

[0007] The embodiments of the present specification can provide a touch display device with improved display quality by improving screen flickering.

[0008] The embodiments of the present specification can provide a touch display device with improved touch sensing accuracy of a touch electrode adjacent to a non-display area. means of solving the problem

[0009] Embodiments of the present specification may provide a touch display device comprising a multiplexer including two or more signal lines transmitting clock signals having the same frequency and different phases, input nodes into which clock signals transmitted through the two or more signal lines are input, and an output node that outputs one of the clock signals input to the input nodes.

[0010] The embodiments of the present specification may provide a gate driving circuit comprising a multiplexer including two or more input nodes and one or more output nodes, and a gate signal output circuit that receives a signal output from an output node of the multiplexer and generates a gate signal input to a subpixel. Effects of the invention

[0011] According to the embodiments of the present specification, a touch display device with improved display quality and improved screen flickering can be provided.

[0012] According to the embodiments of the present specification, a touch display device can be provided in which the touch sensing accuracy of the outermost touch electrode adjacent to the non-display area is improved. Brief explanation of the drawing

[0013] FIG. 1 is a drawing showing a touch display device according to embodiments of the present specification. FIG. 2 is a drawing showing a display part in a touch display device according to embodiments of the present specification. FIG. 3 is a diagram illustrating, by way of example, a touch sensor structure in a touch display panel of the present specification. FIG. 4 is a partial cross-sectional view of a touch display panel of the present specification, showing an example of the cross-sectional structure of the XX' portion shown in FIG. 3. FIG. 5 is a block diagram showing a gate driving circuit according to embodiments of the present specification. Figure 6 is a diagram showing an example of the gate signal output circuit (GOC) of Figure 5. FIG. 7 is a diagram for explaining why the touch sensing accuracy of touch electrodes adjacent to a non-display area is low in a touch display device according to the embodiments of the present specification. FIG. 8 is a diagram showing the change in display quality according to the frequency of the gate clock signal when the frequency of the touch driving signal is constant in a touch display device according to the embodiments of the present specification. FIG. 9 is a drawing for explaining a touch display device including a multiplexer. Figure 10 is a diagram showing an example of a gate signal output circuit into which a signal output from a multiplexer is input. FIG. 11 is a diagram exemplarily showing the timing diagram of the gate clock signal (GCLK's) and the multiplexer control signal of FIG. 10. Figure 12 is an example of the II' cross-sectional structure of Figure 7. Specific details for implementing the invention

[0014] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions may obscure the essence of the present disclosure, such detailed description may be omitted. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may include a plural unless there is a special explicit description otherwise.

[0015] Additionally, terms such as first, second, A, B, (a), (b), etc., may be used to describe the components of the present disclosure. These terms are used merely to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by such terms.

[0016] In describing the positional relationship of components, where it is stated that two or more components are "connected," "combined," or "joined," it should be understood that while the two or more components may be directly "connected," "combined," or "joined," they may also be "connected," "combined," or "joined" with other components "intervened." Here, the other components may be included in one or more of the two or more components that are "connected," "combined," or "joined" with one another.

[0017] In describing the temporal flow relationship regarding components, methods of operation, or methods of production, for example, when the temporal or sequential relationship is described using "after," "following," "next," or "before," it may include cases where the relationship is not continuous unless "immediately" or "directly" is used.

[0018] Meanwhile, where numerical values ​​or corresponding information regarding a component (e.g., levels, etc.) are mentioned, even without separate explicit notation, the numerical values ​​or corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0019] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0020] FIG. 1 is a drawing showing a touch display device (100) according to embodiments of the present specification.

[0021] The touch display device (100) according to the embodiments of the present specification can provide not only an image display function but also a touch sensing function using a finger and / or a pen, etc.

[0022] Here, the ‘pen’ may include an active pen that has signal transmission and reception functions, can perform operation in conjunction with a touch display device (100), or includes its own power source, and a passive pen that does not have signal transmission and reception functions or its own power source.

[0023] Such a touch display device (100) may include a display area (AA: Active Area) where an image is displayed and a non-display area (NA: Non-active Area) around the display area (AA).

[0024] The touch display device (100) according to the embodiments of the present specification may be, for example, a television (TV), a monitor, etc., or a mobile device such as a tablet, a smartphone, etc.

[0025] A touch display device (100) according to the embodiments of the present specification may include a display part configured to provide an image display function and a touch sensing part configured to provide a touch sensing function.

[0026] Below, with reference to FIGS. 2 to 4, the structure of the display part and touch sensing part of the touch display device (100) is briefly described.

[0027] FIG. 2 is a drawing showing a display part in a touch display device (100) according to embodiments of the present specification.

[0028] Referring to FIG. 2, the display part of the touch display device (100) according to the embodiments of the present specification may include a display panel (210), a data driving circuit (220), a gate driving circuit (230a, 230b), and a display controller (240), etc.

[0029] In the display area (AA) of the display panel (210), a plurality of data lines (DL) and a plurality of gate lines (GL) are arranged, and a plurality of subpixels (SP) are arranged in the area where the plurality of data lines (DL) and the plurality of gate lines (GL) intersect.

[0030] The non-display area (LNA, RNA) of the display panel (210) is an area where the input image is not displayed, and where subpixels (SP) are not placed, and various signal lines and a gate driving circuit (230) can be placed.

[0031] The data driving circuit (220) is configured to drive the multiple data lines (DL) by supplying data voltage to the multiple data lines (DL).

[0032] The gate driving circuit (230a, 230b) is configured to drive a plurality of gate lines (GL) by sequentially supplying scan signals to a plurality of gate lines (GL).

[0033] The display controller (240) supplies a data driving circuit control signal (DCS) and a gate driving circuit control signal (GCS) to the data driving circuit (DDC) and the gate driving circuit (GDC) to control the operation of the data driving circuit (DDC) and the gate driving circuit (GDC).

[0034] The display controller (240) starts scanning according to the timing implemented in each frame, converts the image data input from the outside to match the data signal format used by the data driving circuit (220), and outputs the converted image data (Data).

[0035] The display controller (240) may be a timing controller (TCON) used in conventional display technology, or a control device that performs other control functions in addition to the timing controller (TCON).

[0036] This display controller (240) may be implemented as a separate component from the data driving circuit (220), or it may be implemented as an integrated circuit together with the data driving circuit (220).

[0037] The data driving circuit (220) may be implemented by including at least one source driver integrated circuit (SDIC).

[0038] Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital analog converter (DAC), an output buffer, etc.

[0039] Each source driver integrated circuit (SDIC) may, in some cases, further include an analog-to-digital converter (ADC).

[0040] The gate driving circuit (230) may be implemented by including at least one gate driver integrated circuit (GDIC).

[0041] Each gate driver integrated circuit (GDIC) may include a shift register, a level shifter, etc.

[0042] The data driving circuit (220) may be located only on one side (e.g., the upper or lower side) of the display panel (210), or, depending on the driving method, panel design method, etc., may be located on both sides (e.g., the upper and lower sides) of the display panel (210).

[0043] The gate driving circuit (230a, 230b) may be located only on one side (e.g., left or right) of the display panel (210), and in some cases, depending on the driving method, panel design method, etc., it may be located on both sides (e.g., left and right) of the display panel (210).

[0044] The gate driving circuit (230a, 230b) can be implemented in a Gate In Panel (GIP) manner, formed in the form of a thin-film transistor on a non-display area (LNA, RNA) on a display panel (210).

[0045] The gate driving circuit (230a, 230b) may include a scan signal generating circuit for outputting a scan signal used to turn on or turn off switching transistors included in subpixels (SP).

[0046] The gate driving circuit (230a, 230b) may include a light-emitting signal generating circuit that outputs a light-emitting signal used to turn on or off light-emitting control transistors included in subpixels (SP).

[0047] The gate driving circuit (230a, 230b) can be arranged into a plurality of stages (ST: Stage) in the non-display area.

[0048] FIG. 3 is a diagram illustrating an exemplary touch sensor structure in a touch panel (310) of the present specification.

[0049] The touch panel (310) of the present specification may include one or more touch electrodes for providing a touch sensing function and at least one touch routing wire electrically connected to the touch electrodes.

[0050] The touch panel (310) may exist outside the display panel of FIG. 2 described above. That is, the touch panel (310) and the display panel (210) may be manufactured separately and combined. Such a touch panel (310) is referred to as an external type or an add-on type.

[0051] Alternatively, the touch panel (310) may be embedded inside the display panel. That is, when manufacturing the display panel, the touch sensor structure, such as a plurality of touch electrodes and a plurality of touch routing wires constituting the touch panel (310), may be formed together with electrodes and signal lines for driving the display. Such a touch panel (310) is referred to as an embedded type. Below, for convenience of explanation, an example is given in which the touch panel (310) is of the embedded type.

[0052] The touch display device (100) according to the embodiments of the present specification is a capacitance-based touch sensing method, and may sense touch using a mutual capacitance method or a self capacitance method.

[0053] In the case of a mutual capacitance-based touch sensing method, multiple touch electrodes can be classified into a touch driving electrode to which a touch driving signal is applied through a touch driving line, and a touch sensing electrode to which a touch sensing signal is applied through a touch sensing line and which forms capacitance with the touch driving electrode. At this time, the touch driving line and the touch sensing line are collectively referred to as a touch line, and the touch driving signal and the touch sensing signal are collectively referred to as a touch signal.

[0054] In the case of such a mutual capacitance-based touch sensing method, the presence or absence of touch and touch coordinates are detected based on the change in mutual capacitance occurring between the touch driving electrode and the touch sensing electrode depending on the presence or absence of a pointer such as a finger or pen.

[0055] In the case of a self-capacitance-based touch sensing method, each touch electrode can perform both the role of a touch driving electrode and a touch sensing electrode. That is, a touch driving signal is applied to a touch electrode through a single touch line, and a touch sensing signal transmitted from the touch electrode to which the touch driving signal is applied is received through the same touch line. Therefore, in a self-capacitance-based touch sensing method, there is no distinction between the touch driving electrode and the touch sensing electrode, nor between the touch driving line and the touch sensing line.

[0056] In the case of such self-capacitance-based touch sensing methods, the presence or absence of a touch and / or touch coordinates can be detected based on changes in capacitance occurring between a pointer, such as a finger or pen, and a touch electrode.

[0057] Referring to FIG. 3, a touch display device (100) according to embodiments of the present specification may have a mutual capacitance-based touch sensing method.

[0058] In a touch display device (100) according to the embodiments of the present specification, a mutual capacitance-based touch sensing structure may include a plurality of X-touch electrode lines (X-TEL) and a plurality of Y-touch electrode lines (Y-TEL).

[0059] A plurality of X-touch electrode lines (X-TEL) and a plurality of Y-touch electrode lines (Y-TEL) can be located on the encapsulation portion (ENCAP).

[0060] A plurality of X-touch electrode lines (X-TEL) may be arranged in a first direction, and a plurality of Y-touch electrode lines (Y-TEL) may be arranged in a second direction different from the first direction.

[0061] For example, the first direction may be the x-axis direction and the second direction may be the y-axis direction. Conversely, the first direction may be the y-axis direction and the second direction may be the x-axis direction. Also, the first direction and the second direction may be orthogonal to each other, but they may not be orthogonal.

[0062] A plurality of X-touch electrode lines (X-TEL) may be composed of multiple electrically connected X-touch electrodes. A plurality of Y-touch electrode lines (Y-TEL) may be composed of multiple electrically connected Y-touch electrodes.

[0063] Multiple X-touch electrodes and multiple Y-touch electrodes may be electrodes whose functions are distinct from each other.

[0064] For example, a plurality of X-touch electrodes may be touch driving electrodes, and a plurality of Y-touch electrodes may be touch sensing electrodes. In this case, a plurality of X-touch electrode lines (X-TEL) correspond to touch driving electrode lines, and a plurality of Y-touch electrode lines (Y-TEL) correspond to touch sensing electrode lines.

[0065] Conversely, a plurality of X-touch electrodes may be touch sensing electrodes, and a plurality of Y-touch electrodes may be touch driving electrodes. In this case, a plurality of X-touch electrode lines (X-TEL) correspond to touch sensing electrode lines, and a plurality of Y-touch electrode lines (Y-TEL) correspond to touch driving electrode lines.

[0066] Referring to FIG. 3, the touch sensor structure may include one or more touch routing lines (TL: Touch routing Line).

[0067] The touch routing wiring (TL) may include an X-touch routing wiring (X-TL) electrically connected to an X-touch electrode line (X-TEL) and a Y-touch routing wiring (Y-TL) electrically connected to a Y-touch electrode line (Y-TEL).

[0068] The X-Touch electrode line (X-TEL) may include a plurality of X-Touch electrodes arranged in the same row (or column) and one or more X-Touch electrode connecting lines that electrically connect them. Here, the X-Touch electrode connecting line that electrically connects two adjacent X-Touch electrodes may be a metal integrated with the two adjacent X-Touch electrodes, or a metal that is electrically connected to the two adjacent X-Touch electrodes through a contact hole.

[0069] In the area where the X-touch electrode line (X-TEL) and the Y-touch electrode line (Y-TEL) intersect, the X-touch electrode connection line and the Y-touch electrode connection line may intersect.

[0070] In the area where touch electrode lines intersect, when the X-touch electrode connection line and the Y-touch electrode connection line intersect, the X-touch electrode connection line and the Y-touch electrode connection line may be located on different layers.

[0071] In order to arrange a plurality of X-touch electrode lines (X-TEL) and a plurality of Y-touch electrode lines (Y-TEL) to intersect, a plurality of X-touch electrodes, a plurality of X-touch electrode connection lines, a plurality of Y-touch electrodes, and a plurality of Y-touch electrode connection lines may be located in two or more layers.

[0072] Multiple X-touch electrode lines (X-TEL) are electrically connected to the corresponding X-touch pads (X-TP) through one or more X-touch routing wires (X-TL). That is, among the multiple X-touch electrodes included in a single X-touch electrode line (X-TEL), the outermost X-touch electrode is electrically connected to the corresponding X-touch pad (X-TP) through the X-touch routing wire (X-TL).

[0073] Multiple Y-touch electrode lines (Y-TEL) are electrically connected to the corresponding Y-touch pads (Y-TP) through one or more Y-touch routing wires (Y-TL). That is, among the multiple Y-touch electrodes included in a single Y-touch electrode line (Y-TEL), the Y-touch electrode positioned at the outermost edge is electrically connected to the corresponding Y-touch pad (Y-TP) through the Y-touch line (Y-TL).

[0074] Here, when a plurality of X-touch electrodes constituting a plurality of X-touch electrode lines (X-TEL) are touch driving electrodes, a touch driving signal is supplied to the plurality of X-touch electrodes through a plurality of X-touch routing wires (X-TL). Additionally, when a plurality of Y-touch electrodes constituting a plurality of Y-touch electrode lines (Y-TEL) are touch sensing electrodes, a touch sensing signal generated at the plurality of Y-touch electrodes will be transmitted to a touch driving circuit (not shown) through a Y-touch routing wire (Y-TL).

[0075] At this time, a plurality of X-touch routing lines (X-TL) and a plurality of Y-touch routing lines (Y-TL) may be extended along a non-display area (NA) located at the outer edge of a display area (AA), and a plurality of X-touch routing lines (X-TL) and a plurality of Y-touch routing lines (Y-TL) may partially overlap in the non-display area (NA).

[0076] For example, when a plurality of X-touch routing lines (X-TL) and a plurality of Y-touch routing lines (Y-TL) are formed on different layers in a non-display area (NA), the plurality of X-touch routing lines (X-TL) and the plurality of Y-touch routing lines (Y-TL) may overlap in some sections of the outer edge of the display area (AA).

[0077] At this time, in the area adjacent to the touch pad (TP), the touch routing wiring (TL) may be formed as a single electrode structure for transmitting a touch signal, or it may be formed as a double stacked structure connected to at least one contact hole to reduce electrical resistance to the touch signal or to prepare for the case of a disconnection.

[0078] When the touch routing wiring (TL) is formed in a double-layered structure, a touch bridge line extending in the same direction as the touch routing wiring (TL) may be located at a vertical upper or vertical lower position of the touch routing wiring (TL).

[0079] In the non-display area (NA), one or more contact holes that electrically connect the touch routing wiring (TL) and the touch bridge line may be formed at regular intervals.

[0080] Meanwhile, when multiple X-touch routing lines (X-TL) and multiple Y-touch routing lines (Y-TL) are formed on the same layer, there may be no overlapping areas.

[0081] FIG. 4 is a partial cross-sectional view of a touch display panel of the present specification, showing an example of the cross-sectional structure of the XX' portion shown in FIG. 3.

[0082] In FIG. 4, the touch electrode (TE) is shown in a plate shape, but this is merely an example and it may be of a mesh type. And, if the touch electrode (TE) is of a mesh type, the opening (OA) of the touch electrode (TE) may be located on the light-emitting area of ​​the subpixel.

[0083] A driving transistor (DRT) that controls the current supplied to the light-emitting element (ED) placed in each subpixel of the active area can be placed on the substrate (SUB).

[0084] The driving transistor (DRT) includes a first node electrode (NE1) corresponding to the gate electrode, a second node electrode (NE2) corresponding to either the source electrode or the drain electrode, a third node electrode (NE3) corresponding to the other electrode corresponding to the source electrode or the drain electrode, and a semiconductor layer (SEMI), etc.

[0085] The first node electrode (NE1) and the semiconductor layer (SEMI) can be overlapped with the gate insulating film (GI) in between. The second node electrode (NE2) is formed on the insulating layer (INS) and contacts one side of the semiconductor layer (SEMI), and the third node electrode (NE3) is formed on the insulating layer (INS) and contacts the other side of the semiconductor layer (SEMI).

[0086] The light-emitting element (ED) may include a first electrode (E1) corresponding to an anode electrode (or cathode electrode), a light-emitting layer (EL) formed on the first electrode (E1), and a second electrode (E2) corresponding to a cathode electrode (or anode electrode) formed on the light-emitting layer (EL).

[0087] The first electrode (E1) is electrically connected to the second node electrode (NE2) of the driving transistor (DRT) exposed through a pixel contact hole penetrating the planarization layer (PLN).

[0088] A light-emitting layer (EL) is formed on a first electrode (E1) of a light-emitting region provided by a bank. The light-emitting layer (EL) is formed by stacking a hole-related layer, a light-emitting layer, and an electron-related layer in that order, or in reverse order, on the first electrode (E1). A second electrode (E2) is formed to face the first electrode (E1) with the light-emitting layer (EL) in between.

[0089] The encapsulation section (ENCAP) blocks external moisture or oxygen from penetrating the light-emitting element (ED), which is vulnerable to external moisture or oxygen.

[0090] The encapsulation portion (ENCAP) may be arranged as a single layer, but as illustrated in FIG. 4, it may also be arranged as a plurality of layers (PAS1, PCL, PAS2). For example, when the encapsulation portion (ENCAP) is composed of a plurality of layers (PAS1, PCL, PAS2), the encapsulation portion (ENCAP) may include one or more inorganic encapsulation layers (PAS1, PAS2) and one or more organic encapsulation layers (PCL). As a specific example, the encapsulation portion (ENCAP) may be arranged in a structure in which a first inorganic encapsulation layer (PAS1), an organic encapsulation layer (PCL), and a second inorganic encapsulation layer (PAS2) are stacked in sequence.

[0091] Here, the organic encapsulation layer (PCL) may further include at least one organic encapsulation layer or at least one inorganic encapsulation layer.

[0092] A first inorganic encapsulation layer (PCL) is formed on a substrate (SUB) on which a second electrode (E2), corresponding to the cathode electrode, is formed so as to be closest to the light-emitting element (ED). This first inorganic encapsulation layer (PAS1) is formed from an inorganic insulating material capable of low-temperature deposition, such as silicon nitride (SilNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3), for example. Since the first inorganic encapsulation layer (PAS1) is deposited at a low temperature, the first inorganic encapsulation layer (PAS1) can prevent damage to the light-emitting layer (EL), which contains organic materials susceptible to high temperatures, during the deposition process.

[0093] The organic encapsulation layer (PCL) can be formed with an area smaller than that of the first inorganic encapsulation layer (PAS1), and in this case, the organic encapsulation layer (PCL) can be formed to expose both ends of the first inorganic encapsulation layer (PAS1).

[0094] The organic encapsulation layer (PCL) acts as a buffer to relieve stress between layers caused by bending of the organic light-emitting touch display and can enhance planarization performance. The organic encapsulation layer (PCL) can be formed from organic insulating materials such as, for example, acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbon (SiOC).

[0095] Meanwhile, when the organic encapsulation layer (PCL) is formed using an inkjet method, one or more dams (DAM) may be formed in the dam area corresponding to the boundary area between the non-display area (NA) and the display area (AA), or in a part of the non-display area (NA).

[0096] For example, referring to FIG. 4, the dam area is located between the pad area and the display area (AA), where a plurality of X-touch pads (X-TP) and a plurality of Y-touch pads (Y-TP) are formed in the non-display area (NA). In this dam area, there may be a primary dam (DAM1) adjacent to the display area (AA) and a secondary dam (DAM2) adjacent to the pad area.

[0097] One or more dams (DAM) placed in the dam area can prevent the liquid organic encapsulation layer (PCL) from collapsing in the direction of the non-display area (NA) and encroaching upon the pad area when the liquid organic encapsulation layer (PCL) is laminated on the display area (AA).

[0098] This effect can be further enhanced when a primary dam (DAM1) and a secondary dam (DAM2) are provided, as shown in FIG. 4.

[0099] The primary dam (DAM1) and / or secondary dam (DAM2) may be formed as a single-layer or multi-layer structure. For example, the primary dam (DAM1) and / or secondary dam (DAM2) may be formed simultaneously with at least one of a bank and a spacer (not shown) using the same material. In this case, the dam structure can be formed without a separate additional mask process or increased costs.

[0100] Additionally, the primary dam (DAM1) and / or secondary dam (DAM2) may have a structure in which a first weapon encapsulation layer (PAS1) and / or a second weapon encapsulation layer (PAS2) are stacked on a bank, as shown in FIG. 4.

[0101] Additionally, the organic bag layer (PCL) containing organic material may be located only on the inner side of the primary dam (DAM1), as shown in FIG. 4. Alternatively, the organic bag layer (PCL) containing organic material may also be located on the upper part of at least some of the primary dam (DAM1) and the secondary dam (DAM2). For example, the organic bag layer (PCL) may be located on the upper part of the primary dam (DAM1).

[0102] The second inorganic encapsulation layer (PAS2) may be formed on a substrate (SUB) on which the organic encapsulation layer (PCL) is formed, so as to cover the upper surface and side surface of the organic encapsulation layer (PCL) and the first inorganic encapsulation layer (PAS1), respectively. The second inorganic encapsulation layer (PAS2) can minimize or block external moisture or oxygen from penetrating into the organic encapsulation layer (PCL) and the first inorganic encapsulation layer (PAS1). This second inorganic encapsulation layer (PAS2) may be formed from an inorganic insulating material, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride oxide (SiON), or aluminum oxide (Al2O3), for example.

[0103] A touch buffer film (T-BUF) can be placed on this encapsulation portion (ENCAP).

[0104] A touch buffer film (T-BUF) may be located between a touch sensor metal comprising an X-touch electrode (X-TE), a Y-touch electrode (Y-TE), an X-touch electrode connection wire (X-CL), and a Y-touch electrode connection wire (Y-CL), and a second electrode (E2) of a light-emitting element (ED).

[0105] The touch buffer film (T-BUF) can be designed so that the distance between the touch sensor metal and the second electrode (E2) of the light-emitting element (ED) is maintained at a predetermined minimum distance (e.g., 1 μm). Accordingly, parasitic capacitance formed between the touch sensor metal and the second electrode (E2) of the light-emitting element (ED) can be reduced or prevented, thereby preventing a decrease in touch sensitivity caused by parasitic capacitance.

[0106] Without such a touch buffer film (T-BUF), an X-touch electrode (X-TE), a Y-touch electrode (Y-TE), an X-touch electrode connection wire (X-CL), and a Y-touch electrode connection wire (Y-CL) may be disposed on the encapsulation portion (ENCAP).

[0107] In addition, the touch buffer film (T-BUF) can block chemicals (such as developing solution or etching solution) used during the manufacturing process of the touch sensor metal placed on the touch buffer film (T-BUF) or moisture from the outside from penetrating into the light-emitting layer (EL) containing organic material. Accordingly, the touch buffer film (T-BUF) can prevent damage to the light-emitting layer (EL), which is vulnerable to chemicals or moisture.

[0108] The touch buffer film (T-BUF) can be formed at a low temperature (e.g., 100°C) or lower to prevent damage to the light-emitting layer (EL) containing organic material that is susceptible to high temperatures. The touch buffer film (T-BUF) can be formed from an organic insulating material having a low dielectric constant of 1 to 3. The touch buffer film (T-BUF) can be formed from an acrylic-based, epoxy-based, or siloxane-based material. The touch buffer film (T-BUF), which has planarization performance due to the organic insulating material, can prevent damage to each encapsulation layer (PAS1, PCL, PAS2) constituting the encapsulation portion (ENCAP) due to bending of the organic light-emitting touch display device and prevent breakage of the touch sensor metal formed on the touch buffer film (T-BUF).

[0109] In some cases, this touch buffer film (T-BUF) may be omitted in a form that is not located on the encapsulation portion (ENCAP). For example, by increasing the thickness of the second inorganic encapsulation layer (PAS2), the touch buffer film (T-BUF) may not be placed, and the touch sensor metal may be placed directly on the encapsulation portion (ENCAP).

[0110] According to the mutual-capacitance-based touch sensor structure, an X-touch electrode line (X-TEL) and a Y-touch electrode line (Y-TEL) are disposed on a touch buffer film (T-BUF), and the X-touch electrode line (X-TEL) and the Y-touch electrode line (Y-TEL) can be disposed in an intersecting manner.

[0111] A Y-touch electrode line (Y-TEL) may include a plurality of Y-touch electrodes (Y-TE) and a plurality of Y-touch electrode connection wires (Y-CL) that electrically connect the plurality of Y-touch electrodes (Y-TE).

[0112] Referring to FIG. 4, a plurality of Y-touch electrodes (Y-TE) and a plurality of Y-touch electrode connecting wires (Y-CL) may be located on different layers with a touch insulating film (ILD) in between. Additionally, Y-touch electrodes (Y-TE) arranged adjacently in one direction may be electrically connected to each other through the Y-touch electrode connecting wires (Y-CL).

[0113] The Y-touch electrode connection wiring (Y-CL) can be arranged to overlap with the bank. Accordingly, it is possible to prevent the opening rate from being reduced by the Y-touch electrode connection wiring (Y-CL).

[0114] The X-touch electrode connection wiring (X-CL) is placed on the same plane as the X-touch electrode (X-TE) and is electrically connected to two adjacent X-touch electrodes (X-TE) in one direction without a separate contact hole, or can be formed integrally with two adjacent X-touch electrodes (X-TE) in one direction.

[0115] The X-touch electrode connection wiring (X-CL) can be arranged to overlap with the bank. Accordingly, the aperture ratio can be prevented from being reduced by the X-touch electrode connection wiring (X-CL).

[0116] Meanwhile, the Y-touch electrode line (Y-TEL) can be electrically connected to the touch driving circuit through the Y-touch routing wiring (Y-TL) and the Y-touch pad (Y-TP). Similarly, the X-touch electrode line (X-TEL) can be electrically connected to the touch driving circuit through the X-touch routing wiring (X-TL) and the X-touch pad (X-TP).

[0117] A touch driving circuit (not shown) is a circuit that supplies a touch driving signal to a touch panel (310) and detects a touch sensing signal from the touch panel (310).

[0118] The touch display device (100) according to the embodiments of the present specification may further include a touch controller (not shown) that senses whether a user touches and / or the touch location on a touch panel (310) based on a touch sensing signal detected by a touch driving circuit.

[0119] The touch driving circuit and touch controller may be implemented as separate components, or, in some cases, integrated into a single component.

[0120] The X-touch pad (X-TP) may be formed separately from the X-touch routing wiring (X-TL), or it may be formed by extending the X-touch routing wiring (X-TL). The Y-touch pad (Y-TP) may be formed separately from the Y-touch routing wiring (Y-TL), or it may be formed by extending the Y-touch routing wiring (Y-TL).

[0121] In the case where an X-touch pad (X-TP) is formed by extending an X-touch routing wire (X-TL) and a Y-touch pad (Y-TP) is formed by extending a Y-touch routing wire (Y-TL), the X-touch pad (X-TP), the X-touch routing wire (X-TL), the Y-touch pad (Y-TP), and the Y-touch routing wire (Y-TL) may be composed of the same first conductive material. Here, the first conductive material may be formed in a single-layer or multi-layer structure using a metal with strong corrosion and acid resistance and good conductivity, such as Al, Ti, Cu, or Mo, for example.

[0122] For example, the X-touch pad (X-TP), X-touch routing wiring (X-TL), Y-touch pad (Y-TP), and Y-touch routing wiring (Y-TL) made of the first conductive material can be formed into a three-layer stacked structure, such as Ti / Al / Ti or Mo / Al / Mo.

[0123] Meanwhile, a pad cover electrode (not shown) capable of covering the X-touch pad (X-TP) and the Y-touch pad (Y-TP) may also be placed.

[0124] The cover electrode may be composed of a second conductive material. Here, the second conductive material may be formed from a transparent conductive material such as ITO or IZO, which has strong corrosion resistance and acid resistance. This pad cover electrode may be bonded to a touch driving circuit by being formed to be exposed by a touch buffer film (T-BUF), or may be bonded to a circuit film on which a touch driving circuit is mounted.

[0125] The Y-touch routing wiring (Y-TL) may be electrically connected to the Y-touch electrode (Y-TE) through a touch routing wiring contact hole, or may be integrated with the Y-touch electrode (Y-TE).

[0126] These Y-touch routing wires (Y-TL) can be extended to the non-display area (NA) and electrically connected to the Y-touch pad (Y-TP) by passing through the top and side of the encapsulation portion (ENCAP) and the top and side of the dam (DAM). Accordingly, the Y-touch routing wires (Y-TL) can be electrically connected to the touch driving circuit through the Y-touch pad (Y-TP).

[0127] The Y-touch routing wiring (Y-TL) can transmit a touch sensing signal from the Y-touch electrode (Y-TE) to the touch driving circuit, or receive a touch driving signal from the touch driving circuit and transmit it to the Y-touch electrode.

[0128] The X-touch routing wiring (X-TL) may be electrically connected to the X-touch electrode through a touch routing wiring contact hole, or may be integrated with the X-touch electrode (X-TE).

[0129] These X-touch routing wires (X-TL) can be extended to the non-display area (NA) and passed through the top and side of the encapsulation area (ENCAP) and the top and side of the dam (DAM) to be electrically connected to the X-touch pad (X-TP). Accordingly, the X-touch routing wires (X-TL) can be electrically connected to the touch driving circuit through the X-touch pad (X-TP).

[0130] The X-touch routing wiring (X-TL) can receive a touch driving signal from the touch driving circuit and transmit it to the X-touch electrode (X-TE), and can also transmit a touch sensing signal from the X-touch electrode (X-TE) to the touch driving circuit.

[0131] The arrangement of X-touch routing wiring (X-TL) and Y-touch routing wiring (Y-TL) can be varied depending on the panel design specifications.

[0132] A touch protection film (PAC) may be placed on the X-touch electrode (X-TE) and the Y-touch electrode (Y-TE). This touch protection film (PAC) may be extended to the front or back of the dam and placed on the X-touch routing wiring (X-TL) and the Y-touch routing wiring (Y-TL).

[0133] Meanwhile, the cross-sectional view of FIG. 4 conceptually illustrates the structure, and depending on the viewing direction or position, the position, thickness, or width of each pattern (various layers or various electrodes) may vary, and the connection structure of the various patterns may also be changed. Additionally, there may be extra layers in addition to the various layers depicted, and some of the various layers depicted may be omitted or integrated. For example, the width of the bank may be narrower than shown in the drawing, and the height of the dam may be lower or higher than shown in the drawing.

[0134] Additionally, the cross-sectional view of FIG. 4 illustrates a structure in which a touch electrode (TE), a touch routing wire (TL), etc. are arranged entirely on a subpixel to show an example of a structure electrically connected to a touch pad (TP) along the inclined surface of a touch routing wire (TL) and an encapsulation portion (ENCAP). However, if the touch electrode (TE), etc. is of a mesh type, an opening (OA) of the touch electrode (TE) may be located on the light-emitting area of ​​the subpixel. Furthermore, a color filter may be additionally arranged on the encapsulation portion (ENCAP), and the color filter may be located on the touch electrode (TE) or between the encapsulation portion (ENCAP) and the touch electrode (TE).

[0135] FIG. 5 is a block diagram showing a gate driving circuit according to embodiments of the present specification.

[0136] Referring to FIG. 5, the gate driving circuit includes a gate signal output circuit (GOC).

[0137] Referring to FIG. 5, the gate driving circuit is arranged in a gate-in-panel (GIP) manner in the non-display area (NA) of the display panel and includes a plurality of stages (ST1, ST2, ST3, ST4, etc.).

[0138] The gate driving circuit operates based on two-phase gate clock signals (GCLKs), a start signal (GVST), a low potential gate voltage (VGL), and a high potential gate voltage (VGH) to generate a gate output signal (GO: Gate Output signal), and the generated gate output signals (GO1, GO2, GO3, GO4, etc.) are supplied to each subpixel (SP1, PS2, SP3, SP4, etc.).

[0139] Meanwhile, as described above, the gate driving circuit may include a scan signal generating circuit and a light emission signal generating circuit.

[0140] The gate signal (Vgate) may be a scan signal (SCAN) for controlling the turn-on and turn-off of a switching transistor included in a subpixel (SP). Alternatively, the gate signal (Vgate) may be a light emission signal (EM) for controlling the turn-on and turn-off of a light emission control transistor included in a subpixel (SP).

[0141] For convenience of explanation, the following description is exemplified as a circuit in which the gate signal output circuit (GOC) is configured to output a scan signal (SCAN); however, the embodiments of this specification may be applied in the same way even if the gate signal output circuit (GOC) is configured to output a light emission signal (EM).

[0142] Figure 6 is a diagram showing an example of the gate signal output circuit (GOC) of Figure 5.

[0143] Referring to FIG. 6, a gate signal output circuit (GOC) according to embodiments of the present specification may include first to seventh transistors (T1 to T7), an auxiliary transistor (Tbv), a first capacitor (CB), and a second capacitor (CQB).

[0144] The first transistor (T1) is switched according to the second gate clock signal (GCLK2) to supply a start signal (GVST) to the Q1 node (Q1).

[0145] The second transistor (T2) is switched according to the first gate clock signal (GCLK1), so that either the source electrode or the drain electrode is electrically connected to the Q1 node (Q1).

[0146] The third transistor (T3) is switched according to the potential of the QB node (QB) to supply a high potential gate voltage (VGH) to either the source electrode or the drain electrode of the second transistor (T2).

[0147] The fourth transistor (T4) is switched according to the second gate clock signal (GCLK2) to supply a low potential gate voltage (VGL) to the QB node (QB).

[0148] The fifth transistor (T5) is switched according to the potential of the Q1 node (Q1) to supply the second gate clock signal (GCLK2) to the QB node (QB).

[0149] The sixth transistor (T6) is an output buffer whose operation is controlled according to the potential of the Q2 node (Q2). When the sixth transistor (T6) is activated when the Q2 node (Q2) is at a low gate voltage (VGL), it outputs a scan signal of a high gate voltage (VGH) to the output node (N).

[0150] The auxiliary transistor (Tbv) is kept in a turned-on state by the low potential gate voltage (VGL). The auxiliary transistor (Tbv) keeps the voltages of the Q1 node (Q1) and the Q2 node (Q2) substantially the same.

[0151] The first capacitor (CQ) is connected between the Q2 node (Q2) and the output node (N) and can be configured to store the voltage of the Q2 node (Q2).

[0152] A second capacitor (CQB) is connected between the QB node (QB) and the input terminal of the high potential gate voltage (VGH) and can be configured to store the voltage of the QB node (QB).

[0153] FIG. 7 is a diagram for explaining why the touch sensing accuracy of touch electrodes adjacent to a non-display area (NA) is low in a touch display device (100) according to embodiments of the present specification.

[0154] Referring to FIG. 7, the touch display device (100) according to the embodiments of the present specification has touch routing wires (TL) and signal wires (SL) located in a non-display area (LNA, RNA) outside the display area (AA).

[0155] As described above, the touch routing lines (TL) are electrically connected to an X-touch electrode line (X-TEL) and a Y-touch electrode line (Y-TEL) disposed on a touch panel, and the X-touch electrode line (X-TEL) and the Y-touch electrode line (Y-TEL) each include one or more touch electrodes.

[0156] Meanwhile, a gate driving circuit of the gate-in-panel (GIP) type may be disposed in at least one of the non-display areas (LNA, RNA) on both sides of the display panel.

[0157] The gate driving circuit receives a gate clock signal (GCLK) and outputs a gate signal to the gate line. This gate clock signal (GCLK) can be input to the gate driving circuit through a signal line (SL) located in the non-label area (LNA, RNA).

[0158] The touch routing wiring (TL) and the signal line (SL) can both be placed in the non-display area (LNA, RNA). To prevent interference between the touch routing wiring (TL) and the signal line (SL), the touch routing wiring (TL) and the signal line (SL) can be placed on different layers. Additionally, to prevent interference between the touch routing wiring (TL) and the signal line (SL), a shielding electrode (not shown) can be placed between the touch routing wiring (TL) and the signal line (SL).

[0159] However, during the process of forming these shielding electrodes, if the shielding electrodes are formed incompletely, interference may occur between the touch routing wiring (TL) and the signal line (SL). The interference problem between the touch routing wiring (TL) and the signal line (SL) can be particularly significant in the outermost touch routing wiring (TL) adjacent to the signal line (SL) that transmits the gate clock signal (GCLK).

[0160] In the X-touch electrode line (X-TEL) and Y-touch electrode line (Y-TEL) electrically connected to the outermost touch routing wiring (TL), a problem of reduced touch sensing accuracy may occur. The problem described above may become more serious when the frequency of the gate clock signal (GCLK) and the frequency of the touch driving signal input to the touch routing wiring (TL) are the same or similar.

[0161] The touch driving circuit (TDC) supplies a touch driving signal to the touch panel and detects a touch sensing signal from the touch panel, but due to interference between the touch routing wiring (TL) and the signal line (SL), a problem may occur in which touch accuracy is reduced in some areas of the touch panel.

[0162] FIG. 8 is a diagram showing the change in display quality according to the frequency of the gate clock signal (GCLK) when the frequency of the touch driving signal (TDS) is constant in a touch display device (100) according to embodiments of the present specification.

[0163] Referring to FIG. 8, it can be seen that when the frequency of the touch driving signal (TDS) is constant, the level of screen flickering of the touch display device (100) increases in the range where the frequency of the gate clock signal (GCLK) is the same as or similar to the frequency of the touch driving signal (TDS).

[0164] Screen flickering may be a phenomenon caused by interference occurring between a signal line (SL) into which a gate clock signal (GCLK) is input and a touch driving signal (TDS) having a frequency equal to or similar to that of the gate clock signal (GCLK).

[0165] The screen flicker level may be a relative value. When the screen flicker level is 1, it may be the state of the screen at the point when screen flicker is visually perceived on the display panel.

[0166] For example, when the frequency of the touch driving signal (TDS) input to the touch routing wiring is constant at about 233 kHz, screen flickering may be visible in the range where the frequency of the gate clock signal (GCLK) is about 230 kHz to about 260 kHz.

[0167] When the frequency of the touch driving signal (TDS) is constant, the frequency band of the gate clock signal (GCLK) where screen flickering is visible can be defined as the high interference frequency band.

[0168] When the frequency of the touch driving signal (TDS) is constant, the frequency band of the gate clock signal (GCLK) at which screen flickering is visible below a certain level can be defined as a non-interference frequency band or a low-interference frequency band.

[0169] Referring to FIG. 8, based on the case where the frequency of the touch driving signal (TDS) is approximately 233 kHz, the band in which the frequency of the gate clock signal (GCLK) is 230 kHz or higher and 260 kHz or lower can be defined as a high interference frequency band. When the frequency of the gate clock signal (GCLK) is 255 kHz, the screen flickering phenomenon can be most clearly observed.

[0170] In addition, the band where the frequency of the gate clock signal (GCLK) is less than 230 kHz and the band where it exceeds 260 kHz can be defined as a non-interference frequency band or a low-interference frequency band.

[0171] If the frequency of the gate clock signal (GCLK) falls within the non-interference frequency band or the low-interference frequency band, screen flickering may not be visible on the display panel.

[0172] Accordingly, there is a need for a method to switch the frequency band of the gate clock signal (GCLK) input to the signal line (SL) from a high-interference frequency band to a non-interference frequency band or a low-interference frequency band.

[0173] FIG. 9 is a drawing for explaining a touch display device (100) including a multiplexer.

[0174] Referring to FIG. 9, a touch display device (100) according to embodiments of the present specification includes at least one multiplexer (MUX).

[0175] These multiplexers (MUX) can be located inside the gate driving circuits (230a, 230b). When the gate driving circuits (230a, 230b) are located in a gate-in-panel (GIP) manner, the multiplexers (MUX) can be placed in each stage (ST1, ST2, ST3, ST4, etc.).

[0176] Two or more gate clock signals (GCLKs) are input to the multiplexer (MUX). The operation timing of the multiplexer (MUX) is controlled by a multiplexer control signal (MCS). The multiplexer control signal (MCS) may be a type of gate drive circuit control signal (GCS).

[0177] The multiplexer (MUX) outputs at least one gate clock signal among two or more input gate clock signals (GCLK's) to the gate signal output circuit (GOC).

[0178] The gate clock signal (GCLK's) and the multiplexer control signal (MCS) can be transmitted through the signal line (SL) of the non-display area (NA) and input to the multiplexer (MUX) of each stage (ST1, ST2, ST3, ST4).

[0180] * FIG. 10 is a diagram showing an example of a gate signal output circuit (GOC) into which a signal output from a multiplexer (MUX) is input. FIG. 11 is a diagram showing an exemplary timing diagram of the gate clock signal (GCLK's) and multiplexer control signal (MCS) of FIG. 10.

[0181] Referring to FIG. 10, the multiplexer (MUX) may include two sub-multiplexers (Sub MUX1, Sub MUX2).

[0182] At least two gate clock signals (GCLK1-1, GCLK1-2) are input to the first sub-multiplexer (Sub MUX1). The first gate clock signal (GCLK1-1) is input to the first node (N1), which is the input node of the first sub-multiplexer (Sub MUX1). The second gate clock signal (GCLK1-2) is input to the second node (N2), which is the input node of the first sub-multiplexer (Sub MUX1).

[0183] The first sub-multiplexer (Sub MUX1) has its operation timing determined by a multiplexer control signal (MCS) and outputs either the signal input to the first node (N1) or the signal input to the second node (N2) to the third node (N3), which is the output node.

[0184] The signal output from the third node (N3) of the first sub-multiplexer (Sub MUX1) is input to the first gate clock signal (GCLK1) input node of the gate signal output circuit (GOC).

[0185] Referring to FIGS. 10 and FIGS. 11, the first sub-multiplexer (Sub MUX1) can electrically connect the first node (N1) and the third node (N3) when the voltage level of the multiplexer control signal (MCS) is either a high level or a low level. The first sub-multiplexer (Sub MUX1) can electrically connect the second node (N2) and the third node (N3) when the voltage level of the multiplexer control signal (MCS) is either a high level or a low level.

[0186] Meanwhile, at least two gate clock signals (GCLK2-1, GCLK2-2) are input to the second sub-multiplexer (Sub MUX2). The second-1 gate clock signal (GCLK2-1) is input to the first node (N1), which is the input node of the second sub-multiplexer (Sub MUX2). The second-2 gate clock signal (GCLK2-2) is input to the second node (N2), which is the input node of the second sub-multiplexer (Sub MUX2).

[0187] The second sub-multiplexer (Sub MUX2) has its operation timing determined by a multiplexer control signal (MCS) and outputs either the signal input to the first node (N1) or the signal input to the second node (N2) to the third node (N3), which is the output node.

[0188] The signal output from the third node (N3) of the second sub-multiplexer (Sub MUX2) is input to the second gate clock signal (GCLK2) of the gate signal output circuit (GOC).

[0189] Referring to FIGS. 10 and 11, the second sub-multiplexer (Sub MUX2) can electrically connect the first node (N1) and the third node (N3) when the voltage level of the multiplexer control signal (MCS) is either a high level or a low level. The first sub-multiplexer (Sub MUX1) can electrically connect the second node (N2) and the third node (N3) when the voltage level of the multiplexer control signal (MCS) is either a high level or a low level.

[0190] The multiplexer control signal (MCS) input to the first sub-multiplexer (Sub MUX1) and the second sub-multiplexer (Sub MUX2) may be the same signal. By placing a single multiplexer control signal (MCS) input wiring in the non-display area (NA), both sub-multiplexers (Sub MUX1, Sub MUX2) can be controlled.

[0191] For convenience of explanation, the following description assumes that the first sub-multiplexer (Sub MUX1) and the second sub-multiplexer (Sub MUX2) electrically connect the first node (N1) and the third node (N3) when the voltage level of the multiplexer control signal (MCS) is high, and electrically connect the second node (N2) and the third node (N3) when the voltage level of the multiplexer control signal (MCS) is low.

[0192] Referring to FIG. 11, the frequency of the first-1 gate clock signal (GCLK1-1) and the first-2 gate clock signal (GCLK1-2) input to the first sub-multiplexer (Sub MUX1) is half the frequency of the first gate clock signal (GCLK1) input to the gate signal output circuit (GOC).

[0193] Additionally, the frequency of the 2-1 gate clock signal (GCLK2-1) and the 2-2 gate clock signal (GCLK2-2) input to the 2nd sub-multiplexer (Sub MUX2) is half the frequency of the 2nd gate clock signal (GCLK2) input to the gate signal output circuit (GOC).

[0194] During the period when the voltage level of the multiplexer control signal (MCS) is at a high level, the multiplexer (MUX) can output the first-1 gate clock signal (GCLK1-1) and the second-1 gate clock signal (GCLK2-1) to the gate signal output circuit (GOC), respectively.

[0195] During the period when the voltage level of the multiplexer control signal (MCS) is at a low level, the multiplexer (MUX) can output the first-2 gate clock signal (GCLK1-2) and the second-2 gate clock signal (GCLK2-2) to the gate signal output circuit (GOC), respectively.

[0196] The first-1 gate clock signal (GCLK1-1), the first-2 gate clock signal (GCLK1-2), the second-1 gate clock signal (GCLK2-1), and the second-2 gate clock signal (GCLK2-2) are each signals having a high-level voltage period of 1 horizontal signal period (1H) and a low-level voltage period of 3 horizontal signal periods (3H) during one cycle.

[0197] The phase difference between the 1-1 gate clock signal (GCLK1-1) and the 1-2 gate clock signal (GCLK1-2) is 180 degrees (180°). The phase difference between the 2-1 gate clock signal (GCLK2-1) and the 2-2 gate clock signal (GCLK2-2) is 180 degrees (180°).

[0198] During the period when the voltage level of the 1-1 gate clock signal (GCLK1-1) is at a high level, the voltage level of the 2-1 gate clock signal (GCLK2-1) is at a low level. During the period when the voltage level of the 1-1 gate clock signal (GCLK1-1) is at a low level, the voltage level of the 2-1 gate clock signal (GCLK2-1) is at a high level.

[0199] During the period when the voltage level of the first-2 gate clock signal (GCLK1-2) is at a high level, the voltage level of the second-2 gate clock signal (GCLK2-2) is at a low level. During the period when the voltage level of the first-2 gate clock signal (GCLK1-2) is at a low level, the voltage level of the second-2 gate clock signal (GCLK2-2) is at a high level.

[0200] The multiplexer control signal (MCS) is a signal having a high-level voltage period of two horizontal signal periods (2H) and a low-level voltage period of two horizontal signal periods (2H) during one cycle.

[0201] The period of the multiplexer control signal (MCS) and the period of the first-1 gate clock signal (GCLK1-1), the first-2 gate clock signal (GCLK1-2), the second-1 gate clock signal (GCLK2-1), and the second-2 gate clock signal (GCLK2-2) may be the same, for example, the same as 4 horizontal periods (4H).

[0202] 1 The length of the horizontal period (1H) can be defined as the length of the period during which the gate signal (Vgate) of the turn-on level voltage is input to the subpixel (SP).

[0203] Below, with reference to FIG. 11, the signal input to the first gate clock signal (GCLK1) input node and the signal input to the second gate clock signal (GCLK2) input node during one cycle of the multiplexer control signal (MCS) are described.

[0204] During the first horizontal signal period of Fig. 11, the voltage level of the multiplexer control signal (MCS) is high, and the multiplexer (MUX) outputs the first-1 gate clock signal (GCLK1-1) and the second-1 gate clock signal (GCLK2-1).

[0205] Accordingly, a high-level first-1 gate clock signal (GCLK1-1) is input to the first gate clock signal (GCLK1) input node of the gate signal output circuit (GOC), and a low-level second-1 gate clock signal (GCLK2-1) is input to the second gate clock signal (GCLK2) input node.

[0206] During the second horizontal signal period of Fig. 11, the voltage level of the multiplexer control signal (MCS) is low, and the multiplexer (MUX) outputs the first-2 gate clock signal (GCLK1-2) and the second-2 gate clock signal (GCLK2-2).

[0207] Accordingly, a low-level first-second gate clock signal (GCLK1-2) is input to the input node of the first gate clock signal (GCLK) of the gate signal output circuit (GOC), and a high-level second-second gate clock signal (GCLK2-2) is input to the input node of the second gate clock signal (GCLK2).

[0208] During the third horizontal signal period of Fig. 11, the voltage level of the multiplexer control signal (MCS) is low, and the multiplexer (MUX) outputs the first-2 gate clock signal (GCLK1-2) and the second-2 gate clock signal (GCLK2-2).

[0209] Accordingly, a high-level first-second gate clock signal (GCLK1-2) is input to the input node of the first gate clock signal (GCLK) of the gate signal output circuit (GOC), and a low-level second-second gate clock signal (GCLK2-2) is input to the input node of the second gate clock signal (GCLK2).

[0210] During the fourth horizontal signal period of Fig. 11, the voltage level of the multiplexer control signal (MCS) is high, and the multiplexer (MUX) outputs the first-1 gate clock signal (GCLK1-1) and the second-1 gate clock signal (GCLK2-1).

[0211] Accordingly, a low-level first-1 gate clock signal (GCLK1-1) is input to the first gate clock signal (GCLK1) input node of the gate signal output circuit (GOC), and a high-level second-1 gate clock signal (GCLK2-1) is input to the second gate clock signal (GCLK2) input node.

[0212] To summarize the above, by using four gate clock signals (GCLK1-1, GCLK1-2, GCLK2-1, GCLK2-2) with a period of 4 horizontal periods, two gate clock signals (GCLK1, GCLK2) with a period of 2 horizontal periods can be generated.

[0213] The gate signal output circuit (GOC) can operate as described in FIG. 6 above, and below, the operation of the gate signal output circuit (GOC) is briefly explained with reference to FIG. 10 and FIG. 11.

[0214] During the first horizontal period and the second horizontal period, the start signal (GVST) has a high level voltage, and the gate signal output circuit (GOC) outputs a gate high voltage (VGH) at the output node (N). A gate signal (Vgate) of a turn-off level voltage is output at the output node (N).

[0215] During the third horizontal period, the start signal (GVST) has a low level voltage, and the gate signal output circuit (GOC) outputs a gate high voltage (VGH) at the output node (N). At the same time, the voltage output at the output node (N) can also be said to be the voltage of the signal input to the first gate clock signal (GCLK1) input node. A gate signal (Vgate) of a turn-off level voltage is output at the output node (N).

[0216] During the fourth horizontal period, the start signal (GVST) has a high level voltage. The gate signal output circuit (GOC) outputs the signal input to the first gate clock signal (GCLK1) input node at the output node (N). Here, the signal output from the output node (N) is the gate signal (Vgate) of the turn-on level voltage.

[0217] During the fifth and sixth horizontal periods, the start signal (GVST) has a high level voltage, and the gate signal output circuit (GOC) outputs a gate high voltage (VGH) to the output node (N). A gate signal (Vgate) of a turn-off level voltage is output to the output node (N).

[0218] Accordingly, the gate signal output circuit (GOC) can output the gate signal (Vgate) to the subpixel (SP).

[0219] Referring to FIGS. 9 to 11, a gate driving circuit (230a, 230b) according to embodiments of the present specification may have a multiplexer (MUX) arranged for each stage (ST1, ST2, ST3, ST4, etc.). A signal line (SL) transmits a first-1 gate clock signal (GCLK1-1), a first-2 gate clock signal (GCLK1-2), a second-1 gate clock signal (GCLK2-1), a second-2 gate clock signal (GCLK2-2), a start signal (GVST), and a multiplexer control signal (MCS) to the gate driving circuit (230a, 230b).

[0220] The frequency of the first-1 to second-2 gate clock signals (GCLK1-1 to GCLK2-2) transmitted to the gate driving circuit (230a, 230b) through the signal line (SL) may be only half the frequency of the signal input to the first gate clock signal (GCLK1) input node and the second gate clock signal (GCLK2) input node of the gate signal output circuit (GOC).

[0221] Accordingly, in the touch display device (100) according to the embodiments of the present invention, even if the frequencies of the first gate clock signal (GCLK1) and the second gate clock signal (GCLK2) are included in a high-interference frequency band that is the same as or similar to the frequency of the touch driving signal (TDS), the problem of reduced touch sensing accuracy of the touch electrode adjacent to the non-display area (NA) or the problem of visible screen flickering in the display area (AA) can be resolved.

[0222] Figure 12 is an example of the II' cross-sectional structure of Figure 7.

[0223] Referring to FIG. 12, in the non-display area (NA) of the touch display device (100) according to the embodiments of the present specification, a plurality of signal lines (SL) and a plurality of touch routing lines (TL0~TL6) may be located.

[0224] A plurality of signal lines (SL) may be placed on a substrate (SUB), and a gate insulating film (GI) is located on the plurality of signal lines (SL). The plurality of signal lines (SL) shown in FIG. 12 may be configured to transmit gate clock signals (GCLK's) and multiplexer control signals (MCS) to gate driving circuits (230a, 230b).

[0225] For example, referring to FIG. 12, a plurality of signal lines (SL) may include wiring that transmits four gate clock signals for generating a scan signal (SCAN), wiring that transmits two gate clock signals for generating a light emission signal (EM), and wiring that transmits a multiplexer control signal (MCS) for controlling a multiplexer (MUX).

[0226] Although not illustrated, the touch display device (100) according to the embodiments of the present specification may further include wiring for transmitting four gate clock signals for generating a light emission signal (EM), a gate signal output circuit (GOC) configured to generate a light emission signal (EM), a multiplexer (MUX) disposed in front of the gate signal output circuit (GOC), and wiring for transmitting a multiplexer control signal (MCS) for controlling the multiplexer (MUX).

[0227] A number of signal lines (SL) can be positioned opposite the first metal (M1) with the gate insulating film (GI) in between.

[0228] The first metal (M1) may be a shielding electrode to prevent interference from occurring between the signal line (SL) and the touch routing wiring (TL). The first metal (M1) may be in a floating state where no positive voltage is applied, but a positive voltage (e.g., ELVSS) may be applied to the first metal (M1).

[0229] The first metal (M1) of the non-display area (NA) can be electrically connected to a second electrode (E2) extending from the display area (AA). The second electrode (E2) can be electrically connected to the first metal (M1) through a contact hole in which a portion of the flattening layer (PLN) on the first metal (M1) is removed.

[0230] The second electrode (E2) may be an electrode configured to apply a common voltage (ELVSS) to light-emitting elements (ED) included in a plurality of subpixels (SP) in a display area (AA).

[0231] The second electrode (E2) may extend from the inner portion (I) of the non-display area (NA) toward the outer portion (I'). The second electrode (E2) may function as a shielding electrode to prevent interference between a plurality of signal lines (SL) and touch routing wiring (TL).

[0232] An encapsulation portion (ENCAP) is located on the second electrode (E2). The encapsulation portion (ENCAP) may be arranged as a single layer, but may also be arranged as multiple layers (PAS1, PCL, PAS2). For example, if the encapsulation portion (ENCAP) consists of multiple layers (PAS1, PCL, PAS2), the encapsulation portion (ENCAP) may include one or more inorganic encapsulation layers (PAS1, PAS2) and one or more organic encapsulation layers (PCL). For example, the encapsulation portion (ENCAP) may be arranged in a structure in which a first inorganic encapsulation layer (PAS1), an organic encapsulation layer (PCL), and a second inorganic encapsulation layer (PAS) are stacked in sequence.

[0233] A touch buffer film (T-BUF) can be placed on the encapsulation portion (ENCAP).

[0234] A touch buffer film (T-BUF) may be positioned between the touch routing wires (TL0 to TL6) and the second electrode (E2). The touch buffer film (T-BUF) may be designed so that the distance between the touch routing wires (TL0 to TL6) and the second electrode (E2) is maintained at a predetermined minimum distance (e.g., 1 μm). Accordingly, parasitic capacitance formed between the touch routing wires (TL0 to TL6) and the second electrode (E2) can be reduced or prevented, thereby reducing or preventing parasitic capacitance applied to the touch routing wires (TL0 to TL6) and improving touch sensing accuracy.

[0235] Touch routing lines (TL0~TL6) may be placed on the encapsulation portion (ENCAP) without a touch buffer film (T-BUF) in the non-display area (NA). In this case, the thickness of the second inorganic encapsulation layer (PAS2) may be increased so that the touch routing lines (TL0~TL6) are placed on the encapsulation portion (ENCAP) without placing the touch buffer film (T-BUF).

[0236] Touch routing lines (TL0 to TL6) located in the non-display area (NA) are each electrically connected to touch electrode lines (TEL) placed on the touch panel. For example, the outermost touch routing line (TL0) can be electrically connected to a touch electrode line (TEL) located at the outermost edge of the touch panel.

[0237] Referring to Fig. 12, a guard electrode and a ground electrode (GND) may be further located on the outer edge of the outermost touch routing wiring (TL0).

[0238] A preset voltage can be applied to the guard electrode and the ground electrode (GND). Accordingly, the guard electrode and the ground electrode (GND) can minimize the impact of the touch routing wiring (TL0~TL6) on electromagnetic waves entering from the outside.

[0239] The guard electrode and the ground electrode (GND) may be located in the same layer as the touch routing wires (TL0 to TL6). For example, the touch routing wires (TL0 to TL6), the guard electrode, and the ground electrode (GND) may be located on the touch buffer film (T-BUF). The guard electrode and the ground electrode (GND) may be formed of the same material as the touch routing wires (TL0 to TL6).

[0240] Referring to FIG. 12, a first metal (M1) and a second electrode (E2) may be positioned as shielding electrodes between the touch routing wires (TL0~TL6) and the plurality of signal lines (SL). That is, the first metal (M1) and the second electrode (E2) can physically prevent interference from occurring between the plurality of touch routing wires (TL0~TL6) and the plurality of signal lines (SL).

[0241] However, due to process errors, interference may occur between the outermost touch routing wiring (TL0) and multiple signal lines (SL) despite the presence of the first metal (M1) and the second electrode (E2).

[0242] In particular, if the frequency of a signal transmitted through multiple signal lines (SL) falls within a high-interference frequency band that is the same or similar to the frequency of a signal transmitted through touch routing wiring (TL), problems may arise such as reduced touch sensing accuracy or degraded display quality.

[0243] A touch display device according to the embodiments of the present specification can reduce the frequency of a signal transmitted to a signal line (SL) to half of the existing frequency by providing a gate driving circuit including a multiplexer.

[0244] Accordingly, the frequency band of the signal transmitted through the signal line (SL) may be included in a non-interference frequency band or a low-interference frequency band.

[0245] At the same time, the touch display device according to the embodiments of the present specification can maintain the same frequency as the existing gate signal (Vgate) input to the gate line (GL). Accordingly, high-speed driving is possible to drive the touch display device at a refresh rate of 120 Hz or higher.

[0246] Accordingly, the touch display device (100) according to the embodiments of the present specification has the advantage of improved touch sensing accuracy and display quality compared to conventional devices, and high-speed driving is possible.

[0247] The embodiments of the present specification described above are briefly explained as follows.

[0248] A touch display device (100) according to embodiments of the present specification may provide a touch display device (100) comprising: two or more signal lines (SL) that transmit clock signals (GCLK's; GCLK1-1, GCLK1-2, GCLK2-1, GCLK2-2) having the same frequency and different phases; input nodes (N1, N2) into which clock signals (GCLK's) transmitted through the two or more signal lines (SL) are input; and an output node (N3) that outputs one of the clock signals (GCLK's) input to the input nodes (N1, N2).

[0249] A touch display device (100) according to the embodiments of the present specification may provide a touch display device (100) including a gate driving circuit (230a, 230b) including the multiplexer (MUX).

[0250] A touch display device (100) according to embodiments of the present specification may provide a touch display device (100) in which the multiplexer (MUX) includes at least one sub-multiplexer (Sub MUX), and the two or more signal lines (SL) are electrically connected to the input nodes (N1, N2).

[0251] A touch display device (100) according to the embodiments of the present specification may provide a touch display device (100) that further includes a gate signal output circuit (GOC) into which a clock signal (GCLK1, GCLK2) output from the multiplexer (MUX) is input.

[0252] A touch display device (100) according to embodiments of the present specification may provide a touch display device (100) comprising at least one touch routing wire (TL) located in a non-display area (NA) and at least one touch electrode (TE) electrically connected to said at least one touch routing wire (TL).

[0253] A touch display device (100) according to embodiments of the present specification may provide a touch display device (100) in which a signal line (SL) is further disposed in the non-display area (NA) to receive a multiplexer control signal (MCS) for controlling the operation timing of the multiplexer (MUX), and the touch routing wiring (TL) is located on a different layer from the two or more signal lines (SL) that transmit the clock signals (GCLK's).

[0254] A touch display device (100) according to the embodiments of the present specification may provide a touch display device (100) in which the gate driving circuit (230a, 230b) is arranged in a gate-in-panel (GIP) manner.

[0255] A touch display device (100) according to embodiments of the present specification may be provided, comprising a display panel (210) including a display area (AA) in which one or more subpixels (SP) are arranged and a non-display area (NA) around the display area (AA), wherein the non-display area (NA) has two or more signal lines (SL) for transmitting clock signals (GCLK's) and a signal line (SL) for transmitting a multiplexer control signal (MCS) for controlling the operation timing of the multiplexer (MUX).

[0256] A touch display device (100) according to the embodiments of the present specification may provide a touch display device (100) in which the frequency of the multiplexer control signal (MCS) is the same as the frequency of the clock signals (GCLK's).

[0257] A touch display device (100) according to embodiments of the present specification may provide a touch display device (100) in which the two or more signal lines (SL) transmitting the clock signals (GCLK's) are located on the same layer as the signal line (SL) transmitting the multiplexer control signal (MCS).

[0258] A touch display device (100) according to embodiments of the present specification may provide a touch display device (100) in which each of the clock signals (GCLK's) is a signal in which the period of high level voltage during one cycle is longer than the period of low level voltage, or a signal in which the period of low level voltage during one cycle is longer than the period of high level voltage.

[0259] A touch display device (100) according to the embodiments of the present specification may provide a touch display device (100) in which the multiplexer (MUX) includes two or more sub-multiplexers (Sub MUX1, Sub MUX2), and the same multiplexer control signal (MCS) is input to the two or more sub-multiplexers (Sub MUX1, Sub MUX2).

[0260] A gate driving circuit (230a, 230b) according to embodiments of the present specification may provide a gate driving circuit (230a, 230b) comprising: a multiplexer (MUX) comprising two or more input nodes (N1, N2) and one or more output nodes (N3); and a gate signal output circuit (GOC) that receives a signal output from the output node (N3) of the multiplexer (MUX) and generates a gate signal (Vgate) input to a subpixel (SP).

[0261] A gate driving circuit (230a, 230b) according to the embodiments of the present specification may provide a gate driving circuit (230a, 230b) in which the frequency of a signal (GCLK's) input to each of the input nodes (N1, N2) of the multiplexer (MUX) is half the frequency of a signal output from the output node of the multiplexer (GCLK1, GCLK2).

[0262] The gate driving circuit (230a, 230b) according to the embodiments of the present specification can provide a gate driving circuit (230a, 230b) in which the multiplexer (MUX) receives a signal (GCLK's) in which the lengths of the period during which the voltage level is high and the period during which the voltage level is low are different at each of the two or more input nodes (N1, N2).

[0263] The foregoing description is merely an illustrative explanation of the technical concept of the present disclosure, and those skilled in the art to which the present disclosure pertains may make various modifications and variations within the scope of the essential characteristics of the present disclosure. Furthermore, the embodiments disclosed in the present disclosure are intended to explain, not limit, the technical concept of the present disclosure, and thus the scope of the technical concept of the present disclosure is not limited by these embodiments. The scope of protection of the present disclosure shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present disclosure. Explanation of the symbols

[0265] 100: Touch display device 210: Display panel 220: Data driving circuit 230a, 230b: Gate driving circuits 240: Display controller 310: Touch panel

Claims

Claim 1 A touch display device comprising: a substrate including a display area and a non-display area; a thin-film transistor disposed on the substrate; a planarization layer disposed on the thin-film transistor; a light-emitting part disposed on the planarization layer and including an anode, a light-emitting layer and a cathode; an encapsulation layer disposed on the light-emitting part and including a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer; an organic touch insulating layer disposed on the encapsulation layer; a touch electrode line disposed on the organic touch insulating layer within the display area; a touch protective film disposed on the touch electrode line; a dam area disposed in the non-display area; and a touch routing wiring connected to the touch electrode line and intersecting the dam area, wherein at least one of the first inorganic encapsulation layer and the second inorganic encapsulation layer is disposed up to the dam area, and the organic touch insulating layer is disposed up to the dam area. Claim 2 A touch display device according to claim 1, wherein the dam area is formed of the same material as the bank. Claim 3 A touch display device according to claim 1, wherein the touch electrode line comprises a first touch electrode line and a second touch electrode line. Claim 4 A touch display device according to paragraph 3, wherein the first touch electrode line and the second touch electrode line have a mesh structure. Claim 5 A touch display device according to claim 4, wherein the opening of the mesh structure is located on the light-emitting area of ​​the light-emitting part. Claim 6 A touch display device according to claim 1, wherein the dam area includes a primary dam adjacent to the display area and a secondary dam adjacent to the touch pad area. Claim 7 In claim 6, the organic bag layer is a touch display device located on the inner surface of the primary dam. Claim 8 A touch display device according to claim 1, wherein the organic touch insulating layer is a touch buffer film or a touch insulating film. Claim 9 A touch display device according to paragraph 3, wherein the first touch electrode line includes a first touch electrode connecting wire that electrically connects first touch electrodes adjacent to each other, and the second touch electrode line includes a second touch electrode connecting wire that electrically connects second touch electrodes adjacent to each other. Claim 10 A touch display device according to claim 9, wherein the second touch electrodes and the second touch electrode connecting wiring are located on different layers with the organic touch insulating layer in between. Claim 11 A touch display device according to claim 9, wherein the first touch electrode connecting wiring and the second touch electrode connecting wiring are arranged to overlap with a bank. Claim 12 A touch display device according to claim 1, wherein the touch routing wiring extends to the non-display area and passes through the upper and side of the encapsulation layer and the upper and side of the dam area and is electrically connected to a touch pad. Claim 13 A touch display device according to claim 1, wherein the touch protective film extends to the front or back of the dam area and is also disposed on the touch routing wiring. Claim 14 A touch display device according to claim 12, wherein the touch routing wiring and the touch pad are composed of the same first conductive material. Claim 15 A touch display device according to claim 1, wherein in the non-display area, a guard electrode and a ground electrode (GND) are further located on the outer edge of the outermost touch routing wiring. Claim 16 A touch display device according to claim 1, wherein a plurality of signal lines are located in the non-display area, and the touch routing wiring is located on a different layer from the plurality of signal lines. Claim 17 A touch display device according to claim 16, wherein a first metal is positioned as a shielding electrode between the touch routing wiring and the plurality of signal lines in the above non-display area. Claim 18 A touch display device according to claim 17, wherein the cathode extends from the inner portion of the non-display area toward the outer portion and is electrically connected to the first metal. Claim 19 A touch display device according to claim 16, further comprising two or more signal lines transmitting gate clock signals having the same frequency and different phases, and a gate driving circuit to which the gate clock signals are input. Claim 20 A touch display device according to claim 19, wherein the gate driving circuit is implemented in a gate-in-panel (GIP) manner and placed on the non-display area.

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