A substrate structure comprising stacked substrates disposed within a shell

Abstract

In one embodiment, the substrate structure comprises: a plurality of substrates encapsulated in a shell in a stacking relationship; at least one electronic component on each of the plurality of substrates, wherein the at least one electronic component comprises at least a first terminal and a second terminal; a first redistribution layer (RDL) disposed on each of the plurality of substrates and configured to electrically couple the first terminal of the at least one electronic component to an individual first terminal disposed on the outer edge of the shell; and a second RDL disposed on each of the plurality of substrates and configured to electrically couple the second terminal of the at least one electronic component to an individual second terminal disposed on the outer edge of the shell.

Description

Technology Field

[0001] The present disclosure generally relates to substrates, and more specifically to a laminated substrate structure having edge terminals and methods for manufacturing the substrate structure. Background Technology

[0002] Integrated circuit (IC) technology has made significant progress in enhancing computing capabilities through the miniaturization of electrical components. An IC can be implemented as an IC chip upon which a set of circuits is integrated. In some implementations, one or more IC chips can be physically carried and protected by an IC package, where various power and signal nodes of the IC chips can be electrically coupled to individual conductive terminals of the IC package via electrical paths formed within the package substrate. Various packaging technologies can be found in many electronic devices, including processors, servers, and radio frequency (RF) integrated circuits. Advanced packaging and processing techniques can be used to implement complex devices, such as multi-electronic component devices and system-on-a-chip (SOC) devices, which may include multiple functional blocks, each of which is designed to perform a specific function, such as, for example, microprocessor functions, graphics processing unit (GPU) functions, and communication functions (e.g., WiFi, Bluetooth, and other communications).

[0003] In some implementations, embedded electronic components such as deep trench capacitors have been integrated into IC packaging to improve performance and reduce package size. One factor driving the use of these embedded electronic components is the demand for small form factor products that have electrical performance equivalent to or better than their larger electronic component counterparts.

[0004] The following presents a simplified summary relating to one or more embodiments disclosed herein. Accordingly, the following summary should not be construed as a comprehensive overview relating to all embodiments considered, nor should it be construed as identifying key or decisive elements relating to all embodiments considered, or describing categories associated with any particular embodiment. Accordingly, the following summary is intended solely to present specific concepts relating to one or more embodiments relating to the mechanisms disclosed herein, in a simplified form preceding the detailed description provided below.

[0005] In one embodiment, the substrate structure comprises: a plurality of substrates encapsulated in a shell in a stacking relationship; at least one electronic component on each of the plurality of substrates, wherein the at least one electronic component comprises at least a first terminal and a second terminal; a first redistribution layer (RDL) disposed on each of the plurality of substrates and configured to electrically couple the first terminal of the at least one electronic component to an individual first terminal disposed on the outer edge of the shell; and a second RDL disposed on each of the plurality of substrates and configured to electrically couple the second terminal of the at least one electronic component to an individual second terminal disposed on the outer edge of the shell.

[0006] In one embodiment, the electronic device comprises a substrate structure, wherein the substrate structure comprises a plurality of substrates encapsulated in a shell in a stacking relationship; at least one electronic component on each of the plurality of substrates, wherein the at least one electronic component comprises at least a first terminal and a second terminal; a first redistribution layer (RDL) disposed on each of the plurality of substrates and configured to electrically couple the first terminal of the at least one electronic component to an individual first terminal disposed on the outer edge of the shell; and a second RDL disposed on each of the plurality of substrates and configured to electrically couple the second terminal of the at least one electronic component to an individual second terminal disposed on the outer edge of the shell.

[0007] In one embodiment, a method for manufacturing a substrate structure comprises: a step of orienting a plurality of substrates for simultaneous processing, wherein each of the plurality of substrates comprises at least one electronic component, and the at least one electronic component comprises at least a first terminal and a second terminal; a step of forming a first redistribution layer (RDL) on each of the plurality of substrates, wherein the first RDL is electrically coupled to the first terminal of at least one electronic component of each of the plurality of substrates; a step of forming a second RDL on each of the plurality of substrates, wherein the second RDL is electrically coupled to the second terminal of at least one electronic component; and a step of encapsulating a plurality of substrates in a stacked relationship in a shell. The method comprises the step of forming a metallized structure on the outer edge of the shell, wherein the metallized structure is configured to electrically couple a first RDL of each substrate to an individual first terminal on the outer edge of the shell and to couple a second RDL of each substrate to an individual second terminal on the outer edge of the shell.

[0008] Other objects and advantages associated with the embodiments disclosed in this specification will be apparent to those skilled in the art based on the accompanying drawings and detailed description. Brief explanation of the drawing

[0009] A more complete understanding of the embodiments of the present disclosure and the many advantages associated therewith will be readily obtained by referring to the following detailed description, which is better understood when considered in relation to the accompanying drawings, which are presented merely for illustrative purposes and not as a limitation of the present disclosure. FIG. 1 illustrates a substrate having a plurality of deep trench capacitors (DTCs) formed thereon according to embodiments of the present disclosure. FIG. 2 illustrates a substrate having a metallized structure formed on a plurality of DTCs formed on the substrate according to embodiments of the present disclosure. FIGS. 3a and 3b illustrate examples of substrate structures according to embodiments of the present disclosure. FIGS. 4a through 4m illustrate exemplary operations that can be used to manufacture a substrate structure according to embodiments of the present disclosure. FIG. 5 is a flowchart illustrating an exemplary method for manufacturing a substrate structure according to embodiments of the present disclosure. FIG. 6 illustrates a profile view of a package including a surface-mount asymmetric substrate, an integrated device, and an integrated passive device according to embodiments of the present disclosure. FIG. 7 illustrates an exemplary method for providing or manufacturing a package comprising an integrated device including an electronic component mounted in a core, according to embodiments of the present disclosure. FIG. 8 illustrates various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, interposer packages, PoP (package-on-package), SiP (System in Package), or System on Chip (SoC). Specific details for implementing the invention

[0010] Aspects of the present disclosure are illustrated in the following description and related drawings relating to specific embodiments. Alternative aspects or embodiments may be devised without departing from the scope of the teachings of this specification. Additionally, well-known elements of the exemplary embodiments of this specification may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings of this disclosure.

[0011] In certain described exemplary implementations, parts of various component structures and operations are taken from known conventional techniques and subsequently arranged according to one or more exemplary embodiments. In such instances, internal details of the known conventional component structures and / or parts of operations may be omitted to help avoid potential obfuscation of the concept exemplified in the exemplary embodiments disclosed herein.

[0012] The terms used herein are intended to describe only specific embodiments and are not intended to be limiting. As used herein, singular forms are intended to include plural forms as well, unless the context clearly indicates otherwise. It will be further understood that as used herein, the terms “comprising,” “comprising,” “comprising,” and / or “comprising” specify the presence of the mentioned characteristics, integers, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other characteristics, integers, steps, actions, elements, components, and / or groups thereof.

[0013] Based on the teachings of the present disclosure, it will be recognized that the term “over” indicates a sequential or hierarchical arrangement of layers in which one layer is functionally ‘over’ another layer but does not necessarily need to be in physical contact.

[0014] Specific embodiments of the present disclosure relate to substrate structures having stacked substrates having edge connections. In one embodiment, the substrates may include active devices (e.g., transistors) and / or passive components (e.g., resistors, capacitors, inductors, etc.). In the context of the present disclosure, each of the stacked substrates includes deep trench capacitors (DTCs) interconnected with one another. However, based on the teachings of the present disclosure, it will be recognized that each of the substrates may support other devices and components. Also, based on the teachings of the present disclosure, it will be recognized that a given substrate of the stacked substrates may support devices and / or components different from other substrates of the stacked substrates.

[0015] FIG. 1 illustrates a substrate (100) having a plurality of DTCs (102) formed thereon according to embodiments of the present disclosure. In one embodiment, the substrate (100) may have a conventional thickness (T1) of 760 micrometers. Additionally, the DTCs (102) may have a conventional trench depth (T2) of 8 micrometers. Thus, a significant portion of the thickness (T1) of the substrate (100) remains unused, which may complicate the ability of the structure to meet the increased demands for reduced device sizes.

[0016] FIG. 2 illustrates a substrate structure (200) having a metallized structure (202) formed on a plurality of DTCs (204) formed on a substrate (206) according to embodiments of the present disclosure. In one embodiment, the metallized structure (202) electrically couples the terminals (208) of the DTCs (204) (e.g., parts of each DTC forming nodes of a capacitor) to individual terminals (210) on the upper surface of the substrate structure (200). In this example, there are two terminals (210) associated with each DTC (204), and each terminal (210) is electrically coupled to an individual terminal (208) of the corresponding DTC (204).

[0017] Certain embodiments of the present disclosure are implemented with the recognition that conventional substrate structures, such as those shown in FIGS. 1 and 2, may not be suitable for the increased miniaturization challenges associated with future electronic device designs. FIGS. 3a and 3b illustrate examples of a substrate structure (300) according to embodiments of the present disclosure. FIG. 3a is a side cross-sectional view of an exemplary substrate structure (300) seen along the cross-sectional line (3A) shown in FIG. 3b is a top view of an exemplary substrate structure (300), where line (3A) illustrates how a cross-section is formed through the substrate structure (300) as shown in FIG. 3a. In one embodiment, the substrate structure (300) may be utilized to achieve high-density component configurations suitable for existing and future miniaturization challenges.

[0018] According to various embodiments of the present disclosure, a substrate structure (300) comprises a plurality of substrates (302) in a stacked relationship, encapsulated in a protective shell (304). In one embodiment, the protective shell (304) may be made of a molding compound. In an example such as that shown in FIG. 3a, there are a plurality of molding compound structures (306 and 308) forming the protective shell (304). The plurality of molding compound structures (306 and 308) may be formed from the same molding compound or different molding compounds depending on the process used to manufacture the substrate structure (300) and / or the device requirements to be met by the substrate structure (300).

[0019] According to additional embodiments of the present disclosure, a plurality of electronic components (310) are formed on each substrate (302) of a plurality of stacked substrates. In one embodiment, each electronic component (310) of the plurality of components formed on each substrate (302) includes at least a first terminal (312) and a second terminal (314). In an example as illustrated in FIG. 3a, each of the electronic components (310) is formed as a 2-terminal DTC. However, based on the teachings of the present disclosure, it will be recognized that 1) electronic components (310) other than DTCs may be formed on each substrate (302), 2) a given substrate (302) may include more than one type of electronic component (310), 3) a given substrate (302) may include electronic components (310) different from the electronic components formed on different substrates (302), or 4) any combination thereof may be possible. Additionally, based on the teachings of the present disclosure, it will be recognized that electronic components (310) may have more than two terminals.

[0020] In an exemplary substrate structure (300) as illustrated in FIG. 3a, a first redistribution layer (RDL) (316) is disposed on each substrate (302) to electrically couple first terminals (312) of a plurality of electronic components (310) of the substrate (302) to first terminals (318) disposed on the outer edge (320) of the protective shell (304). The exemplary substrate structure (300) further includes a second RDL (322) disposed on each substrate (302) to electrically couple second terminals (314) of a plurality of electronic components (310) to individual second terminals (324) disposed on the outer edge (320) of the protective shell (304). In one embodiment, individual first terminals (318) and individual second terminals (324) disposed on the outer edge (320) of the protective shell (304) may be configured to electrically couple the substrate structure with an interconnect structure (e.g., an interconnect layer, a printed circuit board, etc.).

[0021] In one embodiment, an exemplary substrate structure (300) comprises a plurality of dielectric layers (326, 328, 330, and 332) disposed on each substrate (302). Here, the patterned dielectric layer (326) electrically insulates the first terminal (312) from the second terminal (314) of the plurality of electronic components (310). The patterned dielectric layer (328) electrically insulates the portions (340) of the first RDL (316) coupled to the first terminal (312) of the electronic components (310) from the portions (342) of the second RDL (322) coupled to the second terminal (314) of the electronic components (310). The patterned dielectric layer (330) electrically insulates the first RDL (316) from the second RDL (322). The dielectric layer (332) separates the second RDL (322) from the adjacent substrate (302). In one embodiment, the patterned dielectric layer (330) and the dielectric layer (332) may be formed from a polyimide (PI) material.

[0022] In one embodiment, a plurality of substrates (302) are stacked along the length of a substrate structure (300). A first RDL (316) of each substrate (302) of the plurality of substrates extends along the height of the substrate structure (300). A second RDL (322) of each substrate (302) of the plurality of substrates extends along the height of the substrate structure (300). An outer edge (320) of the substrate structure (300) extends along the length of the substrate structure (300).

[0023] FIG. 3b is a plan view of an exemplary substrate structure (300) illustrating the relationship between the first RDL (316) and the second RDL (322) of each laminated substrate (302). As shown in FIG. 3b, the first RDL (316) and the second RDL (322) are laterally offset from each other, some of which are not immediately apparent when viewing FIG. 3a alone.

[0024] FIGS. 4a through 4l illustrate exemplary operations that may be used to manufacture a substrate structure according to embodiments of the present disclosure. FIG. 4a illustrates an example of an initial substrate configuration (400) that may be accommodated to manufacture a substrate structure. In this example, the initial substrate configuration (400) comprises a plurality of DTCs (402) formed on a substrate (404). The initial substrate configuration (400) comprises an initial metallization structure (406) disposed on the upper surface of the substrate (404). The initial metallization structure (406) electrically couples each first terminal (408) of the DTCs (402) to an individual pad (410). Likewise, the initial metallization structure (406) electrically couples each second terminal (412) of the DTCs (402) to an individual pad (414). In one embodiment, the substrate may be subjected to wafer thinning and / or sawing operations to reduce its thickness.

[0025] In FIG. 4b, a plurality of initial substrate configurations (400) are placed on a carrier (416) and encapsulated in a molding compound (418), which will be used to form part of a protective shell of the final substrate structure. In one embodiment, the molding compound may be initially placed over the entire perimeter of the initial substrate configurations (400) and subjected to grinding and / or chemical mechanical polishing operations to expose the pads (410 and 414).

[0026] In FIG. 4c, a first RDL (420) and a second RDL (422) are formed on the upper surface of each initial substrate configuration (400). The first RDL (420) electrically couples the pads (410) (and accordingly the first terminals of the DTCs) of the individual initial substrate configuration (400) to each other. Similarly, the second RDL (422) electrically couples the pads (414) (and accordingly the second terminals of the DTCs) of the individual substrate configuration (400) to each other. In this example, the first RDL (420) and the second RDL (422) are separated from each other by a dielectric layer (424) (e.g., a polyimide layer). Additionally, an additional dielectric layer (426) is disposed on the second RDL (422).

[0027] In FIG. 4d, an additional set of initial substrate configurations (428) is placed on the dielectric layers (426) associated with each initial substrate configuration (400).

[0028] In FIG. 4e, the initial substrate configurations (428) are encapsulated in an additional layer of molding compound (430), which will be used together with a layer of molding compound (418) to form part of the protective shell of the final substrate structure.

[0029] A third RDL (436) and a fourth RDL (438) are formed on the upper surface of each initial substrate configuration (428). The third RDL (436) electrically couples the pads (440) (and accordingly the first terminals of the DTCs) of the individual initial substrate configuration (428) to each other. Similarly, the fourth RDL (438) electrically couples the pads (442) (and accordingly the second terminals of the DTCs) of the individual substrate configuration (428) to each other. In this example, the third RDL (436) and the fourth RDL (438) are separated from each other by a dielectric layer (444) (e.g., a polyimide layer). Additionally, an additional dielectric layer (446) is placed on the fourth RDL (438).

[0030] In FIG. 4f, an additional set of initial substrate configurations (450) is placed on dielectric layers (426) associated with each initial substrate configuration (428). Here, the initial substrate configurations (450) are encapsulated in an additional layer of molding compound (452), which will be used together with layers of molding compound (418 and 430) to form part of a protective shell of the final substrate structure.

[0031] A fifth RDL (454) and a sixth RDL (456) are formed on the upper surface of each initial substrate configuration (450). The fifth RDL (454) electrically couples the pads (458) (and accordingly the first terminals of the DTCs) of the individual initial substrate configuration (450) to each other. Similarly, the sixth RDL (456) electrically couples the pads (460) (and accordingly the second terminals of the DTCs) of the individual initial substrate configuration (450) to each other. In this example, the fifth RDL (454) and the sixth RDL (456) are separated from each other by a dielectric layer (462) (e.g., a polyimide layer). Additionally, an additional dielectric layer (464) is placed on the sixth RDL (456).

[0032] In FIG. 4g, an additional layer of molding compound (468) is placed over the fifth RDL (454), the sixth RDL (456), the dielectric layer (462), and the dielectric layer (464), which will be used together with the layers of molding compounds (418, 430, and 452) to form part of the protective shell of the final substrate structure.

[0033] In FIG. 4h, the structure (466) illustrated in FIG. 4g is debonded from the carrier (416) and separated (e.g., through a sawing process) to form a plurality of substructures (470) (only two of these substructures (470) are illustrated in FIG. 4h).

[0034] In FIG. 4i, a plurality of substructures (470) are reoriented to an additional processing position and bonded to another carrier (472). A layer of molding compound (474) is formed around all of the plurality of substructures (470). In one embodiment, the material used to form the layer of molding compound (474) may be the same or different from the material used to form the layers of molding compounds (418, 430, 452, and 468) (see FIG. 4g).

[0035] In FIG. 4j, the upper portion of the layer of the molding compound (474) is removed (e.g., through a grinding and / or chemical mechanical polishing process) to expose the conductive end portions of the RDL structures (476) of the plurality of substructures (470).

[0036] In FIG. 4k, a metallized structure (478) is formed on the outer edge (480). In one embodiment, the metallized structure (478) electrically couples each of the RDLs of the RDL structures (476) to individual pads (482 and 484).

[0037] In FIG. 4L, terminals (486 and 488) are formed on a metallized structure (478) electrically coupled to individual pads (482 and 484).

[0038] In FIG. 4m, layers of the molding compound (e.g., layers (418, 430, 452 and 468) and 474, collectively labeled as layers (487)) are debonded from the carrier (472), and the resulting compound structure (490) (see FIG. 4l) is subsequently subjected to a separation process (e.g., a sawing operation) to form separate substrate structures (492), such as the substrate structure (300) shown in FIG. 3a.

[0039] FIG. 5 is a flowchart illustrating an exemplary method (500) for manufacturing a substrate structure according to embodiments of the present disclosure. In operation (502), a plurality of substrates are oriented for simultaneous processing, wherein each of the plurality of substrates comprises at least one electronic component and at least one electronic component comprises at least a first terminal and a second terminal. In operation (504), a first redistribution layer (RDL) is formed on each of the plurality of substrates, wherein the first RDL is electrically coupled to the first terminal of at least one electronic component of each of the plurality of substrates. In operation (506), a second RDL is formed on each of the plurality of substrates, wherein the second RDL is electrically coupled to the second terminal of at least one electronic component. In operation (508), the plurality of substrates are encapsulated in a stacked relationship in a shell. In operation (510), a metallized structure is formed on the outer edge of the shell, wherein the metallized structure is configured to electrically couple a first RDL of each substrate to an individual first terminal on the outer edge of the shell and to couple a second RDL of each substrate to an individual second terminal on the outer edge of the shell.

[0040] The technical advantage of the exemplary method (500) is that it can be used to form a substrate structure that interconnects electronic components, thereby reducing the size of the substrate structure while increasing the density of the electronic components.

[0041] FIG. 6 illustrates a profile view of a package (600) comprising a surface-mount asymmetric substrate (602), an integrated device (603), and an integrated passive device (605) according to embodiments of the present disclosure. The package (600) may be coupled to a printed circuit board (PCB) (606) through a plurality of solder interconnects (610). The PCB (606) may include at least one board dielectric layer (660) and a plurality of board interconnects (662).

[0042] The surface mount substrate (602) comprises at least one dielectric layer (620) (e.g., a substrate dielectric layer), a plurality of interconnects (622) (e.g., substrate interconnects), a solder resist layer (640), and a solder resist layer (642). An integrated device (603) may be coupled to the surface mount asymmetric substrate (602) through a plurality of solder interconnects (630). An integrated device (603) may be coupled to the surface mount asymmetric substrate (602) through a plurality of pillar interconnects (632) and a plurality of solder interconnects (630). An integrated passive device (605) may be coupled to the surface mount asymmetric substrate (602) through a plurality of solder interconnects (650). The integrated passive device (605) can be coupled to a surface-mount asymmetric substrate (602) through a plurality of pillar interconnects (652) and a plurality of solder interconnects (650).

[0043] The package (e.g., 600) may be implemented as a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 600) may be configured to provide Wireless Fidelity (WiFi) communication and / or cellular communication (e.g., 2G, 3G, 4G, 5G). The package (e.g., 600) may be configured to support Global System for Mobile (GSM) communications, Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The package (e.g., 600) may be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0044] FIG. 7 illustrates an exemplary method (700) for providing or manufacturing a package comprising an integrated device including an electronic component mounted in a core, according to aspects of the present disclosure. In some embodiments, the method (700) of FIG. 7 may be used to provide or manufacture the package (600) of FIG. 6 described in the present disclosure. However, the method (700) may be used to provide or manufacture any of the packages described in the present disclosure.

[0045] It should be noted that the method of FIG. 7 may combine one or more processes to simplify and / or clarify a method for providing or manufacturing a package comprising an integrated device including an electronic component mounted in a core, according to aspects of the present disclosure. In some implementations, the order of the processes may be changed or modified.

[0046] The method provides a substrate (e.g., 602) (in 705). The surface mount asymmetric substrate (602) may be provided or manufactured by a supplier. The surface mount asymmetric substrate (602) comprises at least one dielectric layer (620) and a plurality of interconnects (622). The surface mount asymmetric substrate (602) may comprise an embedded trace substrate (ETS). In some embodiments, the at least one dielectric layer (620) may comprise prepreg layers.

[0047] The method (in 710) couples at least one integrated device (e.g., 603) to a first surface of a substrate (e.g., 602). For example, the integrated device (603) may be coupled to a surface-mount asymmetric substrate (602) via a plurality of pillar interconnects (632) and a plurality of solder interconnects (630). The plurality of pillar interconnects (632) may be optional. The plurality of solder interconnects (630) are coupled to a plurality of interconnects (622). A solder reflow process may be used to couple the integrated device (603) to the plurality of interconnects via the plurality of solder interconnects (630).

[0048] The method also (in 710) couples at least one integrated passive device (e.g., 605) to a first surface of a substrate (e.g., 602). For example, the integrated passive device (605) may be coupled to a surface-mount asymmetric substrate (602) via a plurality of pillar interconnects (652) and a plurality of solder interconnects (650). The plurality of pillar interconnects (652) may be optional. The plurality of solder interconnects (650) are coupled to a plurality of interconnects (622). A solder reflow process may be used to couple the integrated passive device (605) to the plurality of interconnects via the plurality of solder interconnects (650).

[0049] The method (in 715) couples a plurality of solder interconnects (e.g., 610) to a second surface of a substrate (e.g., 602). A solder reflow process may be used to couple the plurality of solder interconnects (610) to the substrate.

[0050] FIG. 8 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, interposer packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device (802), a laptop computer device (804), a fixed-position terminal device (806), a wearable device (808), or a vehicle (810) may include a device (800) as described herein. The device (800) may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices (802, 804, 806, 808) and the vehicle (810) illustrated in FIG. 8 are merely exemplary. Other electronic devices may also feature a device (800) comprising, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld PCS (personal communication systems) units, portable data units such as personal digital assistants, GPS (global positioning system) capable devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automobiles (e.g., autonomous vehicles), or any other device for storing or retrieving data or computer commands, or any combination thereof.

[0051] Examples of implementation are described in the following numbered modalities:

[0052] Aspect 1. A substrate structure comprising: a plurality of substrates encapsulated in a shell in a stacked relationship; at least one electronic component in each of the plurality of substrates, wherein the at least one electronic component comprises at least a first terminal and a second terminal; a first redistribution layer (RDL) disposed on each of the plurality of substrates and configured to electrically couple the first terminal of the at least one electronic component to an individual first terminal disposed on the outer edge of the shell; and a second RDL disposed on each of the plurality of substrates and configured to electrically couple the second terminal of the at least one electronic component to an individual second terminal disposed on the outer edge of the shell.

[0053] Embodiment 2. In the substrate structure of Embodiment 1, at least one electronic component in each of the plurality of substrates includes a plurality of passive components.

[0054] Embodiment 3. In any one of embodiments 1 to 2, in a substrate structure, at least one electronic component in each of the plurality of substrates includes a plurality of deep trench capacitors.

[0055] Aspect 4. In any one of embodiments 1 to 3, a separate first terminal disposed on the outer edge of the shell and a separate second terminal disposed on the outer edge of the shell are configured to electrically couple the substrate structure to an interconnect structure.

[0056] Aspect 5. A substrate structure of any one of embodiments 1 to 4 further comprises a metallized structure disposed on the outer edge of a shell, wherein the metallized structure is configured to electrically couple a first RDL disposed on each of the plurality of substrates to an individual first terminal disposed on the outer edge of the shell.

[0057] Embodiment 6. In the substrate structure of Embodiment 5, the metallized structure disposed on the outer edge of the shell is configured to electrically couple a second RDL disposed on each of the plurality of substrates with an individual second terminal disposed on the outer edge of the shell.

[0058] Embodiment 7. A substrate structure of any one of embodiments 1 to 6 further comprises: a first dielectric layer disposed on a first side of each of the plurality of substrates and between the first side of the substrate and the first RDL; and a second dielectric layer disposed on the first side of each of the plurality of substrates between the first RDL and the second RDL.

[0059] Embodiment 8. The substrate structure of Embodiment 7 further comprises a third dielectric layer disposed on the second RDL of each of the plurality of substrates.

[0060] Embodiment 9. In the substrate structure of Embodiment 8, a third dielectric layer associated with at least one of the plurality of substrates separates at least one substrate from an adjacent substrate encapsulated in a shell.

[0061] Embodiment 10. In any one of embodiments 1 to 9, a plurality of substrates are stacked along the length of the substrate structure; a first RDL of each of the plurality of substrates extends along the height of the substrate structure; a second RDL of each of the plurality of substrates extends along the height of the substrate structure; and an outer edge of the substrate structure extends along the length of the substrate structure.

[0062] Aspect 11. An electronic device comprising: a substrate structure, wherein the substrate structure comprises a plurality of substrates encapsulated in a shell in a stacked relationship; at least one electronic component in each of the plurality of substrates, wherein the at least one electronic component comprises at least a first terminal and a second terminal; a first redistribution layer (RDL) disposed on each of the plurality of substrates and configured to electrically couple the first terminal of the at least one electronic component to an individual first terminal disposed on the outer edge of the shell; and a second RDL disposed on each of the plurality of substrates and configured to electrically couple the second terminal of the at least one electronic component to an individual second terminal disposed on the outer edge of the shell.

[0063] Embodiment 12. In the electronic device of Embodiment 11, at least one electronic component on each of the plurality of substrates includes a plurality of passive components.

[0064] Embodiment 13. In any one of embodiments 11 to 12, in an electronic device, at least one electronic component on each of the plurality of substrates comprises a plurality of deep trench capacitors.

[0065] Aspect 14. In any one of the electronic devices of Aspects 11 to 13, an individual first terminal disposed on the outer edge of the shell and an individual second terminal disposed on the outer edge of the shell are configured to electrically couple a substrate structure with an interconnect structure.

[0066] Embodiment 15. An electronic device of any one of embodiments 11 to 14 further comprises a metallized structure disposed on the outer edge of a shell, wherein the metallized structure is configured to electrically couple a first RDL disposed on each of a plurality of substrates to an individual first terminal disposed on the outer edge of the shell.

[0067] Embodiment 16. In any one of embodiments 11 to 15, the metallized structure disposed on the outer edge of the shell is configured to electrically couple a second RDL disposed on each of the substrates to an individual second terminal disposed on the outer edge of the shell.

[0068] Embodiment 17. An electronic device of any one of embodiments 11 to 16 further comprises: a first dielectric layer disposed on a first side of each of the plurality of substrates and between the first side of the substrate and the first RDL; and a second dielectric layer disposed on the first side of each of the plurality of substrates between the first RDL and the second RDL.

[0069] Embodiment 18. An electronic device of any one of embodiments 11 to 17 further comprises a third dielectric layer disposed on a second RDL of each of the plurality of substrates.

[0070] Embodiment 19. In the electronic device of Embodiment 18, a third dielectric layer associated with at least one substrate of a plurality of substrates separates at least one substrate from an adjacent substrate encapsulated in a shell.

[0071] Embodiment 20. In any one of embodiments 11 to 19, an electronic device, wherein a plurality of substrates are stacked along the length of a substrate structure; a first RDL of each of the plurality of substrates extends along the height of the substrate structure; a second RDL of each of the plurality of substrates extends along the height of the substrate structure; and an outer edge of the substrate structure extends along the length of the substrate structure.

[0072] Aspect 21. In any one of the electronic devices of embodiments 11 to 20, an individual first terminal disposed on the outer edge of the shell and an individual second terminal disposed on the outer edge of the shell each include a terminal configured to electrically couple a substrate structure with an interconnect structure.

[0073] Aspect 22. In any one of the electronic devices of Aspects 11 to 21, the electronic device comprises at least one of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, or an in-vehicle device.

[0074] Aspect 23. A method for manufacturing a substrate structure, comprising: a step of orienting a plurality of substrates for simultaneous processing, wherein each of the plurality of substrates comprises at least one electronic component, and the at least one electronic component comprises at least a first terminal and a second terminal; a step of forming a first redistribution layer (RDL) on each of the plurality of substrates, wherein the first RDL is electrically coupled to the first terminal of at least one electronic component of each of the plurality of substrates; a step of forming a second RDL on each of the plurality of substrates, wherein the second RDL is electrically coupled to the second terminal of at least one electronic component; and a step of encapsulating a plurality of substrates in a stacked relationship in a shell. The method comprises the step of forming a metallized structure on the outer edge of the shell, wherein the metallized structure is configured to electrically couple a first RDL of each substrate to an individual first terminal on the outer edge of the shell and to couple a second RDL of each substrate to an individual second terminal on the outer edge of the shell.

[0075] Embodiment 24. In the method of Embodiment 23, at least one electronic component formed on each of the plurality of substrates includes a plurality of passive components.

[0076] Embodiment 25. In any one of embodiments 23 to 24, at least one electronic component formed on each of the plurality of substrates comprises a plurality of deep trench capacitors.

[0077] Aspect 26. In any one of aspects 23 to 25, the method comprises the step of forming an individual first terminal disposed on the outer edge of the shell and an individual second terminal disposed on the outer edge of the shell to electrically couple the substrate structure with the interconnect structure.

[0078] Aspect 27. In any one of Aspects 23 to 26, the method further comprises the steps of: stacking a plurality of substrates along the length of a substrate structure; forming a first RDL of each of the plurality of substrates along the height of the substrate structure; forming a second RDL of each of the plurality of substrates along the height of the substrate structure; and forming an outer edge of the substrate structure extending along the length of the substrate structure.

[0079] It should be noted that the drawings of this disclosure may depict actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be scaled. In some cases, for clarity, not all components and / or parts may be depicted. In some instances, the positions, locations, sizes, and / or shapes of various parts and / or components in the drawings may be exemplary. In some implementations, various components and / or parts in the drawings may be optional.

[0080] The word “exemplary” is used herein to mean “functioning as an example, example, or illustration.” Any embodiment or aspect described herein as “exemplary” is not necessarily to be interpreted as being advantageous or preferred over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed features, advantages, or modes of operation. The term “coupled” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically touches object B and object B touches object C, objects A and C may still be considered coupled to each other—even if they do not physically touch each other directly. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together so that current (e.g., signal, power, ground) can travel between the two objects. Two electrically coupled objects may or may not have an electric current flowing between the two objects. The use of the terms "first," "second," "third," and "fourth" (and / or any of the fourth or higher) is optional. Any of the described components may be the first component, the second component, the third component, or the fourth component. For example, a component referred to as the second component may be the first component, the second component, the third component, or the fourth component. The term "encapsulating" means that an object may partially or completely encapsulate another object. The terms "top" and "bottom" are optional. A component located on the top may be located on top of a component located on the bottom. A top component may be considered a bottom component, and vice versa.As described in the present disclosure, a first component positioned "on" a second component may mean that the first component is positioned above or below the second component, depending on how the bottom or top is arbitrarily defined. In other examples, the first component may be positioned on (e.g., above) a first surface of the second component, and a third component may be positioned on (e.g., below) a second surface of the second component, wherein the second surface is opposite to the first surface. Also, note that the term "on," as used in the context of one component being positioned on another component in this application, may be used to mean a component that is on and / or within the other component (e.g., on the surface of the component or encapsulated by the component). Accordingly, for example, a first component on a second component may mean (1) that the first component is on the second component but is not directly touching the second component, (2) that the first component is on the second component (e.g., on its surface), and / or (3) that the first component is inside the second component (e.g., encapsulated inside). A first component located "in" the second component may be partially located within the second component or completely located within the second component. As used in this disclosure, the term "about 'value X'" or "approximately value X" means within 10% of 'value X'. For example, a value of about 1 or approximately 1 will mean a value within the range of 0.9 to 1.1.

[0081] In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include an electrically conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include one or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metallization layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form interconnects. In some implementations, chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, sputtering processes, spray coating, and / or plating processes may be used to form interconnects.

[0082] Additionally, it should be noted that the various disclosures included in this specification may be described as processes depicted as flowcharts, flowcharts, structural diagrams, or block diagrams. While flowcharts may describe operations as sequential processes, most operations may be performed in parallel or simultaneously. Furthermore, the order of operations may be rearranged. A process terminates when its operations are completed.

[0083] In the detailed description above, it can be seen that different features are grouped together in examples. This disclosure should not be understood as intended to imply that the exemplary aspects have more features than are explicitly stated in each aspect. Rather, the various aspects of this disclosure may include fewer features than all the features of the individual exemplary aspects disclosed. Accordingly, the following aspects should be considered incorporated into the description, and each aspect itself may exist as a separate example. Each dependent aspect may refer to a specific combination of one of the other aspects, but the aspect(s) of the dependent aspect are not limited to that specific combination. It will also be recognized that other exemplary aspects may include a combination of the dependent aspect(s) and any other dependent or independent aspect claimed subject, or a combination of any feature and other dependent and independent aspects. The various embodiments disclosed herein explicitly include such combinations unless it is explicitly expressed or readily inferable that a particular combination is not intended (e.g., contradictory embodiments such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is also intended that embodiments of one embodiment may be included in any other independent embodiment, even if that embodiment does not directly depend on any other independent embodiment.

[0084] It should be noted that while the foregoing disclosures represent exemplary embodiments of the present disclosure, various changes and modifications may be made in this specification without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps, and / or actions of the method claims according to the embodiments of the present disclosure described herein do not need to be performed in any particular order. Additionally, while the elements of the present disclosure may be described or claimed in the singular, the plural is considered unless a limitation to the singular is explicitly stated.

Claims

Claim 1 A substrate structure comprising: a plurality of substrates encapsulated in a shell in a stacked relationship; at least one electronic component in each of the plurality of substrates, wherein the at least one electronic component comprises at least a first terminal and a second terminal; a first redistribution layer (RDL) disposed on each of the plurality of substrates and configured to electrically couple the first terminal of the at least one electronic component to an individual first terminal disposed on the outer edge of the shell; and a second RDL disposed on each of the plurality of substrates and configured to electrically couple the second terminal of the at least one electronic component to an individual second terminal disposed on the outer edge of the shell. Claim 2 In claim 1, the at least one electronic component in each of the plurality of substrates comprises: a substrate structure including a plurality of passive components. Claim 3 In claim 1, the at least one electronic component in each of the plurality of substrates comprises: a substrate structure including a plurality of deep trench capacitors. Claim 4 A substrate structure according to claim 1, wherein the individual first terminal disposed on the outer edge of the shell and the individual second terminal disposed on the outer edge of the shell are configured to electrically couple the substrate structure with an interconnect structure. Claim 5 A substrate structure according to claim 1, further comprising a metallized structure disposed on the outer edge of the shell, wherein the metallized structure is configured to electrically couple the first RDL disposed on each of the plurality of substrates with the individual first terminal disposed on the outer edge of the shell. Claim 6 A substrate structure according to claim 5, wherein the metallized structure disposed on the outer edge of the shell is configured to electrically couple the second RDL disposed on each of the plurality of substrates with the individual second terminal disposed on the outer edge of the shell. Claim 7 A substrate structure according to claim 1, further comprising: a first dielectric layer disposed on a first side of each of the plurality of substrates and between the first side of the substrate and the first RDL; and a second dielectric layer disposed on the first side of each of the plurality of substrates between the first RDL and the second RDL. Claim 8 A substrate structure according to claim 7, further comprising a third dielectric layer disposed on the second RDL of each of the plurality of substrates. Claim 9 In claim 8, the third dielectric layer associated with at least one of the plurality of substrates separates the at least one substrate from an adjacent substrate encapsulated in the shell, forming a substrate structure. Claim 10 A substrate structure according to claim 1, wherein the plurality of substrates are stacked along the length of the substrate structure, and the first RDL of each of the plurality of substrates extends along the height of the substrate structure; the second RDL of each of the plurality of substrates extends along the height of the substrate structure; and the outer edge of the substrate structure extends along the length of the substrate structure. Claim 11 As an electronic device, it includes a substrate structure, and the substrate structure is: Multiple substrates encapsulated in a shell in a stacked relationship; At least one electronic component on each of the plurality of substrates, wherein the at least one electronic component comprises at least a first terminal and a second terminal; A first redistribution layer (RDL) disposed on each of the plurality of substrates and configured to electrically couple the first terminal of the at least one electronic component with an individual first terminal disposed on the outer edge of the shell; and An electronic device comprising a second RDL disposed on each of the plurality of substrates and configured to electrically couple the second terminal of the at least one electronic component to an individual second terminal disposed on the outer edge of the shell. Claim 12 In claim 11, the at least one electronic component on each of the plurality of substrates comprises: a plurality of passive components, an electronic device. Claim 13 In claim 11, the at least one electronic component on each of the plurality of substrates comprises: a plurality of deep trench capacitors, an electronic device. Claim 14 An electronic device according to claim 11, wherein the individual first terminal disposed on the outer edge of the shell and the individual second terminal disposed on the outer edge of the shell are configured to electrically couple the substrate structure with the interconnect structure. Claim 15 An electronic device according to claim 11, further comprising a metallized structure disposed on the outer edge of the shell, wherein the metallized structure is configured to electrically couple the first RDL disposed on each of the plurality of substrates to the individual first terminal disposed on the outer edge of the shell. Claim 16 An electronic device according to claim 11, wherein the metallized structure disposed on the outer edge of the shell is configured to electrically couple the second RDL disposed on each of the plurality of substrates with the individual second terminal disposed on the outer edge of the shell. Claim 17 An electronic device according to claim 11, further comprising: a first dielectric layer disposed on a first side of each of the plurality of substrates and between the first side of the substrate and the first RDL; and a second dielectric layer disposed on the first side of each of the plurality of substrates between the first RDL and the second RDL. Claim 18 An electronic device according to claim 11, further comprising a third dielectric layer disposed on the second RDL of each of the plurality of substrates. Claim 19 An electronic device according to claim 18, wherein the third dielectric layer associated with at least one of the plurality of substrates separates the at least one substrate from an adjacent substrate encapsulated in the shell. Claim 20 An electronic device according to claim 11, wherein the plurality of substrates are stacked along the length of the substrate structure, and the first RDL of each of the plurality of substrates extends along the height of the substrate structure; the second RDL of each of the plurality of substrates extends along the height of the substrate structure; and the outer edge of the substrate structure extends along the length of the substrate structure. Claim 21 An electronic device according to claim 11, wherein the individual first terminal disposed on the outer edge of the shell and the individual second terminal disposed on the outer edge of the shell each comprise a terminal configured to electrically couple the substrate structure with an interconnect structure. Claim 22 In claim 11, the electronic device comprises at least one of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, or an in-vehicle device. Claim 23 A method for manufacturing a substrate structure, comprising: a step of orienting a plurality of substrates for simultaneous processing, wherein each of the plurality of substrates comprises at least one electronic component, and the at least one electronic component comprises at least a first terminal and a second terminal; a step of forming a first redistribution layer (RDL) on each of the plurality of substrates, wherein the first RDL is electrically coupled to the first terminal of the at least one electronic component of each of the plurality of substrates; a step of forming a second RDL on each of the plurality of substrates, wherein the second RDL is electrically coupled to the second terminal of the at least one electronic component; and a step of encapsulating the plurality of substrates in a stacked relationship in a shell. A method for manufacturing a substrate structure, comprising the step of forming a metallized structure on the outer edge of the shell, wherein the metallized structure is configured to electrically couple the first RDL of each substrate to an individual first terminal at the outer edge of the shell and to couple the second RDL of each substrate to an individual second terminal at the outer edge of the shell. Claim 24 In claim 23, the at least one electronic component formed on each of the plurality of substrates comprises: a plurality of passive components, a method for manufacturing a substrate structure. Claim 25 In claim 23, the at least one electronic component formed on each of the plurality of substrates comprises: a plurality of deep trench capacitors, a method for manufacturing a substrate structure. Claim 26 A method for manufacturing a substrate structure according to claim 23, comprising the step of forming the individual first terminal disposed on the outer edge of the shell and the individual second terminal disposed on the outer edge of the shell to electrically couple the substrate structure with an interconnect structure. Claim 27 A method for manufacturing a substrate structure according to claim 23, further comprising the steps of: stacking the plurality of substrates along the length of the substrate structure; forming the first RDL of each of the plurality of substrates along the height of the substrate structure; forming the second RDL of each of the plurality of substrates along the height of the substrate structure; and forming the outer edge of the substrate structure extending along the length of the substrate structure.

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