Devices and methods for improving multi-stream write amplification factors
Patent Information
- Application Number
- KR1020267023446
- Authority / Receiving Office
- KR · KR
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-12-22
- Filing Date
- 2024-11-20
- Publication Date
- 2026-08-14
Smart Images
Figure PCT00001_ABST
Abstract
Description
Technology Field
[0001] The present disclosure relates to devices and methods for performing fragmentation removal or garbage collection.
[0002] According to the present disclosure, devices and methods for performing defraction of a plurality of sets of source memory bands of a device are provided. The device includes memory, which may include memory blocks having pages or super pages of memory. The memory may be organized into sets of source memory bands, and each set of source memory bands includes at least one source memory band. Each source memory band is configured to store data (e.g., host data) associated with a host or write stream. The device and method disclosed herein may use a merit score function to determine a merit score for each individual source memory band based on at least one of (a) the amount of valid data within each source memory band and (b) the age of the data within each source memory band. The merit score function enables the processing circuit of the device to prioritize defraction of source memory bands having high merit scores. In some embodiments, the merit score of each source memory band increases as the amount of valid data within each source memory band decreases. In some embodiments, the merit score of each source memory band increases as the age of the data within each source memory band increases. Generally, the merit score of a source memory band increases as it becomes more advantageous for each source memory band to be selected by the processing circuit for garbage collection / fragmentation removal.
[0003] Typically, for a device such as a storage device (e.g., a solid-state drive device), the device's processing circuitry periodically consolidates regions of memory that partially store valid data. This garbage collection or defraction process ensures that the processing circuitry provides available memory resources for new, incoming data (e.g., new host data). In some embodiments, the processing circuitry performs defraction of valid data or garbage collection of invalid data as a background procedure when the processing circuitry executes instructions. Therefore, background activities of garbage collection and defraction processes consume processing resources, which affects the overall performance and durability of the device. The processing circuitry may use a merit score function to identify source memory bands to perform defraction or garbage collection on. However, in some examples, a problem of recency bias exists, where partially garbage-collected source memory bands with a newly reduced amount of valid data are prioritized for further garbage collection, but this may not be the best choice for optimally allocating the device's processing resources for defraction / garbage collection. The devices and methods disclosed herein reduce the impact on performance due to recency bias when using merit score functions by identifying a set of source memory bands among a plurality of sets of source memory bands for garbage collection based on the second highest merit score of the source memory bands for each set of source memory bands.
[0004] The device may include a processing circuit, and the processing circuit is configured to determine a respective merit score corresponding to each source memory band of each set of source memory bands based on at least one characteristic of at least one portion of data of each corresponding source memory band. The processing circuit is also configured to determine each source memory band corresponding to the second highest merit score for each set of source memory bands. Once each source memory band corresponding to the second highest merit score for each set of source memory bands is determined, the processing circuit identifies a set of source memory bands including a source memory band corresponding to the highest merit score among the second highest merit scores from a plurality of sets of source memory bands. Finally, the processing circuit stores at least one portion of valid data from at least one source memory band of the identified set of source memory bands in a defraction destination memory band. Such devices and methods provided herein improve the overall performance and durability of the processing circuit of the device (e.g., a solid-state drive (SSD) device).
[0005] In some embodiments, a device (e.g., a storage device) is provided with memory and processing circuitry that are coupled to communicate with each other. In some embodiments, the processing circuitry receives write requests containing data stored in each source memory band of a set of source memory bands. In some embodiments, parts of the data stored in the source memory bands may be invalidated, which is a characteristic of the data stored in the source memory bands that can be used by the processing circuitry to determine each merit score of the source memory bands. Brief explanation of the drawing
[0006] The following description includes a discussion of drawings having illustrations given as an example of implementations of the embodiments of the present disclosure. The drawings should be understood as an example, not as a limiting one. As used herein, references to one or more “exemplars” should be understood as describing specific features, structures, and / or characteristics included in at least one implementation. Accordingly, phrases such as “in one embodiment” or “in an alternative embodiment” appearing herein describe various embodiments and implementations and do not necessarily refer to the same embodiment. However, they are also not necessarily mutually exclusive. FIG. 1 illustrates an exemplary drawing of a system comprising a device having a host and a processing circuit and a memory, according to some embodiments of the present disclosure. FIG. 2 illustrates an exemplary drawing showing the fragmentation of sets of source memory bands into fragmentation removal destination memory bands according to some embodiments of the present disclosure. FIG. 3 illustrates a flowchart of exemplary steps for performing defractionation on a plurality of sets of source memory bands of a device according to some embodiments of the present disclosure. FIG. 4 illustrates a flowchart of exemplary steps of a subprocess for performing garbage collection of valid data of each set of source memory bands according to some embodiments of the present disclosure. FIG. 5 illustrates a flowchart of exemplary steps of a subprocess for updating the merit scores of source memory bands according to some embodiments of the present disclosure. Specific details for implementing the invention
[0007] According to the present disclosure, devices and methods are provided for performing defragmentation / garbage collection on a plurality of sets of source memory bands of a device (e.g., an SSD device) while reducing recency bias by using a merit score function when determining source memory bands to be garbage collected. The device (e.g., an SSD device) may include a plurality of memory dies (e.g., NAND memory dies) and is configured to perform garbage collection / defragmentation on a plurality of sets of source memory bands that store host data from a plurality of hosts. Typically, for a device such as a storage device (e.g., a solid-state drive device), the processing circuit of the device periodically consolidates regions of memory that partially store valid data. This garbage collection or defragmentation process ensures that the processing circuit provides available memory resources for new, incoming data (e.g., new host data). In some embodiments, the processing circuit performs defragmentation of valid data or garbage collection of invalid data as a background procedure when the processing circuit executes instructions. Therefore, background activities of garbage collection and defraud processes consume processing resources, which affects the overall performance and durability of the device. One metric for measuring this impact on performance and durability is the write amplification factor, defined as the ratio of the total number of writes to the number of host writes. A lower write amplification factor indicates fewer total writes compared to the number of host writes received and executed by the processing circuitry, and thus indicates a more efficient device.In some examples of systems having a device coupled to a host for communication, the host may include multiple virtual machines or applications that are unaware that other virtual machines or applications can access the device's memory.
[0008] The features of the disclosure described herein are in the context of a device having a processing circuit and memory (e.g., an SSD device). However, the principles of the disclosure may be applied to any other suitable context in which defraction of a plurality of sets of source memory bands of the device is performed. The device may include memory and a processing circuit, and the processing circuit and the memory are coupled to communicate with each other by a network bus or an interface. In some embodiments, the processing circuit determines merit scores—each merit score corresponds to a source memory band for each set of source memory bands—and determines each source memory band corresponding to the second-highest merit score for each set of source memory bands. The processing circuit then identifies a set of source memory bands including a source memory band corresponding to the highest merit score among the second-highest merit scores, and stores at least one portion of valid data from at least one source memory band of the identified set of source memory bands in a defraction destination memory band. In some embodiments, requests are transmitted from a host to the device via a network bus or an interface.
[0009] Specifically, the present disclosure provides devices and methods for performing fragmentation removal on a plurality of sets of source memory bands on a device to improve the overall performance and durability of the processing circuit portion of the device.
[0010] In some embodiments, the processor of the processing circuit may be a highly parallelized processor capable of rapidly processing high bandwidths of incoming data (e.g., by simultaneously starting the processing of write requests or instructions before the completion of previously received write requests or instructions).
[0011] In some embodiments, the memory of the device disclosed herein may include any of the following memory densities—single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), penta-level cells (PLCs), and any suitable memory density greater than 5 bits per memory cell.
[0012] In some embodiments, the devices and methods of the present disclosure may refer to a storage device system (e.g., an SSD storage system) comprising a storage device such as a solid-state drive device that is communicably coupled to a host (e.g., a host device) by a network bus or interface.
[0013] An SSD is a data storage device that uses integrated circuit assemblies as memory to permanently store data. SSDs do not have moving mechanical components, and this feature distinguishes them from traditional electromechanical magnetic disks, such as hard disk drives (HDDs) or floppy disks, which include spinning disks and movable read / write heads. Compared to electromechanical disks, SSDs are typically more resistant to physical shock, operate quietly, and have lower access times and lower latency.
[0014] Many types of SSDs utilize NAND-based flash memory, which includes non-volatile storage technology that retains data without power. The Quality of Service (QoS) of an SSD may relate to the consistency of high Input / Output Operations Per Second (IOPS) and the predictability of low latency while servicing read / write Input / Output (I / O) workloads. This means that latency or I / O command completion times need to remain within a specific range without exhibiting unexpected outliers. Additionally, throughput or I / O rates may need to be strictly controlled to avoid causing sudden degradation in performance levels.
[0015] The subject matter of the present disclosure can be better understood by referring to FIGS. 1 through 5.
[0016] FIG. 1 illustrates an exemplary diagram of a system (100) comprising a host (108) and a device (102) having a processing circuit (104), a communication circuit (105), and a memory (106), according to some embodiments of the present disclosure. In some embodiments, the device (102) may be a storage device such as a solid-state storage device (e.g., an SSD device). In some embodiments, the processing circuit (104) may include a processor or any suitable processing unit. In some embodiments, the memory (106) may be a non-volatile memory. It will be understood that the embodiments of the present disclosure are not limited to SSDs. For example, in some embodiments, the device (102) may include a hard disk drive (HDD) device in addition to or instead of an SSD. In some embodiments, the communication circuit (105) includes temporary memory (e.g., cache or other suitable volatile memory) for storing write requests (e.g., write request (110)) received through the port (107). The communication circuit (105) is configured to receive write requests (e.g., write request (110)) from the host (108) and to transmit data from the device (102) to the host (108). In some embodiments, each source memory band of each set of source memory bands stores data associated with the same host write stream from each host (e.g., host (108)).
[0017] In some embodiments, the processing circuit (104) is configured to receive write requests (e.g., write requests (110)) from a host (108), and each write request (110) contains host data. In some embodiments, the host data or write requests (e.g., write requests (110)) are stored in memory (106). In some embodiments, the write requests (110) are transmitted to the processing circuit (104) via the communication circuit (105) over a network bus or interface. In some embodiments, the write requests (110) are transmitted from an external source (e.g., a host (108) that is communically coupled to the device (102) via a port (107). The processing circuit (104) may receive write requests (e.g., write requests (110)) from both internal and external sources of the device (102). In some embodiments, the communication circuit (105) includes a volatile memory configured to temporarily store any unprocessed write requests (e.g., write requests (110)) to be processed by the processing circuit (104). In some embodiments, the device may receive any one of NVMe write requests, peripheral device high-speed interconnect (PCIe) write requests, and write requests of any other suitable interface protocol.
[0018] Additionally, the device (102) includes a memory (106). In some embodiments, the memory (106) includes any one or more of non-volatile memories such as phase change memory (PCM), PCM and switch (PCMS), ferroelectric random access memory (FeRAM), or ferroelectric transistor random access memory (FeTRAM), memristor, spin-transfer torque random access memory (STT-RAM), and magnetoresistive random access memory (MRAM), any other suitable memory, or any combination thereof. In some embodiments, the memory (106) is of a memory density, and such memory density is any one of (a) single-level cell (SLC) memory density, (b) multi-level cell (MLC) memory density, (c) triple-level cell (TLC) memory density, (d) quad-level cell (QLC) memory density, (e) penta-level cell (PLC) memory density, or (f) memory density greater than 5 bits per memory cell. In some embodiments, the processing circuit (104) is communicably coupled to the memory (106) to store and access data within memory blocks or pages. In some embodiments, a data bus interface is used to transmit write / read commands or data between the processing circuit (104) and the memory (106).
[0019] In some embodiments, the device (102) also includes a volatile memory, which may include any one or more volatile memories such as static random access memory (SRAM). In some embodiments, the volatile memory is configured to temporarily store data (e.g., a write request (110)) during the execution of operations by the processing circuit (104). In some embodiments, the processing circuit (104) and the communication circuit (105) are each communicably coupled to the volatile memory to store and access the write request (110) data of the volatile memory. In some embodiments, a data bus interface is used to transmit the write request (110) data from the volatile memory to the processing circuit (104). In some embodiments, the volatile memory is communicably coupled to the memory (106), and the volatile memory is configured to function as a cache or temporary memory storage for the memory (106). In some embodiments, the data bus interface between the memory (106) and the volatile memory provides a network bus for accessing data in the memory (106) or writing data from the memory (106).
[0020] In some embodiments, the processor or processing unit of the processing circuit (104) may include a hardware processor, a software processor (e.g., a processor emulated using a virtual machine), or any combination thereof. The processor, also referred to in the specification as the processing circuit (104), may include any suitable software, hardware, or both for controlling the memory (106) and the processing circuit (104). In some embodiments, the device (102) may further include a multi-core processor. The memory (106) may also include hardware elements for non-transient storage of instructions, instructions, or requests.
[0021] The processing circuit (104) is configured to perform defraction on multiple sets of source memory bands of the device (102) while reducing the recency bias using a merit score function when determining the source memory band to be garbage collected. The processing circuit (104) determines a merit score corresponding to each source memory band of each set of source memory bands based on at least one characteristic of at least one part of the data of each corresponding source memory band. The characteristics that may be used by the processing circuit (104) to determine the merit score of each individual source memory band are (a) the amount of valid data within each source memory band and (b) the age of the valid data within each source memory band. Once the processing circuit (104) determines a merit score corresponding to each source memory band of each set of source memory bands, the processing circuit (104) may then determine each source memory band corresponding to the second highest merit score of each set of source memory bands. In some embodiments, when each set of source memory bands includes one source memory band, the only source memory band may be considered to be the second highest merit score for each set of source memory bands. The processing circuit (104) then identifies a set of source memory bands that includes a source memory band corresponding to the highest merit score among the second highest merit scores from a plurality of sets of source memory bands. Finally, the processing circuit (104) stores at least one portion of valid data from at least one source memory band of the identified set of source memory bands in a defraction destination memory band. In some embodiments, the processing circuit (104) performs defraction / garbage collection of the source memory bands of the identified set of source memory bands in descending order of merit score.The processing circuit (104) first stores portions of valid data from the first source memory band corresponding to the highest merit score in the defraction destination memory band. In some embodiments, as long as the defraction destination memory band has memory available to store additional defraction data, or the set of identified source memory bands includes additional portions of defraction valid data, the processing circuit (104) continues to store portions of valid data from the source memory bands of the set of identified source memory bands in the defraction destination memory band. The processing circuit (104) performs optimal garbage collection or defraction on the source memory bands of the set of identified source memory bands based on the highest merit score among the second highest merit scores, thereby reducing the influence of recency bias in performing garbage collection or defraction by using a merit score function. In some embodiments, when the defractionation destination memory band is full, the processing circuit (104) closes the defractionation destination memory band for any additional defractionation valid data. In some embodiments, the processing circuit (104) then clears the completely defractionation source memory bands of the set of identified source memory bands so that each of the cleared source memory bands is reused to store new host data.
[0022] In some embodiments, the device (102) may be a storage device (e.g., an SSD device) that may include one or more packages or memory dies (e.g., memory (106)), and each die may include storage cells. In some embodiments, the storage cells of the memory (106) are composed of sets of source memory bands, each set comprising at least one source memory band. When a plurality of hosts are communicably coupled to the device (102), each set of source memory bands may include host data originating from the same respective host (e.g., host (108)). In some embodiments, each source memory band of each set of source memory bands includes data from the same respective application or virtual machine running on the host (e.g., host (108)) when the host is running on a plurality of applications or implemented virtual machines. Additionally, the memory (106) also includes blocks or pages of memory allocated as defraction destination memory bands, or bands of memory (106) configured to store defractionated portions of valid data of source memory bands. In some embodiments, storage cells are composed of pages or super pages, and pages and super pages are composed of blocks, and each page or super page is included in a source memory band within a set of source memory bands. In some embodiments, each storage cell may store one or more information bits.
[0023] For clarity and brevity, and not as a limitation, the present disclosure is provided in the context of performing defraction on a plurality of sets of source memory bands of a device while reducing recency bias by using a merit score function when determining source memory bands to be garbage collected. The processing circuit (104) performs garbage collection or defraction on the source memory bands of the identified set of source memory bands based on the highest merit score among the second highest merit scores, thereby reducing the influence of recency bias in performing garbage collection or defraction by using a merit score function. The processing circuit (104) then stores valid data from at least one source memory band of the identified set of source memory bands in a defraction destination memory band. The process of performing defraction on a plurality of sets of source memory bands of a device may be configured by any suitable software, hardware, or both for implementing such features and functions. As disclosed, performing defraction of multiple sets of source memory bands of a device may be implemented at least partially, for example, in the device (102) (for example, as part of the processing circuit (104) or any other suitable device). For example, for a solid-state storage device (for example, device (102)), performing defraction of multiple sets of source memory bands of the device may be implemented in the processing circuit (104).
[0024] FIG. 2 illustrates an exemplary time (200) representing the defraction of sets of source memory bands (e.g., a first set of source memory bands (202) and a second set of source memory bands (204)) to defraction definitive destination memory bands (e.g., a first defraction definitive destination memory band (218), a second defraction definitive destination memory band (220), and a third defraction definitive destination memory band (222)) according to some embodiments of the present disclosure. As illustrated in FIG. 2, the first set of source memory bands (202) comprises four source memory bands including a first source memory band (206), a second source memory band (208), a third source memory band (210), and a fourth source memory band (212), and the second set of source memory bands (204) comprises two source memory bands including a fifth source memory band (214) and a sixth source memory band (216). Each source memory band of each set of source memory bands (e.g., the first set of source memory bands (202) and the second set of source memory bands (204)) (e.g., the first source memory band (206), the second source memory band (208), the third source memory band (210), the fourth source memory band (212), the fifth source memory band (214), and the sixth source memory band (216)) includes at least one portion of valid data. In the memory of FIG. 2, the first source memory band (206) includes two portions of valid data (201), the second source memory band (208) includes three portions of valid data (203), the third source memory band (210) includes four portions of valid data (205), and the fourth source memory band (212) includes five portions of valid data (207).Additionally, within the set (204) of the second source memory bands, the fifth source memory band (214) contains four portions of valid data (209), and the sixth source memory band (216) contains four portions of valid data (211). In some embodiments, for each individual source memory band, any portion of each source memory band that does not store valid data may store invalid or old data, or may be empty. In some embodiments, the merit score of each individual source memory band is based on any one or more of (a) the amount of valid data within each source memory band and (b) the age of the valid data within each source memory band. For example, when a merit score function uses the amount of valid data within each source memory band to determine the corresponding merit score of each source memory band, the source memory bands illustrated in FIG. 2 (e.g., first source memory band (206), second source memory band (208), third source memory band (210), fourth source memory band (212), fifth source memory band (214), and sixth source memory band (216)) may be sorted by merit score to prioritize specific source memory bands for a fragmentation removal / garbage collection process. For the purposes of the illustrated time (200), the merit score function used by the processing circuit (104) to determine the corresponding merit score of each source memory band is based on the amount of valid data stored in each source memory band.
[0025] At time (t1), the source memory bands may be arranged in descending order of merit points: first source memory band (206), second source memory band (208), third source memory band (210), fifth source memory band (214), sixth source memory band (216), and fourth source memory band (212). In some embodiments, when two source memory bands have the same amount of valid data, the source memory band having older data has a higher merit point. The processing circuit (104) then determines each source memory band corresponding to the second highest merit point for each set of source memory bands (e.g., the first set of source memory bands (202) and the second set of source memory bands (204)). Based on the determined merit scores of each source memory band, the merit score of the second source memory band (208) is the second highest merit score for the set of first source memory bands (202), and the merit score of the sixth source memory band (216) is the second highest merit score for the set of second source memory bands (204). The processing circuit (104) then identifies a set of source memory bands including a source memory band corresponding to the highest merit score among the second highest merit scores. At time (t1), the second source memory band (208) corresponds to the highest merit score among the second highest merit scores, and therefore the processing circuit (104) performs defraction / garbage collection on the set of first source memory bands (202).When the processing circuit (104) identifies a set (202) of first source memory bands, the processing circuit (104) then performs fragmentation removal / garbage collection of the source memory bands (e.g., first source memory band (206), second source memory band (208), third source memory band (210), and fourth source memory band (212)) of the set (202) of first source memory bands in descending order of merit score.
[0026] To perform either a fragmentation removal process or a garbage collection process, the processing circuit (104) stores each portion of valid data (e.g., valid data (201, 203, 205, and 207)) of source memory bands (e.g., first source memory band (206), second source memory band (208), third source memory band (210), and fourth source memory band (212)) of a set of first source memory bands (202) in the first fragmentation removal destination memory band (218). Based on source memory bands sorted by merit score, the processing circuit (104) first stores two portions of valid data (201) from the first source memory band (206) in the first fragmentation removal destination memory band (218) by data transfer (224). Since the first fragmentation removal destination memory band (218) has available memory for storing additional fragmentation removal data, the processing circuit (104) stores three portions of valid data (203) from the second source memory band (208) in the first fragmentation removal destination memory band (218) by data transmission (226), and finally stores three of four portions of valid data (205) from the third source memory band (210) in the first fragmentation removal destination memory band (218) by data transmission (228). When the first fragmentation removal destination memory band (218) is full, the processing circuit (104) closes the first fragmentation removal destination memory band (218) for any additional fragmentation removal valid data. The processing circuit (104) can then clear the first source memory band (206) and the second source memory band (208) so that each of the cleared source memory bands can be reused to store new host data.
[0027] At time (t2), the source memory bands may be arranged in descending order of merit scores: the third source memory band (210), the fifth source memory band (214), the sixth source memory band (216), and the fourth source memory band (212). The processing circuit (104) then determines that the fourth source memory band (212) corresponds to the second highest merit score in the set (202) of the first source memory bands, and the sixth source memory band (216) corresponds to the second highest merit score in the set (204) of the second source memory bands. The processing circuit (104) then identifies a set of source memory bands including the source memory band corresponding to the highest merit score among the second highest merit scores. At time (t2), the sixth source memory band (216) corresponds to the highest merit score among the second highest merit scores, and therefore the processing circuit (104) performs defraction / garbage collection on the set (204) of the second source memory bands. When the processing circuit (104) identifies the set (204) of the second source memory bands, the processing circuit (104) then performs defraction / garbage collection on the source memory bands (e.g., the fifth source memory band (214), and the sixth source memory band (216)) of the set (204) of the second source memory bands in descending order of merit scores.
[0028] During the defraction / garbage collection process of the set of second source memory bands (204), the processing circuit (104) stores each portion of valid data (e.g., valid data (209 and 211)) of the source memory bands (e.g., the fifth source memory band (214) and the sixth source memory band (216)) of the set of second source memory bands (204) in the second defraction destination memory band (220). Based on the source memory bands sorted by merit score, the processing circuit (104) first stores four portions of valid data (209) from the fifth source memory band (214) in the second defraction destination memory band (220) by data transfer (230). Since the second defraction removal destination memory band (220) has available memory for storing additional defractionated data, the processing circuit (104) stores four portions of valid data (211) from the sixth source memory band (216) in the second defraction removal destination memory band (220) by data transfer (232). When the second defraction removal destination memory band (220) is full, the processing circuit (104) closes the second defraction removal destination memory band (220) for any additional defractionated valid data. In some embodiments, the processing circuit (104) is configured to clear the fifth source memory band (214) and the sixth source memory band (216) so that each of the cleared source memory bands is reused to store new host data. By using the highest merit score among the second-highest merit scores as a basis for identifying a set of source memory bands, the processing circuit (104) performs garbage collection more efficiently and optimally. This reduces the impact on performance and durability caused by the recency bias of garbage collection / fragmentation processes using merit score functions.
[0029] At time (t3), the source memory bands may be arranged in descending order of merit points: a third source memory band (210) and a fourth source memory band (212). In some embodiments, the processing circuit (104) identifies that the set of first source memory bands (202) is the only remaining set of source memory bands to be defractionated. In some embodiments, the processing circuit (104) determines that the fourth source memory band (212) corresponds to the second highest merit point in the set of first source memory bands (202), and then identifies that the set of first source memory bands (202) includes a source memory band (e.g., the fourth source memory band (212)) that corresponds to the highest merit point among the second highest merit points. Therefore, the processing circuit (104) performs defraction / garbage collection on the source memory bands (e.g., the third source memory band (210) and the fourth source memory band (212)) of the first set of source memory bands (202) in descending order of merit score. During the defraction / garbage collection process of the first set of source memory bands (202), the processing circuit (104) stores each portion of the valid data (e.g., valid data (205 and 207)) of the source memory bands (e.g., the third source memory band (210) and the fourth source memory band (212)) of the first set of source memory bands (202) in the third defraction destination memory band (222). Based on source memory bands aligned by merit points, the processing circuit (104) first stores one remaining portion of valid data (205) from the third source memory band (210) in the third fragmentation removal destination memory band (222) by data transfer (234).Since the third defraction removal destination memory band (222) has available memory for storing additional defractionated data, the processing circuit (104) subsequently stores five portions of valid data (207) from the fourth source memory band (212) in the third defraction removal destination memory band (222) by data transfer (236). When each portion of valid data (parts of valid data (205 and 211)) from the third source memory band (210) and the fourth source memory band (212) is stored in the third defraction removal destination memory band (222), the processing circuit (104) closes the third defraction removal destination memory band (222) for any additional defractionated valid data. In some embodiments, the processing circuit (104) is configured to clear the third source memory band (210) and the fourth source memory band (212) so that the cleared source memory bands are used to store new host data.
[0030] FIG. 3 illustrates a flowchart of exemplary steps of a process (300) for performing defraction of a plurality of sets of source memory bands of a device according to some embodiments of the present disclosure. In some embodiments, the referenced system, device, processing circuit, communication circuit, memory, port, host, and write request may be implemented as a system (100), device (102), processing circuit (104), communication circuit (105), memory (106), port (107), host (108), and write request (110), respectively. In some embodiments, the process (300) may be modified, for example, by rearranging, changing, adding, and / or removing steps.
[0031] In step (302), the processing circuit determines a merit score corresponding to each source memory band of each set of source memory bands based on at least one characteristic of at least one part of the data of each corresponding source memory band. The characteristics that can be used by the processing circuit to determine the merit score of each source memory band are (a) the amount of valid data within each source memory band and (b) the age of the valid data within each source memory band. When two source memory bands have the same amount of valid data, the source memory band having older data has a higher merit score. Once the processing circuit determines a merit score corresponding to each source memory band of each set of source memory bands, the processing circuit may, in step (304), then determine each source memory band corresponding to the second highest merit score for each set of source memory bands.
[0032] In step (304), the processing circuit determines each source memory band corresponding to the second highest merit score for each set of source memory bands. In some embodiments, when each set of source memory bands includes one source memory band, the only source memory band may be considered to be the second highest merit score for each set of source memory bands. When the processing circuit determines each source memory band corresponding to the second highest merit score for each set of source memory bands, the processing circuit then, in step (306), identifies a set of source memory bands including the source memory band corresponding to the highest merit score among the second highest merit scores.
[0033] In step (306), the processing circuit identifies a set of source memory bands that includes the source memory band corresponding to the highest merit score among the second-highest merit scores from a plurality of sets of source memory bands. In some embodiments where the processing circuit partially performs garbage collection for the source memory bands, this step helps to reduce the recency bias of merit function-based decisions to improve fairness in performing garbage collection of the source memory bands of the identified set of source memory bands. The processing circuit then, in step (308), performs defraction / garbage collection for the set of source memory bands that includes the source memory band corresponding to the highest merit score among the second-highest merit scores.
[0034] In step (308), the processing circuit stores at least one portion of valid data from at least one source memory band of the set of identified source memory bands in the defraction destination memory band. In some embodiments, the processing circuit performs defraction / garbage collection of the source memory bands of the identified source memory bands in descending order of merit score. The processing circuit first stores portions of valid data from the first source memory band corresponding to the highest merit score in the defraction destination memory band. In some embodiments, as long as the defraction destination memory band has memory available to store additional defraction data, or the set of identified source memory bands includes additional portions of defraction valid data, the processing circuit continues to store portions of valid data from the source memory bands of the set of identified source memory bands in the defraction destination memory band. The processing circuit performs optimal garbage collection or defraction on the source memory bands of the set of identified source memory bands based on the highest merit score among the second-highest merit scores, thereby reducing the influence of recency bias in performing garbage collection or defraction by using a merit score function. In some embodiments, when the defraction destination memory band is full, the processing circuit closes the defraction destination memory band for any additional defractionable valid data. In some embodiments, the processing circuit then clears the completely defractionated source memory bands of the set of identified source memory bands so that each of the cleared source memory bands is used to store new host data.
[0035] FIG. 4 illustrates a flowchart of exemplary steps of a subprocess (400) for performing garbage collection of valid data of each set of source memory bands according to some embodiments of the present disclosure. In some embodiments, the referenced system, device, processing circuit, communication circuit, memory, port, host, and write request may be implemented as system (100), device (102), processing circuit (104), communication circuit (105), memory (106), port (107), host (108), and write request (110), respectively. In some embodiments, the subprocess (400) may be modified, for example, by rearranging, changing, adding, and / or removing steps.
[0036] In step (402), the processing circuit determines that the defraction of the set of identified source memory bands is complete. In some embodiments, the defraction of the set of identified source memory bands is completed when the defraction destination memory band is full and any additional valid data can no longer be stored from the set of identified source memory bands. The processing circuit may determine that the defraction destination memory band is full based on an interrupt signal from memory indicating a full defraction destination memory band. In other embodiments, the defraction of the set of identified source memory bands is completed when defraction is performed on each of the source memory bands of the identified source memory bands. Since the valid data of the set of identified source memory bands is stored in the defraction destination memory band, the processing circuit may mark each portion of the valid data already stored in the defraction destination memory band. This mark may be implemented as an invalid bit or flag indicating that the portion of the data may be cleared or overwritten by new data (e.g., host data).
[0037] In step (404), the processing circuit continues to the next step based on the determination of whether the defraction of the set of identified source memory bands in step (402) is complete. If the processing circuit determines that the defraction of the set of identified source memory bands is not complete, the processing circuit continues to perform the defraction of the set of identified source memory bands in step (402) and continues to determine whether the defraction of the set of identified source memory bands is complete. If the processing circuit determines that the defraction of the set of identified source memory bands is complete, the processing circuit closes the defraction destination memory band in step (406).
[0038] In step (406), the processing circuit closes the defractionation destination memory band. When defractionation of the set of identified source memory bands is completed, the corresponding defractionation destination memory band is closed and any additional valid data from the set of identified source memory bands can no longer be stored. When the defractionation destination memory band is closed, the processing circuit, in step (408), subsequently clears at least one source memory band of the set of identified source memory bands.
[0039] In step (408), the processing circuit clears each of at least one source memory band of the identified source memory bands. In some embodiments, the data cleared by the processing circuit is invalid or old data. When the processing circuit clears each of the source memory bands of the set of identified source memory bands, the source memory bands of the set of identified source memory bands can be reused to store additional host data or write stream data. In some embodiments, not all source memory bands of the set of identified source memory bands are cleared by the processing circuit, but each source memory band on which defraction is performed is cleared by the processing circuit. Therefore, when the set of source memory bands is partially defractionated into at least one source memory band having data not yet stored in the corresponding defraction destination memory band, the processing circuit clears all defractionated source memory bands except for at least one source memory band. When the defractionated source memory bands of the identified set of source memory bands are cleared, the processing circuit identifies the set of source memory bands for which the processing circuit performs defraction / garbage collection based on the second-highest merit scores of each source memory band for each set of source memory bands. Additionally, the processing circuit allocates another defraction destination memory band to store portions of valid data from the next identified set of source memory bands.
[0040] FIG. 5 illustrates a flowchart of exemplary steps of a subprocess (500) for updating the merit scores of source memory bands according to some embodiments of the present disclosure. In some embodiments, the referenced system, device, processing circuit, communication circuit, memory, port, host, and write request may be implemented as a system (100), device (102), processing circuit (104), communication circuit (105), memory (106), port (107), host (108), and write request (110), respectively. In some embodiments, the subprocess (500) may be modified, for example, by rearranging, changing, adding, and / or removing steps.
[0041] In step (502), the processing circuit updates the respective merit score corresponding to each source memory band of the set of identified source memory bands, and updates the respective merit score based on at least one characteristic of at least one part of the data of each corresponding source memory band. In some embodiments, when each source memory band of the set of identified source memory bands is partially defractionated by the processing circuit, the merit score of each source memory is updated to reflect a change in at least one characteristic of each part of the data within each partially defractionated source memory band. When updating the merit score corresponding to the source memory band, the processing circuit uses the same merit score function as when determining the merit scores of each source memory band for each set of source memory bands. In some embodiments, the updated merit score for each source memory band is based on at least one of (a) the amount of valid data within each source memory band and (b) the age of the valid data within each source memory band.
[0042] The terms “an embodiment,” “embodiment,” “embodiments,” “the embodiment,” “the embodiments,” “one or more embodiments,” “some embodiments,” and “one embodiment” mean “one or more (but not all) embodiments” unless otherwise clearly specified.
[0043] Unless otherwise explicitly stated, the listing of enumerated items does not imply that any or all of these items are mutually exclusive.
[0044] The terms "including," "comprising," "having," and variations thereof mean "including, but not limited to," unless otherwise clearly specified.
[0045] The terms "a," "an," and "the" mean "one or more" unless otherwise explicitly specified.
[0046] Devices communicating with each other do not need to communicate continuously unless otherwise clearly specified. Additionally, devices communicating with each other may communicate directly or indirectly through one or more intermediate devices.
[0047] The description of an embodiment having various components communicating with one another does not imply that all such components are necessary. On the contrary, various optional components are described to illustrate various possible embodiments. Additionally, while process steps, method steps, algorithms, etc., may be described in a sequential order, these processes, methods, and algorithms may be configured to operate in alternative orders. That is, the sequence or order of steps that may be described does not imply a requirement that the steps must be performed in that order. The steps of the processes described herein may be performed in any practical order. Furthermore, some steps may be performed simultaneously.
[0048] When a single device or article is described in this specification, it will be readily apparent that more than one device / article may be used in the single device / article (whether or not they cooperate). Similarly, when more than one device or article (whether or not they cooperate) is described in this specification, it will be readily apparent that the single device / article may be used instead of more than one device or article, or that a different number of devices / articles may be used instead of the number of devices or programs described. The functions and / or features of the device may be alternatively implemented by one or more other devices not explicitly described as having such functions / features. Accordingly, other embodiments do not need to include the device itself.
[0049] At least certain operations that may be exemplified in the drawings illustrate specific events occurring in a specific order. In alternative embodiments, certain operations may be performed in a different order, modified, or removed. Additionally, steps may be added to the logic described above and may still follow the described embodiments. Furthermore, the operations described herein may occur sequentially, or certain operations may be processed in parallel. Additionally, the operations may be performed by a single processing unit or distributed processing units.
[0050] The foregoing description in various embodiments is provided for illustrative and illustrative purposes only. It is not intended to be comprehensive or limited to the exact forms disclosed. Various modifications and variations are possible in light of the above teachings.
Claims
Claim 1 A method for performing defraction of a plurality of sets of source memory bands of a device, wherein each set of source memory bands includes at least one source memory band storing data of each data type, and each of the at least one source memory band includes at least one portion of valid data, and the method comprises: a step of determining, by a processing circuit of the device, a respective merit score corresponding to each source memory band of each set of source memory bands based on at least one characteristic of at least one portion of data of each corresponding source memory band; a step of determining, by the processing circuit, for each set of source memory bands, each source memory band corresponding to the second highest merit score; a step of identifying, by the processing circuit, a set of source memory bands including a source memory band corresponding to the highest merit score among the second highest merit scores of the plurality of sets of source memory bands; and a step of storing at least one portion of valid data from the at least one source memory band of the identified set of source memory bands in a defraction destination memory band by the processing circuit. Claim 2 In claim 1, the method comprises: determining that the defraction of the set of identified source memory bands is complete; and in response to the determination that the defraction of the set of identified source memory bands is complete: The step of closing the above-mentioned fragmentation removal destination memory band; and A method further comprising the step of clearing each of the at least one source memory band of the set of the identified source memory bands. Claim 3 A method according to paragraph 2, wherein the step of determining that the defraction of the set of identified source memory bands is completed includes the step of determining that the defraction destination memory band is filled with stored valid data. Claim 4 A method according to paragraph 2, wherein the step of determining that the defraction of the set of identified source memory bands is completed comprises the step of determining that each part of the valid data of at least one source memory band of the set of identified source memory bands is stored in the defraction destination memory band. Claim 5 The method of claim 1 further comprises: a step of updating each merit score corresponding to each source memory band of the set of identified source memory bands, wherein the step of updating each merit score is based on at least one characteristic of at least one part of the data of each corresponding source memory band. Claim 6 The method of claim 1 further comprises: the step of initializing the fragmentation removal destination memory band, wherein the fragmentation removal destination memory band is configured to store data of each data type corresponding to the set of the identified source memory bands. Claim 7 A method according to claim 1, wherein at least one characteristic of at least one part of the data of each corresponding source memory band comprises at least one of (a) a value representing the amount of valid data within the corresponding source memory band and (b) a value representing the age of the data within the corresponding source memory band. Claim 8 As a device, it includes a memory; and a processing circuit portion that is communicably coupled to the memory, wherein the memory is: A plurality of sets of source memory bands - each set of source memory bands includes at least one source memory band for storing data of each data type, and each of the at least one source memory band includes at least one portion of valid data -; and The processing circuit includes a fragmentation removal destination memory band, and: Based on at least one characteristic of at least one part of the data of each corresponding source memory band, each merit score corresponding to each source memory band of each set of source memory bands is determined; For each set of source memory bands, determine each source memory band corresponding to the second highest merit score; Identifying a set of source memory bands including a source memory band corresponding to the highest merit score among the second highest merit scores from a plurality of sets of the above source memory bands; A device that stores at least one portion of valid data from at least one source memory band of the set of identified source memory bands in the fragmentation removal destination memory band. Claim 9 In paragraph 8, the processing circuit further: determines that the defraction of the set of identified source memory bands is completed; and in response to the determination that the defraction of the set of identified source memory bands is completed: Close the above fragmentation removal destination memory band; A device for clearing each of the at least one source memory band of the set of the identified source memory bands. Claim 10 In claim 9, the device, wherein the processing circuit determines that the fragmentation removal destination memory band is filled with stored valid data in order to determine that the fragmentation removal of the set of identified source memory bands is completed. Claim 11 A device according to claim 9, wherein, in order to determine that the defraction of the set of identified source memory bands is completed, the processing circuit determines that each part of the valid data of at least one source memory band of the set of identified source memory bands is stored in the defraction destination memory band. Claim 12 In paragraph 8, the processing circuit further comprises: updating each merit score corresponding to each source memory band of the set of identified source memory bands—updating each merit score is based on at least one characteristic of at least one part of the data of each corresponding source memory band—; device. Claim 13 In paragraph 8, the processing circuit further comprises: initializing the fragmentation removal destination memory band - the fragmentation removal destination memory band is configured to store data of each of the data types corresponding to the set of the identified source memory bands -; device. Claim 14 A device according to claim 8, wherein the at least one characteristic of each portion of the data of each corresponding source memory band comprises at least one of (a) a value representing the amount of valid data within the corresponding source memory band and (b) a value representing the age of the data within the corresponding source memory band. Claim 15 In claim 8, the device, wherein the data stored in at least one source memory band of each set of source memory bands corresponds to the data from each of the hosts of the plurality of hosts. Claim 16 In claim 8, the device, wherein the data stored in at least one source memory band of each set of source memory bands corresponds to data from each tenant of a plurality of tenants of the host. Claim 17 In claim 8, the device, wherein the data stored in at least one source memory band of each set of source memory bands corresponds to data from each application of a plurality of applications performed on a host. Claim 18 A non-transient computer-readable medium encoded with instructions that, when executed by a processing circuit, cause a method for defractionating a plurality of sets of source memory bands to be performed, wherein each set of source memory bands includes at least one source memory band storing data of each data type, and each of the at least one source memory band includes at least one portion of valid data, and the method comprises: determining each merit score corresponding to each source memory band of each set of source memory bands based on at least one characteristic of each portion of data of each corresponding source memory band; determining each source memory band corresponding to the second highest merit score for each set of source memory bands; identifying a set of source memory bands including a source memory band corresponding to the highest merit score among the second highest merit scores from the plurality of sets of source memory bands; and storing at least one portion of valid data from the at least one source memory band of the identified set of source memory bands in a defractionating destination memory band. Claim 19 In paragraph 18, the method comprises: determining that the defraction of the set of identified source memory bands is complete; and in response to the determination that the defraction of the set of identified source memory bands is complete: The step of closing the above-mentioned fragmentation removal destination memory band; and A non-transient computer-readable medium further comprising the step of clearing each of the at least one source memory band of the set of the identified source memory bands. Claim 20 A non-transient computer-readable medium, wherein, in claim 19, the step of determining that the defraction of the set of identified source memory bands is complete comprises the step of determining that the defraction destination memory band is filled with stored valid data.