Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Abstract

Disclosed are memory devices, memory systems, and methods of operating memory devices and memory systems, wherein a single instruction, such as a single refresh instruction that triggers the memory device to perform both a refresh instruction and a mode register read, can trigger the memory device to perform a plurality of operations. One such memory device comprises a memory, a mode register, and a circuit configured to perform a refresh operation on the memory and perform a read of the mode register in response to receiving an instruction to perform a refresh operation on the memory. The memory may be a first memory portion, and the memory device may include a second memory portion, and the circuit may be further configured to provide an on-die termination to the second memory portion of the memory system during at least a portion of the read of the mode register in response to the instruction.

Description

Technology Field

[0001] Cross-reference of related applications

[0002] This application claims the benefit of U.S. application No. 62 / 680,422 filed on June 4, 2018, the entirety of which is incorporated herein by reference.

[0003] Technology field

[0004] The present disclosure generally relates to memory devices and systems, more specifically to methods for performing a plurality of memory operations in response to a single instruction and memory devices and systems utilizing the same. Background Technology

[0005] Memory devices are widely used to store information related to various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and other similar items. Information is stored by programming different states of memory cells. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), and synchronous dynamic RAM (SDRAM). Memory devices can be volatile or non-volatile. Improving memory devices generally includes, among other metrics, increasing memory cell density, increasing read / write speeds or reducing other operational latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs. Brief explanation of the drawing

[0006] FIG. 1 is a simplified block diagram schematically illustrating a memory device according to one embodiment of the present technology. FIGS. 2 and FIGS. 3 are simplified timing diagrams schematically illustrating the operations of memory devices and systems. FIGS. 4 to 6 are simplified timing diagrams schematically illustrating the operations of memory devices and systems according to embodiments of the present technology. FIG. 7 is a flowchart illustrating a method of operating a memory system according to one embodiment of the present technology. Specific details for implementing the invention

[0007] Many memory devices, such as Double Data Rate (DDR) DRAM devices, can operate in various modes (e.g., at different clock speeds, at different refresh rates, etc.). In many cases, various operating parameters of the memory device (e.g., voltage, temperature, device lifespan, etc.) can be used to determine the appropriate mode. In some memory devices, the connected host may periodically poll one or more of these operating parameters of the memory device to determine whether to adjust the mode. For example, the connected host may poll the device temperature (e.g., or information corresponding to the device temperature) to determine whether to modify the device's refresh rate. Polling the device temperature may require a dedicated command for the memory device's command / address bus, and the polling may be frequent enough to adversely affect the command / address bus (e.g., through congestion).

[0008] Accordingly, various embodiments of the present invention relate to memory devices, systems including memory devices, and methods of operating memory devices, wherein a single command on a command / address bus, such as a single refresh command that triggers the memory device to perform both a refresh command and a mode register read (e.g., and output information from it to a host device), can trigger the memory device to perform more than one operation. In one embodiment, the memory device includes a memory, a mode register, and a circuit configured to perform a refresh operation on the memory and perform a read of the mode register in response to receiving a command to perform a refresh operation on the memory. In some embodiments, the memory may be a first memory portion, and the memory device may include a second memory portion, and the circuit may be further configured to provide an on-die termination to the second memory portion of the memory system during at least a portion of the read of the mode register in response to the command.

[0009] FIG. 1 is a block diagram schematically illustrating a memory device (100) according to one embodiment of the present technology. The memory device (100) may include an array of memory cells such as a memory array (150). The memory array (500) may include a plurality of banks (e.g., banks 0-15 in the example of FIG. 1), and each bank may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at the intersections of the word lines and bit lines. The selection of the word lines (WL) may be performed by a row decoder (140), and the selection of the bit lines (BL) may be performed by a column decoder (145). Sense amplifiers (SAMPs) can be provided to corresponding bit lines (BL) and connected to at least one individual local I / O line pair (LIOT / B), which in turn can be connected to at least one main I / O line pair (MIOT / B) through transfer gates (TGs) (which can function as switches).

[0010] The memory device (100) may employ a plurality of external terminals including command and address terminals connected to a command bus and an address bus, respectively, to receive command signals (CMD) and address signals (ADDR). The memory device may further include a chip select terminal for receiving a chip select signal (CS), clock terminals for receiving clock signals (CK and CKF), data clock terminals for receiving data clock signals (WCK and WCKF), data terminals (DQ, RDQS, DBI and DMI), and power supply terminals (VDD, VSS, VDDQ and VSSQ).

[0011] Address signals and bank address signals can be supplied from the outside to command terminals and address terminals. The address signals and bank address signals supplied to the address terminals can be transmitted to the address decoder (110) through the command / address input circuit (105). The address decoder (110) can receive the address signals and supply the decoded row address signal (XADD) to the row decoder (140), and supply the decoded column address signal (YADD) to the column decoder (145). The address decoder (110) can also receive the bank address signal (BADD) and supply the bank address signal to both the row decoder (140) and the column decoder (145).

[0012] Command signals (CMD), address signals (ADDR), and chip select signals (CS) from a memory controller may be supplied to the command and address terminals. The command signals may represent various memory commands from the memory controller (e.g., access commands, which may include read commands and write commands). The select signal (CS) may be used to select a memory device (100) to respond to the commands and addresses provided to the command and address terminals. When an active CS signal is provided to the memory device (100), the commands and addresses may be decoded and memory operations may be performed. The command signals (CMD) may be provided to the command decoder (115) as internal command signals (ICMD) through the command / address input circuit (105). The instruction decoder (115) may include circuits that decode internal instruction signals (ICMD) to generate various internal signals and instructions for performing memory operations, such as a row instruction signal for selecting a word line and a column instruction signal for selecting a bit line. The internal instruction signals may also include output and input enable instructions, such as a clocked instruction (CMDCK).

[0013] When a read command is issued and the read command is supplied to the row address and column address in a timely manner, read data is read from memory cells in the memory array (150) specified by these row address and column address. The read command may be received by an instruction decoder (115), which may provide internal instructions to the input / output circuit (160) so that read data can be output from data terminals (DQ, RDQS, DBI, and DMI) through the read / write amplifier (155) and the input / output circuit (160) according to the RDQS clock signals. The read data may be provided to the memory device (100) at a time defined by read latency information (RL), which can be programmed, for example, in a mode register (not shown in FIG. 1). The read latency information (RL) may be defined with respect to the clock cycles of the CK clock signal. For example, the read latency information (RL) may be the number of clock cycles of the CK signal after the read command is received by the memory device (100) when the related read data is provided.

[0014] When a write command is issued and the command is supplied to the row address and column address in a timely manner, write data may be supplied to the data terminals (DQ, DBI, and DMI) according to the WCK and WCKF clock signals. The write command may be received by the command decoder (115), which may provide internal commands to the input / output circuit (160) so that the write data may be received by the data receivers of the input / output circuit (160) and supplied to the memory array (150) through the input / output circuit (160) and the read / write amplifiers (155). The write data may be written to the memory cell specified by the row address and column address. The write data may be provided to the data terminals at a time defined by the write latency (WL) information. The write latency (WL) information may be programmed into the memory device (100), for example, the mode register (not shown in FIG. 1). The write latency (WL) information may be defined with respect to the clock cycles of the CK clock signal. For example, the write latency information (WL) may be the number of clock cycles of the CK signal after the write command is received by the memory device (100) when the related write data is received.

[0015] Power supply potentials (VDD and VSS) may be provided to the power supply terminals. These power potentials (VDD and VSS) may be provided to the internal voltage generator circuit (170). The internal voltage generator circuit (170) may generate various internal potentials (VPP, VOD, VARY, VPERI, etc.) based on the power supply potentials (VDD and VSS). The internal potential (VPP) may be used in the row decoder (140), the internal potentials (VOD and VARY) may be used in the sense amplifiers included in the memory array (150), and the internal potential (VPERI) may be used in many other circuit blocks.

[0016] A power potential (VDDQ) may also be supplied to the power supply terminal. The power potential (VDDQ) may be supplied to the input / output circuit (160) together with the power potential (VSS). In one embodiment of the present invention, the power potential (VDDQ) may be the same potential as the power potential (VDD). In another embodiment of the present invention, the power potential (VDDQ) may be a different potential from the power potential (VDD). However, a dedicated power potential (VDDQ) may be used for the input / output circuit (160) so that power noise generated by the input / output circuit (160) does not propagate to other circuit blocks.

[0017] External clock signals and complementary external clock signals may be supplied to the clock terminals and data clock terminals. External clock signals (CK, CKF, WCK, WCKF) may be supplied to the clock input circuit (120). The CK and CKF signals may be complementary, and the WCK and WCKF signals may also be complementary. The complementary clock signals may have opposite clock levels and may switch between opposite clock levels simultaneously. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. In addition, when the clock signal is switched from a low clock level to a high clock level, the complementary clock signal is switched from a high clock level to a low clock level, and when the clock signal is switched from a high clock level to a low clock level, the complementary clock signal is switched from a low clock level to a high clock level.

[0018] Input buffers included in the clock input circuit (120) can receive external clock signals. For example, when enabled by a CKE signal from the command decoder (115), the input buffer can receive CK and CKF signals and WCK and WCKF signals. The clock input circuit (120) can receive external clock signals and generate internal clock signals (ICLK). The internal clock signals (ICLK) can be supplied to the internal clock circuit (130). The internal clock circuit (130) can provide various phase and frequency controlled internal clock signals based on the received internal clock signals (ICLK) and the clock enable signal (CKE) from the command / address input circuit (105). For example, the internal clock circuit (130) may include a clock path (not shown in FIG. 1) that receives an internal clock signal (ICLK) and provides various clock signals to the instruction decoder (115). The internal clock circuit (130) may further provide input / output (IO) clock signals. The IO clock signals may be supplied to the input / output circuit (160) and may be used as timing signals to determine the output timing of read data and the input timing of write data. The IO clock signals may be provided at multiple clock frequencies so that data can be output from the memory device (100) and input thereto at different data rates. A higher clock frequency may be desirable when a high memory speed is required. A lower clock frequency may be desirable when lower power consumption is required. The internal clock signals (ICLK) may also be supplied to the timing generator (135) and, accordingly, various internal clock signals may be generated.

[0019] Memory devices such as the memory device (100) of FIG. 1 may be able to operate in various modes (e.g., at different clock speeds, at different refresh rates, etc.). In many cases, various operating parameters of the memory device (100) (e.g., voltage, temperature, device lifespan, etc.) may be stored in its mode register and used to determine an appropriate mode (e.g., by a connected host device). For example, the connected host may periodically poll one or more of these operating parameters of the memory device (100) to determine whether to adjust the mode (e.g., increase the refresh rate due to an increased device temperature, or decrease the refresh rate due to a decreased device temperature).

[0020] One approach to polling the operating parameters of a memory device involves a host that transmits a dedicated command to the memory device to perform a mode register read operation and output the values ​​therefrom onto the memory device's data bus. For example, as can be seen by referring to the simplified timing diagram (200) shown in FIG. 2, in response to the host device providing a mode register read command (including first a first MRR1 portion (222) and a second MRR2 portion (223)) on the command / address bus (220), the memory device outputs the mode register read (MRR) data (251) to the host device via its data bus (250) (e.g., after a predetermined delay). As can be seen by referring to FIG. 2, as is common practice for polling memory devices for operating parameters that may affect the required refresh rate, the mode register read command follows immediately (e.g., immediately) the refresh command (221). As can be further seen by referring to FIG. 2, the mode register read command consumes two cycles of the device clock (210) on the command / address bus.

[0021] FIG. 3 is a simplified timing diagram (300) that schematically illustrates the operation of a memory system having a plurality of memory portions (e.g., channels, dies, ranks, banks, etc.). As can be seen from FIG. 3, in response to a host device providing a mode register read command (including first MRR1 portion (322) and second MRR2 portion (323)) on a command / address bus (320) to a first memory portion (e.g., indicated as assigning a row chip select signal (331) on a first chip select terminal (330) during a first clock cycle of the mode register read command), the first memory portion outputs MRR data (351) to the host device through the data bus (350) of the memory device (e.g., after a predetermined delay). A mode register read command may follow immediately (e.g., immediately) a refresh command (321) directed toward the same memory portion, as is common practice for polling memory devices for operational parameters that may affect the required refresh rate (as indicated by the assertion of a low chip select signal (331) on the first chip select terminal (330) during the refresh command (321). To prevent degradation of MRR data (351) over the shared data bus, the second memory portion (360) may be instructed to provide an on-die termination (ODT) (361) while transmitting MRR data (351) (e.g., by asserting a low chip select signal (341) on the second chip select terminal (340) during both clock cycles of the mode register read command). As can be further seen with reference to FIG. 3, the mode register read command consumes two cycles of the device clock (310) on the command / address bus.

[0022] Considering the frequency at which the operation parameters of a memory device stored in a mode register can be polled by a connected host device (e.g., as often as refresh commands are transmitted in some cases), the consumption of command / address bus bandwidth by mode register read commands can rise to an unfavorable level. Accordingly, embodiments of the present technology can reduce the consumption of command / address bandwidth by solving the aforementioned problems by providing a method for a connected host device to poll the operation parameters of a memory device without providing a dedicated mode register read command.

[0023] Referring to FIG. 4, there is a simplified timing diagram (400) schematically illustrating the operation of a memory device according to one embodiment of the present technology. As can be seen by referring to FIG. 4, in response to a host device providing a refresh command (421) on the command / address bus (420) in addition to performing a commanded refresh operation (not shown), the memory device outputs mode register read (MRR) data (451) to the host device via its data bus (450) (e.g., after a predetermined delay). By configuring the memory device to perform a mode register read operation in addition to the refresh operation in response to the refresh command, the amount of command / address bus bandwidth consumed can be significantly reduced (e.g., using one cycle of the clock (410) to transmit a single command that triggers the same operations that previously took three cycles of the clock (410) to trigger).

[0024] According to one aspect of the present disclosure, the refresh command (421) may be a standard refresh command without any additional information indicating additional mode register read operations to be performed, as in one embodiment where the memory device is configured to interpret all refresh commands received (e.g., through a mode register setting or other configuration mechanism) as refresh commands accompanied by mode register read commands. Alternatively, the refresh command (421) may be a modified refresh command provided with one or more bit flags to indicate to the memory device that a mode register read operation will be performed.

[0025] Referring to FIG. 5, there is a simplified timing diagram (500) schematically illustrating the operation of a memory system comprising a plurality of memory portions (e.g., dies, devices, channels, ranks, banks, etc.) according to one embodiment of the present technology. As can be seen by referring to FIG. 5, in a memory device or system having two or more individually addressable portions (e.g., two channels of a memory device, two memory devices of a memory system), a common command / address bus (520) may be used to indicate to the portions that a refresh operation and a mode register read will be performed by one of the portions (e.g., via a refresh command (521)). However, unlike the approach illustrated in FIG. 3, in the approach illustrated in FIG. 5, in response to an indication to the memory portion that it is not the target of a refresh / mode register read command, the memory portion enters an on-die termination mode during the communication period of the mode register contents on the common data bus.

[0026] In the example of FIG. 5, a refresh command (521) is transmitted with a corresponding indication (531) on a first chip select terminal (530) that the target of the refresh command corresponds to a first part of the memory device (e.g., by pulsing the first chip select terminal (530) low for one cycle of the clock (510) to indicate the target part, and leaving the second chip select terminal (540) corresponding to the non-target part high to indicate that it is not the target part). In response to this, the first part of the memory device performs a refresh operation (not shown) and also outputs MRR data (551) to the host device through its data bus (550) (e.g., after a predetermined delay). Also, in response to the same refresh command (521), the second part (560) of the memory device enters an on-die termination mode (561) during the communication (551) of the first channel (550).

[0027] According to one aspect of the present disclosure, the refresh command (521) may be a standard refresh command without any additional information indicating additional mode register read operations to be performed, as in one embodiment where the memory device is configured to interpret all refresh commands received (e.g., via a mode register setting or other configuration mechanism) as refresh commands accompanied by mode register read commands. Alternatively, the refresh command (521) may be a modified refresh command provided with one or more bit flags to indicate to the memory device that a mode register read operation will be performed. The refresh command (521) may further include one or more bit flags indicating to the memory device that on-die termination will be performed by untargeted portions of the memory device during the output of the mode register read data.

[0028] As the approach illustrated in FIG. 5, in which a refresh command transmits information that is not the target of the refresh operation to memory portions (as indicated by corresponding chip select signals), may entail portions that are not the target of memory device decoding commands, such an approach may entail additional power consumption that may be undesirable in specific power-sensitive memory environments (e.g., mobile). Accordingly, FIG. 6 is a simplified timing diagram (600) illustrating the operation of a memory system comprising a plurality of memory portions (e.g., dies, devices, channels, ranks, banks, etc.) according to an embodiment of the present technology in which decoding by the untargeted memory portions can be avoided.

[0029] As can be seen by referring to FIG. 6, in a memory device or system having two or more individually addressable parts (e.g., two channels of a memory device, two memory devices of a memory system), a common command / address bus (620) can be used to indicate to the parts that a refresh operation and a mode register read will be performed by one of the parts (e.g., through a refresh command (621)). However, unlike the approach illustrated in FIG. 5, in the approach illustrated in FIG. 6, the refresh command (621) is transmitted with a corresponding indication (631) on the first chip select terminal (630) that the target of the refresh command corresponds to a first part of the memory device (e.g., by pulsing the first chip select terminal (630) low for one cycle of the clock (610) to indicate the target part, and leaving the second chip select terminal (640) corresponding to the non-target part high to indicate that it is not the target part), as well as with an indication (646) on the dedicated "mode register read enable" terminal (645) that the refresh command (621) must also be decoded by the non-target memory parts (e.g., to allow the non-target parts to provide on-die termination). In response to this, the first part of the memory device performs a refresh operation (not shown) and also outputs MRR data (651) to the host device via its data bus (650) (e.g., after a predetermined delay). Additionally, in response to the same refresh command (621) configured to be decoded by the second part of the memory device in response to the indication (646) on the mode register read enable terminal (645), the second part of the memory device (660) enters an on-die termination mode (661) during the communication (651) of the first channel (650).

[0030] This arrangement, in which commands are decoded only by the non-targeted portions when the enable signal is asserted, eliminates the need for the non-targeted portions of the memory device to decode other commands (read commands, write commands, etc.), while still allowing for proper on-die termination during mode register read output, thereby providing desirable power savings despite the cost of dedicating the terminal to the enable signal. However, in some embodiments, the enable signal may also be provided on a shared terminal dedicated to other functions, such as loopback DQ (LBDQ) and / or loopback DQS (LBDQS) terminals.

[0031] In the examples described above, memory devices are illustrated and explained as responding to refresh commands with both refresh operations and mode register read operations; however, in other embodiments of the present invention, other commands may be configured to trigger other combinations of operations to provide a similar reduction in command / address bus bandwidth. Additionally, while memory devices in the examples described above are illustrated and explained as responding to all refresh commands with both refresh operations and mode register read operations, in other embodiments of the present invention, the response of the memory device to such commands may be configured (e.g., a mode register setting indicating whether multiple operations are enabled in response to a single command mode, authorized enable signals, etc.).

[0032] FIG. 7 is a flowchart illustrating a method of operating a memory device according to one embodiment of the present technology. The method includes the step of receiving a command to refresh the memory device (Box 710). According to one aspect of the present disclosure, the receiving features of Box (710) may be implemented as a command / address input circuit (105), terminals connected thereto and / or a command decoder (115), as illustrated in more detail above in FIG. 1. The method further includes the step of refreshing the memory device in response to the command (Box 720) and the step of performing a read of the mode register of the memory device (Box 730). According to one aspect of the present disclosure, the refresh features and mode register read features of Boxes (720 and 730) may be implemented as a memory array (150), read / write amplifiers (155), an input / output circuit (160), terminals connected thereto and / or other circuit elements of the memory device (100), as illustrated in more detail above in FIG. 1.

[0033] It should be noted that the methods described above illustrate possible implementations, and that operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more of the above methods may be combined.

[0034] The information and signals described herein may be represented using any of the various different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the foregoing description may be represented as voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. While some drawings may depict signals as a single signal; it will be understood by a person skilled in the art that a signal may represent a bus of signals, wherein the bus may have various bit widths.

[0035] The devices discussed herein, including memory devices, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on other substrates. The conductivity of the substrate, or subregions of the substrate, may be controlled through doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation or any other doping means during the initial formation or growth of the substrate.

[0036] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functions may also be physically located in various locations, including distributed so that parts of the functions are implemented in different physical locations.

[0037] When used herein, including in the claims, the phrase "or" (e.g., a list of items ending in a phrase such as "at least one of" or "one or more of") indicates a comprehensive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A, B, and C). Additionally, when used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, a representative step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, when used herein, the phrase "based on" should be construed in the same way as the phrase "at least partially based on".

[0038] From this, it will be understood that while specific embodiments of the present invention have been described herein for illustrative purposes, various modifications may be made without departing from the scope of the invention. More precisely, in the foregoing description, many specific details are discussed to provide a detailed and enabling description of embodiments of the present technology. However, a person skilled in the art will recognize that the present disclosure may be practiced without one or more of the specific details. In other cases, well-known structures or operations typically associated with memory systems and devices have not been illustrated or described in detail to avoid obscuring other aspects of the present technology. In general, it should be understood that various other devices, systems, and methods may be within the scope of the present technology in addition to such specific embodiments disclosed herein.

Claims

Claim 1 A memory system comprising: a plurality of memory portions; and a circuit configured to perform a refresh operation on a first memory portion among the plurality of memory portions during a first period in response to receiving a refresh command; and to perform a mode register read operation on a mode register in the first memory portion during a second period following the first period for a predetermined amount of time, wherein the refresh command indicates to the memory system to perform the refresh operation and the mode register read operation. Claim 2 The memory system of claim 1, wherein the circuit is further configured to configure the memory system to interpret the refresh command as being accompanied by a mode register read command. Claim 3 A memory system according to claim 1, wherein the refresh command is modified compared to other refresh commands. Claim 4 A memory system according to claim 1, wherein the refresh command comprises one or more bits indicating that the mode register read operation will be performed. Claim 5 A memory system according to claim 1, wherein, for performing the mode register read operation, the circuit is configured to output data from the mode register during the second period. Claim 6 A memory system according to claim 5, wherein the circuit is further configured to receive, through a second chip select terminal, a signaling including an indication that a second memory portion among the plurality of memory portions will provide on-die termination for at least one part of the second period. Claim 7 A memory system according to claim 5, wherein the data includes information corresponding to the temperature of the first memory portion or information corresponding to the refresh rate of the first memory portion. Claim 8 A memory system according to claim 1, wherein the circuit is further configured to receive, through a first chip select terminal, a signaling including an indication that the first memory portion is the target of the refresh operation. Claim 9 A memory system according to claim 8, wherein the circuit is further configured to receive, through a second chip select terminal, a signaling including an indication that a second memory portion is not a target of the refresh operation. Claim 10 A memory device comprising a controller configured to cause the memory device to: receive a refresh command; perform a refresh operation during a first period; and, after receiving the refresh command, output data from a mode register of the memory device during a second period following the first period for a predetermined amount of time, wherein the refresh command indicates to the memory device to perform the refresh operation and to output the data from the mode register. Claim 11 A memory device according to claim 10, wherein the refresh command is received via a command / address bus. Claim 12 A memory device according to claim 10, wherein the data includes information corresponding to the temperature of the memory device. Claim 13 A memory device according to claim 10, wherein the data includes information corresponding to the refresh rate of the memory device. Claim 14 A method by a memory system comprising: receiving a refresh command; performing a refresh operation on a first memory portion of the memory system for a first period, at least partially based on the refresh command; and performing a mode register read operation on a mode register in the first memory portion for a second period following the first period, at least partially based on the refresh command, wherein the refresh command indicates to the memory system to perform the refresh operation and the mode register read operation. Claim 15 A method according to claim 14, further comprising the step of configuring the memory system to interpret the refresh command as being accompanied by a mode register read command. Claim 16 A method according to claim 14, wherein the refresh command is modified compared to other refresh commands. Claim 17 A method according to claim 14, wherein the refresh command comprises one or more bits indicating that the mode register read operation will be performed. Claim 18 The method of claim 14, wherein the step of performing the mode register read operation comprises: outputting data from the mode register during the second period. Claim 19 A method according to claim 14, further comprising the step of receiving a signaling through a first chip select terminal that includes an indication that the first memory portion becomes the target of the refresh operation. Claim 20 A method according to claim 19, further comprising the step of receiving a signaling through a second chip select terminal that includes an indication that the second memory portion is not a target of the refresh operation.

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