Data Storage Apparatus for Pending and Processing Read Command Based On Processing Status of Write Command and Operation Method Thereof, Memory Controller Therefor

Abstract

A data storage device according to one embodiment may include a storage medium and a memory controller. The memory controller may determine whether to hold the first read command based on a flag set in the first write command when the read address to perform the first read command matches at least partially with the write address of the first write command currently being executed, store the held first read command in a read-ready queue, and control the command queued in the read-ready queue to be processed after the execution of the first write command is completed.

Description

Technology Field

[0001] The present invention relates to a semiconductor integrated circuit, and more specifically, to a data storage device that holds and processes a read command according to a write command processing state, a method of operation thereof, and a memory controller for the same. Background Technology

[0002] A data storage device can store data in a memory device or read data stored in a memory device and provide it to an external device in response to a request from an external device.

[0003] The performance of a data storage device can be determined not only by the speed at which the memory device writes or reads data, but also by the technique by which the memory controller operates the memory device.

[0004] Therefore, technology is required to write and read data more efficiently in response to requests from external devices. The problem to be solved

[0005] An embodiment of the present technology can provide a data storage device and a method of operation thereof that can efficiently process read requests for data being written so as to maintain data consistency, and a memory controller for the same. means of solving the problem

[0006] A data storage device according to one embodiment of the present technology comprises: a storage medium; and a memory controller that, when a read address to perform a first read command matches at least partially with a write address of a first write command currently being executed, determines whether to hold the first read command based on a flag set in the first write command, stores the held first read command in a read-ready queue, and controls the command queued in the read-ready queue to be processed after the execution of the first write command is completed; wherein the flag may be configured to indicate whether the first write data associated with the first write command has been transmitted from the buffer memory device to the storage medium.

[0007] A memory controller according to one embodiment of the present technology may be configured to receive a first write command including a first write address and first write data, store the first write data in a buffer memory device and set a flag to a first state, transmit the first write data to a storage medium and then set the flag to a second state, and if a read address associated with a first read command received during the execution of the first write command matches at least partially with the first write address, determine whether to hold the first read command based on the flag, and store the held first read command in a read-ready queue.

[0008] A method of operation of a data storage device according to one embodiment of the present technology comprises: a step in which a memory controller determines whether to hold a first read command based on a flag set in the first write command when the read address to perform the first read command matches at least partially with the write address of the first write command currently being executed; a step in which the memory controller stores the held first read command in a read-ready queue; and a step in which the controller processes a command queued in the read-ready queue after the execution of the first write command is completed; wherein the flag may be configured to indicate whether the first write data associated with the first write command has been transferred from the buffer memory device to the storage medium. Effects of the invention

[0009] According to the present technology, if the data for which a lead was requested is being written, the lead request can be put on hold, and the put-on lead request can be processed preferentially after the writing operation is completed.

[0010] Accordingly, the release time of the write buffer can be advanced while guaranteeing the processing speed of read requests. Brief explanation of the drawing

[0011] FIG. 1 is a configuration diagram of a data processing system according to one embodiment. FIG. 2 is a configuration diagram of a memory controller according to one embodiment. FIG. 3 is a drawing for explaining a buffer memory device according to one embodiment. FIG. 4 is a diagram illustrating a read ready queue according to one embodiment. FIG. 5 is a drawing for explaining a light descriptor according to one embodiment. FIG. 6 is a drawing for explaining a lead descriptor according to one embodiment. FIG. 7 is a diagram illustrating a method of writing to a data storage device according to one embodiment. FIG. 8 is a diagram illustrating a method of operation of a data storage device according to one embodiment. FIG. 9 is a diagram illustrating a method of operation of a data storage device according to one embodiment. FIG. 10 is a diagram illustrating a method of operation of a data storage device according to one embodiment. Specific details for implementing the invention

[0012] Hereinafter, embodiments of the present technology will be described in more detail with reference to the attached drawings.

[0013] FIG. 1 is a configuration diagram of a data processing system according to one embodiment.

[0014] Referring to FIG. 1, the data processing system (10) may include an external device (100) and a data storage device (200).

[0015] The external device (100) may include at least one processor. The external device (100) may be the processor itself, or an electronic device or system including the processor. The external device (100) may operate as a host device for a data storage device (200).

[0016] The data storage device (200) may include a memory controller (210), a buffer memory device (220), and a storage medium (260). The storage medium (260) may include at least a plurality of non-volatile memory devices (NVM1, NVM2, …, NVMn; 230, 240, 250) electrically connected to the memory controller (210) through at least one channel (CH1, CH2, …, CHn).

[0017] The external device (100) may transmit a write request to the data storage device (200) including a write command (WT), an address (ADD), and write data (DATA) to record data. In response, the data storage device (200) may control the write data to be programmed into the storage medium (260).

[0018] The external device (100) may transmit a read request including a read command (RD) and an address (ADD) to the data storage device (200) to read data. The data storage device (200) may read the requested data (DATA) from the storage medium (260) or the buffer memory device (220) and transmit it to the external device (100).

[0019] The data storage device (200) may internally generate a read command or a write command to perform internal management operations for managing the storage medium (260) and read or write data from the storage medium (260). The internal management operations may include housekeeping operations performed independently of requests from the external device (100) to efficiently use the storage space of the storage medium (260) or to ensure the reliability of data stored in the storage medium (260), such as wear leveling operations, garbage collection operations, and read reclaim operations.

[0020] In one embodiment, the storage medium (260) may be composed of at least one of various types of non-volatile memory devices (230, 240, 250), such as a NAND flash memory device, a NOR flash memory device, a ferroelectric RAM (FRAM) using a ferroelectric capacitor, a magnetic RAM (MRAM) using a tunneling magneto-resistive (TMR) film, a phase change memory device (PRAM) using chalcogenide alloys, and a resistive memory device (RERAM) using a transition metal oxide.

[0021] Each of the non-volatile memory devices (230, 240, 250) includes a plurality of memory cells. Each of the memory cells can operate as a single-level cell (SLC) capable of storing 1 bit of data, or as a multi-level cell (MLC) capable of storing 2 bits or more of data. Some of the non-volatile memory devices (230, 240, 250) may be configured to operate as single-level cell (SLC) memory devices, and some as multi-level cell (MLC) memory devices. Some of the memory cells of each of the non-volatile memory devices (230, 240, 250) may operate as single-level cells (SLC), and other memory cells may operate as multi-level cells (MLC).

[0022] The buffer memory device (220) can temporarily store data transmitted between the external device (100) and the data storage device (200) during a write or read operation. In some embodiments, the data storage device (200) may be a DRAM-less device that does not have a buffer memory device (220). The buffer memory device (220) may be provided inside the memory controller (210).

[0023] The buffer memory device (220) can temporarily store system data, such as descriptors related to requests from external devices (100) and map data for data stored in a storage medium (260). In the case of a DRAM-less device, system data can be stored in memory within the memory controller (210) or in memory of the external device (100).

[0024] The descriptor may be a work description containing information necessary for the memory controller (210) to process a request received from an external device (100). The descriptor may include a write descriptor, a read descriptor, etc.

[0025] Map data may be a set of mapping information between an address (physical address) of a physical storage space constituting the storage medium (260) and logical addresses assigned to the storage medium (260) by an external device. Map data is stored in the storage medium (260), and the memory controller (210) may use at least partially load the map data required for the operation of the data storage device (200) into the buffer memory device (220) or the internal memory (not shown) of the memory controller (210).

[0026] The memory controller (210) can manage write commands and write data by generating a write descriptor to perform a write operation in response to a write request from an external device (100). In one embodiment, the memory controller (210) can manage whether the write data related to the write operation currently in progress has been released from the buffer memory device (220) through the write descriptor.

[0027] The memory controller (210) can read data from a buffer memory device (220) or a storage medium (260) and provide it to the external device (100) depending on whether the write data is released when the address included in the read request of the external device (100) is associated with a write request currently being executed.

[0028] In one embodiment, when an address included in a read request is associated with a write request currently in progress and the write data is released, the memory controller (210) may store the read command included in the read request in the read ready queue of the buffer memory device (220). The memory controller (210) may control the read command in the read ready queue to be processed preferentially when the write operation currently in progress is completed.

[0029] The concept of holding and processing a read request associated with the address of a write request currently in progress will be explained in detail with reference to FIGS. 2 through 10.

[0030] FIG. 2 is a configuration diagram of a memory controller according to one embodiment.

[0031] Referring to FIG. 2, a memory controller (210) according to one embodiment may include a processor (211), a first core (213), a second core (215), and an operating memory (217).

[0032] The processor (211) may be configured to operate by executing firmware or software provided for various operations of the memory controller (210) on the hardware. The processor (211) may be implemented in a combined form of hardware and firmware or software operating on the hardware. The processor (211) may perform functions such as a flash conversion layer (FTL) for managing a data storage device (200).

[0033] The first core (213) can receive command and clock signals from an external device (100) under the control of the processor (211) and provide a communication channel for controlling the input and output of data. The first core (213) can provide a physical connection between the external device (100) and the data storage device (200).

[0034] In one embodiment, the first core (213) can communicate with an external device (100) based on an interface using at least one of various interface protocols such as USB (Universal Serial Bus) protocol, MMC (multimedia card) protocol, PCI (peripheral component interconnection) protocol, PCI-E (PCI-Express) protocol, ATA (Advanced Technology Attachment) protocol, SATA (Serial-ATA) protocol, PATA (Parallel-ATA) protocol, SCSI (small computer system interface) protocol, ESDI (enhanced small disk interface) protocol, IDE (Integrated Drive Electronics) protocol, private protocol, SMBus (System Management Bus) protocol, I2C (Inter-Integrated Circuit) protocol, I3C (Improved Inter-Integrated Circuit) protocol, etc.

[0035] The first core (213) can interpret and store commands included in a request received from an external device (100). In response to a write request from the external device (100), the first core (213) can queue the write command included in the write request into an operation memory (217) and generate a write descriptor under the control of the processor (211). The first core (213) can store the write descriptor and write data in a buffer memory device (220). The write descriptor may include buffering status information indicating whether the write data related to the write request has been stored in the buffer memory device (220).

[0036] The first core (213) can respond to a read request from an external device (100), queue a read command in the operation memory (217) under the control of the processor (211), generate a read descriptor, and store it in the buffer memory device (220).

[0037] The second core (215) can provide a communication channel for transmitting and receiving signals between the memory controller (210) and the storage medium (260). The second core (215) can dequeue commands queued in the buffer memory device (220) and process commands based on descriptors associated with the dequeued commands.

[0038] If the dequeued command is a write command, the second core (215) can generate a program command based on the write descriptor generated by the first core (213) and provide the program command and write data to the storage medium (260). After transmitting the write data to the storage medium (26), the second core (215) can release the write data from the buffer memory device (220), that is, release the allocation for the write data storage area of ​​the buffer memory device (220) and change the buffering status information of the write descriptor.

[0039] If the dequeued command is a read command, the second core (215) can determine whether the address included in the read request is associated with the write request currently being executed based on the read descriptor generated by the first core (213). If the address included in the read request is associated with the write request currently being executed and the buffer area where the write data is stored is released, the second core (215) can assign an index to the read command and store it in the read ready queue (2175) of the operation memory (217) to hold the read operation. The memory controller (210) can control the read command in the read ready queue (2175) to be processed preferentially when the write operation currently being executed is completed. In one embodiment, the index assigned to the holdable read command may be the address of the read ready queue (2175) where the read command is stored.

[0040] Read requests associated with the address of a write request currently in progress may be received sequentially multiple times. The second core (215) may manage the indices of multiple read commands associated with the write request currently in progress as a linked list in the read ready queue (2175).

[0041] A linked list is a data structure that stores one piece of data along with the location of the next piece of data, logically connecting data by index (address).

[0042] The second core (215) may store the indices of pending read commands associated with the executing write request as a read command list in the write descriptor. The read command list may include the leading index and the last index of the pending read commands stored as a linked list in the read ready queue (2175).

[0043] When the executing write operation is completed, the second core (215) can dequeue the read commands stored in the read ready queue (2175) based on the read command list stored in the write descriptor and generate a read command to provide to the storage medium (260). At this time, the second core (215) can control the storage medium (260) so that the pending read command is processed preferentially over other commands.

[0044] When the pending read command is completed, the second core (215) can release the index assigned to the pending read command.

[0045] The operating memory (217) may be composed of a random access memory device such as dynamic random access memory (DRAM) or static random access memory (SRAM), but is not specifically limited thereto. The operating memory (217) may cache data stored in the buffer memory device (220).

[0046] The operation memory (217) can store firmware driven by the processor (211). Additionally, the operation memory (217) can store data required for the operation of the firmware, for example, metadata. The metadata is stored in a storage medium (260), and the processor (211) can load the metadata required for the operation of the data storage device (200) into the operation memory (217) for use.

[0047] Additionally, the operation memory (217) can operate as a buffer memory for storing write data provided from an external device (100) and read data read from a storage medium (260).

[0048] FIG. 3 is a drawing for explaining a buffer memory device according to one embodiment.

[0049] Referring to FIG. 3, a buffer memory device (220) according to one embodiment may include an FTL buffer (FTL BUFFER) in which a flash translation layer (FTL) is stored, a metadata buffer (META BUFFER), a descriptor buffer (DESCRIPTOR BUFFER), a write buffer (WRITE BUFFER), a read buffer (READ BUFFER), a map update buffer (MAP UPDATE BUFFER), and a read ready queue (READ READY QUEUE).

[0050] The flash conversion layer (FTL) is software driven by the memory controller (210), and the memory controller (210) drives the flash conversion layer (FTL) to control the unique operation of the data storage device (200) and can provide device compatibility to the external device (100). Through the operation of the flash conversion layer (FTL), the external device (100) can recognize and use the data storage device (200) as a storage device such as a disk.

[0051] The flash conversion layer (FTL) can perform read functions, write functions, garbage collection functions, wear-leveling functions, bad block management functions, mapping functions, etc. The flash conversion layer (FTL) is stored in a system area (not shown) of a storage medium (260), and when the data storage device (200) is powered on, it can be read from the system area of ​​the storage medium (260) and loaded into a buffer memory device (220).

[0052] The flash translation layer (FTL) loaded into the buffer memory device (220) may also be loaded into the operation memory (217) of the memory controller (210).

[0053] Metadata buffers can store meta-information such as P2L (Physical-to-Logical) tables.

[0054] The descriptor buffer can store various descriptors generated to process requests from external devices (100), such as write descriptors and read descriptors generated by the first core (213).

[0055] The write buffer may temporarily store write data to be transferred from an external device (100) to a storage medium (260).

[0056] Read buffer can temporarily store read data to be read from storage medium (260) and transmitted to external device (100).

[0057] The map update buffer can temporarily store map segments to be updated among the mapping information.

[0058] A Read Ready Queue may queue pending read commands associated with the address of a running write request. An index is assigned to a pending read command, and the index may be the address of the Read Ready Queue to queue the pending read command. When multiple read requests associated with the address of a single running write request are received and pending, the index assigned to each pending read command may be managed as a linked list according to the order in which the read commands are received.

[0059] FIG. 4 is a diagram illustrating a read ready queue according to one embodiment.

[0060] Referring to FIG. 4, the first to third pending read commands (PRC1, PRC2, PRC3) can be queued in the read ready queue.

[0061] Index 3 (IDX3) is assigned to the first hold read command (PRC1). It can be seen that 0 is stored in the linked list field (LINK) indicating the hold read command to be processed following the first hold read command (PRC1). That is, the hold read command indicated by index 0 (IDX0) can be processed following the first hold read command (PRC1) indicated by index 3 (IDX3).

[0062] Since 2 is stored in the linked list field (LINK) of the second hold read command (PRC2) assigned to index 0 (IDX0), the hold read command indicated by index 2 (IDX2) can be processed following the second hold read command (PRC2).

[0063] The linked list field (LINK) of the third hold read command (PRC3) to which index 2 (IDX2) is assigned has an invalid value (INV), which may mean that there is no hold read command to be processed following the third hold read command (PRC3).

[0064] The first to third pending read commands (PRC1, PRC2, PRC3) that are queued in the read ready queue associated with the address of a single write request currently in progress are read commands for the same address. When the processing of the write request currently in progress is completed, the second core (215) can dequeue the pending read commands within the range of the leading index and the last index of the read command list identified from the write descriptor from the read ready queue. Then, any one of the dequeued pending read commands can be arbitrarily selected to control the storage medium (260) to execute. The data read according to the execution of the selected read command can be shared by all dequeued pending read commands (PRC1, PRC2, PRC3) to complete the execution of the pending read commands (PRC1, PRC2, PRC3).

[0065] FIG. 5 is a drawing for explaining a light descriptor according to one embodiment.

[0066] Referring to FIG. 5, the light descriptor (DES_Wx) may include a light descriptor identifier field (DES ID), an address field (START LA, LENGTH), an index field (WB INDEX), a command attribute field (CMD ATRB), a command identifier field (CMD NO), a flag field (FLAG), and a read command list field (RD HEAD, WD TAIL).

[0067] The address of the descriptor buffer (DESCRIPTOR BUFFER) where the light descriptor (DES_Wx) is stored can be stored in the light descriptor identifier field (DES ID).

[0068] The address field (START LA, LENGTH) can store the start logical address (START LA) and length information (LENGTH) associated with the write command.

[0069] The index field (WB INDEX) may store first buffering information, which is the address of the write buffer (WRITE BUFFER) where the write data is stored.

[0070] The command attribute field (CMD ATRB) can store the type of the command. In the case of a light descriptor (DES_Wx), the command attribute field (CMD ATRB) can store a value indicating that the command is a light command.

[0071] The Command Identifier field (CMD NO) may store an identifier value to distinguish the write command.

[0072] The flag field (FLAG) may store a value indicating whether the light data corresponding to the light descriptor (DES_Wx) is effectively stored in the light buffer (WRITE BUFFER), or whether the light data is transferred to the storage medium (260) and the allocation of the light buffer (WRITE BUFFER) is released.

[0073] For example, when the first write data (WD1) is stored in the write buffer, the first core (213) can set the flag field (FLAG) to the first state. At this time, the flag of the first state can indicate that the first write command is dequeued and being processed and that the write data is being maintained in the write buffer.

[0074] The second core (215) can provide the program command and the first write data (WD1) to the storage medium (260) and release the area allocated for buffering the first write data (WD1). After releasing the buffering area of ​​the first write data (WD1), the second core (215) can set the flag field (FLAG) to a second state. The flag of the second state can indicate that the first write data (WD1) has been transferred to the storage medium (260), or, from another perspective, that the buffering of the first write data (WD1) has been released.

[0075] In the read command list fields (RD HEAD, RD TAIL), the leading index (RD HEAD) and the last index (RD TAIL) of the read command associated with the address (START LA, LENGTH) of the write command corresponding to the write descriptor (DES_Wx) can be stored when the write command is being executed.

[0076] For example, when a first read command for a first address is received while a first write command for a first address is being executed, an index L (where L is a natural number) is assigned to the first read command and stored in the read ready queue, and L may be stored as the leading index (RD HEAD) in the read list field of the first write descriptor (DES_W1). If no read command for a first address is received following the first read command, the same value as the leading index (RD HEAD) may be stored in the last index (RD TAIL).

[0077] When the first write command is still executing, if a second read command for the first address is received following the first read command, an index M (where M is a natural number) may be assigned to the second read command. The first read command and the second read command may be organized into a linked list and stored in a read ready queue. That is, M may be stored in the link field of the first read command. In the read list field of the first write descriptor (DES_W1), L may be stored as the leading index (RD HEAD) and M may be stored as the last index (ED TAIL).

[0078] Subsequently, if a read command for the first address is not received, the link field of the second read command in the read ready queue may be set to an invalid value.

[0079] In one embodiment, the address field (START LA, LENGTH), index field (WB INDEX), command attribute field (CMD ATRB), and command identifier field (CMD NO) may be set by the first core (213), and the read command list field (RD HEAD, RD TAIL) may be set by the second core (215). The flag field (FLAG) may be set by the first core (213) and the second core (215).

[0080] FIG. 6 is a drawing for explaining a lead descriptor according to one embodiment.

[0081] Referring to FIG. 6, the read descriptor (DES_Rx) may include a read descriptor identifier field (DES ID), an address field (START LA, LENGTH), a command attribute field (CMD ATRB), a command identifier field (CMD NO), and an index field (RB INDEX).

[0082] The read descriptor identifier field (DES ID) may store the address of the descriptor buffer (DESCRIPTOR BUFFER) where the read descriptor (DES_Rx) is stored.

[0083] The address field (START LA, LENGTH) can store the start logical address (START LA) and length information (LENGTH) associated with the read command.

[0084] The command attribute field (CMD ATRB) can store the type of the command. In the case of a read descriptor (DES_Rx), the command attribute field (CMD ATRB) can store a value indicating that the command is a read command.

[0085] The command identifier field (CMD NO) may store an identifier value to distinguish read commands.

[0086] The index field (RB INDEX) may store second buffering information, which is the address of the write buffer (READ BUFFER) where the read data is stored.

[0087] FIG. 7 is a diagram illustrating a method of writing to a data storage device according to one embodiment.

[0088] When a first write command (CMD_W1) and a first write data (WD1) are received from an external device (100) (①), the first core (213) can queue the received first write command (CMD_W1) in the request queue (2171) of the operation memory (217) (②). The first core (213) can generate a first write descriptor (DES_W1) based on the first write command (CMD_W1) and store the first write descriptor (DES_W1) in the descriptor buffer (DESCRIPTOR BUFFER) of the buffer memory device (220) (②). Additionally, the first core (213) can store the light descriptor identifier (DES ID), which is the storage location of the first light descriptor (DES_W1), by matching it with the first light command (CMD_W1) of the request queue (2171).

[0089] The data transmission block (225) can store the first write data (WD1) received from the external device (100) in the write buffer (WRITE BUFFER) of the buffer memory device (220) according to the control signal (CTRL_IN) provided from the first core (213) (②). The data transmission block (225) may be provided inside the first core (213).

[0090] As the first write data (WD1) is stored in the write buffer, the first core (213) can store first buffering information, which is the address of the write buffer where the first write data (WD1) is stored, in the index field (WB INDEX) of the write descriptor (DES_W1) (WB INDEX='1').

[0091] The first core (213) can set the flag field (FLAG) to the first state (logical 0) to indicate that the first write data (WD1) is being effectively buffered in the write buffer (WRITE BUFFER).

[0092] Meanwhile, the second core (215) can periodically poll the request queue (2171) of the operation memory (217). When the first core (213) queues the first write command (CMD_W1) into the request queue (2171), the second core (215) can dequeue the first write command (CMD_W1) from the request queue (2171) (③). At this time, the first write descriptor identifier (DES ID) for the first write command (CMD_W1) can be read.

[0093] The second core (215) can check that the command dequeued from the request queue (2171) is a write command and access the descriptor buffer (DESCRIPTOR BUFFER) according to the descriptor identifier (DES ID) to read the first write descriptor (DES_W1) (④).

[0094] The second core (215) can interpret the first write descriptor (DES_W1) to convert the logical address to be written into a physical address (⑤). For example, if the start logical address (START LA) and length (LENTH) information stored in the address field of the first write descriptor (DES_W1) are 'LA1' and '6', respectively, the second core (215) can convert 'LA1 to LA6' into corresponding physical addresses (PAs) by sequentially storing 'LA1 to LA6' in the P2L table (P2L Table) of the buffer memory device (220).

[0095] The second core (215) can access the location of the write buffer (WRITE BUFFER) corresponding to the first buffering information (WB INDEX='1') to read the first write data (WD1) (⑥), generate the first program command (PGM_W1), and provide the program command (PGM_W1) and the first write data (WD1) to the storage medium (260) (⑦).

[0096] The second core (215) can release the allocation of the write buffer for the first write data (WD1) immediately after transferring the first write data (WD1) to the storage medium (260) (⑧).

[0097] The second core (215) can set the flag field (FLAG) of the first write descriptor (DES_W1) stored in the descriptor buffer (DESCRIPTOR BUFFER) to a second state (logical 1) to indicate that the first write data (WD1) associated with the first write command (CMD_W1) has been transferred to the storage medium (260) (⑧). The flag of the second state can indicate that the buffer allocation for the first write data (WD1) associated with the first write command has been released, that is, that the data stored at the location corresponding to the first buffering information (WB INDEX='1') has been invalidated.

[0098] The storage medium (260) can program the first write data (WD1) based on the first program command (PGM_W1) received from the second core (215) and provide a response signal (RES_W1) including the result of the program operation to the second core (215) (⑨).

[0099] The second core (215) can queue a response signal (RES_W1) received from the storage medium (260) into the response queue (2173) of the operation memory (291) (⑩). The queued response signal (RES_W1) can be transmitted to an external device (100) through the first core (213) (⑪, ⑫).

[0100] As the light operation is completed, the first core (213) can delete or invalidate the first light descriptor (DES_W1).

[0101] By managing the validity of data stored in the write buffer with a flag, if a read request associated with the address of a currently executing write command is received, the processing of the read command can be deferred until after the write operation is completed based on the flag.

[0102] FIG. 8 is a diagram illustrating a method of operation of a data storage device according to one embodiment.

[0103] When a first read command (CMD_R1) is received from an external device (100) (①), the first core (213) can queue the received first read command (CMD_R1) in the request queue (2171) of the operation memory (217) (②). The first core (213) can generate a first read descriptor (DES_R1) based on the first read command (CMD_R1) and store the first read descriptor (DES_R1) in the descriptor buffer (DESCRIPTOR BUFFER) of the buffer memory device (220) (②). Additionally, the first core (213) can store a read descriptor identifier (DES ID), which is the storage location of the first read descriptor (DES_R1), by matching it with the first read command (CMD_R1) in the request queue (2171).

[0104] The second core (215) can periodically poll the request queue (2171) of the operation memory (217). When the first core (213) queues the first read command (CMD_R1) into the request queue (2171), the second core (215) can dequeue the first read command (CMD_R1) from the request queue (2171) (③). At this time, the read descriptor identifier (DES ID) for the first read command (CMD_R1) can be read.

[0105] The second core (215) can determine that the command dequeued from the request queue (2171) is a read command and access the descriptor buffer (DESCRIPTOR BUFFER) according to the descriptor identifier (DES ID) to read the first read descriptor (DES_R1) (④). The second core (215) can interpret the first read descriptor (DES_R1) to determine whether the logical address to be read is associated with the currently executing write logical address.

[0106] For example, the second core (215) can look up the descriptor buffer (DESCRIPTOR BUFFER) to check if there exists a write descriptor having a logical address that includes at least a portion of the logical address written to the first read descriptor (DES_R1).

[0107] For example, if the start logical address (START LA) and length (LENTH) information stored in the address field of the first read descriptor (DES_R1) are 'LA11' and '6', respectively, the second core (215) can check whether there exists a write descriptor containing at least a portion of the logical addresses 'LA11' to 'LA16'.

[0108] If there is no write descriptor for logical addresses 'LA11' to 'LA16', the second core (215) can obtain physical addresses (PAs) corresponding to read logical addresses from the P2L table (P2L Table) of the buffer memory device (220) (⑤). For example, if the start logical address (START LA) and length (LENTH) information stored in the address field of the first read descriptor (DES_R1) are 'LA11' and '6', respectively, the second core (215) can obtain physical addresses 'PA11' to 'PA16' (PAs) corresponding to 'LA11' to 'LA16' from the P2L table (P2L Table) of the buffer memory device (220).

[0109] The second core (215) can generate a first read command (RD_R1) containing physical addresses (PAs) and provide it to the storage medium (260) (⑥).

[0110] The storage medium (260) can read the first read data (RD1) from a location corresponding to a physical address (PAs) and transmit it to the second core (215) (⑦). The second core (215) can store the first read data (RD1) in a read buffer (READ BUFFER) (⑧) and store the address of the read buffer (READ BUFFER) where the first read data (RD1) is stored, for example, '1', in the index field (RD INDEX) of the first read descriptor (DES_R1) (⑧).

[0111] The data transmission block (225) can read the first read data (RD1) stored in the read buffer (READ BUFFER) according to the control signal (CTRL_OUT) provided from the second core (215) (⑨) and transmit it to the external device (100) (⑩).

[0112] In this way, if a write request for a logical address associated with a read command is not buffered, the data requested to be read can be read from the storage medium (260).

[0113] FIG. 9 is a diagram illustrating a method of operation of a data storage device according to one embodiment.

[0114] When a second read command (CMD_R2) is received from an external device (100) (①), the first core (213) can queue the received second read command (CMD_R2) in the request queue (2171) of the operation memory (217) (②). The first core (213) can generate a second read descriptor (DES_R2) based on the second read command (CMD_R2) and store the second read descriptor (DES_R2) in the descriptor buffer (DESCRIPTOR BUFFER) of the buffer memory device (220) (②). Additionally, the first core (213) can store a read descriptor identifier (DES ID), which is the storage location of the second read descriptor (DES_R2), by matching it with the second read command (CMD_R2) in the request queue (2171).

[0115] The second core (215) can periodically poll the request queue (2171) of the operation memory (217) to dequeue the second read command (CMD_R2) from the request queue (2171) (③). At this time, the read descriptor identifier (DES ID) for the second read command (CMD_R2) can be read.

[0116] The second core (215) can determine that the command dequeued from the request queue (2171) is a read command and access the descriptor buffer (DESCRIPTOR BUFFER) according to the descriptor identifier (DES ID) to read the second read descriptor (DES_R2) (④). The second core (215) can interpret the second read descriptor (DES_R2) to determine whether the logical address to be read is associated with the currently executing write logical address.

[0117] For example, the second core (215) can look up the descriptor buffer (DESCRIPTOR BUFFER) to check if there exists a write descriptor having a logical address that includes at least a portion of the logical address of the second read descriptor (DES_R2).

[0118] For example, if the start logical address (START LA) and length (LENTH) information stored in the address field of the second read descriptor (DES_R2) are 'LA1' and '6', respectively, the second core (215) can check whether there exists a write descriptor containing at least a portion of the logical addresses 'LA1' to 'LA6'.

[0119] When the first write descriptor (DES_W1) is stored in the descriptor buffer (DESCRIPTOR BUFFER) and the start logical address (START LA) and length (LENTH) information stored in the address field of the first write descriptor (DES_W1) are 'LA1' and '6', respectively, the second core (215) can determine that a write operation related to the read logical addresses 'LA1' to 'LA16' is being executed.

[0120] The second core (215) can determine whether the first write data (WD1) is being buffered in the write buffer by checking the flag field (FLAG) of the first write descriptor (DES_W1). For example, if the flag field (FLAG) is set to the first state (logical 0), the second core (215) can determine that the first write data (WD) is being effectively buffered in the write buffer.

[0121] The second core (215) can store the address of the read buffer (READ BUFFER) where the second read data (RD2) is stored in the index field (RD INDEX) of the second read descriptor (DES_R2) without needing to transmit the second read command (CMD_R2) to the storage medium (260), for example, the address where the first write data (WD1) is stored, for example, WB INDEX='1' (⑤).

[0122] The data transmission block (225) can read the second read data (RD2) stored in the write buffer (WRITE BUFFER) according to the control signal (CTRL_OUT) provided from the second core (215) (⑥) and transmit it to the external device (100) (⑦).

[0123] In this way, when the write command and write data for the logical address associated with the read command are buffered, the write data buffered in the buffer memory device (220) can be provided as read data without accessing the storage medium (260).

[0124] FIG. 10 is a diagram illustrating a read operation method of a data storage device according to one embodiment.

[0125] Referring to FIG. 10, when a second read command (CMD_R2) is received from an external device (100) (①), the first core (213) can queue the received second read command (CMD_R2) in the request queue (2171) of the operation memory (217) (②). The first core (213) can generate a second read descriptor (DES_R2) based on the second read command (CMD_R2) and store the second read descriptor (DES_R2) in the descriptor buffer (DESCRIPTOR BUFFER) of the buffer memory device (220) (②). Additionally, the first core (213) can store the read descriptor identifier (DES ID), which is the storage location of the second read descriptor (DES_R2), by matching it with the second read command (CMD_R2) of the request queue (2171).

[0126] The second core (215) can periodically poll the request queue (2171) of the operation memory (217) to dequeue the second read command (CMD_R2) from the request queue (2171) (③). At this time, the read descriptor identifier (DES ID) for the second read command (CMD_R2) can be read.

[0127] The second core (215) can determine that the command dequeued from the request queue (2171) is a read command and access the descriptor buffer (DESCRIPTOR BUFFER) according to the descriptor identifier (DES ID) to read the second read descriptor (DES_R2) (④). The second core (215) can interpret the second read descriptor (DES_R2) to determine whether the logical address to be read is associated with the currently executing write logical address.

[0128] For example, the second core (215) can look up the descriptor buffer (DESCRIPTOR BUFFER) to check if there exists a write descriptor having a logical address that includes at least a portion of the logical address of the second read descriptor (DES_R2).

[0129] For example, if the start logical address (START LA) and length (LENTH) information stored in the address field of the second read descriptor (DES_R2) are 'LA1' and '6', respectively, the second core (215) can check whether there exists a write descriptor containing at least a portion of the logical addresses 'LA1' to 'LA6'.

[0130] When the first write descriptor (DES_W1) is stored in the descriptor buffer (DESCRIPTOR BUFFER) and the start logical address (START LA) and length (LENTH) information stored in the address field of the first write descriptor (DES_W1) are 'LA1' and '6', respectively, the second core (215) can determine that a write operation related to the read logical addresses 'LA1' to 'LA16' is being executed.

[0131] The second core (215) can determine whether the first write data (WD1) is being buffered in the write buffer by checking the flag field (FLAG) of the first write descriptor (DES_W1). For example, if the flag field (FLAG) is set to a second state (logical 1) or has a value (NULL) where the state cannot be determined, the second core (215) can determine that the first write data (WD) is not being buffered in the write buffer (WRITE BUFFER). The flag of the second state can indicate that the first write data (WD1) has been transferred to the storage medium (260), or, from another perspective, that the buffering of the first write data (WD1) has been released.

[0132] When the first write data (WD1) is not buffered in the write buffer, the second core (215) may assign an index to the second read command (CMD_R2) and store it in the read ready queue (2175) of the operation memory (217) to defer processing of the second read command (CMD_R2) (⑤). In one embodiment, the index assigned to the deferred second read command (CMD_R2) may be the address of the read ready queue (2175) where the second read command (CMD_R2) is stored. FIG. 10 illustrates the case where index 3 (IDX3) is assigned to the second read command (CMD_R2).

[0133] Read requests associated with the address of a write request currently in progress may be received sequentially multiple times. The second core (215) may manage the indices of multiple read commands associated with the write request currently in progress as a linked list in the read ready queue (2175).

[0134] If a read command for the same logical address is not received following the second read command (CMD_R2), the link value of the second read command (CMD_R2) stored in the read ready queue (2175) may be an invalid value (INV).

[0135] The second core (215) can store the index of a pending read command associated with the first write command (CMD_W1) currently running as a read command list in the write descriptor (⑥). The read command list may include the leading index and the last index of the pending read command stored as a linked list in the read ready queue (2175). If there is only one pending read command, the same value as the leading index may be stored in the last index of the read command list. Referring to FIG. 10, it can be seen that 3 is stored in the leading index and the last index of the read command list of the first write descriptor (DES_W1).

[0136] A third read command (CMD_RD3) for the same logical address may be received following the second read command (CMD_R2). If the flag field (FLAG) of the first write descriptor (DES_W1) is set to the second state (logical 1) or is a value (NULL) that cannot be verified, the second core (215) may assign an index (e.g., 0) to the third read command (CMD_R3) and store it in the read ready queue (2175) to defer processing of the third read command (CMD_R3). At this time, the link value of the second read command (CMD_R2) stored in the read ready queue (2175) is changed to the index assigned to the third read command (CMD_R3), for example, 0, and the link value of the third read command (CMD_R3) can be set to an invalid value (INV).

[0137] In addition, the last index god of the read command list of the first light descriptor (DES_W1) can be changed from 3 to 0.

[0138] When the processing of the first write command (CMD_W1) is completed, the second core (215) can dequeue the read command stored in the read ready queue (READ READY QUEUE) based on the read command list stored in the write descriptor (⑦) and control the storage medium (260) so that it is processed preferentially over other commands.

[0139] The second core (215) can obtain physical addresses (PAs) corresponding to read logical addresses from the P2L table (P2L Table) of the buffer memory device (220) (⑧). For example, if the start logical address (START LA) and length (LENTH) information stored in the address field of the second read descriptor (DES_R2) are 'LA1' and '6', respectively, physical addresses 'PA11' to 'PA6' (PAs) corresponding to 'LA1 to LA6' can be obtained from the P2L table (P2L Table) of the buffer memory device (220).

[0140] The second core (215) can generate a second read command (RD_R2) containing physical addresses (PAs) and provide it to the storage medium (260) (⑨).

[0141] The storage medium (260) can read the second read data (RD2) from a location corresponding to a physical address (PAs) and transmit it to the second core (215) (⑩). The second core (215) can store the second read data (RD2) in a read buffer (READ BUFFER) and store the address of the read buffer (READ BUFFER) where the second read data (RD2) is stored, for example, '1', in the index field (RD INDEX) of the second read descriptor (DES_R2) (⑪).

[0142] The data transmission block (225) can read (⑫) the second read data (RD2) stored in the read buffer (READ BUFFER) according to the control signal (CTRL_OUT) provided from the second core (215) and transmit it to the external device (100) (⑬).

[0143] Meanwhile, the second read data (RD2) can be shared by the third read command (CMD_RD2) to prevent unnecessary access to the storage medium (260).

[0144] When the pending read command is completed, the second core (215) can release the index assigned to the pending read command.

[0145] In this way, if a write command for a logical address associated with a read command is not buffered, the read command is withheld, and when the processing of the write command is completed, the data requested to be read from the storage medium (260) can be read.

[0146] When operating in a Fire & Forget mode, where the buffer in which the light data is stored is released immediately after the light data buffered in the buffer memory device (220) is flushed to the storage medium (260), the read data can be provided from the buffer memory device (220) or the storage medium (260) by managing whether the light data is buffered or flushed with a flag.

[0147] Therefore, it is possible to ensure consistency between write data and read data while advancing the release time of the buffer memory device during a write operation.

[0148] As such, those skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and their equivalents should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0149] 10: Data Processing System 100 : External device 200 : Data storage device 210: Memory Controller 220: Buffer memory device 260 : Storage medium

Claims

Claim 1 A data storage device comprising: a storage medium; and a memory controller that, when a read address to perform a first read command matches at least partially with a write address of a first write command currently being executed, determines whether to hold the first read command based on a flag set in the first write command, stores the held first read command in a read-ready queue, and controls the command queued in the read-ready queue to be processed after the execution of the first write command is completed; wherein the flag is configured to indicate whether the first write data associated with the first write command has been transferred from a buffer memory device to the storage medium. Claim 2 A data storage device according to claim 1, wherein the memory controller reads the first write data from the buffer memory device and outputs it as read data corresponding to the first read command when the flag is in a first state, and the first state indicates that the first write data is stored in the buffer memory device. Claim 3 A data storage device according to claim 1, wherein the memory controller is configured to read first read data from the storage medium and output it as read data corresponding to the first read command when the flag is in a second state, and the second state is configured to indicate that the first write data is flushed from the buffer memory device to the storage medium. Claim 4 A data storage device according to claim 1, wherein the memory controller is configured to assign an index to the reserved first read command and store the reserved first read command in an area of ​​the read-ready queue corresponding to the index. Claim 5 In claim 4, the memory controller is a data storage device configured to store the index as a read command list in the descriptor of the first write command. Claim 6 In claim 1, the memory controller is a data storage device configured to store the plurality of read commands as a linked list in the read-ready queue when a plurality of read commands, each including a read address that matches at least partially with the write address of the first write command, are received sequentially and held in reserve. Claim 7 In claim 6, the memory controller is a data storage device that assigns an index to each of the plurality of reserved read commands and stores the index as a link value according to the order in which the plurality of reserved read commands are received to form the linked list. Claim 8 In claim 7, the memory controller is configured to store the leading index and the last index of a linked list stored in the read-ready queue in relation to the first write command as a read command list in the descriptor of the first write command. Claim 9 In claim 7, the memory controller executes any one of the plurality of read commands stored in the read-ready queue in relation to the first write command after the processing of the first write command is completed to receive read data from the storage medium, and controls each of the plurality of read commands to share the read data. Claim 10 A memory controller configured to receive a first write command including a first write address and first write data, store the first write data in a buffer memory device and set a flag to a first state, transmit the first write data to a storage medium and then set the flag to a second state, determine whether to hold the first read command based on the flag if the read address associated with the first read command received during the execution of the first write command matches at least partially with the first write address, and store the held first read command in a read-ready queue. Claim 11 A memory controller configured to read the first write data from the buffer memory device and output it as read data corresponding to the first read command when the flag is in the first state according to claim 10. Claim 12 A memory controller configured to read first read data from the storage medium and output read data corresponding to the first read command when the flag is in a second state, in claim 10. Claim 13 A memory controller configured to assign an index to the reserved first read command in claim 10 and to store the reserved first read command in an area of ​​the read-ready queue corresponding to the index. Claim 14 In claim 13, a memory controller configured to store the index as a read command list in the descriptor of the first write command. Claim 15 A memory controller configured such that, in the case where a plurality of read commands including a read address that matches at least partially with the first write address are received sequentially and held, an index is assigned to each of the plurality of read commands, and the index is assigned as a link value according to the order in which the plurality of held read commands are received and stored as a linked list in the read-ready queue. Claim 16 A memory controller configured to store the leading index and the last index of a linked list stored in the read-ready queue in relation to the first write command as a read command list in the descriptor of the first write command. Claim 17 A method of operation of a data storage device, comprising: a step in which a memory controller determines whether to hold a first read command based on a flag set in the first write command when the read address to perform the first read command matches at least partially with the write address of the first write command currently being executed; a step in which the memory controller stores the held first read command in a read-ready queue; and a step in which the controller processes a command queued in the read-ready queue after the execution of the first write command is completed; wherein the flag is configured to indicate whether the first write data associated with the first write command has been transferred from the buffer memory device to the storage medium. Claim 18 A method of operation of a data storage device according to claim 17, further comprising the step of, when the flag is in a first state, the memory controller reading the first write data from the buffer memory device and outputting it as read data corresponding to the first read command, wherein the first state is configured to indicate that the first write data is stored in the buffer memory device. Claim 19 A method of operation of a data storage device according to claim 17, wherein when the flag is in a second state, the memory controller further comprises the step of reading first read data from the storage medium and outputting it as read data corresponding to the first read command, and the second state is configured to indicate that the first write data is in a state of being flushed from the buffer memory device to the storage medium. Claim 20 A method of operation of a data storage device configured to further include, in claim 17, the step of the memory controller assigning an index to the reserved first read command; and the step of storing the reserved first read command in an area of ​​the read-ready queue corresponding to the index. Claim 21 A method of operation of a data storage device configured such that, in claim 20, the memory controller further comprises the step of storing the index as a read command list in the descriptor of the first write command. Claim 22 A method of operation of a data storage device according to claim 17, wherein, when a plurality of read commands including a read address that matches at least partially with the write address of the first write command are sequentially received and held, the memory controller further comprises the step of storing the plurality of read commands as a linked list in the read-ready queue. Claim 23 A method of operation of a data storage device configured such that, in claim 22, the step of storing as a linked list further comprises: a step of assigning an index to each of the plurality of reserved read commands; and a step of constructing the linked list by storing the index as a link value according to the order in which the plurality of reserved read commands are received. Claim 24 A method of operation of a data storage device configured such that, in claim 23, the memory controller further comprises the step of storing the leading index and the last index of a linked list stored in the read-ready queue in relation to the first write command as a read command list in the descriptor of the first write command. Claim 25 A method of operation of a data storage device according to claim 23, further comprising: a step in which, after the processing of the first write command is completed, the memory controller executes any one of the plurality of read commands stored in the read-ready queue in relation to the first write command to receive read data from the storage medium; and a step of controlling each of the plurality of read commands to share the read data.

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