Image sensor

Abstract

An image sensor is provided. The image sensor comprises: a first semiconductor substrate; a second semiconductor substrate on the first semiconductor substrate; a floating diffusion region provided within the first semiconductor substrate; a contact plug provided between the first and second semiconductor substrates and connected to the floating diffusion region; a through plug penetrating the second semiconductor substrate and connected to the contact plug; a pixel transistor provided on the second semiconductor substrate; and an upper connection pattern connecting the through plug and the pixel transistor on the second semiconductor substrate, wherein the upper connection pattern may contact the upper surface of the through plug.

Description

Technology Field

[0001] The present invention relates to an image sensor, and more specifically, to an image sensor with improved electrical and optical characteristics. Background Technology

[0002] Image sensors convert optical images into electrical signals. Recently, with the development of the computer and telecommunications industries, the demand for high-performance image sensors is increasing in various fields such as digital cameras, camcorders, PCS (Personal Communication System), gaming devices, security cameras, and medical micro cameras.

[0003] Image sensors include Charge Coupled Devices (CCDs) and CMOS image sensors. Among these, CMOS image sensors offer a simple driving method and allow for the integration of signal processing circuits onto a single chip, enabling product miniaturization. CMOS image sensors also consume very little power, making them suitable for products with limited battery capacity. Furthermore, CMOS image sensors can utilize compatible CMOS process technologies, which helps reduce manufacturing costs. Consequently, the use of CMOS image sensors is rapidly increasing as technological advancements enable the realization of high resolutions. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide an image sensor having improved electrical and optical characteristics.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] To achieve the above-mentioned problem, an image sensor according to embodiments of the present invention comprises: a first semiconductor substrate; a second semiconductor substrate on the first semiconductor substrate; a floating diffusion region provided within the first semiconductor substrate; a contact plug provided between the first and second semiconductor substrates and connected to the floating diffusion region; a through plug penetrating the second semiconductor substrate and connected to the contact plug; a pixel transistor provided on the second semiconductor substrate; and an upper connection pattern connecting the through plug and the pixel transistor on the second semiconductor substrate, wherein the upper connection pattern may contact the upper surface of the through plug.

[0007] To achieve the above-mentioned problem, an image sensor according to embodiments of the present invention may include: a first semiconductor substrate; a second semiconductor substrate on the first semiconductor substrate; a floating diffusion region provided within the first semiconductor substrate; a lower connection pattern disposed on the first semiconductor substrate and in contact with the floating diffusion region; a contact plug provided between the first and second semiconductor substrates and connected to the lower connection pattern; a through plug penetrating the second semiconductor substrate and connected to the contact plug; a through insulation pattern penetrating the second semiconductor substrate and surrounding the sidewall of the through plug; a source follower gate electrode disposed on the second semiconductor substrate; and an upper connection pattern in contact with the upper surface of the through plug and the upper surface of the source follower gate electrode.

[0008] To achieve the above-mentioned problem, an image sensor according to embodiments of the present invention comprises: a first semiconductor substrate; a second semiconductor substrate on the first semiconductor substrate; a pixel isolation structure disposed within the first semiconductor substrate to define pixel regions; photoelectric conversion regions provided in each of the pixel regions within the first semiconductor substrate; floating diffusion regions provided in each of the pixel regions within the first semiconductor substrate; transmission gate electrodes provided between the photoelectric conversion regions and the floating diffusion regions; a lower connection pattern in contact with the floating diffusion regions of at least two adjacent pixel regions; a contact plug provided between the first and second semiconductor substrates and connected to the lower connection pattern; a through plug penetrating the second semiconductor substrate and connected to the contact plug; a through insulation pattern penetrating the second semiconductor substrate and surrounding the sidewall of the through plug; a pixel transistor provided on the second semiconductor substrate; and an upper connection pattern connecting the through plug and the pixel transistor, wherein the upper connection pattern may contact the upper surface of the through plug.

[0009] To achieve the above-mentioned problem, a method for manufacturing an image sensor according to embodiments of the present invention may include: forming a pixel separation structure defining pixel regions within a first semiconductor substrate; forming floating diffusion regions in each of the pixel regions of the first semiconductor substrate; forming a lower connection pattern in contact with the floating diffusion regions of at least two adjacent pixel regions; forming a lower insulating film covering the first semiconductor substrate; forming a contact plug that penetrates the lower insulating film and is connected to the lower connection pattern; forming a second semiconductor substrate on the lower insulating film; forming a through-insulating pattern that penetrates the second semiconductor substrate and exposes the upper surface of the contact plug; forming a through-plug connected to the contact plug within the through-insulating pattern; forming a pixel transistor on the upper surface of the second semiconductor substrate; and forming an upper connection pattern that contacts the upper surface of the through-plug and is connected to the pixel transistor.

[0010] In the embodiments, forming the through-insulating pattern may include: patterning the second semiconductor substrate to form a through hole that exposes the upper surface of the contact plug; forming an insulating film that covers the inner wall of the through hole with a uniform thickness; and etching back the insulating film to expose a portion of the upper surface of the contact plug.

[0011] In the embodiments, the through-insulation pattern may be made of a low dielectric material having a dielectric constant lower than that of silicon oxide.

[0012] In the embodiments, before forming the contact plug, the method may further include forming a contact hole that penetrates the first interlayer insulating film and exposes a portion of the lower connection pattern; and forming a first doping region within the lower connection pattern by doping the upper surface of the lower connection pattern exposed in the contact hole with an impurity of a first conductivity type.

[0013] In the embodiments, before forming the through plug, it may further include forming a second doping region within the contact plug by doping the upper surface of the contact plug exposed by the through insulation pattern with a first conductivity type impurity.

[0014] In the embodiments, before forming the upper connection pattern, it may further include doping the upper surface of the through plug with a first conductive impurity to form a third doping region within the through plug.

[0015] In the embodiments, prior to forming the through-insulation pattern, the device isolation pattern defining an active portion within the second semiconductor substrate is further formed, and the through-insulation pattern may penetrate a portion of the device isolation pattern.

[0016] In the embodiments, forming the pixel transistor comprises: forming a pixel gate electrode on the active portion of the second semiconductor substrate; and forming source and drain regions within the active portion on both sides of the pixel gate electrode, wherein the upper connection pattern may be in contact with the upper surface of the pixel gate electrode.

[0017] In the embodiments, before forming the lower connection pattern, the method may further include forming photoelectric conversion regions within the first semiconductor substrate in each of the pixel regions; and forming a transmission gate electrode between the floating diffusion region and the photoelectric conversion region in each of the pixel regions.

[0018] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0019] According to embodiments of the present invention, a floating diffusion region provided on a first semiconductor substrate and a pixel transistor provided on a second semiconductor substrate on the first semiconductor substrate can be connected to each other through a contact plug and a through plug. Accordingly, since the through plug can be formed in a form embedded in the second semiconductor substrate, the size of the through plug can be reduced. Therefore, the size of the unit pixel of the image sensor can be further reduced.

[0020] In addition, by forming a connection conductivity pattern connecting the floating diffusion region and the pixel transistor on the second semiconductor substrate, the increase in capacitance and signal delay that occurs when connecting using a metal layer can be prevented, and the conversion gain at the unit pixel can be improved. Furthermore, the wiring freedom of the image sensor can be enhanced. Brief explanation of the drawing

[0021] FIG. 1 is a block diagram showing an image sensor according to embodiments of the present invention. FIGS. 2a and FIGS. 2b are circuit diagrams showing unit pixels of a pixel array according to embodiments of the present invention. FIG. 3 is a schematic plan view of an image sensor according to embodiments of the present invention. Figure 4 is a schematic cross-sectional view of the image sensor shown in Figure 3. Figure 5 is an enlarged view of the P1 portion of Figure 3. FIGS. 6, FIGS. 7, FIGS. 8, and FIGS. 9 are cross-sectional views of an image sensor according to embodiments of the present invention. FIG. 10 is a schematic plan view of an image sensor according to embodiments of the present invention. FIG. 11 is a cross-sectional view schematically showing the image sensor illustrated in FIG. 10. FIG. 12 is a schematic plan view of an image sensor according to embodiments of the present invention. FIG. 13 is a cross-sectional view schematically showing the image sensor illustrated in FIG. 12. FIG. 14 is a schematic cross-sectional view of an image sensor according to embodiments of the present invention. FIGS. 15 to 19 are cross-sectional views illustrating a method for manufacturing an image sensor according to embodiments of the present invention. FIG. 20 is a schematic plan view of an image sensor according to embodiments of the present invention. FIGS. 21 and 22 are cross-sectional views of an image sensor according to embodiments of the present invention, showing a cross-section cut along the line I-I' of FIG. 20. Specific details for implementing the invention

[0022] Hereinafter, an image sensor and a method for manufacturing the same according to embodiments of the present invention will be described in detail with reference to the drawings.

[0023] FIG. 1 is a block diagram showing an image sensor according to embodiments of the present invention.

[0024] Referring to FIG. 1, the image sensor includes a pixel array (1; Pixel array), a row decoder (2), a row driver (3), a column decoder (4), a timing generator (5), a Correlated Double Sampler (CDS; 6), an Analog to Digital Converter (ADC; 7), and an I / O buffer (8).

[0025] The pixel array (1) includes a plurality of unit pixels arranged along rows and columns, and the unit pixels convert incident light into electrical signals. The pixel array (1) can be driven by a plurality of driving signals, such as a selection signal, a reset signal, and a transfer signal, provided by a row decoder (2).

[0026] The row decoder (2) can provide driving signals for each row of unit pixels. Additionally, the electrical signal converted in the pixel array (1) in response to the driving signals is provided to the correlation double sampler (6).

[0027] The row driver (3) provides a plurality of driving signals to the pixel array (1) to drive a plurality of unit pixels according to the result decoded by the row decoder (2). If the unit pixels are arranged in a matrix form, driving signals may be provided for each row.

[0028] The timing generator (5) controls row and column decoders (2, 4), a correlated dual sampler (6), an analog-to-digital converter (7), and an input / output buffer (8), and can supply control signals such as a clock signal and a timing control signal to their operation. The timing generator (5) may include a logic control circuit, a phase lock loop (PLL) circuit, a timing control circuit, and a communication interface circuit.

[0029] The correlated double sampler (CDS; 6) receives, holds, and samples the electrical signal generated from the pixel array (1). The correlated double sampler (6) double-samples the signal level by a specific noise level and the electrical signal, and outputs a difference level corresponding to the difference between the noise level and the signal level.

[0030] The analog-to-digital converter (ADC; 7) converts the analog signal corresponding to the difference level output from the correlated double sampler (6) into a digital signal and outputs it.

[0031] The input / output buffer (8) latches digital signals output from the analog-to-digital converter, and the latched signals are sequentially output to a video signal processing unit (not shown) according to the decoding result in the column decoder (4).

[0032] FIGS. 2a and FIGS. 2b are circuit diagrams showing unit pixels of a pixel array according to embodiments of the present invention.

[0033] Referring to FIG. 2a, a unit pixel (P) may include a photoelectric conversion circuit (10P) and a pixel circuit (20P).

[0034] The photoelectric conversion circuit (10P) may include first, second, third, and fourth photoelectric conversion elements (PD1, PD2, PD3, PD4), first, second, third, and fourth transfer transistors (TX1, TX2, TX3, TX4), and a floating diffusion region (or charge detection node; FD).

[0035] The first to fourth transfer transistors (TX1, TX2, TX3, TX4) can transfer charges accumulated in the first to fourth photoelectric conversion elements (PD1~PD4) to a floating diffusion region (FD). The first to fourth transfer transistors (TX1, TX2, TX3, TX4) can share the floating diffusion region (FD). The transfer gate electrodes of the first to fourth transfer transistors (TX1, TX2, TX3, TX4) can be controlled by the first to fourth transfer signals (TG1, TG2, TG3, TG4).

[0036] In detail, the first to fourth photoelectric conversion elements (PD1 to PD4) can generate and accumulate charges corresponding to incident light. The first and second photoelectric conversion elements (PD1, PD2) may be, for example, a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), and combinations thereof.

[0037] The floating diffusion region (FD) receives and cumulatively stores charges generated from at least one of the first to fourth photodiodes (PD1 to PD4). The source follower transistor (SF) can be controlled according to the amount of photocharges accumulated in the floating diffusion region (FD).

[0038] The pixel circuit (20P) may include a reset transistor (RX), a source follower transistor (SF), and a selection transistor (SEL). In the embodiments, each unit pixel (PX) is disclosed to include three pixel transistors, but the invention is not limited thereto, and the number of pixel transistors in each unit pixel (PX) may vary.

[0039] Specifically, the reset transistor (RX) can periodically reset the charges accumulated in the floating diffusion region (FD) according to a reset signal (RG) applied to the reset gate electrode. Specifically, the source terminal of the reset transistor (RX) can be connected to the floating diffusion region (FD), and the drain terminal is connected to the pixel power supply voltage (VPIX). When the reset transistor (RX) is turned on, the pixel power supply voltage (VPIX) is delivered to the floating diffusion region (FD). Accordingly, the charges accumulated in the floating diffusion region (FD) are discharged, and the floating diffusion region (FD) can be reset.

[0040] The source follower transistor (SF) may be a source follower buffer amplifier that generates a source-drain current in proportion to the amount of charge in the floating diffusion region (FD) input to the source follower gate electrode. The source follower transistor (SF) amplifies the potential change at the charge detection node and outputs the amplified signal to the output line (Vout) through the select transistor (SX). The drain terminal of the source follower transistor (SF) is connected to the pixel power supply voltage (VPIX), and the source terminal of the source follower transistor (SF) may be connected to the drain terminal of the select transistor (SX).

[0041] The select transistor (SX) can select unit pixels (P) to be read row by row. When the select transistor (SX) is turned on by a select signal (SG) applied to the select gate electrode, the electrical signal output to the source electrode of the source follower transistor (SF) can be output to the output line (Vout).

[0042] Referring to FIG. 2b, the unit pixel (P) may include a photoelectric conversion circuit (10P) and a pixel circuit (20P) as described with reference to FIG. 2a, and the photoelectric conversion circuit (10P) may include first to eighth photoelectric conversion elements (PD1 to PD8), first to eighth transfer transistors (TX1 to TX8), and a floating diffusion region (FD).

[0043] The first to eighth transfer transistors (TX1 to TX8) may share a floating diffusion region (FD). The transfer gate electrodes of the first to eighth transfer transistors (TX1 to TX8) may be controlled by the first to eighth transfer signals (TG1 to TG8).

[0044] As previously described with reference to FIG. 2a, the pixel circuit (20P) may include a reset transistor (RX), a source follower transistor (SF), and a select transistor (SX), and may further include a dual conversion gain transistor (DCX).

[0045] A double conversion gain transistor (DCX) can be connected between a reset transistor (RX) and a floating diffusion region (FD). When the reset transistor (RX) and the double conversion gain transistor (DCX) are turned on, the pixel power voltage (VPIX) is transferred to the floating diffusion region (FD). Accordingly, charges accumulated in the floating diffusion region (FD) are discharged, and the floating diffusion region (FD) can be reset.

[0046] A dual-conversion gain transistor (DCX) can be connected between a floating diffusion region (FD) and a reset transistor (RX). The dual-conversion gain transistor (DCX) can vary the conversion gain of a unit pixel (PX) by varying the capacitance of the floating diffusion region (FD) in response to a dual-conversion gain control signal (DCG).

[0047] Specifically, when capturing an image, low-light and high-light light may be incident on the pixel array, and the dual conversion gain transistor (DCX) may be turned on in high-light mode and turned off in low-light mode. Different conversion gains may be provided in high-light mode and low-light mode by the dual conversion gain transistor (DCX).

[0048] When the dual conversion gain transistor (DCX) is turned on, the capacitance of the floating diffusion region (FD) increases, which may reduce the conversion gain, and when the dual conversion gain transistor (DCX) is turned off, the capacitance of the floating diffusion region (FD) decreases, which may increase the conversion gain.

[0049] FIG. 3 is a schematic plan view of an image sensor according to embodiments of the present invention. FIG. 4 is a schematic cross-sectional view of the image sensor shown in FIG. 3. FIG. 5 is an enlarged view of portion P1 of FIG. 3.

[0050] Referring to FIGS. 3 and 4, an image sensor according to embodiments of the present invention may include, from a vertical perspective, a photoelectric conversion circuit layer (10), a pixel circuit layer (20), and a light transmission layer (30).

[0051] The photoelectric conversion circuit layer (10) may be disposed between the pixel circuit layer (20) and the light transmission layer (30) in a vertical view. The photoelectric conversion circuit layer (10) may include a first semiconductor substrate (100), a pixel isolation structure (PIS), a photoelectric conversion region (PD), transmission gate electrodes (TGa~TGd), floating diffusion regions (FDa~FDd), and a first interlayer insulating film (150).

[0052] The first semiconductor substrate (100) may have a first surface (100a; or front) and a second surface (100b; or back) facing each other. The first semiconductor substrate (100) may be a substrate in which a first conductivity type (e.g., p-type) epitaxial layer is formed on a first conductivity type bulk silicon substrate, and may be a substrate in which the bulk silicon substrate is removed during the manufacturing process of an image sensor so that only the p-type epitaxial layer remains. Alternatively, the first semiconductor substrate (100) may be a bulk semiconductor substrate including a well of the first conductivity type.

[0053] The first semiconductor substrate (100) may include a plurality of pixel groups (PG). Each pixel group (PG) may include at least 4, 8, or 16 pixel regions (PR). In each pixel group (PG), the pixel regions (PR) may be arranged in a matrix form along a first direction (D1) and a second direction (D2) that intersect each other. Each pixel region (PR) may be defined by a pixel isolation structure (PIS) provided within the first semiconductor substrate (100).

[0054] A pixel separation structure (PIS) may be disposed within a first semiconductor substrate (100). The pixel separation structure (PIS) may define pixel regions (PR) on the first semiconductor substrate (100). The pixel regions (PR) may be arranged in a matrix form along a first direction (D1) and a second direction (D2).

[0055] The pixel separation structure (PIS) may include first portions (P1) that extend parallel to each other along a first direction (D1) and second portions (P2) that extend parallel to each other along a second direction (D2) across the first portions (P1). The pixel separation structure (PIS) may surround each of the pixel regions (PR) in a planar view.

[0056] For example, the pixel separation structure (PIS) may penetrate the first semiconductor substrate (100). Specifically, the pixel separation structure (PIS) may have a length in a direction perpendicular to the surface of the first semiconductor substrate (100) (i.e., the third direction (D3)), and the length of the pixel separation structure (PIS) may be substantially equal to the vertical thickness of the first semiconductor substrate (100). As another example, the pixel separation structure (PIS) may extend vertically from the first surface (100a) of the first semiconductor substrate (100) to the second surface (100b) and may be spaced apart from the second surface (100b) of the first semiconductor substrate (100).

[0057] The width of the pixel separation structure (PIS) may gradually decrease from the first surface (100a) to the second surface (100b) of the first semiconductor substrate (100). Conversely, the width of the pixel separation structure (PIS) may gradually increase from the first surface (100a) to the second surface (100b) of the first semiconductor substrate (100).

[0058] For example, a pixel isolation structure (PIS) may include a liner insulation pattern (111), a buried pattern (113), and a capping insulation pattern (115). The buried pattern (113) may vertically penetrate a portion of the first semiconductor substrate (100), and the liner insulation pattern (111) may be provided between the buried pattern (113) and the first semiconductor substrate (100). The capping insulation pattern (115) may be placed on the buried pattern (113). The liner insulation pattern (111) and the capping insulation pattern (115) may include at least one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film. The buried pattern (113) may include an undoped polysilicon film or a polysilicon film doped with impurities. The buried pattern (113) may include an air gap or a void. The capping insulation pattern (115) of the pixel isolation structure (PIS) may include the same insulating material as the device isolation film (STI), and in some examples, the boundary between the capping insulation pattern (115) and the device isolation film (STI) may not be observed.

[0059] Photoelectric conversion regions (PDs) may be provided within the first semiconductor substrate (100) in pixel regions (PR). The photoelectric conversion regions (PDs) may generate photocharges in proportion to the intensity of incident light. The photoelectric conversion regions (PDs) may be formed by ion implanting impurities of a second conductivity type opposite to the first conductivity type of the first semiconductor substrate (100) into the first semiconductor substrate (100). Photodiodes may be formed by a junction between the first semiconductor substrate (100) of the first conductivity type and the photoelectric conversion region (PD) of the second conductivity type.

[0060] According to some embodiments, the photoelectric conversion regions (PDs) may have a difference in impurity concentration between a region adjacent to the first surface (100a) and a region adjacent to the second surface (100b) so as to have a potential gradient between the first surface (100a) and the second surface (100b) of the first semiconductor substrate (100). For example, the photoelectric conversion regions (PDs) may include a plurality of vertically stacked impurity regions.

[0061] A device isolation layer (STI) may be disposed adjacent to a first surface (100a) of a first semiconductor substrate (100) in each of the pixel regions (PR). The device isolation layer (STI) may define an active portion on the first surface (100a) of the first semiconductor substrate (100). The device isolation layer (STI) may be provided within a device isolation trench formed by recessing the first surface (100a) of the first semiconductor substrate (100). The device isolation layer (STI) may be made of an insulating material.

[0062] Transmission gate electrodes (TGa, TGb, TGc, or TGd) may be provided in each of the pixel regions (PR). The transmission gate electrodes (TGa to TGd) may be disposed on the first surface (100a) of the first semiconductor substrate (100). The transmission gate electrodes (TGa to TGd) may overlap with the photoelectric conversion regions (PD) in a planar view. The transmission gate electrodes (TGa to TGd) may be disposed within the first semiconductor substrate (100). The transmission gate electrodes (TGa to TGd) may include a lower portion inserted into the first semiconductor substrate (100) and an upper portion connected to the lower portion and protruding over the first surface (100a) of the first semiconductor substrate (100). The lower portion of the transmission gate electrodes (TGa to TGd) may vertically penetrate a portion of the first semiconductor substrate (100). The bottom surface of the transmission gate electrodes (TGa~TGd) may be located at a lower level than the first surface (100a) of the first semiconductor substrate (100). A gate insulating film may be interposed between the transmission gate electrodes (TGa~TGd) and the first semiconductor substrate (100).

[0063] Floating diffusion regions (FDa–FDd) may be provided within the first semiconductor substrate (100) in each of the pixel regions (PR). The floating diffusion regions (FDa–FDd) may be positioned adjacent to the device isolation layer (STI). In each pixel region (PR), the floating diffusion regions (FDa–FDd) may vertically overlap with a portion of the photoelectric conversion region (PD).

[0064] Floating diffusion regions (FDa~FDd) can be formed by doping a dopant of a second conductivity type opposite to that of the first semiconductor substrate (100). For example, the floating diffusion regions (FDa~FDd) may be n-type dopant regions.

[0065] Floating diffusion regions (FDa~FDd) may each include doping regions (DRa, DRb) in contact with the lower connection pattern (ICP1), as shown in FIG. 5. The dopant concentration in the doping regions (DRa, DRb) may be greater than the dopant concentration in the floating diffusion regions (FDa~FDd).

[0066] In each of the pixel regions (PR), a ground impurity region (GR) may be provided within the first semiconductor substrate (100) spaced apart from the transmission gate electrodes (TGa to TGd). The ground impurity region (GR) may vertically overlap with a portion of the photoelectric conversion region (PD). The ground impurity region (GR) may be formed by doping impurities of the same first conductivity type as the first semiconductor substrate (100). For example, the ground impurity region (GR) may be a p-type impurity region. A ground voltage may be applied to the first semiconductor substrate (100) through the ground impurity region (GR).

[0067] According to embodiments, a lower connection pattern (ICP1) may be disposed on a first surface (100a) of a first semiconductor substrate (100) and may be commonly connected to floating diffusion regions (FDa–FDd) provided in at least two adjacent pixel regions (PR). For example, the lower connection pattern (ICP1) may be commonly connected to floating diffusion regions (FDa–FDd) of four adjacent pixel regions (PR). Alternatively, the lower connection pattern (ICP1) may be commonly connected to six, eight, or twelve, or the like, adjacent floating diffusion regions. The lower connection pattern (ICP1) may be in direct contact with the floating diffusion regions (FDa–FDd) of the pixel regions (PR).

[0068] The lower connection pattern (ICP1) may be made of a conductive material. The lower connection pattern (ICP1) may be made of single-crystal silicon or polysilicon doped with a dopant of the second conductivity type. Additionally, the lower connection pattern (ICP1) may include metallic materials such as tungsten, titanium, tantalum, cobalt, etc. In the lower connection pattern (ICP1), the concentration of the dopant of the second conductivity type may be higher than the dopant concentration in the second doping region (FDb) of the floating diffusion regions (FDa to FDd).

[0069] The lower connection pattern (ICP1) can be in direct contact with the upper surface of the device isolation film (STI) and a portion of the upper surface of the pixel isolation structure (PIS). The lower connection pattern (ICP1) may have a first thickness on the first surface (100a) of the first semiconductor substrate (100), and each of the transmission gate electrodes (TGa~TGd) may have a second thickness on the first surface (100a) of the semiconductor substrate (100). Here, the second thickness may be greater than the first thickness.

[0070] Referring to FIG. 5, the bottom surface of the lower connection pattern (ICP1) may be located at a lower level than the top surface of the device isolation film (STI).

[0071] A first interlayer insulating film (150) may cover transmission gate electrodes (TGa~TGd) on a first surface (100a) of a first semiconductor substrate (100). The first interlayer insulating film (150) may include a plurality of stacked insulating films. The first interlayer insulating film (150) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0072] Conductive lines may be provided within the first interlayer insulating film (150). The conductive lines may include metals such as, for example, tungsten, copper, aluminum, or alloys thereof.

[0073] According to embodiments, a contact plug (CP) can be connected to a lower connection pattern (ICP1) by penetrating the first interlayer insulating films (150). The lower connection pattern (ICP1) may include a high-concentration first doping region (DR1) in contact with the contact plug (CP). The first doping region (DR1) may include, for example, a dopant of a second conductivity type (e.g., n-type).

[0074] The contact plug (CP) may include a second doping region (DR2) of high concentration in its upper portion that contacts the through plug (TP). The second doping region (DR2) may include, for example, a dopant of a second conductivity type (e.g., n-type).

[0075] The contact plug (CP) may be made of a conductive material, for example. The lower connection pattern (ICP1) may be made of single-crystal silicon or polysilicon doped with a dopant of the second conductive type. Alternatively, the contact plug (CP) may include a metal such as, for example, tungsten, copper, aluminum, or an alloy thereof.

[0076] According to embodiments, a pixel circuit layer (20) may be disposed on a first interlayer insulating film (150) of a photoelectric conversion circuit layer (10). The pixel circuit layer (20) may include a pixel circuit (20P) of unit pixels (see PX in FIG. 2a and FIG. 2b). The pixel circuit layer (20) may be disposed between the photoelectric conversion circuit layer (10) and the logic circuit layer (40) in a vertical view.

[0077] The pixel circuit layer (20) may include a second semiconductor substrate (200), a through-plug (TP), a through-insulation pattern (221), and pixel transistors. The pixel transistors may include a source follower transistor (see SF in FIG. 2a and 2b), a reset transistor (see RX in FIG. 2a and 2b), a dual conversion gain transistor (see DCX in FIG. 2b), and a select transistor (see SX in FIG. 2a and 2b).

[0078] More specifically, the second semiconductor substrate (200) may have a first surface (200a) and a second surface (200b) facing each other. The second semiconductor substrate (200) may include a semiconductor material of the first conductivity type, for example, silicon, germanium, or silicon-germanium. The second semiconductor substrate (200) may be a bulk substrate or an epitaxial layer.

[0079] The second surface (200b) of the second semiconductor substrate (200) can be in contact with the first interlayer insulating film (150).

[0080] The device isolation pattern (210) may be disposed within the second semiconductor substrate (200) and may define an active part (ACT). The device isolation pattern (210) may be disposed adjacent to the first surface (200a) of the second semiconductor substrate (200). The device isolation pattern (210) may be made of an insulating material. The device isolation pattern (210) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0081] According to the embodiments, a through plug (TP) can be connected to a contact plug (CP) by penetrating a second semiconductor substrate (200).

[0082] A through-plug (TP) can penetrate the second semiconductor substrate (200) in each pixel group (PG). The through-plug (TP) can electrically connect the photoelectric conversion circuits of the photoelectric conversion circuit layer (10) and the pixel transistors of the pixel circuit layer (20), for example, source follower transistors.

[0083] Specifically, the through-plug (TP) can electrically connect the floating diffusion regions (FDa–FDd) of each pixel group (PG) to the gate terminal of the source follower transistor. In one example, the through-plug (TP) is provided to each pixel group (PG), and each pixel group (PG) may include four pixel regions (PR). That is, four pixel regions (PR) may share one through-plug (TP).

[0084] The penetration plug (TP) can penetrate the device isolation pattern (210) of the second semiconductor substrate (200).

[0085] The through plug (TP) may be made of a conductive material, for example. The lower connection pattern (ICP1) may be made of single-crystal silicon or polysilicon doped with a dopant of the second conductive type. Alternatively, the through plug (TP) may include a metal such as, for example, tungsten, copper, aluminum, or an alloy thereof.

[0086] The diameter at the bottom surface of the through plug (TP) may be smaller than the diameter at the top surface of the contact plug (CP).

[0087] The upper surface of the through plug (TP) can substantially co-plane with the first surface (200a) of the second semiconductor substrate. The lower surface of the through plug (TP) can substantially co-plane with the second surface (200b) of the second semiconductor substrate (200).

[0088] Referring to FIG. 5, the through plug (TP) may include a third doping region (DR3) with a high concentration that contacts the upper connection pattern (ICP2). The third doping region (DR3) may include, for example, a dopant of a second conductivity type (e.g., n-type).

[0089] The through-insulation pattern (221) can penetrate the device isolation pattern (210) of the second semiconductor substrate (200). The through-insulation pattern (221) can surround the side wall of the through-plug (TP). That is, the through-insulation pattern (221) can be placed between the through-plug (TP) and the second semiconductor substrate (200). The upper surface of the through-insulation pattern (221) can form a co-plane with the first surface (200a) of the second semiconductor substrate (200), and the lower surface of the through-insulation pattern (221) can form a co-plane with the second surface (200b) of the second semiconductor substrate (200). The through-insulation pattern (221) can contact a portion of the upper surface of the contact plug (CP).

[0090] The through-insulation pattern (221) may be formed, for example, from a low dielectric material having a dielectric constant lower than that of silicon oxide. The through-insulation pattern (221) may have a dielectric constant of about 1.0 to 3.0. The through-insulation pattern (221) may be a silicon oxide containing carbon. The through-insulation pattern (221) may be formed, for example, from an impurity-doped silicon oxide series material or an organic polymer having a low dielectric constant (Low-k). The impurity-doped oxide series material may be, for example, a fluorine-doped oxide (or FSG), a carbon-doped oxide (e.g., SiC, SiCN), HSQ (hydrogen silsesquioxane; SiO:H), MSQ (methyl silsesquioxane; SiO:CH3), or a-SiOC (SiOC:H), etc. By forming the through-insulation pattern (221) with a low dielectric material, the parasitic capacitance between the floating diffusion regions (FDa~FDd) and the pixel transistor (e.g., source follower transistor) can be reduced.

[0091] According to the embodiments, pixel transistors may be provided on the first surface (200a) of the second semiconductor substrate (200). As an example, a source follower transistor (see SF in FIG. 2a, FIG. 2b) may be provided on the active portion (ACT) of the second semiconductor substrate (200).

[0092] In detail, as a gate electrode of a source follower transistor, a pixel gate electrode (PG) may be disposed on an active portion (ACT) of a second semiconductor substrate (200), and source and drain regions may be provided within the active portion (ACT) of the second semiconductor substrate (200) on both sides of the pixel gate electrode (PG). Here, the source and drain regions may be impurity regions doped with impurities of a second conductivity type. A gate spacer made of an insulating material may be provided on the side walls of the pixel gate electrode (PG). The pixel gate electrode (PG) of the source follower transistor may be adjacent to a device isolation pattern (210) and a through-insulation pattern (221).

[0093] According to the embodiments, an upper connection pattern (ICP2) may be disposed on a first surface (200a) of a second semiconductor substrate (200). The upper connection pattern (ICP2) may extend continuously from the upper surface of a through plug (TP) onto the upper surface of a pixel gate electrode (PG). The upper connection pattern (ICP2) may be in direct contact with the upper surface of the through plug (TP) and may be in direct contact with the upper surface of the pixel gate electrode (PG).

[0094] The upper connection pattern (ICP2) may have a substantially uniform thickness and may be in contact with the upper surface of the through-insulation pattern (221) and the upper surface of the device isolation pattern (210). The thickness of the upper connection pattern (ICP2) may be smaller than the thickness of the pixel gate electrode (PG).

[0095] The upper connection pattern (ICP2) may be made of a conductive material. The upper connection pattern (ICP2) may be made of single-crystal silicon or polysilicon doped with a dopant of the second conductive type. Additionally, the upper connection pattern (ICP2) may include metallic materials such as tungsten, titanium, tantalum, cobalt, etc.

[0096] The upper connection pattern (ICP2) can connect the through-plug (TP) and the pixel gate electrode (PG) of the source follower transistor. The upper connection pattern (ICP2) can be in contact with the upper surface of the pixel gate electrode (PG) and the upper surface of the through-plug (TP).

[0097] By connecting the pixel transistor and the floating diffusion regions through the upper connection pattern (ICP2), the capacitance can be reduced by the wiring provided within the second interlayer insulating film (250). Thus, the conversion gain of the unit pixel can be increased, thereby enabling the realization of an image sensor with sharp image quality.

[0098] A second interlayer insulating film (250) may cover pixel transistors on a first surface (200a) of a second semiconductor substrate (200). The second interlayer insulating film (250) may include a plurality of stacked insulating films, and the second interlayer insulating film (250) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0099] A light-transmitting layer (30) may be disposed on a second surface (100b) of a first semiconductor substrate (100). The light-transmitting layer (30) may include a flat insulating film (510), a grating structure (520), color filters (530), and microlenses (540). The light-transmitting layer (30) may collect and filter light incident from the outside and provide it to the photoelectric conversion circuit layer (10).

[0100] A flat insulating film (510) may cover a second surface (100b) of a first semiconductor substrate (100). The flat insulating film (510) may be made of a transparent insulating material and may include a plurality of layers. The flat insulating film (510) may be made of an insulating material having a different refractive index from the first semiconductor substrate (100). The flat insulating film (510) may include a metal oxide and / or silicon oxide.

[0101] A grid structure (520) may be disposed on a flat insulating film (510). The grid structure (520) may have a grid shape in a planar view, similar to a pixel separation structure (PIS). The grid structure (520) may overlap with the pixel separation structure (PIS) in a planar view. That is, the grid structure (520) may include first portions extending in a first direction (D1) and second portions extending in a second direction (D2) across the first portions. The width of the grid structure (520) may be substantially equal to or smaller than the minimum width of the pixel separation structure (PIS).

[0102] The lattice structure (520) may include a conductive pattern and / or a low-refractive index pattern. The light-blocking pattern may include a metallic material such as titanium, tantalum, or tungsten, for example. The low-refractive index pattern may be made of a material having a lower refractive index than the conductive pattern. The low-refractive index pattern may be made of an organic material and may have a refractive index of about 1.1 to 1.3. For example, the lattice structure may be a polymer layer containing silica nanoparticles.

[0103] Color filters (530) may be formed corresponding to pixel areas (PR). Color filters (530) may fill the space defined by the grid structure (520). Depending on the unit pixel, the color filters (530) may include red, green, or blue color filters, or magenta, cyan, or yellow color filters. As another example, some of the color filters (530) may include white color filters or infrared filters.

[0104] Micro-lenses (540) may be placed on color filters (530). Micro-lenses (540) may have a convex shape and a predetermined radius of curvature. Micro-lenses (540) may be formed of a light-transmitting resin. Micro-lenses (540) may be placed on color filters (530) corresponding to each of the pixel regions (PR). As another example, at least one of the micro-lenses (540) may be placed commonly on at least two pixel regions (PR).

[0105] Hereinafter, image sensors according to various embodiments of the present invention will be described. For the sake of brevity, the description of technical features identical to those of the image sensors described earlier with reference to FIGS. 3, 4, and 5 will be omitted, and the differences will be described.

[0106] FIGS. 6, FIGS. 7, FIGS. 8, and FIGS. 9 are cross-sectional views of an image sensor according to embodiments of the present invention.

[0107] Referring to FIG. 6, a contact plug (CP) can be connected to a lower connection pattern (ICP1) within the first interlayer insulating film (150). A conductive pad (PP) may be provided on the upper surface of the contact plug (CP), and a through plug (TP) may be connected to the conductive pad (PP) by penetrating a portion of the second semiconductor substrate (200) and the first interlayer insulating film (150). That is, the bottom surface of the through plug (TP) may be located at a lower level than the second surface (200b) of the second semiconductor substrate (200).

[0108] Referring to FIG. 7, unlike the preceding embodiments, the upper connection pattern may be omitted, and a portion of the pixel gate electrode (PG) may come into direct contact with the through plug (TP) on the first surface (200a) of the second semiconductor substrate (200).

[0109] In detail, a portion of the pixel gate electrode (PG) may overlap with the through plug (TP) and the through insulation pattern (221), and a gate insulating film may be interposed between the first surface (200a) of the second semiconductor substrate and the lower surface of the pixel gate electrode (PG). A portion of the pixel gate electrode (PG) may also come into direct contact with the device isolation pattern (210) and the through insulation pattern (221).

[0110] Referring to FIG. 8, the upper connection pattern (ICP2) can be continuously extended from the upper surface of the pixel gate electrode (PG) to the upper surface of the contact plug (CP).

[0111] In detail, the upper connection pattern (ICP2) may include a first portion (PPa) that vertically penetrates the second semiconductor substrate (200) and a second portion (PPb) disposed on the first surface (200a) of the second semiconductor substrate (200). A penetrating insulation pattern (221) that penetrates the second semiconductor substrate (200) may surround the first portion (PPa) of the upper connection pattern (ICP2).

[0112] The upper connection pattern (ICP2) can directly contact the upper surface of the contact plug (CP) and can directly contact the upper surface of the pixel gate electrode (PG).

[0113] Referring to FIG. 9, the through plug (TP) and the through insulation pattern (221) can penetrate a portion of the second interlayer insulating film (250) provided on the first surface (200a) of the second semiconductor substrate (200).

[0114] Specifically, the upper surface of the through-plug (TP) may be located at a different level from the first surface (200a) of the second semiconductor substrate (200). For example, the upper surface of the through-plug (TP) may be located at a higher level than the upper surface of the through-plug (TP). The upper surface of the through-plug (TP) may be located at substantially the same level as the upper surface of the pixel gate electrode (PG).

[0115] The upper connection pattern (ICP2) has a uniform thickness and can make direct contact with the upper surface of the through plug (TP) and the upper surface of the pixel gate electrode (PG).

[0116] FIG. 10 is a schematic plan view of an image sensor according to embodiments of the present invention. FIG. 11 is a schematic cross-sectional view of the image sensor illustrated in FIG. 10.

[0117] Referring to FIGS. 10 and 11, the image sensor may include, from a vertical perspective, a photoelectric conversion circuit layer (10), a pixel circuit layer (20), and a light transmission layer (30).

[0118] The photoelectric conversion circuit layer (10) may include a first semiconductor substrate (100), a pixel separation structure (PIS), a photoelectric conversion region (PD), transmission gate electrodes (TGa~TGd), floating diffusion regions (FDa~FDd), a lower connection pattern (ICP1), and a first interlayer insulating film (150).

[0119] The pixel circuit layer (20) may include a second semiconductor substrate (200), a through-plug (TP), a through-insulation pattern (221), and pixel transistors. As an example, a reset transistor (RX in FIG. 2a and FIG. 2b) and a select transistor (SX in FIG. 2a and FIG. 2b) may be provided on a first surface (200a) of the second semiconductor substrate (200).

[0120] In detail, a device isolation pattern (210) defining an active portion (ACT) within the second semiconductor substrate (200) may be provided, and first and second pixel gate electrodes (PG1, PG2) may be spaced apart from each other on the active portion (ACT).

[0121] Source and drain regions (SDR) may be provided within the active portion (ACT) of the second semiconductor substrate (200) on both sides of the first and second pixel gate electrodes (PG1, PG2). Here, the source and drain regions (SDR) may be impurity regions doped with impurities of the second conductivity type.

[0122] In the embodiments, the upper connection pattern (ICP2) may extend from the upper surface of the through plug (TP) to the upper surface of one of the source and drain regions (SDR). That is, the upper connection pattern (ICP2) may directly connect the through plug (TP) and one of the source and drain regions (SDR). In other words, the upper connection pattern (ICP2) may directly contact the upper surface of the through plug (TP) and the upper surface of one of the source and drain regions (SDR).

[0123] FIG. 12 is a schematic plan view of an image sensor according to embodiments of the present invention. FIG. 13 is a schematic cross-sectional view of the image sensor illustrated in FIG. 12.

[0124] Referring to FIGS. 12 and 13, in each of the pixel regions (PR), a ground impurity region (GR) may be provided within the first semiconductor substrate (100) spaced apart from the transmission gate electrodes (TGa to TGd). The ground impurity region (GR) may be formed by doping with an impurity of the same first conductivity type as the first semiconductor substrate (100). For example, the ground impurity region (GR) may be a p-type impurity region. A ground voltage may be applied to the first semiconductor substrate (100) through the ground impurity region (GR). The ground impurity regions (GR) of the pixel regions (PR) may be arranged adjacent to each other.

[0125] The lower connection pattern (ICP1) can be commonly connected to adjacent ground impurity regions (GR). The lower connection pattern (ICP1) can be in direct contact with the ground impurity regions (GR).

[0126] A contact plug (CP) can penetrate the first interlayer insulating film (150) and be connected to the lower connection pattern (ICP1).

[0127] A device isolation pattern (210) defining an active portion (ACT) may be disposed within the second semiconductor substrate (200). As an example, a ground impurity region (GR) doped with an impurity of the first conductivity type may be provided within the active portion (ACT) of the second semiconductor substrate (200).

[0128] A through plug (TP) can penetrate the second semiconductor substrate (200) and be connected to a contact plug (CP), and an upper connection pattern (ICP2) can extend from the upper surface of the through plug (TP) onto the upper surface of a ground impurity region (GR) within the second semiconductor substrate (200). The upper connection pattern (ICP2) can be in direct contact with the upper surface of the through plug (TP) and the upper surface of the ground impurity region (GR).

[0129] According to an embodiment, a ground impurity region (GR) in a second semiconductor substrate (200) can be electrically connected to ground impurity regions (GR) in a first semiconductor substrate (100) through an upper connection pattern (ICP2), a through plug (TP), a contact plug (CP), and a lower connection pattern (ICP1).

[0130] FIG. 14 is a schematic cross-sectional view of an image sensor according to embodiments of the present invention.

[0131] Referring to FIG. 14, an image sensor according to embodiments of the present invention may include a photoelectric conversion circuit layer (10), a pixel circuit layer (20), a light transmission layer (30), and a logic circuit layer (40).

[0132] The photoelectric conversion circuit layer (10), pixel circuit layer (20), and light transmission layer (30) may include substantially the same technical features as the embodiments described above with reference to FIGS. 3 and FIGS. 4. The pixel circuit layer (20) may further include first bonding pads (BP1) provided on the top metal layer in addition to the configuration of the preceding embodiments. The first bonding pads (BP1) may be disposed within the top layer of the first interlayer insulating film (150). The first bonding pads (BP1) may include, for example, at least one of tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0133] The upper surfaces of the first bonding pads (BP1) can be substantially co-planar with the upper surface of the first interlayer insulating film (150). The first bonding pads (BP1) can be electrically connected to pixel transistors through contact plugs and metal wiring.

[0134] The logic circuit layer (40) can be bonded to the pixel circuit layer (20). The logic circuit layer (40) may include logic circuits (see 2, 3, 4, 5, 6, 7, 8 in FIG. 1), a power circuit, an input / output interface, and / or an image signal processor, etc. That is, the logic circuit layer (40) may include components other than the pixel array (1) in the image sensor of FIG. 1.

[0135] In detail, the logic circuit layer (40) may include a third semiconductor substrate (300), logic circuits (LC), a logic interlayer insulating film (350) covering the logic circuits (LC), and logic wiring (311) connected to the logic circuits (LC). The logic interlayer insulating film (350) may include a plurality of stacked insulating films.

[0136] Second bonding pads (BP2) may be provided within the uppermost layer of the logic interlayer insulating film (350), and the upper surfaces of the second bonding pads (BP2) may substantially co-plane with the uppermost surface of the logic interlayer insulating film (350). The second bonding pads (BP1) may include, for example, at least one of tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0137] The first bonding pads (BP1) and the second bonding pads (BP2) can be directly electrically connected to each other in a hybrid bonding manner. In other words, the top surface of the logic interlayer insulating film (350) can be bonded to the second interlayer insulating film (250) of the pixel circuit layer (20). The second bonding pads (BP1) can be bonded to the first bonding pads (BP1) of the pixel circuit layer (20).

[0138] By directly bonding the first and second bonding pads (BP1, BP2) to each other, the photoelectric conversion circuit layer (10) and the pixel circuit layer (20) can be electrically connected to the logic circuit layer (40).

[0139] FIGS. 15 to 19 are cross-sectional views illustrating a method for manufacturing an image sensor according to embodiments of the present invention.

[0140] Referring to FIG. 15, a first semiconductor substrate (100) of a first conductivity type (e.g., p-type) may be provided. As an example, the first semiconductor substrate (100) may include an epitaxial layer. The first semiconductor substrate (100) may have a first surface (100a) and a second surface (100b) facing each other.

[0141] In contrast, the first semiconductor substrate (100) may be a bulk semiconductor substrate containing a well of the first conductivity type. As another example, the first semiconductor substrate (100) may be a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, or a silicon-germanium substrate.

[0142] In each pixel region (PR), a device isolation layer (STI) may be formed adjacent to the first surface (100a) of the first semiconductor substrate (100) and defining active regions on the first semiconductor substrate (100). The device isolation layer (STI) may include patterning the first surface (100a) of the first semiconductor substrate (100) to form a shallow first trench, forming a liner insulating layer that conformally covers the inner wall of the first trench, and forming an insulating layer that fills the first trench where the liner insulating layer is formed. Forming the device isolation layer (STI) may be formed before or after forming the photoelectric conversion regions (PD).

[0143] A pixel isolation structure (PIS) defining pixel regions (PR) may be formed on a first semiconductor substrate (100). Forming the pixel isolation structure (PIS) may include patterning a first surface (100a) of the first semiconductor substrate (100) to form a second trench, forming a liner insulating film that conformally covers the inner wall of the second trench, depositing a semiconductor film to fill the second trench where the liner insulating film is formed, and flattening the liner insulating film and the buried pattern (113) so that the first surface (100a) of the first semiconductor substrate (100) is exposed to form a liner insulating pattern (111), a buried pattern (113), and a capping insulating pattern (115) within the second trench.

[0144] The liner insulation pattern (111) and the capping insulation pattern (115) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The buried pattern (113) may include an impurity-doped polysilicon film and / or an undoped polysilicon film.

[0145] Next, photoelectric conversion regions (PD) can be provided in each of the pixel regions (PR) within the first semiconductor substrate (100).

[0146] In the pixel regions (PR), photoelectric conversion regions (PD) may be formed by doping impurities of a second conductivity type (e.g., n-type) different from the first conductivity type within the first semiconductor substrate (100). The photoelectric conversion regions (PD) may be spaced apart from the first surface (100a) and the second surface (100b) of the semiconductor substrate (100). The photoelectric conversion regions (PD) may be formed before or after forming the pixel isolation structure (PIS).

[0147] Subsequently, transmission gate electrodes (TGa to TGd) may be formed on the first semiconductor substrate (100) of the pixel regions (PR). Forming the transmission gate electrodes (TGa to TGd) includes patterning the first surface (100a) of the first semiconductor substrate (100) to form a gate recess region in each of the pixel regions (PR), forming a gate insulating film that conformally covers the inner wall of the gate recess region, forming a gate conductive film that fills the gate recess region, and patterning the gate conductive film. In the embodiments, each of the transmission gate electrodes (TGa to TGd) may include two vertical portions disposed within the first semiconductor substrate (100).

[0148] The gate insulating film may include a silicon oxide film, a silicon oxynitride film, or a silicon nitride film. The gate insulating film (GIL) may be formed by performing a deposition process to conformally cover the inner wall of the vertical trench (VT).

[0149] The transmission gate electrodes (TGa~TGd) can be formed by forming a gate conductive film that fills a vertical trench in which a gate insulating film is formed, and then patterning the gate conductive film. The gate conductive film may include a doft polysilicon film, a metal silicide film, a conductive metal nitride film, or a metal film.

[0150] After forming the transmission gate electrodes (TGa~TGd), floating diffusion regions (FDa~FDd) may be formed within the first semiconductor substrate (100) on one side of the transmission gate electrodes (TGa~TGd). The floating diffusion regions (FDa~FDd) may be formed by ion implanting impurities of the second conductivity type using an ion implantation mask.

[0151] Next, a lower connection pattern (ICP1) connecting adjacent floating diffusion regions (FDa~FDd) can be formed on the first surface (100a) of the first semiconductor substrate (100).

[0152] Forming a lower connection pattern (ICP1) may include depositing a spacer insulating film covering the first surface (100a) of the first semiconductor substrate (100) and the sidewalls and upper surfaces of the transmission gate electrodes (TGa~TGd), patterning the spacer insulating film to expose the upper surfaces of the floating diffusion regions (FDa~FDd), depositing a conductive film on the floating diffusion regions (FDa~FDd) and the spacer insulating film, patterning the conductive film, and anisotropically etching the spacer insulating film.

[0154] A first interlayer insulating film (150) covering transmission gate electrodes (TGa~TGd) and a lower connection pattern (ICP1) can be formed on a first surface (100a) of a first semiconductor substrate (100).

[0155] The first interlayer insulating film (150) may include a plurality of stacked insulating films. The first interlayer insulating film (150) may include, for example, at least one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film. The first interlayer insulating film (150) may be formed using at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) techniques.

[0156] Subsequently, a contact plug (CP) may be formed that penetrates the first semiconductor substrate (100) and connects to the lower connection pattern (ICP1). Forming the contact plug (CP) may include patterning the first interlayer insulating film (150) to form a contact hole that exposes a part of the lower connection pattern (ICP1), depositing a conductive film that fills the contact hole, and performing a planarization process so that the upper surface of the first interlayer insulating film (150) is exposed.

[0157] Referring to FIG. 16, a second semiconductor substrate (200) may be bonded to a first interlayer insulating film (150) of a first semiconductor substrate (100). The second semiconductor substrate (200) may have a first surface (200a) and a second surface (200b) facing each other, and the second surface (200b) may be in contact with the upper surface of the first interlayer insulating film (150). The second semiconductor substrate (200) may be a bulk silicon substrate or a substrate on which an epitaxial layer is formed on a bulk silicon substrate.

[0158] A device isolation pattern (210) defining an active part (ACT) may be formed within parts of the second semiconductor substrate (200). The device isolation pattern (210) may include, for example, at least one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.

[0159] Forming the device isolation pattern (210) may include patterning the first surface (200a) of the second semiconductor substrate (200) to form a trench defining an active portion (ACT), depositing an insulating film to fill the trench, and performing a planarization process so that the first surface (200a) of the second semiconductor substrate (200) is exposed. Accordingly, the upper surface of the device isolation pattern (210) may substantially co-plane with the upper surface of the second semiconductor substrate (200).

[0160] The active portion (ACT) corresponds to parts of the second semiconductor substrate (200) and may be single-crystal silicon. The active portion (ACT) may overlap with parts of the photoelectric conversion regions (PD) and parts of the pixel separation structure (PIS) in a planar view. The active portion (ACT) may have a rectangular or bar shape.

[0161] After forming the active portion (ACT), a buffer mask pattern (215) can be formed on the first surface (200a) of the second semiconductor substrate (200).

[0162] Next, a through hole (TH) can be formed by anisotropically etching the second semiconductor substrate (200) using the buffer mask pattern (215) as an etching mask. The through hole (TH) can penetrate the second semiconductor substrate (200) to expose a contact plug (CP).

[0163] Referring to FIG. 17, a spacer insulating film (220) can be deposited on the first surface (200a) of the second semiconductor substrate (200) with a uniform thickness covering the inner wall of the through hole (TH).

[0164] The deposition thickness of the spacer insulating film (220) may be smaller than about 1 / 2 of the diameter of the through hole (TH). The spacer insulating film (220) may define a gap region within the through hole (TH).

[0165] Referring to FIG. 18, an etch-back process can be performed on the spacer insulating film (220) to form a through-insulating pattern (221) within the through-hole (TH). By forming the through-insulating pattern (221), the first surface (200a) of the second semiconductor substrate (200) and the upper surface of the contact plug (CP) can be exposed.

[0166] For example, before forming the through-insulation pattern (221), impurities may be doped into the contact plug (CP) exposed in the through-hole (TH) to form a doped area on the upper part of the contact plug (CP).

[0167] Subsequently, after depositing a conductive film that fills the through hole (TH) in which the through insulation pattern (221) is formed, a planarization process is performed so that the first surface (200a) of the second semiconductor substrate (200) is exposed, thereby forming a through plug (TP).

[0168] The through plug (TP) may comprise, for example, an impurity-doped polysilicon film, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof.

[0169] Referring to FIG. 19, a pixel gate electrode (PG) can be formed by interposing a gate insulating film on an active part (ACT). After forming the pixel gate electrode (PG), source / drain regions (SDR) can be formed within the active part (ACT) on both sides of each pixel gate electrode (PG). The pixel gate electrode (PG) can be positioned adjacent to a through-insulating pattern (221).

[0170] The pixel gate electrode (PG) may include, for example, a high melting point metal film such as cobalt, titanium, nickel, tungsten, and molybdenum and / or a metal nitride film such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and tungsten nitride (WN).

[0171] Subsequently, after forming gate spacers on the side walls of the pixel gate electrode (PG), an upper connection pattern (ICP2) connecting the through plug (TP) and the pixel gate electrode (PG) can be formed. The gate spacers can be formed of an insulating material, and the upper connection pattern (ICP2) can be made of a conductive material.

[0172] The upper connection pattern (ICP2) can be formed by depositing a conductive film on the first surface (200a) of the second semiconductor substrate (200) and the pixel gate electrode (PG), and then patterning the conductive film.

[0173] For example, before forming the upper connection pattern (ICP2), impurities may be doped onto the upper surface of the through plug (TP) to form a doped region on the upper part of the through plug (TP).

[0174] Subsequently, a thinning process can be performed to remove a portion of the first semiconductor substrate (100) in order to reduce the vertical thickness of the first semiconductor substrate (100). The thinning process includes grinding or polishing the second surface (100b) of the first semiconductor substrate (100) and performing anisotropic and isotropic etching. To thin the first semiconductor substrate (100), the top and bottom of the first semiconductor substrate (100) may be inverted. By the grinding or polishing process, the bulk silicon substrate of the first semiconductor substrate (100) may be removed, and the epitaxial layer may be exposed. Subsequently, anisotropic or isotropic etching process may be performed to remove surface defects present on the exposed surface of the epitaxial layer.

[0175] A buried pattern (113) of a pixel isolation structure (PIS) can be exposed on a second surface (100b) of the first semiconductor substrate (100) by a thin film process on the first semiconductor substrate (100). The surface of the buried pattern (113) and the surface of the liner insulation pattern (111) can be located at substantially the same level as the second surface (100b) of the first semiconductor substrate (100).

[0176] Next, as illustrated in FIG. 4, a flat insulating film (510) may be formed on a second surface (100b) of a first semiconductor substrate (100). The flat insulating film (510) may cover the second surface (100b) of the first semiconductor substrate (100). The flat insulating film (510) may be formed by depositing a metal oxide, such as aluminum oxide and / or hafnium oxide.

[0177] Subsequently, a grid structure (520), color filters (530), and micro lenses (540) can be formed on the flat insulating film (510).

[0178] FIG. 20 is a schematic plan view of an image sensor according to embodiments of the present invention. FIG. 21 and FIG. 22 are cross-sectional views of an image sensor according to embodiments of the present invention, showing a cross-section cut along the line I-I' of FIG. 20.

[0179] Referring to FIGS. 20 and 21, the image sensor may include a pixel array region (R1) and a pad region (R2). The pixel array region (R1) may include a plurality of unit pixels (P) arranged two-dimensionally along a first direction (D1) and a second direction (D2) that intersect each other. Each of the unit pixels (PX) may include a photoelectric conversion element and a readout element. An electrical signal generated by incident light may be output from each of the unit pixels (P) of the pixel array region (R1).

[0180] In the light receiving area (AR), the image sensor may include the same technical features as the image sensor described above. That is, the image sensor may include a photoelectric conversion circuit layer (10), a pixel circuit layer (20), a light transmission layer (30), and a logic circuit layer (40), as described above. In a vertical view, the pixel circuit layer (20) may be positioned between the photoelectric conversion circuit layer (10) and the light transmission layer (30), and the pixel circuit layer (20) may be adjacent to the logic circuit layer (40).

[0181] A pixel isolation structure (PIS) within the first semiconductor substrate (100) can define pixel regions in a light-receiving region (AR) and a light-blocking region (OB). A portion of the pixel isolation structure (PIS), for example, a buried pattern (113), can be electrically connected to a rear contact plug (521) in the light-blocking region (OB).

[0182] The flat insulating film (510) of the light-transmitting layer (30) can be extended from the light-receiving region (AR) to the light-blocking region (OB) and the pad region (R2).

[0183] In the light-shielding region (OB), a light-shielding pattern (OBP) may be placed on the flat insulating film (510). The light-shielding pattern (OBP) may block light from being incident on the photoelectric conversion regions (PD) provided in the light-shielding region (OB).

[0184] The light-transmitting layer (30) may include a light-blocking pattern (OBP), a filtering film (335), and an organic film (345) in the light-blocking region (OB). In embodiments, the pixel separation structure (PIS) may extend continuously from the light-receiving region (AR) to the light-blocking region (OB).

[0185] The light-blocking area (OB) can surround the light-receiving area (AR) from a planar perspective. In other words, the light-blocking area (OB) can be positioned above, below, and to the left and right of the light-receiving area (AR) from a planar perspective. Reference pixels are provided in the light-blocking area (OB) where light is not incident, and the electrical signal magnitude detected in the unit pixels (P) can be calculated by comparing the charge amount sensed in the unit pixels (P) of the light-receiving area (AR) with the reference charge amount generated in the reference pixels (P).

[0186] The pixel separation structure (PIS) can define pixel regions in the light-receiving region (AR) and the light-blocking region (OB), and the pixel separation structure (PIS) can have substantially the same structure in the light-receiving region (AR) and the light-blocking region (OB).

[0187] A pixel isolation structure (PIS) may be disposed within a first semiconductor substrate (100) in a light-shielding area (OB). A buried pattern (113) of the pixel isolation structure (PIS) may be electrically connected to a back contact plug (PLG) in the light-shielding area (OB). A predetermined bias may be applied to the buried pattern (113) through the back contact plug (521). The back contact plug (521) may have a width greater than the width of the pixel isolation structure (PIS). The back contact plug (521) may include a metal and / or a metal nitride. For example, the back contact plug (521) may include titanium and / or a titanium nitride.

[0188] A rear contact plug (521) may be provided on the second surface (100b) of the light-shielding region (OB) of the first semiconductor substrate (100). A contact trench may be formed on the second surface (100b) of the first semiconductor substrate (100), and the rear contact plug (521) may be provided within the contact trench.

[0189] A contact pattern (522) may be embedded within a contact hole in which a rear contact plug (521) is formed. The contact pattern (522) may contain a material different from that of the rear contact plug (521). For example, the contact pattern (522) may contain aluminum (Al).

[0190] The contact pattern (522) and the rear contact plug (521) can be electrically connected to the embedded pattern (113) of the pixel isolation structure (PIS). A negative bias can be applied to the embedded pattern (113) of the pixel isolation structure (PIS) through the contact pattern (CT), and the negative bias can be transferred from the light-blocking region (OB) to the light-receiving region (AR). Accordingly, the dark current generated at the interface between the pixel isolation structure (PIS) and the semiconductor substrate (100) can be reduced.

[0191] In the light-shielding area (OB), a light-shielding pattern (OBP) may be placed on a flat insulating film (510). The light-shielding pattern (OBP) may block light from being incident on photoelectric conversion areas (PD) provided in the light-shielding area (OB). In reference pixel areas (PR) of the light-shielding area (OB), the photoelectric conversion areas (PD) may not output a photoelectric signal but may output a noise signal. The noise signal may be generated by electrons produced by heat generation or dark current, etc. The light-shielding pattern (OBP) may include a metal such as, for example, tungsten, copper, aluminum, or an alloy thereof.

[0192] A filtering film (535) may be provided on the light-blocking pattern (OBP). The filtering film (545) may block light of a different wavelength than that of the color filters (530). For example, the filtering film (535) may block infrared light. The filtering film (545) may include a blue color filter, but is not limited thereto.

[0193] An organic film (345) and a passivation film (555) may be provided on the protective film in the light-blocking area (OB) and the pad area (R2). The organic film (345) may contain the same material as the microlenses (340).

[0194] The logic circuit layer (40) can be electrically connected to the photoelectric conversion circuit layer (10) through the first through-conduction pattern (523) and the second through-conduction pattern (525). The logic circuit layer (40) may include a power circuit, an input / output interface, and an image signal processor, etc. The logic circuit layer (40) can be electrically connected to the photoelectric conversion circuit layer (10) through the first through-conduction pattern (523) and the second through-conduction pattern (525).

[0195] In detail, in the light-blocking area (OB), the first through-conduction pattern (523) can penetrate the first semiconductor substrate (100) and be electrically connected to the conduction lines (ML) of the pixel circuit layer (20) and the wiring structure of the logic circuit layer (40). The first through-conduction pattern (523) may have a first bottom surface and a second bottom surface located at different levels. A first embedded pattern (524) may be provided inside the first through-conduction pattern (523). The first embedded pattern (524) may include a low-refractive index material and may have insulating properties.

[0196] In the pad area (R2), a plurality of conductive pads (PADs) used for inputting and outputting control signals and photoelectric signals, etc., on the second surface (100b) of the first semiconductor substrate (100) may be disposed. The pad area (R2) may surround the pixel array area (R1) in a planar view to facilitate electrical connection with external devices. The conductive pads (PADs) can input and output electrical signals generated from unit pixels (P) to an external device.

[0197] In the pad region (R2), conductive pads (PADs) may be embedded within the second surface (100b) of the first semiconductor substrate (100). For example, the conductive pads (PADs) may be provided within a pad trench formed on the second surface (100b) of the first semiconductor substrate (100) in the pad region (R2). The conductive pads (PADs) may include a metal such as aluminum, copper, tungsten, titanium, tantalum, or an alloy thereof. In the mounting process of the image sensor, a bonding wire may be bonded to the conductive pads (PADs). The conductive pads (PADs) may be electrically connected to an external device through the bonding wire.

[0198] In the pad area (R2), a second through-conduction pattern (525) can penetrate the first semiconductor substrate (100) and be electrically connected to the logic wiring (311) of the logic circuit layer (40). The second through-conduction pattern (525) can extend onto the second surface (100b) of the first semiconductor substrate (100) and be electrically connected to the conductive pads (PAD). A portion of the second through-conduction pattern (525) can cover the bottom surface and side wall of the conductive pads (PAD). A second embedded pattern (526) can be provided inside the second through-conduction pattern (525). The second embedded pattern (526) may include a low-refractive index material and may have insulating properties. In the pad area (R2), a pixel isolation structure (PIS) can be provided around the second through-conduction pattern (525).

[0199] In one example, the pixel circuit layer (20) and the logic circuit layer (40) are described as being electrically connected to each other through first and second through-conduction patterns (523, 525), but the present invention is not limited thereto.

[0200] According to the embodiment illustrated in FIG. 22, the first and second through-conduction patterns (523, 525) illustrated in FIG. 21 may be omitted, and the pixel circuit layer (20) and the logic circuit layer (40) may be electrically connected by directly bonding the bonding pads (BP1, BP2) provided on the uppermost metal layer of the pixel circuit layer (20) and the logic circuit layer (40) to each other.

[0201] In detail, the pixel circuit layer (201) of the image sensor may include first bonding pads (BP1) provided on the uppermost metal layer, and the logic circuit layer (40) may include second bonding pads (BP2) provided on the uppermost metal layer among the logic conductive lines (1111). The first and second bonding pads (BP1, BP2) may include, for example, at least one of tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0202] The first bonding pads (BP1) of the pixel circuit layer (20) and the second bonding pads (BP2) of the logic circuit layer (40) can be directly electrically connected to each other by a hybrid bonding method. Hybrid bonding refers to a bonding in which two components containing the same material fuse at their interface. For example, if the first and second bonding pads (BP1, BP2) are made of copper (Cu), they can be physically and electrically connected by copper (Cu)-copper (Cu) bonding. Additionally, the surface of the second interlayer insulating film (250) of the pixel circuit layer (20) and the surface of the third interlayer insulating film (1100) of the logic circuit layer (40) can be joined by dielectric-dielectric bonding.

[0203] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 An image sensor comprising: a first semiconductor substrate; a second semiconductor substrate on the first semiconductor substrate; a floating diffusion region provided within the first semiconductor substrate; a contact plug provided between the first and second semiconductor substrates and connected to the floating diffusion region; a through plug penetrating the second semiconductor substrate and connected to the contact plug; a pixel transistor provided on the second semiconductor substrate; and an upper connection pattern connecting the through plug and the pixel transistor on the second semiconductor substrate, wherein the upper connection pattern contacts the upper surface of the through plug. Claim 2 An image sensor according to claim 1, further comprising a through-insulating pattern that penetrates the second semiconductor substrate and surrounds the sidewall of the through-plug. Claim 3 In claim 2, the through-insulation pattern is an image sensor made of a low dielectric material having a dielectric constant lower than that of silicon oxide. Claim 4 In claim 2, an image sensor in which a portion of the upper surface of the contact plug contacts the through-insulation pattern. Claim 5 In claim 1, the pixel transistor comprises a pixel gate electrode disposed on an active portion defined on the second semiconductor substrate, wherein the upper connection pattern is in contact with the upper surface of the through plug and the upper surface of the pixel gate electrode. Claim 6 In claim 1, the pixel transistor comprises a pixel gate electrode disposed on an active portion defined on the second semiconductor substrate and source / drain regions on both sides of the pixel gate electrode, wherein the upper connection pattern contacts the upper surface of the through plug and the upper surface of one of the source / drain regions. Claim 7 An image sensor according to claim 1, wherein the upper surface of the through plug is substantially co-plane with the upper surface of the second semiconductor substrate, and the lower surface of the through plug is substantially co-plane with the lower surface of the second semiconductor substrate. Claim 8 An image sensor according to claim 1, wherein the contact plug comprises a first conductivity type doped polysilicon, and the contact plug comprises a first conductivity type first doping region in contact with the lower surface of the through plug. Claim 9 An image sensor according to claim 1, wherein the through plug comprises a first conductivity type doped polysilicon, and the through plug comprises a second doping region of the first conductivity type in contact with the upper connection pattern. Claim 10 An image sensor comprising: a first semiconductor substrate; a second semiconductor substrate on the first semiconductor substrate; a floating diffusion region provided within the first semiconductor substrate; a lower connection pattern disposed on the first semiconductor substrate and in contact with the floating diffusion region; a contact plug provided between the first and second semiconductor substrates and connected to the lower connection pattern; a through plug penetrating the second semiconductor substrate and connected to the contact plug; a through insulation pattern penetrating the second semiconductor substrate and surrounding the sidewall of the through plug; a source follower gate electrode disposed on the second semiconductor substrate; and an upper connection pattern in contact with the upper surface of the through plug and the upper surface of the source follower gate electrode.

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