Semiconductor device

Abstract

The present disclosure may provide a semiconductor device with improved integration density. The semiconductor device comprises a plurality of upper sheet patterns spaced apart in a first direction on a first isolation insulating layer, a first gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of upper sheet patterns, a second gate electrode spaced apart from the first gate electrode in a second direction and extending in a second direction, a lower source / drain pattern disposed on one side of the isolation insulating layer, a first upper source / drain pattern disposed on one side of the first upper sheet pattern and spaced apart from the lower source / drain pattern in a first direction, a first through contact extending in a first direction and penetrating at least a portion of the first upper source / drain pattern and at least a portion of the lower source / drain pattern, and a first lower gate contact disposed on the lower surface of the second gate electrode and extending in a second direction, wherein the first lower gate contact may be electrically connected to the first through contact.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor device. Background Technology

[0002] Semiconductor devices are core components used to control or amplify electrical signals in electronic devices, and various types of semiconductor devices can be manufactured. For example, memory devices are primarily used to store and retrieve data, while non-memory devices are used to control or amplify electrical signals. As key elements of electronic devices, semiconductor devices play an important role in diverse fields, including computers, communication equipment, and consumer electronics.

[0003] With the advancement of industry, the performance and functional requirements of electronic devices are increasing. Consequently, high-performance characteristics of semiconductor devices are becoming essential, and to meet these demands, the integration density of semiconductor devices is increasing. Various methods are being researched to form semiconductor devices with superior performance and enhanced integration density. The problem to be solved

[0004] The problem that the present disclosure aims to solve is to provide a semiconductor device with improved integration density.

[0005] The problem that the present disclosure aims to solve is to provide a method for manufacturing a semiconductor device with improved integration. means of solving the problem

[0006] According to some embodiments of the present disclosure for solving the above technical problem, a semiconductor device comprises a plurality of upper sheet patterns spaced apart in a first direction on a first separating insulating layer, a first gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of upper sheet patterns, a second gate electrode spaced apart from the first gate electrode in a second direction and extending in a second direction, a lower source / drain pattern disposed on one side of the separating insulating layer, a first upper source / drain pattern disposed on one side of the first upper sheet pattern and spaced apart from the lower source / drain pattern in a first direction, a first through contact extending in a first direction and penetrating at least a portion of the first upper source / drain pattern and at least a portion of the lower source / drain pattern, and a first lower gate contact disposed on the lower surface of the second gate electrode and extending in a second direction, wherein the first lower gate contact may be electrically connected to the first through contact.

[0007] According to some embodiments of the present disclosure for solving the above technical problem, a semiconductor device comprises: a plurality of upper sheet patterns spaced apart in a first direction on a separating insulating layer; a first gate electrode surrounding the plurality of upper sheet patterns and extending in a second direction intersecting the first direction; a first upper source / drain pattern and a second upper source / drain pattern disposed on both sides of the plurality of upper sheet patterns; a first lower source / drain pattern disposed on one side of the separating insulating layer; a through contact extending in a first direction and penetrating at least a portion of each of the second upper source / drain pattern and the first lower source / drain pattern; a third upper source / drain pattern spaced apart from the second upper source / drain pattern and a third direction intersecting the first direction and the second direction, respectively; a second lower source / drain pattern spaced apart from the first lower source / drain pattern and a third direction; a second gate electrode disposed between the first lower source / drain pattern and the second lower source / drain pattern and between the second upper source / drain pattern and the third upper source / drain pattern; and a first gate electrode and It may include a third gate electrode spaced apart in a second direction, a first upper line wiring electrically connected to a third upper source / drain pattern, a first lower line wiring electrically connected to a second lower source / drain pattern, and a lower gate contact disposed on the lower surface of the third gate electrode, extending in a second direction and electrically connected to a through contact.

[0008] According to some embodiments of the present disclosure for solving the above technical problem, a semiconductor device comprises: a plurality of upper sheet patterns spaced apart in a first direction on a separating insulating layer; a first gate electrode surrounding the plurality of upper sheet patterns and extending in a second direction intersecting the first direction; a first upper source / drain pattern and a second upper source / drain pattern disposed on both sides of the plurality of upper sheet patterns; a first lower source / drain pattern disposed on one side of the separating insulating layer; a through contact extending in a first direction and penetrating each of the second upper source / drain pattern and the first lower source / drain pattern; a third upper source / drain pattern spaced apart from the second upper source / drain pattern and a third direction intersecting the first direction and the second direction, respectively; a second lower source / drain pattern spaced apart from the first lower source / drain pattern and a third direction; a second gate electrode disposed between the first lower source / drain pattern and the second lower source / drain pattern and between the second upper source / drain pattern and the third upper source / drain pattern; and the first gate electrode and the second A third gate electrode spaced apart in a direction, a lower gate contact disposed on the lower surface of the third gate electrode and electrically connected to a through contact and extending in a second direction, a lower via disposed on the lower surface of the through contact, a first lower line wiring disposed on the lower surface of the lower via and connecting the lower via and the lower gate contact, a second lower line wiring electrically connected to a second lower source / drain pattern, a bit line electrically connected to a first upper source / drain pattern, a first upper line wiring electrically connected to a third upper source / drain pattern, and a second upper line wiring electrically connected to the first gate electrode, wherein the first lower line wiring and the second lower line wiring are disposed at the same vertical level, and the bit line, the first upper line wiring, and the second upper line wiring may be disposed at the same vertical level.

[0009] According to some embodiments of the present disclosure for solving other technical problems above, a method for manufacturing a semiconductor device may include the steps of forming a plurality of first to fourth lower sheet patterns and a plurality of first to fourth upper sheet patterns on a substrate; forming first to sixth lower source / drain patterns and first to sixth upper source / drain patterns on a substrate; forming first to fourth gate electrodes on a substrate; forming a first through electrode penetrating at least a portion of a second upper source / drain pattern and at least a portion of a second lower source / drain pattern, and forming a second through electrode penetrating at least a portion of a fifth upper source / drain pattern and at least a portion of a fifth lower source / drain pattern; removing a portion of a first gate electrode to form a first separating insulating layer and removing a portion of a fourth gate electrode to form a second separating insulating layer; and forming a first lower gate contact connected to a third gate electrode and a second lower gate contact connected to a second gate electrode.

[0010] According to some embodiments, the first lower gate contact includes a first portion extending in a first direction and a second portion extending in a second direction intersecting the first direction, and the second portion may contact the lower surface of the first through electrode.

[0011] According to some embodiments, the first lower gate contact includes a first portion extending in a first direction and a second portion extending in a second direction intersecting the first direction, and the second portion may contact the lower surface of the second lower source / drain pattern.

[0012] According to some embodiments, the first penetrating electrode can penetrate the upper and lower surfaces of the second upper source / drain pattern and the upper and lower surfaces of the second lower source / drain pattern.

[0013] According to some embodiments, the first penetrating electrode penetrates the upper and lower surfaces of the second upper source / drain pattern, and one end of the first penetrating electrode may be disposed within the second lower source / drain pattern.

[0014] According to some embodiments, the first separating insulating layer may be overlapped in a direction parallel to a plurality of first lower sheet patterns and the upper surface of the substrate, and the second separating insulating layer may be overlapped in a direction parallel to a plurality of second lower sheet patterns and the upper surface of the substrate.

[0015] According to some embodiments, the first lower gate contact and the second lower gate contact may be positioned at the same vertical level.

[0016] According to some embodiments, the steps of forming a first separating insulating layer and forming a second separating insulating layer may include removing a substrate to expose the lower surface of a first gate electrode and the lower surface of a fourth gate electrode, removing a portion of the first gate electrode and a plurality of third lower sheet patterns to form a first separating insulating layer, and removing a portion of the fourth gate electrode and a plurality of fourth lower sheet patterns to form a second separating insulating layer.

[0017] According to some embodiments, a plurality of first upper sheet patterns may be overlapped in a direction perpendicular to the first separating insulating layer and the upper surface of the substrate, and a plurality of fourth upper sheet patterns may be overlapped in a direction perpendicular to the second separating insulating layer and the upper surface of the substrate.

[0018] According to some embodiments, a semiconductor device manufacturing method may further include the steps of forming a first lower via disposed on the lower surface of a first through-electrode and a second lower via disposed on the lower surface of a second through-electrode, and forming a first lower line wiring connecting a first lower gate contact and the first lower via and a second lower line wiring connecting a second lower gate contact and the second lower via. Effects of the invention

[0019] According to some embodiments of the present disclosure, the integration density of a semiconductor device can be improved by forming a lower gate contact, a lower line wiring, a lower via, and a through contact.

[0020] According to some embodiments of the present disclosure, the integration density of a semiconductor device can be improved by separating the wiring constituting the semiconductor device into upper line wiring and lower line wiring. Brief explanation of the drawing

[0021] FIG. 1 is a circuit diagram for explaining a semiconductor device according to some embodiments of the present disclosure. FIGS. 2 and FIGS. 3 are exemplary plan views for illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 4 is a cross-sectional view taken along the line A-A' of Figures 2 and 3. Figure 5 is a cross-sectional view taken along the B-B' line of Figures 2 and 3. Figure 6 is a cross-sectional view taken along the C-C' line of Figures 2 and 3. Figure 7 is a cross-sectional view taken along the D-D' line of Figures 2 and 3. FIG. 8 is an exemplary plan view for illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 9 is a cross-sectional view taken along the line A-A' of Figure 8. Figure 10 is a cross-sectional view taken along the line B-B' of Figure 8. Figure 11 is a cross-sectional view taken along the line C-C' of Figure 8. Figure 12 is a cross-sectional view taken along the line D-D' of Figure 8. FIGS. 13 and FIGS. 14 are drawings for illustrating a semiconductor device according to some embodiments of the present disclosure. FIGS. 15 and 16 are drawings for illustrating a semiconductor device according to some embodiments of the present disclosure. FIGS. 17 and 18 are exemplary plan views for illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 19 is a cross-sectional view taken along the C-C' line of FIG. 17 and FIG. 18. FIG. 20 is a cross-sectional view taken along the line D-D' of FIG. 17 and FIG. 18. FIGS. 21 and FIGS. 22 are drawings for illustrating a semiconductor device according to some embodiments of the present disclosure. FIGS. 23 to 34 are drawings for explaining a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. Specific details for implementing the invention

[0022] In this disclosure, the terms upper, lower, upper surface, and lower surface are for convenience of explanation and are not limited thereto. The upper, lower, upper surface, and lower surface are described based on what is shown in the drawings, and the terms referring to the vertical relationship may change when the drawings are rotated vertically.

[0023] In this disclosure, although terms such as "first," "second," etc. are used to describe various elements or components, these elements or components are not limited by these terms. These terms should be understood as being used merely to distinguish one element or component from another. It is obvious that the first element or component mentioned below may be the second element or component within the technical scope of this disclosure.

[0024] A semiconductor device according to some embodiments may include a MOSFET, and more specifically, may include a three-dimensional multi-stack semiconductor device referred to as a gate-all-around (GAA) transistor or a multi-bridge channel FET (MBCFET).

[0025] A semiconductor device and a method for manufacturing the same according to some embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0026] FIG. 1 is a circuit diagram for explaining a semiconductor device according to some embodiments of the present disclosure.

[0027] Referring to FIG. 1, a semiconductor device according to some embodiments may include at least one cell. The cell may be, for example, a static random access memory (SRAM) cell. The cell may include a word line (WL), a first bit line (BL1), a second bit line (BL2), and a plurality of transistors. FIG. 1 may be an exemplary circuit diagram illustrating a cell of a semiconductor device.

[0028] A semiconductor device according to some embodiments may include a first pass transistor (PG1), a second pass transistor (PG2), a first pull-up transistor (PU1), a second pull-up transistor (PU2), a first pull-down transistor (PD1), and a second pull-down transistor (PD2).

[0029] The first pull-up transistor (PU1) and the second pull-up transistor (PU2) may be P-type MOSFETs (metal-oxide-semiconductor field effect transistors). The first pass transistor (PG1), the second pass transistor (PG2), the first pull-down transistor (PD1), and the second pull-down transistor (PD2) may be N-type MOSFETs. The semiconductor device may include six transistors composed of four NMOS transistors and two PMOS transistors. However, the present disclosure is not limited thereto.

[0030] The switching electrodes (e.g., gate electrodes) of the first and second pass transistors (PG1, PG2) may be connected to the word line (WL). The source pattern of the first pass transistor (PG1) may be connected to the first bit line (BL1). The source pattern of the second pass transistor (PG2) may be connected to the second bit line (BL2). A positive voltage (e.g., VDD voltage) may be applied to the source pattern of the first pull-up transistor (PU1). A positive voltage (e.g., VDD voltage) may be applied to the source pattern of the second pull-up transistor (PU2). A negative voltage (e.g., VSS voltage) may be applied to the source pattern of the first pull-down transistor (PD1). A negative voltage (e.g., VSS voltage) may be applied to the source pattern of the second pull-down transistor (PD2).

[0031] The drain pattern of the first pass transistor (PG1), the drain pattern of the first pull-up transistor (PU1), and the drain pattern of the first pull-down transistor (PD1) can be electrically connected to the first node (N1).

[0032] The drain pattern of the second pass transistor (PG2), the drain pattern of the second pull-up transistor (PU2), and the drain pattern of the second pull-down transistor (PD2) can be electrically connected to the second node (N2).

[0033] The switching electrode (e.g., gate electrode) of the first pull-up transistor (PU1) and the switching electrode (e.g., gate electrode) of the first pull-down transistor (PD1) can be electrically connected to the second node (N2). The switching electrode (e.g., gate electrode) of the second pull-up transistor (PU2) and the switching electrode (e.g., gate electrode) of the second pull-down transistor (PD2) can be electrically connected to the first node (N1). Accordingly, the first and second pull-up transistors (PU1, PU2) and the first and second pull-down transistors (PD1, PD2) can form a latch circuit consisting of a pair of CMOS inverters.

[0034] FIGS. 2 and 3 are exemplary plan views for illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 4 is a cross-sectional view taken along line A-A' of FIGS. 2 and 3. FIG. 5 is a cross-sectional view taken along line B-B' of FIGS. 2 and 3. FIG. 6 is a cross-sectional view taken along line C-C' of FIGS. 2 and 3. FIG. 7 is a cross-sectional view taken along line D-D' of FIGS. 2 and 3. For reference, FIG. 2 is illustrated with the lower source / drain contacts (160_1, 160_2), lower gate contacts (180_1, 180_2), and lower line wiring (195_1, 195_2, 195_3, 195_4), and FIG. 3 is illustrated with the upper source / drain contacts (260_1, 260_2, 260_3, 260_4), upper line wiring (295_1, 295_2, 295_3, 295_4), and bit lines (BL1, BL2).

[0035] Referring to FIGS. 2 through 7, a semiconductor device according to some embodiments comprises a separating insulating layer (140_1, 140_2), a plurality of lower sheet patterns (NS1_1, NS1_2), a plurality of upper sheet patterns (NS2_1, NS2_2, NS2_3, NS2_4), a gate electrode (120, 220, 320, 420), a lower source / drain pattern (150_1, 150_2, 150_3, 150_4, 150_5, 150_6), an upper source / drain pattern (250_1, 250_2, 250_3, 250_4, 250_5, 250_6), a through contact (170_1, 170_2), a lower gate contact (180_1, 180_2), a lower via (175_1, 175_2), and a lower It may include source / drain contacts (160_1, 160_2), lower line wiring (195_1, 195_2, 195_3, 195_4), upper source / drain contacts (260_1, 260_2, 260_3, 260_4), upper gate contacts (275_1, 275_2), upper vias (265_1, 265_2), upper line wiring (295_1, 295_2, 295_3, 295_4), bit lines (BL1, BL2), and a gate isolation structure (210).

[0036] An active region (AP) may be placed on a lower wiring insulation layer (190). The active region (AP) may be an area where a plurality of lower sheet patterns (NS1_1, NS1_2), a plurality of upper sheet patterns (NS2_1, NS2_2, NS2_3, NS2_4), lower source / drain patterns (150_1, 150_2, 150_3, 150_4, 150_5, 150_6) and upper source / drain patterns (250_1, 250_2, 250_3, 250_4, 250_5, 250_6), which will be described later, are placed. The active region (AP) may extend in a first direction (D1). The first direction (D1) may intersect with a second direction (D2). For example, the first direction (D1) may be perpendicular to the second direction (D2). The third direction (D3) may intersect with the first direction (D1) and the second direction (D2), respectively. For example, the third direction (D3) may be perpendicular to the first direction (D1) and the second direction (D2), respectively. The first direction (D1) and the second direction (D2) may be directions parallel to the upper surface of the lower wiring insulation layer (190), and the third direction (D3) may be a direction perpendicular to the upper surface of the lower wiring insulation layer (190).

[0037] A first isolation insulating layer (140_1) may be disposed on a lower wiring insulating layer (190). The first isolation insulating layer (140_1) may be disposed between a first lower source / drain pattern (150_1) and a second lower source / drain pattern (150_2). A first gate electrode (120) may be disposed on the first isolation insulating layer (140_1). The first isolation insulating layer (140_1) may be spaced apart from a plurality of second lower sheet patterns (NS1_2) in a second direction (D2). The upper surface of the first isolation insulating layer (140_1) may be in contact with the first gate electrode (120).

[0038] A plurality of first upper sheet patterns (NS2_1) may be disposed on an active region (AP). A plurality of first upper sheet patterns (NS2_1) may be spaced apart from the first separating insulating layer (140_1) in a third direction (D3). Each of the plurality of first upper sheet patterns (NS2_1) may have the shape of a nanosheet. Each of the plurality of first upper sheet patterns (NS2_1) may be spaced apart from each other in a third direction (D3). Although the first upper sheet patterns (NS2_1) are illustrated as being three, the present disclosure is not limited thereto.

[0039] A plurality of first lower sheet patterns (NS1_1) may be disposed on an active region (AP). A plurality of first lower sheet patterns (NS1_1) may be spaced apart from a first isolation insulating layer (140_1) in a first direction (D1). A second lower source / drain pattern (150_2) may be disposed between a plurality of first lower sheet patterns (NS1_1) and the first isolation insulating layer (140_1). Each of the plurality of first lower sheet patterns (NS1_1) may have the shape of a nanosheet. Each of the plurality of first lower sheet patterns (NS1_1) may be spaced apart from each other in a third direction (D3). Although the first lower sheet patterns (NS1_1) are illustrated as being three, the present disclosure is not limited thereto.

[0040] A plurality of second upper sheet patterns (NS2_2) may be disposed on an active region (AP). A plurality of second upper sheet patterns (NS2_2) may be disposed on a plurality of first lower sheet patterns (NS1_2). A plurality of second upper sheet patterns (NS2_2) may be spaced apart from a plurality of first lower sheet patterns (NS1_1) in a third direction (D3). A plurality of second upper sheet patterns (NS2_2) may be spaced apart from a plurality of first upper sheet patterns (NS2_1) in a first direction (D1). Each of the plurality of second upper sheet patterns (NS2_2) may have the shape of a nanosheet. Each of the plurality of second upper sheet patterns (NS2_2) may be spaced apart from each other in a third direction (D3). Although three second upper sheet patterns (NS2_2) are depicted, the present disclosure is not limited thereto.

[0041] A plurality of second lower sheet patterns (NS1_2) may be disposed on an active region (AP). A plurality of second lower sheet patterns (NS1_2) may be spaced apart from the lower wiring insulation layer (190) in a third direction (D3). A fifth lower source / drain pattern (150_5) may be disposed between the plurality of second lower sheet patterns (NS1_2) and the second separation insulation layer (140_2). Each of the plurality of second lower sheet patterns (NS1_2) may have the shape of a nanosheet. Each of the plurality of second lower sheet patterns (NS1_2) may be spaced apart from each other in a third direction (D3). Although three second lower sheet patterns (NS1_2) are depicted, the present disclosure is not limited thereto.

[0042] A plurality of third upper sheet patterns (NS2_3) may be disposed on an active region (AP). A plurality of third upper sheet patterns (NS2_3) may be disposed on a plurality of second lower sheet patterns (NS1_2). A plurality of third upper sheet patterns (NS2_3) may be spaced apart from a plurality of second lower sheet patterns (NS1_2) in a third direction (D3). A plurality of third upper sheet patterns (NS2_3) may be spaced apart from a plurality of first upper sheet patterns (NS2_1) in a second direction (D2). Each of the plurality of third upper sheet patterns (NS2_3) may have the shape of a nanosheet. Each of the plurality of third upper sheet patterns (NS2_3) may be spaced apart from each other in a third direction (D3). Although the third upper sheet patterns (NS2_3) are illustrated as being three, the present disclosure is not limited thereto.

[0043] A second isolation insulating layer (140_2) may be disposed on a lower wiring insulating layer (190). The second isolation insulating layer (140_2) may be disposed between a fifth lower source / drain pattern (150_5) and a sixth lower source / drain pattern (150_6). A fourth gate electrode (420) may be disposed on the second isolation insulating layer (140_2). The second isolation insulating layer (140_2) may be spaced apart from a plurality of first lower sheet patterns (NS1_1) in a second direction (D2). The upper surface of the second isolation insulating layer (140_2) may be in contact with the fourth gate electrode (420).

[0044] A plurality of fourth upper sheet patterns (NS2_4) may be disposed on an active region (AP). A plurality of fourth upper sheet patterns (NS2_4) may be spaced apart from the second separating insulating layer (140_2) in a third direction (D3). A plurality of fourth upper sheet patterns (NS2_4) may be spaced apart from a plurality of second upper sheet patterns (NS2_2) in a second direction (D2). Each of the plurality of fourth upper sheet patterns (NS2_4) may have the shape of a nanosheet. Each of the plurality of fourth upper sheet patterns (NS2_4) may be spaced apart from each other in a third direction (D3). Although three fourth upper sheet patterns (NS2_4) are depicted, the present disclosure is not limited thereto.

[0045] Each of the first separating insulating layer (140_1) and the second separating insulating layer (140_2) may include an insulating material. For example, each of the first separating insulating layer (140_1) and the second separating insulating layer (140_2) may include any one of silicon nitride (SIN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), and silicon carbonitride (SiCN).

[0046] Each of the lower sheet patterns (NS1_1, NS1_2) and upper sheet patterns (NS2_1, NS2_2, NS2_3, NS2_4) may include one of the elemental semiconductor materials silicon (Si), silicon germanium (SiGe), group IV-IV compound semiconductor, or group III-V compound semiconductor.

[0047] Group IV-IV compound semiconductors may be, for example, binary compounds or ternary compounds containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn).

[0048] A III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), or indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimony (Sb).

[0049] In some embodiments, a plurality of first upper sheet patterns (NS2_1) may be channel regions of a first pass transistor (e.g., PG1 in FIG. 1). A plurality of second upper sheet patterns (NS2_2) may be channel regions of a first pull-down transistor (e.g., PD1 in FIG. 1). A plurality of third upper sheet patterns (NS2_3) may be channel regions of a second pull-down transistor (e.g., PD2 in FIG. 1). A plurality of fourth upper sheet patterns (NS2_4) may be channel regions of a second pass transistor (e.g., PG2 in FIG. 1). A plurality of first lower sheet patterns (NS1_1) may be channel regions of a first pull-up transistor (e.g., PU1 in FIG. 1). A plurality of second lower sheet patterns (NS2_2) may be channel regions of a second pull-up transistor (e.g., PU2 in FIG. 1).

[0050] The first gate electrode (120) may be disposed on the first isolation insulating layer (140_1). The first gate electrode (120) may extend in a second direction (D2). The first gate electrode (120) may intersect with the active region (AP). The first gate electrode (120) may surround a plurality of first upper sheet patterns (NS2_1). For example, the first gate electrode (120) may surround four sides of the first upper sheet pattern (NS2_1).

[0051] The second gate electrode (220) may be placed on the lower wiring insulation layer (190). The second gate electrode (220) may extend in a second direction (D2). The second gate electrode (220) may be spaced apart from the first gate electrode (120) in a first direction (D1). The second gate electrode (220) may intersect with the active region (AP). The second gate electrode (220) may surround a plurality of first lower sheet patterns (NS1_1) and a plurality of second upper sheet patterns (NS2_2). For example, the second gate electrode (220) may surround four sides of each of the first lower sheet pattern (NS1_1) and the second upper sheet pattern (NS2_1).

[0052] The third gate electrode (320) may be placed on the lower wiring insulation layer (190). The third gate electrode (320) may extend in a second direction (D2). The third gate electrode (320) may be spaced apart from the first gate electrode (120) in the second direction (D2). The first gate electrode (120) may overlap with the third gate electrode (320) in the second direction (D2). A gate separation structure (210) may be placed between the third gate electrode (320) and the first gate electrode (120).

[0053] The third gate electrode (320) may intersect with the active region (AP). The third gate electrode (320) may surround a plurality of second lower sheet patterns (NS1_2) and a plurality of third upper sheet patterns (NS2_3). For example, the third gate electrode (320) may surround four sides of each of the second lower sheet patterns (NS1_2) and the third upper sheet patterns (NS2_3).

[0054] The fourth gate electrode (420) may be disposed on the second isolation insulating layer (140_2). The fourth gate electrode (420) may extend in the second direction (D2). The fourth gate electrode (420) may be spaced apart from the second gate electrode (220) in the second direction (D2). The fourth gate electrode (420) may overlap with the second gate electrode (220) in the second direction (D2). A gate isolation structure (210) may be disposed between the fourth gate electrode (420) and the second gate electrode (220).

[0055] The fourth gate electrode (420) may intersect with the active region (AP). The fourth gate electrode (420) may surround a plurality of fourth upper sheet patterns (NS2_4). For example, the fourth gate electrode (420) may surround four sides of the fourth upper sheet pattern (NS2_4).

[0056] The gate electrode (120, 220, 320, 420) may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride. The gate electrode (120, 220, 320, 420) is, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium It may include at least one of carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof, but the present disclosure is not limited thereto. Conductive metal oxides and conductive metal oxynitrides may include oxidized forms of the materials described above, but the present disclosure is not limited thereto.

[0057] The gate isolation structure (210) may be disposed on the lower wiring insulation layer (190). The gate isolation structure (210) may extend in a first direction (D1) and a third direction (D3). The gate isolation structure (210) may be disposed between the first gate electrode (120) and the third gate electrode (320), and between the first isolation insulation layer (140_1) and the third gate electrode (320). The gate isolation structure (210) may be disposed between the second gate electrode (220) and the fourth gate electrode (420), and between the second gate electrode (220) and the second isolation insulation layer (140_2).

[0058] In some embodiments, the width of the gate isolation structure (210) in the second direction (D2) may not be constant. For example, the width of the gate isolation structure (210) in the second direction (D2) may increase as it moves away from the lower wiring insulation layer (190). The gate isolation structure (210) may include inclined sides. However, the present disclosure is not limited thereto.

[0059] The gate isolation structure (210) may include a liner film (212) and a filling insulating film (214). The liner film (212) may define the side of the gate isolation structure (210). The filling insulating film (214) may be disposed within the liner film (212). The liner film (212) may include, for example, any one of silicon nitride (SiN), silicon nitride oxide (SiON), silicon carbonate nitride (SiOCN), silicon boron nitride (SiBN), silicon oxalo nitride (SiOBN), and silicon oxynitride (SiCN). The filling insulating film (214) may include, for example, at least one of silicon oxide (SiO2), silicon nitride oxide (SiON), silicon carbonate nitride (SiOCN), silicon oxalo nitride (SiOBN), silicon oxycarbonate (SiOC), and combinations thereof.

[0060] A gate insulating film (130) may be disposed between a plurality of first upper sheet patterns (NS2_1) and a first gate electrode (120). A gate insulating film (130) may be disposed between a plurality of second upper sheet patterns (NS2_2) and a second gate electrode (220), and between a plurality of first lower sheet patterns (NS1_1) and a second gate electrode (220). A gate insulating film (130) may be disposed between a plurality of third upper sheet patterns (NS2_3) and a third gate electrode (320), and between a plurality of second lower sheet patterns (NS1_2) and a third gate electrode (320). A gate insulating film (130) may be disposed between a plurality of fourth upper sheet patterns (NS2_4) and a fourth gate electrode (420).

[0061] In some embodiments, the gate insulating film (130) may comprise a plurality of films. For example, the gate insulating film (130) may comprise an interface insulating film and a high dielectric constant insulating film. The interface insulating film may comprise, for example, silicon oxide. The high dielectric constant insulating film may comprise a high dielectric constant material having a dielectric constant greater than that of the interface insulating film. The high dielectric constant insulating film may include, for example, at least one of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0062] The gate spacer (245) may be placed on the sides of the first to fourth gate electrodes (120, 220, 320, 420). For convenience of explanation, the first gate electrode (120) will be described as the central point. For example, the gate spacer (245) may be placed on both sides of the first gate electrode (120) which is placed on the upper surface of the first upper sheet pattern (NS2_1) at the top. The gate spacer (245) may extend along the sides of the first gate electrode (120). The gate spacer (245) may not be placed between the first upper sheet patterns (NS2_1) adjacent in the third direction (D3).

[0063] The gate spacer (245) may include, for example, at least one of silicon nitride (SiN), silicon nitrate (SiON), silicon oxide (SiO2), silicon carbonate nitride (SiOCN), silicon boron nitride (SiBN), silicon oxalo nitride (SiOBN), silicon oxalo carbide (SiOC), or a combination thereof. Although the gate spacer (245) is depicted as a single film, this is for convenience of explanation only and the present disclosure is not limited thereto.

[0064] The gate capping pattern (240) may be disposed on the upper surface of the first to fourth gate electrodes (120, 220, 320, 420). The gate capping pattern (240) may cover the upper surface of the first to fourth gate electrodes (120, 220, 320, 420). Although the gate capping pattern (240) is illustrated as being in contact with the upper surface of the gate spacer (245), the present disclosure is not limited thereto. For example, the gate capping pattern (240) may be disposed between a pair of gate spacers (245) and may be in contact with the side surface of the gate spacer (245).

[0065] The gate capping pattern (240) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or a combination thereof. The gate capping pattern (240) may include a material having an etch selectivity ratio with respect to the upper interlayer insulating film (280).

[0066] The upper interlayer insulating film (280) may be disposed on the upper surface of the first to sixth upper source / drain patterns (250_1, 250_2, 250_3, 250_4, 250_5, 250_6). The upper interlayer insulating film (280) may cover the upper surface of the first to sixth upper source / drain patterns (250_1, 250_2, 250_3, 250_4, 250_5, 250_6). In some embodiments other than illustrated, an etch stop film may be disposed between the upper interlayer insulating film (280) and the upper surface of the first to sixth upper source / drain patterns (250_1, 250_2, 250_3, 250_4, 250_5, 250_6).

[0067] The upper interlayer insulating film (280) may include, for example, at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a low dielectric constant material. Low-k materials include, for example, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethyleyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB), DiAcetoxyDitertiaryButoSiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polyimide nanofoams such as polypropylene oxide, CDO (Carbon Doped silicon Oxide), OSG (Organo Silicate) Glass), SiLK, Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, It may include mesoporous silica or a combination thereof, but the present disclosure is not limited thereto.

[0068] Each of the first lower source / drain pattern (150_1), the second lower source / drain pattern (150_2), and the third lower source / drain pattern (150_3) may be disposed on the lower wiring insulation layer (190). Each of the first lower source / drain pattern (150_1), the second lower source / drain pattern (150_2), and the third lower source / drain pattern (150_3) may be disposed spaced apart from each other in a first direction (D1).

[0069] A first lower source / drain pattern (150_1) may be disposed on one side of the first separation insulation layer (140_1). A second lower source / drain pattern (150_2) may be disposed on the other side of the first separation insulation layer (140_1). The second lower source / drain pattern (150_2) may be disposed on the side of a plurality of first lower sheet patterns (NS1_1). A third lower source / drain pattern (150_3) may be disposed on the side of the first lower sheet pattern (NS1_1). For example, the second lower source / drain pattern (150_2) and the third lower source / drain pattern (150_3) may be disposed on both sides of a plurality of first lower sheet patterns (NS1_1). The second lower source / drain pattern (150_2) and the third lower source / drain pattern (150_3) can be connected to a plurality of first lower sheet patterns (NS1_1).

[0070] Each of the fourth lower source / drain pattern (150_4), the fifth lower source / drain pattern (150_5), and the sixth lower source / drain pattern (150_6) may be disposed on the lower wiring insulation layer (190). Each of the fourth lower source / drain pattern (150_4), the fifth lower source / drain pattern (150_5), and the sixth lower source / drain pattern (150_6) may be disposed spaced apart from each other in a first direction (D1).

[0071] The fourth lower source / drain pattern (150_4) may be disposed on the side of a plurality of second lower sheet patterns (NS1_2). The fifth lower source / drain pattern (150_5) may be disposed on the side of a plurality of second lower sheet patterns (NS1_2). For example, the fourth lower source / drain pattern (150_4) and the fifth lower source / drain pattern (150_5) may be disposed on both sides of a plurality of second lower sheet patterns (NS1_2). The fourth lower source / drain pattern (150_4) and the fifth lower source / drain pattern (150_5) may be connected to a plurality of second lower sheet patterns (NS1_2). The fifth lower source / drain pattern (150_5) may be disposed on one side of the second separation insulation layer (140_2). The sixth lower source / drain pattern (150_6) can be placed on the other side of the second separating insulation layer (140_2).

[0072] The first upper source / drain pattern (250_1) may be spaced apart from the first lower source / drain pattern (150_1) in a third direction (D3). A middle insulating film (200) may be disposed between the first upper source / drain pattern (250_1) and the first lower source / drain pattern (150_1). The first upper source / drain pattern (250_1) may be disposed on the side of a plurality of first upper sheet patterns (NS2_1).

[0073] The second upper source / drain pattern (250_2) may be spaced apart from the second lower source / drain pattern (150_2) in a third direction (D3). A middle insulating film (200) may be disposed between the second upper source / drain pattern (250_2) and the second lower source / drain pattern (150_2). The second upper source / drain pattern (250_2) may be disposed on the side of a plurality of first upper sheet patterns (NS2_1) and on the side of a plurality of second upper sheet patterns (NS2_2).

[0074] The third upper source / drain pattern (250_3) may be spaced apart from the third lower source / drain pattern (150_3) in the third direction (D3). A middle insulating film (200) may be disposed between the third upper source / drain pattern (250_3) and the third lower source / drain pattern (150_3). The third upper source / drain pattern (250_3) may be disposed on the side of a plurality of second upper sheet patterns (NS2_2).

[0075] Each of the first upper source / drain pattern (250_1), the second upper source / drain pattern (250_2), and the third upper source / drain pattern (250_3) may be spaced apart from each other in a first direction (D1). The first upper source / drain pattern (250_1) and the second upper source / drain pattern (250_2) may be placed on both sides of a plurality of first upper sheet patterns (NS2_1). The second upper source / drain pattern (250_2) and the third upper source / drain pattern (250_3) may be placed on both sides of a plurality of second upper sheet patterns (NS2_2).

[0076] The fourth upper source / drain pattern (250_4) may be spaced apart from the fourth lower source / drain pattern (150_4) in the third direction (D3). A middle insulating film (200) may be disposed between the fourth upper source / drain pattern (250_4) and the fourth lower source / drain pattern (150_4). The fourth upper source / drain pattern (250_4) may be disposed on the side of a plurality of third upper sheet patterns (NS2_3).

[0077] The fifth upper source / drain pattern (250_5) may be spaced apart from the fifth lower source / drain pattern (150_5) in the third direction (D3). A middle insulating film (200) may be disposed between the fifth upper source / drain pattern (250_5) and the fifth lower source / drain pattern (250_5). The fifth upper source / drain pattern (250_5) may be disposed on the side of a plurality of third upper sheet patterns (NS2_3) and on the side of a plurality of fourth upper sheet patterns (NS2_4).

[0078] The sixth upper source / drain pattern (250_6) may be spaced apart from the sixth lower source / drain pattern (150_6) in the third direction (D3). A middle insulating film (200) may be disposed between the sixth upper source / drain pattern (250_6) and the sixth lower source / drain pattern (150_6). The sixth upper source / drain pattern (250_6) may be disposed on the side of a plurality of fourth upper sheet patterns (NS2_4).

[0079] Each of the fourth upper source / drain pattern (250_4), the fifth upper source / drain pattern (250_5), and the sixth upper source / drain pattern (250_6) may be spaced apart from each other in the first direction (D1). The fourth upper source / drain pattern (250_4) and the fifth upper source / drain pattern (250_5) may be placed on both sides of a plurality of third upper sheet patterns (NS2_3). The fifth upper source / drain pattern (250_5) and the sixth upper source / drain pattern (250_6) may be placed on both sides of a plurality of fourth upper sheet patterns (NS2_4).

[0080] Any identical content in the descriptions of the materials for each of the first to sixth lower source / drain patterns (150_1, 150_2, 150_3, 150_4, 150_5, 150_6) and the first to sixth upper source / drain patterns (250_1, 250_2, 250_3, 250_4, 250_5, 250_6) is replaced with the description of the first lower source / drain pattern (150_1).

[0081] The first lower source / drain pattern (150_1) may include an epitaxial pattern. The first lower source / drain pattern (150_1) may include a semiconductor material. The first lower source / drain pattern (150_1) may include, for example, an elemental semiconductor material such as silicon (Si) or germanium (Ge). Additionally, the first lower source / drain pattern (150_1) may include, for example, a binary compound, a ternary compound, or a compound doped with a group IV element, comprising at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). For example, the first lower source / drain pattern (150_1) may include silicon (Si), silicon-germanium (SiGe), germanium (Ge), silicon carbide (SiC), etc., but the present disclosure is not limited thereto.

[0082] In some embodiments, the first to sixth lower source / drain patterns (150_1, 150_2, 150_3, 150_4, 150_5, 150_6) may have a first conductivity type, and the first to sixth upper source / drain patterns (250_1, 250_2, 250_3, 250_4, 250_5, 250_6) may have a second conductivity type. The second conductivity type may be different from the first conductivity type. In some embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. However, the present disclosure is not limited thereto. For example, the first conductivity type may be N-type and the second conductivity type may be P-type.

[0083] The first to sixth lower source / drain patterns (150_1, 150_2, 150_3, 150_4, 150_5, 150_6) and the first to sixth upper source / drain patterns (250_1, 250_2, 250_3, 250_4, 250_5, 250_6) are each depicted as a single membrane, but this is for convenience of explanation only and is not limited thereto. In one embodiment, the first to sixth lower source / drain patterns (150_1, 150_2, 150_3, 150_4, 150_5, 150_6) and the first to sixth upper source / drain patterns (250_1, 250_2, 250_3, 250_4, 250_5, 250_6) may each include a plurality of membranes containing different materials. In another embodiment, the first to sixth lower source / drain patterns (150_1, 150_2, 150_3, 150_4, 150_5, 150_6) and the first to sixth upper source / drain patterns (250_1, 250_2, 250_3, 250_4, 250_5, 250_6) each contain the same material and may include a plurality of layers with different concentrations of constituent materials.

[0084] In some embodiments, the first lower source / drain pattern (150_1) may be omitted. For example, the first lower source / drain pattern (150_1) may be omitted and an insulating material may be placed in its place. In some embodiments, the sixth lower source / drain pattern (150_6) may be omitted. For example, the sixth lower source / drain pattern (150_6) may be omitted and an insulating material may be placed in its place.

[0085] The description of the material of the middle insulating film (200) may be the same as the description of the material of the upper interlayer insulating film (280).

[0086] The first through contact (170_1) may extend in a third direction (D3). The first through contact (170_1) may penetrate the upper interlayer insulating film (280), the middle insulating film (200), at least a portion of the second upper source / drain pattern (250_2), and at least a portion of the second lower source / drain pattern (150_2). For example, the first through contact (170_1) may penetrate the upper and lower surfaces of the second upper source / drain pattern (250_2) and the upper and lower surfaces of the second lower source / drain pattern (150_2). The lower surface of the first through contact (170_1) may be placed within the lower wiring insulating layer (190).

[0087] In some embodiments, the width of the first through contact (170_1) in the first direction (D1) may not be constant. For example, the width of the first through contact (170_1) in the first direction (D1) may decrease as it moves away from the first bit line (BL1). Alternatively, the first through contact (170_1) may have a slanted side. However, the present disclosure is not limited thereto. For example, the width of the first through contact (170_1) in the first direction (D1) may be constant.

[0088] The first lower gate contact (180_1) may be disposed within the lower wiring insulation layer (190). The first lower gate contact (180_1) may be disposed on the lower surface of the third gate electrode (320). The first lower gate contact (180_1) may be connected to the third gate electrode (320). The first lower gate contact (180_1) may extend in a second direction (D2). The first isolation insulation layer (140_1), the gate isolation structure (210), and the third gate electrode (320) may be disposed on the upper surface of the first lower gate contact (180_1). A portion of the first lower gate contact (180_1) may overlap with the first isolation insulation layer (140_1) in a third direction (D3).

[0089] The first lower via (175_1) may be placed within the lower wiring insulation layer (190). The first lower via (175_1) may be placed on the lower surface of the first through contact (170_1). The first lower via (175_1) may be connected to the first through contact (170_1). In some embodiments, the lower surface of the first lower via (175_1) and the lower surface of the first lower gate contact (180_1) may be placed at the same vertical level.

[0090] In the present disclosure, the vertical level may represent a vertical level in a third direction (D3). The vertical level may represent a distance in the third direction (D3) from a reference level to the surface of a specific configuration. The reference level may be a vertical level corresponding to the upper or lower surface of any component having a flat surface (e.g., a lower wiring insulation layer (190) or bit lines (BL1, BL2)).

[0091] A first lower line wiring (195_1) may be disposed on the lower surface of the first lower via (175_1) and the lower surface of the first lower gate contact (180_1). The first lower line wiring (195_1) may be disposed within the lower wiring insulation layer (190). The first lower line wiring (195_1) may extend in a first direction (D1). The first lower line wiring (195_1) may connect the first lower via (175_1) and the first lower gate contact (180_1). The first lower gate contact (180_1) may be electrically connected to the first through contact (170_1). For example, the first lower gate contact (180_1) may be electrically connected to the first through contact (170_1) through the first lower line wiring (195_1) and the first lower via (175_1). That is, the third gate electrode (320) can be electrically connected to the second lower source / drain pattern (150_2) and the second upper source / drain pattern (250_2), respectively, through the first lower gate contact (180_1), the first lower line wiring (195_1), the first lower via (175_1), and the first through contact (170_1).

[0092] In the present disclosure, the meaning that a configuration is connected to another configuration may include physical connections and electrical connections. Additionally, the meaning that a configuration is electrically connected to another configuration may include the meaning that a configuration is electrically connected to another configuration directly or indirectly through another configuration between the configurations.

[0093] The second through-contact (170_2) may be spaced apart from the first through-contact (170_1) in a second direction (D2). The second through-contact (170_2) may extend in a third direction (D3). The second through-contact (170_2) may penetrate the upper interlayer insulating film (280), the middle insulating film (200), at least a portion of the fifth upper source / drain pattern (250_5), and at least a portion of the fifth lower source / drain pattern (150_5). For example, the second through-contact (170_2) may penetrate the upper and lower surfaces of the fifth upper source / drain pattern (250_5) and the upper and lower surfaces of the fifth lower source / drain pattern (150_5). The lower surface of the second through-contact (170_2) may be placed within the lower wiring insulating layer (190).

[0094] In some embodiments, the width of the second through contact (170_2) in the first direction (D1) may not be constant. For example, the width of the second through contact (170_2) in the first direction (D1) may decrease as it moves away from the second bit line (BL2). Alternatively, the second through contact (170_2) may have a slanted side. However, the present disclosure is not limited thereto. For example, the width of the second through contact (170_2) in the first direction (D1) may be constant.

[0095] The second lower gate contact (180_2) may be placed within the lower wiring insulation layer (190). The second lower gate contact (180_2) may be spaced apart from the first lower gate contact (180_1) in the first direction (D1). The second lower gate contact (180_2) may overlap with the first lower gate contact (180_1) in the first direction (D1). The second lower gate contact (180_2) may be placed at the same vertical level as the first lower gate contact (180_1).

[0096] The second lower gate contact (180_2) may be disposed on the lower surface of the second gate electrode (220). The second lower gate contact (180_2) may be connected to the second gate electrode (220). The second lower gate contact (180_2) may extend in a second direction (D2). A second isolation insulating layer (140_2), a gate isolation structure (CT), and a second gate electrode (220) may be disposed on the upper surface of the second lower gate contact (180_2). A portion of the second lower gate contact (180_2) may overlap with the second isolation insulating layer (140_2) in a third direction (D3).

[0097] The second lower via (175_2) may be placed within the lower wiring insulation layer (190). The second lower via (175_2) may be placed on the lower surface of the second through contact (170_2). The second lower via (175_2) may be connected to the second through contact (170_2). In some embodiments, the lower surface of the second lower via (175_2) and the lower surface of the second lower gate contact (180_2) may be placed at the same vertical level.

[0098] A second lower line wiring (195_2) may be disposed on the lower surface of the second lower via (175_2) and the lower surface of the second lower gate contact (180_2). The second lower line wiring (195_2) may be disposed within the lower wiring insulation layer (190). The second lower line wiring (195_2) may extend in a first direction (D1). The second lower line wiring (195_2) may connect the second lower via (175_2) and the second lower gate contact (180_2). The second lower gate contact (180_2) may be electrically connected to the second through contact (170_2). For example, the second lower gate contact (180_2) may be electrically connected to the second through contact (170_2) through the second lower line wiring (195_2) and the second lower via (175_2). That is, the second gate electrode (220) can be electrically connected to the fifth lower source / drain pattern (150_5) and the fifth upper source / drain pattern (250_5), respectively, through the second lower gate contact (180_2), the second lower line wiring (195_2), the second lower via (175_2), and the second through contact (170_2).

[0099] Each of the first through-contact (170_1) and the second through-contact (170_2) may include a conductive material. In some embodiments, each of the first through-contact (170_1) and the second through-contact (170_2) may include a contact barrier film and a filling conductive film. The contact barrier film may comprise, for example, any one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), and rhodium (Rh). The filling conductive film may comprise, for example, any one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

[0100] Each of the first lower gate contact (180_1) and the second lower gate contact (180_2) may include a conductive material. In some embodiments, each of the first lower gate contact (180_1) and the second lower gate contact (180_2) may include a contact barrier film and a filling conductive film. The description of the contact barrier film and the filling conductive film of each of the first lower gate contact (180_1) and the second lower gate contact (180_2) may be the same as the description of the contact barrier film and the filling conductive film of the through contact (170_1, 170_2).

[0101] The first lower source / drain contact (160_1) may be placed on the third lower source / drain pattern (150_3). The first lower source / drain contact (160_1) may penetrate the lower surface of the third lower source / drain pattern (150_3). The first lower source / drain contact (160_1) may be connected to the third lower source / drain pattern (150_3).

[0102] A third lower via (175_3) may be placed on the lower surface of the first lower source / drain contact (160_1). The third lower via (175_3) may be connected to the first lower source / drain contact (160_1). A third lower line wiring (195_3) may be placed on the lower surface of the third lower via (175_3). The third lower line wiring (195_3) may extend in a first direction (D1). The third lower line wiring (195_3) may be electrically connected to the third lower source / drain pattern (150_3). For example, the third lower line wiring (195_3) may be electrically connected to the third lower source / drain pattern (150_3) through the third lower via (175_3) and the first lower source / drain contact (160_1). In some embodiments, the VDD voltage of FIG. 1 may be provided to the third lower line wiring (195_3).

[0103] The second lower source / drain contact (160_2) may be placed on the fourth lower source / drain pattern (150_4). The second lower source / drain contact (160_2) may penetrate the lower surface of the fourth lower source / drain pattern (150_4). The second lower source / drain contact (160_2) may be connected to the fourth lower source / drain pattern (150_4).

[0104] A fourth lower via (175_4) may be placed on the lower surface of a second lower source / drain contact (160_2). The fourth lower via (175_4) may be connected to the second lower source / drain contact (160_2). A fourth lower line wiring (195_4) may be placed on the lower surface of the fourth lower via (175_4). The fourth lower line wiring (195_4) may extend in a first direction (D1). The fourth lower line wiring (195_4) may be electrically connected to a fourth lower source / drain pattern (150_4). For example, the fourth lower line wiring (195_4) may be electrically connected to the fourth lower source / drain pattern (150_4) through the fourth lower via (175_4) and the second lower source / drain contact (160_2). In some embodiments, the VDD voltage of FIG. 1 may be provided to the fourth lower line wiring (195_4).

[0105] In some embodiments, each of the first to fourth lower line wirings (195_1, 195_2, 195_3, 195_4) may be placed at the same vertical level. The direction in which each of the first to fourth lower line wirings (195_1, 195_2, 195_3, 195_4) extends may be the same. For example, each of the first to fourth lower line wirings (195_1, 195_2, 195_3, 195_4) may extend in a first direction (D1). Each of the first to fourth lower line wirings (195_1, 195_2, 195_3, 195_4) may include a conductive material. Each of the first to fourth lower line wirings (195_1, 195_2, 195_3, 195_4) may comprise, for example, any one of copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), and molybdenum (Mo). However, the present disclosure is not limited thereto.

[0106] Each of the first lower source / drain contact (160_1) and the second lower source / drain contact (160_2) may include a conductive material. In some embodiments, each of the first lower source / drain contact (160_1) and the second lower source / drain contact (160_2) may include a contact barrier film and a filling conductive film. The description of the contact barrier film and the filling conductive film of each of the first lower source / drain contact (160_1) and the second lower source / drain contact (160_2) may be the same as the description of the contact barrier film and the filling conductive film of the through contact (170_1, 170_2).

[0107] The first upper source / drain contact (260_1) may be placed on the first upper source / drain pattern (250_1). The first upper source / drain contact (260_1) may penetrate the upper interlayer insulating film (280) and the upper surface of the first upper source / drain pattern (250_1). The first upper source / drain contact (260_1) may be connected to the first upper source / drain pattern (250_1).

[0108] The first upper via (265_1) may be placed within the upper wiring insulation layer (290). The first upper via (265_1) may be placed on the upper surface of the first upper source / drain contact (260_1). The first bit line (BL1) may be placed on the upper surface of the first upper via (265_1). The first bit line (BL1) may extend in a first direction (D1). The first bit line (BL1) may be electrically connected to the first upper source / drain pattern (250_1). For example, the first bit line (BL1) may be electrically connected to the first upper source / drain pattern (250_1) through the first upper via (265_1) and the first upper source / drain contact (260_1). In some embodiments, the first bit line (BL1) may correspond to the first bit line (BL1) of FIG. 1.

[0109] The first upper gate contact (275_1) may be disposed on the first gate electrode (120). The first upper gate contact (275_1) may penetrate the upper surface of the gate capping pattern (240) and the first gate electrode (120). The first upper gate contact (275_1) may be connected to the first gate electrode (120).

[0110] The first upper line wiring (295_1) may be placed on the upper surface of the first upper gate contact (275_1). The first upper line wiring (295_1) may extend in a first direction (D1). The first upper line wiring (295_1) may be electrically connected to the first gate electrode (120). For example, the first upper line wiring (295_1) may be electrically connected to the first gate electrode (120) through the first upper gate contact (275_1). In some embodiments, the first upper line wiring (295_1) may correspond to the word line (WL) of FIG. 1.

[0111] The second upper source / drain contact (260_2) may be placed on the third upper source / drain pattern (250_3). The second upper source / drain contact (260_2) may penetrate the upper interlayer insulating film (280) and the upper surface of the third upper source / drain pattern (250_3). The second upper source / drain contact (260_2) may be connected to the third upper source / drain pattern (250_3).

[0112] The second upper via (265_2) may be placed within the upper wiring insulation layer (290). The second upper via (265_2) may be placed on the upper surface of the second upper source / drain contact (260_2). The second upper line wiring (295_2) may be placed on the upper surface of the second upper via (265_2). The second upper line wiring (295_2) may extend in the first direction (D1). The second upper line wiring (295_2) may be electrically connected to the third upper source / drain pattern (250_3). For example, the second upper line wiring (295_2) may be electrically connected to the third upper source / drain pattern (250_3) through the second upper via (265_2) and the second upper source / drain contact (260_2). In some embodiments, the VSS voltage of FIG. 1 may be applied to the second upper line wiring (295_2).

[0113] The third upper source / drain contact (260_3) may be placed on the fourth upper source / drain pattern (250_4). The third upper source / drain contact (260_3) may penetrate the upper interlayer insulating film (280) and the upper surface of the fourth upper source / drain pattern (250_4). The third upper source / drain contact (260_3) may be connected to the fourth upper source / drain pattern (250_4).

[0114] The third upper via (265_3) may be placed within the upper wiring insulation layer (290). The third upper via (265_3) may be placed on the upper surface of the third upper source / drain contact (260_3). The third upper line wiring (295_3) may be placed on the upper surface of the third upper via (265_3). The third upper line wiring (295_3) may extend in the first direction (D1). The third upper line wiring (295_3) may be electrically connected to the fourth upper source / drain pattern (250_4). For example, the third upper line wiring (295_3) may be electrically connected to the fourth upper source / drain pattern (250_4) through the third upper via (265_3) and the third upper source / drain contact (260_3). In some embodiments, the VSS voltage of FIG. 1 may be applied to the third upper line wiring (295_3).

[0115] The second upper gate contact (275_2) may be placed on the fourth gate electrode (420). The second upper gate contact (275_2) may penetrate the upper surface of the gate capping pattern (240) and the fourth gate electrode (420). The second upper gate contact (275_2) may be connected to the fourth gate electrode (420).

[0116] The fourth upper line wiring (295_4) may be placed on the upper surface of the second upper gate contact (275_2). The fourth upper line wiring (295_4) may extend in the first direction (D1). The fourth upper line wiring (295_4) may be electrically connected to the fourth gate electrode (420). For example, the fourth upper line wiring (295_4) may be electrically connected to the fourth gate electrode (420) through the second upper gate contact (275_2). In some embodiments, the fourth upper line wiring (295_4) may correspond to the word line (WL) of FIG. 1.

[0117] The fourth upper source / drain contact (260_4) may be placed on the sixth upper source / drain pattern (250_6). The fourth upper source / drain contact (260_4) may penetrate the upper interlayer insulating film (280) and the upper surface of the sixth upper source / drain pattern (250_6). The fourth upper source / drain contact (260_4) may be connected to the sixth upper source / drain pattern (250_6).

[0118] The fourth upper via (265_4) may be placed within the upper wiring insulation layer (290). The fourth upper via (265_4) may be placed on the upper surface of the fourth upper source / drain contact (260_4). The second bit line (BL2) may be placed on the upper surface of the fourth upper via (265_4). The second bit line (BL2) may extend in the first direction (D1). The second bit line (BL2) may be electrically connected to the sixth upper source / drain pattern (250_6). For example, the second bit line (BL2) may be electrically connected to the sixth upper source / drain pattern (250_6) through the fourth upper via (265_4) and the fourth upper source / drain contact (260_4). In some embodiments, the second bit line (BL2) may correspond to the second bit line (BL2) of FIG. 1.

[0119] Each of the first and second upper gate contacts (275_1, 275_2) and the first to fourth upper source / drain contacts (260_1, 260_2, 260_3, 260_4) may include a conductive material. In some embodiments, each of the first and second upper gate contacts (275_1, 275_2) and the first to fourth upper source / drain contacts (260_1, 260_2, 260_3, 260_4) may include a contact barrier film and a filling conductive film. The description of the contact barrier film and filling conductive film of each of the first and second upper gate contacts (275_1, 275_2) and the first to fourth upper source / drain contacts (260_1, 260_2, 260_3, 260_4) may be the same as the description of the contact barrier film and filling conductive film of the through contact (170_1, 170_2).

[0120] Each of the lower wiring insulation layer (190) and the upper wiring insulation layer (290) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Low dielectric constant materials include, for example, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethylcyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB), DiAcetoxyDitertiaryButoxySiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polyimide nanofoams such as polypropylene oxide, CDO (Carbon Doped silicon Oxide), OSG (Organo Silicate) Glass), SiLK, Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, It may include mesoporous silica or a combination thereof. However, the present disclosure is not limited thereto.

[0121] In some embodiments, the first and second bit lines (BL1, BL2) and the first to fourth upper line lines (295_1, 295_2, 295_3, 295_4) may each be placed at the same vertical level. The direction in which the first and second bit lines (BL1, BL2) and the first to fourth upper line lines (295_1, 295_2, 295_3, 295_4) extend may be the same. For example, the first and second bit lines (BL1, BL2) and the first to fourth upper line lines (295_1, 295_2, 295_3, 295_4) may each extend in a first direction (D1).

[0122] In a semiconductor device according to some embodiments of the present disclosure, a third gate electrode (320) may be electrically connected to a first through-contact (170_1) through a first lower gate contact (180_1), a first lower line wiring (195_1), and a first lower via (175_1). Additionally, a second gate electrode (220) may be electrically connected to a second through-contact (170_2) through a second lower gate contact (180_2), a second lower line wiring (195_2), and a second lower via (175_2). Accordingly, the integration density of the semiconductor device may be improved.

[0123] In a semiconductor device according to some embodiments of the present disclosure, first to fourth lower line wirings (195_1, 195_2, 195_3, 195_4) may be arranged at the same vertical level within a lower wiring insulating layer (190), and first and second bit lines (BL1, BL2) and first to fourth upper line wirings (295_1, 295_2, 295_3, 295_4) may be arranged at the same vertical level within an upper wiring insulating layer (290). That is, by separating the wirings constituting the SRAM into upper and lower sections, the integration density of the semiconductor device can be improved.

[0124] FIG. 8 is an exemplary plan view for illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 9 is a cross-sectional view taken along line A-A' of FIG. 8. FIG. 10 is a cross-sectional view taken along line B-B' of FIG. 8. FIG. 11 is a cross-sectional view taken along line C-C' of FIG. 8. FIG. 12 is a cross-sectional view taken along line D-D' of FIG. 8. For convenience of explanation, the description will focus on configurations different from those described in FIG. 2 through 7.

[0125] Referring to FIGS. 8 to 12, in a semiconductor device according to some embodiments, a first lower gate contact (180_1) may include a first portion (P1) and a second portion (P2).

[0126] A first portion (P1) of the first lower gate contact (180_1) may be extended in a second direction (D2). A second portion (P2) of the first lower gate contact (180_1) may be extended from the first portion (P1) in a first direction (D1). The first lower gate contact (180_1) may resemble a rotated "L" in a planar view.

[0127] The first lower gate contact (180_1) may be electrically connected to the first through contact (170_1). For example, the second portion (P2) of the first lower gate contact (180_1) may contact one end of the first through contact (170_1). The one end of the first through contact (170_1) may be placed on the second portion (P2) of the first lower gate contact (180_1). In some embodiments, the second portion (P2) of the first lower gate contact (180_1) may contact the second lower source / drain pattern (150_2). However, the present disclosure is not limited thereto.

[0128] The second lower gate contact (180_2) may include a third part (P3) and a fourth part (P4). The third part (P3) of the second lower gate contact (180_2) may extend in a second direction (D2). The fourth part (P4) of the second lower gate contact (180_2) may extend from the third part (P3) in a first direction (D1). The second lower gate contact (180_2) may resemble a rotated "L" in a planar view.

[0129] The second lower gate contact (180_2) may be electrically connected to the second through contact (170_2). For example, the fourth portion (P4) of the second lower gate contact (180_2) may contact one end of the second through contact (170_2). One end of the second through contact (170_2) may be placed on the fourth portion (P4) of the second lower gate contact (180_2). In some embodiments, the fourth portion (P4) of the second lower gate contact (180_2) may contact the fifth lower source / drain pattern (150_5). However, the present disclosure is not limited thereto.

[0130] FIGS. 13 and 14 are drawings for illustrating a semiconductor device according to some embodiments of the present disclosure. For convenience of explanation, the description focuses on configurations different from those described in FIGS. 8 through 12.

[0131] Referring to FIGS. 13 and 14, in a semiconductor device according to some embodiments, a first lower gate contact (180_1) may include a first protrusion (PR1), and a second lower gate contact (180_2) may include a second protrusion (PR2).

[0132] The first protrusion (PR1) of the first lower gate contact (180_1) may be positioned at a vertical level higher than the upper surface of the lower wiring insulation layer (190). The first protrusion (PR1) of the first lower gate contact (180_1) may be in contact with the second lower source / drain pattern (150_2). The first protrusion (PR1) of the first lower gate contact (180_1) may be positioned between the first isolation insulation layer (140_1) and the first through contact (170_1). The first protrusion (PR1) of the first lower gate contact (180_1) may overlap with the first isolation insulation layer (140_1) in the first direction (D1).

[0133] The second protrusion (PR2) of the second lower gate contact (180_2) may be positioned at a vertical level higher than the upper surface of the lower wiring insulation layer (190). The second protrusion (PR2) of the second lower gate contact (180_2) may be in contact with the fifth lower source / drain pattern (150_5). The second protrusion (PR2) of the second lower gate contact (180_2) may be positioned between the second isolation insulation layer (140_2) and the second through contact (170_2). The second protrusion (PR2) of the second lower gate contact (180_2) may overlap with the second isolation insulation layer (140_2) in the first direction (D1).

[0134] FIGS. 15 and 16 are drawings for illustrating a semiconductor device according to some embodiments of the present disclosure. For convenience of explanation, the description will focus on configurations different from those described in FIGS. 2 through 7.

[0135] Referring to FIGS. 15 and 16, in a semiconductor device according to some embodiments, a first through-contact (170_1) may penetrate a portion of a second lower source / drain pattern (150_2).

[0136] The first through-contact (170_1) can penetrate the middle insulating film (200), the upper and lower surfaces of the second upper source / drain pattern (250_2), and the upper surface of the second lower source / drain pattern (150_2). One end of the first through-contact (170_1) can be positioned within the second lower source / drain pattern (150_2). For example, the lower surface of the first through-contact (170_1) can be positioned within the second lower source / drain pattern (150_2). The second lower source / drain pattern (150_2) can be positioned between the first through-contact (170_1) and the first lower gate contact (180_1). The first through-contact (170_1) can be connected to the second lower source / drain pattern (150_2) and the second upper source / drain pattern (250_2).

[0137] The first lower gate contact (180_1) may include a first portion and a second portion. The description of the first portion and the second portion of the first lower gate contact (180_1) may be similar to that described in FIGS. 8 through 12. Hereinafter, the description will focus on the other portion. The second portion of the first lower gate contact (180_1) may contact the second lower source / drain pattern (150_2). The first lower gate contact (180_1) may be connected to the second lower source / drain pattern (150_2). That is, the third gate electrode (320) may be electrically connected to the second lower source / drain pattern (150_2) through the first lower gate contact (180_1). Additionally, the third gate electrode (320) can be electrically connected to the second upper source / drain pattern (250_2) through the first lower gate contact (180_1), the second lower source / drain pattern (150_2), and the first through contact (170_1).

[0138] In some embodiments, the first lower gate contact (180_1) may penetrate the lower surface of the third gate electrode (320). A portion of the first lower gate contact (180_1) may be disposed within the third gate electrode (320). However, the present disclosure is not limited thereto. For example, the first lower gate contact (180_1) may be disposed on the lower surface of the third gate electrode (320).

[0139] The second through-contact (170_2) may penetrate a portion of the fifth lower source / drain pattern (150_5). The second through-contact (170_2) may penetrate the middle insulating film (200), the upper and lower surfaces of the fifth upper source / drain pattern (250_5), and the upper surface of the fifth lower source / drain pattern (150_5). One end of the second through-contact (170_2) may be positioned within the fifth lower source / drain pattern (150_5). For example, the lower surface of the second through-contact (170_2) may be positioned within the fifth lower source / drain pattern (150_5). The fifth lower source / drain pattern (150_5) may be positioned between the second through-contact (170_2) and the second lower gate contact (180_2). The second through contact (170_2) can be connected to the fifth lower source / drain pattern (150_5) and the fifth upper source / drain pattern (250_5).

[0140] The second lower gate contact (180_2) may include a third part and a fourth part. The description of the third part and the fourth part of the second lower gate contact (180_2) may be similar to that described in FIGS. 8 through 12. Hereinafter, the description will focus on the other parts. The fourth part of the second lower gate contact (180_2) may contact the fifth lower source / drain pattern (150_5). The second lower gate contact (180_2) may be connected to the fifth lower source / drain pattern (150_5). That is, the second gate electrode (220) may be electrically connected to the fifth lower source / drain pattern (150_5) through the second lower gate contact (180_2). Additionally, the second gate electrode (220) can be electrically connected to the fifth upper source / drain pattern (250_5) through the second lower gate contact (180_2), the fifth lower source / drain pattern (150_5), and the second through contact (170_2).

[0141] In some embodiments, the second lower gate contact (180_2) may penetrate the lower surface of the second gate electrode (220). A portion of the second lower gate contact (180_2) may be disposed within the second gate electrode (220). However, the present disclosure is not limited thereto. For example, the second lower gate contact (180_2) may be disposed on the lower surface of the second gate electrode (220).

[0142] FIGS. 17 and 18 are exemplary plan views for illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 19 is a cross-sectional view taken along the line C-C' of FIGS. 17 and 18. FIG. 20 is a cross-sectional view taken along the line D-D' of FIGS. 17 and 18. For convenience of explanation, the description will focus on configurations different from those described in FIGS. 2 through 7.

[0143] Referring to FIGS. 17 to 20, a semiconductor device according to some embodiments may include an insulating support structure (215).

[0144] The insulating support structure (215) may extend in a first direction (D1) and a third direction (D3). The insulating support structure (215) may be placed on the lower wiring insulating layer (190). The insulating support structure (215) may intersect with the first lower gate contact (180_1) and the second lower gate contact (180_2), respectively.

[0145] In some embodiments, the width of the insulating support structure (215) in the second direction (D2) may be constant. However, the present disclosure is not limited thereto.

[0146] The insulating support structure (215) may be disposed between a plurality of first upper sheet patterns (NS2_1) and a plurality of third upper sheet patterns (NS2_3). The insulating support structure (215) may be disposed between a first separating insulating layer (140_1) and a plurality of second lower sheet patterns (NS1_2). The insulating support structure (215) may be disposed between a plurality of second upper sheet patterns (NS2_2) and a plurality of fourth upper sheet patterns (NS2_4). The insulating support structure (215) may be disposed between a plurality of first lower sheet patterns (NS1_1) and a second separating insulating layer (140_2).

[0147] In some embodiments, the insulating support structure (215) may be in contact with the sides of the upper sheet patterns (NS2_1, NS2_2, NS2_3, NS2_4) and the sides of the lower sheet patterns (NS1_1, NS1_2), respectively. For example, the insulating support structure (215) may be in contact with the sides of the first upper sheet pattern (NS2_1). The first gate electrode (120) may surround three sides of the first upper sheet pattern (NS2_1). The gate insulating film (130) and the first gate electrode (120) may not be placed between the first upper sheet pattern (NS2_1) and the insulating support structure (215). By not placing the first gate electrode (120) between the insulating support structure (215) and the first upper sheet pattern (NS2_1), the distance between the first upper sheet pattern (NS2_1) and the third upper sheet pattern (NS2_3) may be reduced. Accordingly, the integration density of semiconductor devices can be improved.

[0148] FIGS. 21 and 22 are drawings for illustrating a semiconductor device according to some embodiments of the present disclosure. For convenience of explanation, the description will focus on configurations different from those described in FIGS. 2 through 7.

[0149] Referring to FIGS. 21 and 22, in a semiconductor device according to some embodiments, a first through-contact (170_1) may penetrate a portion of a second upper source / drain pattern (250_2).

[0150] The first through-contact (170_1) can penetrate the middle insulating film (200), the upper and lower surfaces of the second lower source / drain pattern (150_2), and the lower surface of the second upper source / drain pattern (250_2). One end of the first through-contact (170_1) can be positioned within the second upper source / drain pattern (250_2). For example, the upper surface of the first through-contact (170_1) can be positioned within the second upper source / drain pattern (250_2). The first through-contact (170_1) can be connected to the second lower source / drain pattern (150_2) and the second upper source / drain pattern (250_2).

[0151] The width of the first through contact (170_1) in the first direction (D1) may not be constant. For example, the width of the first through contact (170_1) in the first direction (D1) may increase as it moves further away from the first bit line (BL1). The first through contact (170_1) may have a slanted side.

[0152] The second through contact (170_2) may penetrate a portion of the fifth upper source / drain pattern (250_5). The second through contact (170_2) may penetrate the middle insulating film (200), the upper and lower surfaces of the fifth lower source / drain pattern (150_5), and the lower surface of the fifth upper source / drain pattern (250_5). One end of the second through contact (170_2) may be positioned within the fifth upper source / drain pattern (250_5). For example, the upper surface of the second through contact (170_2) may be positioned within the fifth upper source / drain pattern (250_5). The second through contact (170_2) may be connected to the fifth lower source / drain pattern (150_5) and the fifth upper source / drain pattern (250_5).

[0153] The width of the second through contact (170_2) in the first direction (D1) may not be constant. For example, the width of the second through contact (170_2) in the first direction (D1) may increase as it moves further away from the second bit line (BL2). The second through contact (170_2) may have a slanted side.

[0154] FIGS. 23 to 34 are drawings for illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIGS. 23, 25, 27, 29, 31, and 33 correspond to cross-sectional views cut along line A-A' of FIGS. 2 and 3, and FIGS. 24, 26, 28, 30, 32, and 34 may correspond to cross-sectional views cut along line B-B' of FIGS. 2 and 3. For convenience of explanation, configurations identical to those described in FIGS. 2 to 7 are omitted or briefly described.

[0155] Referring to FIGS. 23 and 24, a plurality of first to fourth lower sheet patterns (NS1_1, NS1_2, NS1_3, NS1_4), a plurality of first to fourth upper sheet patterns (NS2_1, NS2_2, NS2_3, NS2_4), first to fourth gate electrodes (120, 220, 320, 420), first to sixth lower source / drain patterns (150_1, 150_2, 150_3, 150_4, 150_5, 150_6), and first to sixth upper source / drain patterns (250_1, 250_2, 250_3, 250_4, 250_5, 250_6) may be formed on a substrate (100).

[0156] The substrate (100) may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate (100) may include silicon germanium (SiGe), SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0157] A plurality of first to fourth lower sheet patterns (NS1_1, NS1_2, NS1_3, NS1_4) and a plurality of first to fourth upper sheet patterns (NS2_1, NS2_2, NS2_3, NS2_4) may be formed on a substrate (100). A plurality of third lower sheet patterns (NS1_3) may be spaced apart from a plurality of first lower sheet patterns (NS1_1) in a first direction (D1). A plurality of fourth lower sheet patterns (NS1_4) may be spaced apart from a plurality of second lower sheet patterns (NS1_2) in a first direction (D1).

[0158] Next, first to sixth lower source / drain patterns (150_1, 150_2, 150_3, 150_4, 150_5, 150_6) may be formed on the substrate (100). A middle insulating film (200) may be formed on the first to sixth lower source / drain patterns (150_1, 150_2, 150_3, 150_4, 150_5, 150_6). First to sixth upper source / drain patterns (250_1, 250_2, 250_3, 250_4, 250_5, 250_6) may be formed on the middle insulating film (200). An upper interlayer insulating film (280) may be formed on the upper surface of the first to sixth upper source / drain patterns (250_1, 250_2, 250_3, 250_4, 250_5, 250_6).

[0159] Next, first to fourth gate electrodes (120, 220, 320, 420) may be formed. The first gate electrode (120) may surround a plurality of first upper sheet patterns (NS1_1) and a plurality of third lower sheet patterns (NS1_3). The fourth gate electrode (420) may surround a plurality of fourth upper sheet patterns (NS2_4) and a plurality of fourth lower sheet patterns (NS1_4). A gate capping pattern (240) may be formed on the upper surface of the first to fourth gate electrodes (120, 220, 320, 420).

[0160] Referring to FIGS. 25 and 26, first to fourth upper source / drain contacts (260_1, 260_2, 260_3, 260_4) and first and second through contacts (170_1, 170_2) may be formed.

[0161] Specifically, a first through-contact (170_1) and a second through-contact (170_2) may be formed first. The first through-contact (170_1) may penetrate the upper interlayer insulating film (280), the second upper source / drain pattern (250_2), the middle insulating film (200), and the second lower source / drain pattern (150_2). The second through-contact (170_2) may penetrate the upper interlayer insulating film (280), the fifth upper source / drain pattern (250_5), the middle insulating film (200), and the fifth lower source / drain pattern (150_5). However, the present disclosure is not limited thereto. For example, the shapes of the first through-contact (170_1) and the second through-contact (170_2) may be the same as those in FIG. 15 and FIG. 16.

[0162] Next, first to fourth upper source / drain contacts (260_1, 260_2, 260_3, 260_4) may be formed. The description of the first to fourth upper source / drain contacts (260_1, 260_2, 260_3, 260_4) may be the same as that described above.

[0163] Although it has been described that first and second through contacts (170_1, 170_2) are formed and first to fourth upper source / drain contacts (260_1, 260_2, 260_3, 260_4) are formed, the present disclosure is not limited thereto. For example, first to fourth upper source / drain contacts (260_1, 260_2, 260_3, 260_4) may be formed and first and second through contacts (170_1, 170_2) may be formed.

[0164] Referring to FIGS. 27 and FIGS. 28, a first bit line (BL1) and a second bit line (BL2) can be formed.

[0165] Specifically, a first upper via (265_1) may be formed on a first upper source / drain contact (260_1), and a first bit line (BL1) may be formed on the first upper via (265_1). Additionally, a fourth upper via (265_4) may be formed on a fourth upper source / drain contact (260_4), and a second bit line (BL2) may be formed on the fourth upper via (265_4). In some embodiments, the first to fourth upper line wirings (295_1, 295_2, 295_3, 295_4) described in FIGS. 2 through 7 may be formed by the same process as the first and second bit lines (BL1, BL2).

[0166] Referring to FIGS. 29 and FIGS. 30, a first separating insulating layer (140_1) and a second separating insulating layer (140_2) may be formed.

[0167] Specifically, the substrate (100 in FIG. 27) may be removed, and the lower surface of the first gate electrode (120) and the lower surface of the fourth gate electrode (420) may be exposed. Then, a portion of the first gate electrode (120) and a plurality of third lower sheet patterns (NS1_3 in FIG. 27) may be removed, and a first isolation insulating layer (140_1) may be formed. Likewise, a portion of the fourth gate electrode (420) and a plurality of fourth lower sheet patterns (NS1_4 in FIG. 27) may be removed, and a second isolation insulating layer (140_2) may be formed. Then, a lower wiring insulating layer (190) may be formed.

[0168] Referring to FIGS. 31 and 32, a first lower source / drain contact (160_1) and a second lower source / drain contact (160_2) may be formed.

[0169] A first lower source / drain contact (160_1) may be formed on the third lower source / drain pattern (150_3). The first lower source / drain contact (160_1) may penetrate the lower surface of the third lower source / drain pattern (150_3). A second lower source / drain contact (160_2) may be formed on the fourth lower source / drain pattern (150_4). The second lower source / drain contact (160_2) may penetrate the lower surface of the fourth lower source / drain pattern (150_4).

[0170] Referring to FIGS. 33 and 34, first and second lower gate contacts (180_1, 180_2) and first and second lower vias (175_1, 175_2) may be formed.

[0171] The first lower gate contact (180_1) may extend in a second direction (D2). The first lower gate contact (180_1) may be placed on the lower surface of the first separating insulating layer (140_1) and the lower surface of the third gate electrode (320). The second lower gate contact (180_2) may extend in a second direction (D2). The second lower gate contact (180_2) may be placed on the lower surface of the second separating insulating layer (140_2) and the lower surface of the second gate electrode (220).

[0172] The first lower via (175_1) may be formed on the lower surface of the first through contact (170_1). The second lower via (175_2) may be formed on the lower surface of the second through contact (170_2). Although it has been described that the first and second lower gate contacts (180_1, 180_2) and the first and second lower vias (175_1, 175_2) are formed, the present disclosure is not limited thereto. For example, the first and second lower vias (175_1, 175_2) may be formed and the first and second lower gate contacts (180_1, 180_2) may be formed.

[0173] In some embodiments, the first lower via (175_1) and the second lower via (175_2) are omitted, and each of the first lower gate contact (180_1) and the second lower gate contact (180_2) may include a portion extending in the first direction (D1). For example, the shape of the first lower gate contact (180_1) and the second lower gate contact (180_2) may be the same as in FIGS. 8 to 12. Additionally, the shape of the first lower gate contact (180_1) and the second lower gate contact (180_2) may be the same as in FIGS. 13 and 14 or FIGS. 15 and 16.

[0174] Finally, referring to FIGS. 4 and 5, a first lower line wiring (195_1) and a second lower line wiring (195_2) may be formed. In some embodiments, when the first lower line wiring (195_1) and the second lower line wiring (195_2) are formed, a third lower line wiring (195_3 in FIG. 2) and a fourth lower line wiring (195_4 in FIG. 3) may be formed together.

[0175] Although the present invention has been described above by limited embodiments and drawings, the present invention is not limited thereto, and it is obvious that various modifications and variations are possible within the scope of the technical spirit of the present invention and the equivalent scope of the claims described below by those skilled in the art to which the present invention belongs. Explanation of the symbols

[0176] 120: First gate electrode 140_1: First separating insulating layer 140_2: Second separating insulation layer 160_1: First lower source / drain contact 160_2: Second lower source / drain contact 170_1: First penetrating contact 170_2: Second penetrating contact 175_1: 1st lower via 175_2: Second lower via 175_3: 3rd lower via 175_4: 4th lower via 180_1: First lower gate contact 180_2: Second lower gate contact 195_1: 1st lower line wiring 195_2: Second lower line wiring 195_3: 3rd Lower Line Wiring 195_4: 4th Lower Line Wiring 210: Gate isolation structure 220: Second gate electrode 320: Third gate electrode 420: 4th gate electrode

Claims

Claim 1 A semiconductor device comprising: a plurality of upper sheet patterns spaced apart in a first direction on a first separating insulating layer; a first gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of upper sheet patterns; a second gate electrode spaced apart from the first gate electrode in the second direction and extending in the second direction; a lower source / drain pattern disposed on one side of the separating insulating layer; a first upper source / drain pattern disposed on one side of the first upper sheet pattern and spaced apart from the lower source / drain pattern in the first direction; a first through contact extending in the first direction and penetrating at least a portion of the first upper source / drain pattern and at least a portion of the lower source / drain pattern; and a first lower gate contact disposed on the lower surface of the second gate electrode and extending in the second direction, wherein the first lower gate contact is electrically connected to the first through contact. Claim 2 A semiconductor device according to claim 1, further comprising: a lower via disposed on the lower surface of the first through contact; and a lower line wiring disposed on the lower surface of the lower via and extending in a third direction intersecting each of the first direction and the second direction, wherein the lower line wiring is disposed on the lower surface of the first lower gate contact. Claim 3 A semiconductor device according to claim 1, wherein a portion of the first lower gate contact overlaps with the first separating insulating layer in the first direction. Claim 4 A semiconductor device according to claim 1, further comprising: a third gate electrode spaced apart from the first gate electrode and a third direction intersecting the first direction and the second direction, respectively; a second lower gate contact disposed on the lower surface of the third gate electrode and extending in the second direction; and a second through contact disposed spaced apart from the first through contact and in the second direction, wherein the second lower gate contact is electrically connected to the second through contact. Claim 5 A semiconductor device according to claim 4, further comprising a second separating insulating layer spaced apart from the second gate electrode and the third direction, wherein the lower surface of the first separating insulating layer is positioned at the same vertical level as the lower surface of the second separating insulating layer, and a portion of the second lower gate contact overlaps with the second separating insulating layer in the first direction. Claim 6 A semiconductor device according to claim 1, wherein the first lower gate contact comprises a first portion extending in the second direction and a second portion extending in a third direction intersecting the first direction and the second direction, respectively, from the first portion, and the second portion is disposed on the lower surface of the first through contact. Claim 7 A semiconductor device according to claim 1, wherein the first lower gate contact comprises a first portion extending in the second direction and a second portion extending in a third direction intersecting the first direction and the second direction, respectively, from the first portion, the second portion contacts the lower source / drain pattern, and one end of the first through contact is disposed within the lower source / drain pattern. Claim 8 A semiconductor device according to claim 1, wherein the first penetrating contact penetrates the upper surface of the first upper source / drain pattern and the lower surface of the lower source / drain pattern, respectively. Claim 9 A plurality of upper sheet patterns spaced apart in a first direction on a separating insulating layer; a first gate electrode surrounding the plurality of upper sheet patterns and extending in a second direction intersecting the first direction; a first upper source / drain pattern and a second upper source / drain pattern disposed on both sides of the plurality of upper sheet patterns; a first lower source / drain pattern disposed on one side of the separating insulating layer; a through contact extending in the first direction and penetrating at least a portion of each of the second upper source / drain pattern and the first lower source / drain pattern; a third upper source / drain pattern spaced apart from the second upper source / drain pattern and a third direction intersecting the first direction and the second direction, respectively; a second lower source / drain pattern spaced apart from the first lower source / drain pattern and the third direction; a second gate electrode disposed between the first lower source / drain pattern and the second lower source / drain pattern and between the second upper source / drain pattern and the third upper source / drain pattern; the first gate A semiconductor device comprising: a third gate electrode spaced apart from the electrode in the second direction; a first upper line wiring electrically connected to the third upper source / drain pattern; a first lower line wiring electrically connected to the second lower source / drain pattern; and a lower gate contact disposed on the lower surface of the third gate electrode, extending in the second direction and electrically connected to the through contact. Claim 10 A plurality of upper sheet patterns spaced apart in a first direction on a separating insulating layer; a first gate electrode surrounding the plurality of upper sheet patterns and extending in a second direction intersecting the first direction; a first upper source / drain pattern and a second upper source / drain pattern disposed on both sides of the plurality of upper sheet patterns; a first lower source / drain pattern disposed on one side of the separating insulating layer; a through contact extending in the first direction and penetrating each of the second upper source / drain pattern and the first lower source / drain pattern; a third upper source / drain pattern spaced apart from the second upper source / drain pattern and in a third direction intersecting the first direction and the second direction, respectively; a second lower source / drain pattern spaced apart from the first lower source / drain pattern and in the third direction; a second gate electrode disposed between the first lower source / drain pattern and the second lower source / drain pattern and between the second upper source / drain pattern and the third upper source / drain pattern; the first gate electrode and A semiconductor device comprising: a third gate electrode spaced apart in the second direction; a lower gate contact disposed on the lower surface of the third gate electrode, electrically connected to the through contact, and extending in the second direction; a lower via disposed on the lower surface of the through contact; a first lower line wiring disposed on the lower surface of the lower via and connecting the lower via and the lower gate contact; a second lower line wiring electrically connected to the second lower source / drain pattern; a bit line electrically connected to the first upper source / drain pattern; a first upper line wiring electrically connected to the third upper source / drain pattern; and a second upper line wiring electrically connected to the first gate electrode, wherein the first lower line wiring and the second lower line wiring are disposed at the same vertical level, and the bit line, the first upper line wiring, and the second upper line wiring are disposed at the same vertical level.

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