Bitline-source line voltage detection circuit for optimizing write termination of MRAM

Abstract

A bitline-source line voltage sensing circuit for optimizing write termination of an MRAM according to various embodiments of the present invention may include: a first capacitor connected to the bitline of the MRAM to capacitively couple a voltage change of the bitline to a first node; and a second capacitor connected to the sourceline of the MRAM to capacitively couple a voltage change of the sourceline to a second node.

Description

Technology Field

[0001] The present invention relates to a bitline-source line voltage sensing circuit for optimizing write termination of an MRAM. This research is an ICT creative project conducted with the support of the Samsung Electronics Future Technology Development Center, and is related to the 'Development of Artificial Intelligence for Embedded Memory Performance Prediction and Automatic Optimal Design Generation (SRFC-IT2102-06)', with a research period from January 1, 2025 to November 30, 2025. Background Technology

[0002] The content described in this section merely provides background information regarding the present embodiment and does not constitute prior art.

[0003] MRAM (Magnetoresistive Random Access Memory) is a non-volatile memory technology that utilizes the magnetoresistance effect. Unlike conventional DRAM or SRAM, it retains data even when the power is turned off and offers faster speeds than flash memory. The core principle of MRAM is to store data using a Magnetic Tunnel Junction (MTJ) structure, where an insulating layer is placed between two magnetic layers to represent 0 and 1 based on changes in resistance. Thanks to this structure, it possesses high durability and fast read / write speeds, as well as excellent low power consumption characteristics.

[0004] MRAM offers several advantages compared to existing semiconductor memory technologies. First, it consumes less standby power because it does not require a continuous power supply like DRAM. Second, it contributes to improved system performance by enabling data reading and writing at much faster speeds than NAND flash. Third, it boasts high durability due to minimal cell wear, making it suitable for use as a long-lasting memory solution. Thanks to these characteristics, MRAM is increasingly being adopted in embedded systems, industrial IoT, and automotive electronics.

[0005] As a next-generation memory technology, MRAM has significant potential for application across various fields. Currently utilized in some high-performance computing systems and the embedded memory market, it is expected to play a crucial role in the fields of artificial intelligence (AI) and edge computing in the future. In particular, MRAM’s high speed and low power consumption can contribute to energy savings in battery-powered mobile devices and data centers. Furthermore, the ease of mass production due to the ability to utilize existing semiconductor processes serves as an industrial advantage. As materials and process technologies advance, MRAM is highly likely to establish itself as a next-generation memory capable of replacing DRAM and NAND. Prior art literature

[0006] Korean Patent Publication No. 10-1158721 (June 15, 2012) The problem to be solved

[0007] The objective of the present invention is to provide a bitline-source line voltage sensing circuit for optimizing write termination of an MRAM by detecting voltage changes between BL and SL in real time during an MRAM write operation and performing optimal termination.

[0008] Other unspecified objects of the present invention may be further considered to the extent that they can be easily inferred from the following detailed description and effects. means of solving the problem

[0009] A bitline-sourceline voltage sensing circuit according to one embodiment of the present invention for achieving the above-described purpose may include, in a voltage sensing circuit of an MRAM, a first capacitor connected to a bitline of the MRAM to capacitively couple a voltage change of the bitline to a first node; and a second capacitor connected to a sourceline of the MRAM to capacitively couple a voltage change of the sourceline to a second node.

[0010] Herein, it is characterized by further including a first switch element connected to a first node and charging the first node according to operation.

[0011] Herein, it is characterized by further including a second switch element connected between a third node and ground (GND) that is connected to the first switch element and provides an output signal of the voltage sensing circuit to the outside.

[0012] Herein, it is characterized by further including a sixth switch element connected between the first node and the third node.

[0013] Herein, it is characterized by further including a third switch element that connects the first node and ground and is connected to the second node.

[0014] Herein, it is characterized by further including a fourth switch element connecting the first node and the second node.

[0015] Here, it is characterized by further including a fifth switch element connecting the second node and ground.

[0016] Here, the output signal from the third node is activated when the voltage of the first node drops below the trip voltage (VTRIP) of the first switch element or the second switch element.

[0017] A resistive memory device according to one embodiment of the present invention for achieving the above-described purpose comprises: a resistive memory cell; a source line connected to one end of the resistive memory cell; a bit line connected to the other end of the resistive memory cell; and a bit line-source line voltage sensing circuit connected to the source line and the bit line, wherein the bit line-source line voltage sensing circuit may include: a first capacitor connected to the bit line to capacitively couple a voltage change of the bit line to a first node; and a second capacitor connected to the source line to capacitively couple a voltage change of the source line to a second node.

[0018] Here, the resistive memory cell is characterized by including an MRAM (Magnetic Random Access Memory) cell. Effects of the invention

[0019] As described above, according to one embodiment of the present invention, by providing a bitline-source line voltage sensing circuit for optimizing write termination of MRAM, voltage changes between BL and SL are detected in real time during an MRAM write operation to perform optimal termination, thereby reducing unnecessary current consumption and improving termination reliability, which enables high power efficiency and accurate write termination compared to conventional methods. As a result, the write speed and data stability of MRAM are improved, and excellent performance can be expected even in high-speed memory environments.

[0020] Even if an effect is not explicitly mentioned herein, the effects and potential effects described in the following specification expected by the technical features of the present invention are treated as described in the specification of the present invention. Brief explanation of the drawing

[0021] Figure 1 is a diagram illustrating the write operation of MRAM. Figure 2 is a diagram showing the Resistance Monitoring Write Termination structure of the Real-time Detection-Based Resistance Monitoring Write Termination (RM-WT) method of MRAM. Figure 3 is a graph showing the timing diagram of the RM-WT circuit. FIG. 4 is a diagram showing a bitline-source line voltage sensing circuit for optimizing write termination of an MRAM according to one embodiment of the present invention. FIG. 5 is a diagram illustrating the coupling operation of a capacitor included in a bitline-source line voltage sensing circuit for optimizing write termination of an MRAM according to one embodiment of the present invention. FIG. 6 is a diagram showing the operation process of a bitline-source line voltage sensing circuit for optimizing write termination of an MRAM according to one embodiment of the present invention. FIG. 7 is a diagram showing the write pulse waveform when the bitline-source line voltage sensing circuit for optimizing write termination of an MRAM according to one embodiment of the present invention is not applied and when it is applied. FIG. 8 is a table comparing the performance of a bitline-source line voltage sensing circuit for optimizing write termination of an MRAM according to one embodiment of the present invention with and without application. Specific details for implementing the invention

[0022] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The advantages and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the attached drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Unless otherwise defined, all terms used in this specification (including technical and scientific terms) may be used in a meaning that is commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0023] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, terms such as “have,” “may have,” “include,” or “may include” are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Terms including ordinal numbers, such as “second,” “first,” etc., may be used to describe various components, but said components are not limited by said terms.

[0024] The above terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items.

[0025] In this specification, identification symbols (e.g., a, b, c, etc.) for each step are used for convenience of explanation and do not indicate the order of the steps; the steps may occur differently from the specified order unless the context clearly indicates a specific order. That is, the steps may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

[0026] Figure 1 is a diagram illustrating the write operation of MRAM.

[0027] MRAM (Magnetoresistive Random Access Memory) stores data using the Spin-Transfer Torque (STT) method and operates by switching the state of the MTJ (Magnetic Tunnel Junction) by applying current. In Figure 1, Write 0 sets BL to VDD and SL to GND, and Write 1 sets BL to GND and SL to VDD, thereby changing the state of the MTJ.

[0028] If unnecessary current persists even after MTJ switching is complete, it can lead to power waste and reduced device reliability. To prevent this, a write termination technique is required; however, existing fixed-time-based termination methods have limitations in that unnecessary write pulses are maintained even after MTJ switching is complete. To address this, a more precise real-time write termination method is required.

[0029] Figure 2 is a diagram showing the Resistance Monitoring Write Termination structure of the MRAM's real-time sensing-based Resistance Monitoring Write Termination (RM-WT) method. Figure 3 is a graph showing the timing diagram of the RM-WT circuit.

[0030] The RM-WT method performs termination by detecting a change in the resistance of the MTJ. As shown in Fig. 2, it generates an output signal (OUT_D) by comparing the voltage of BL or SL with a reference voltage (VREF). When OUT_D is activated, a WD signal is generated through a logic gate, which is used to terminate the write pulse. This reduces unnecessary write pulses and decreases power consumption, and enables more efficient termination than the existing time-based termination method.

[0031] However, since the existing RM-WT method performs termination by detecting only a single node of either BL or SL, the accuracy of the termination timing may be reduced, as shown in Fig. 3. Because OUT_D changes and termination occurs only after a certain amount of time has passed following the switching of the MTJ, there is a limitation in that the interaction of voltage changes between BL and SL cannot be considered. To compensate for this, a method that simultaneously detects voltage changes in BL and SL is required, which enables more accurate termination and improves power efficiency.

[0032] Various embodiments of a bitline-source line voltage sensing circuit for optimizing write termination of an MRAM according to the present invention will be described in detail below with reference to the attached drawings.

[0033] The present invention relates to an MRAM write termination circuit that performs accurate termination by detecting voltage changes between the BL and SL during MTJ switching. The present invention relates to a sensing circuit for optimizing the write termination of an MRAM. Accurate termination is critical in the write operation of an MRAM, and to this end, a method that simultaneously detects voltage changes between the BL (Bit Line) and SL (Source Line) is required. Existing termination methods used time-based termination or single-node sensing, which limited accuracy. In the present invention, by configuring a circuit that performs termination by simultaneously detecting voltage changes between the BL and SL, unnecessary power consumption is reduced and the write reliability of the MRAM is improved.

[0034] FIG. 4 is a diagram showing a bitline-source line voltage sensing circuit for optimizing write termination of an MRAM according to one embodiment of the present invention.

[0035] Referring to FIG. 4, a bitline-sourceline voltage sensing circuit (100) for optimizing write termination of an MRAM may include a first capacitor (C1, 111) connected to the bitline (Bitline, BL) of the MRAM to capacitively couple a voltage change of the bitline to a first node (LBL, 121), and a second capacitor (C2, 112) connected to the sourceline (Sourceline, SL) of the MRAM to capacitively couple a voltage change of the sourceline to a second node (LSL, 122).

[0036] The bitline-source line voltage sensing circuit (100) for optimizing the write termination of the MRAM may further include a first switch element (M1, 131) connected to a first node (121) and charging the first node (121) according to operation.

[0037] The bitline-source line voltage sensing circuit (100) for optimizing the write termination of the MRAM may further include a second switch element (M2, 132) connected between a third node (123) that is connected to the first switch element (131) and provides an output signal (OUT_D signal) of the voltage sensing circuit to the outside and ground (GND).

[0038] The bitline-source line voltage sensing circuit (100) for optimizing the write termination of the MRAM may further include a sixth switch element (B, 136) connected between the first node (121) and the third node (123).

[0039] The bitline-source line voltage sensing circuit (100) for optimizing the write termination of the MRAM may further include a third switch element (M3, 133) connected between the first node (121) and ground and connected to the second node (122).

[0040] The bitline-source line voltage sensing circuit (100) for optimizing the write termination of the MRAM may further include a fourth switch element (C, 134) connecting between the first node (121) and the second node (122).

[0041] The bitline-source line voltage sensing circuit (100) for optimizing the write termination of the MRAM may further include a fifth switch element (A, 135) connecting the second node (122) and ground.

[0042] A bitline-source line voltage sensing circuit (100) for optimizing the write termination of an MRAM can activate an output signal from a third node (123) when the voltage of the first node (121) drops below the trip voltage (VTRIP) of the first switch element (M1, 131) or the second switch element (M2, 132).

[0043] The bitline-source line voltage sensing circuit (100) for optimizing the write termination of the MRAM illustrated in FIG. 4 may be included in a resistive memory device.

[0044] A resistive memory device may include a resistive memory cell, a source line connected to one end of the resistive memory cell, a bit line connected to the other end of the resistive memory cell, and a bit line-source line voltage sensing circuit connected to the source line and the bit line.

[0045] Resistive memory cells may include MRAM (Magnetic Random Access Memory) cells.

[0046] Among the various components illustrated exemplarily in FIG. 4, some components may be omitted or additional components may be included.

[0047] FIG. 5 is a diagram illustrating the coupling operation of a capacitor included in a bitline-source line voltage sensing circuit for optimizing write termination of an MRAM according to one embodiment of the present invention.

[0048] This circuit is designed to perform write termination by detecting voltage changes in BL and SL in real time. As shown in FIG. 4, when MTJ switching occurs, the voltages of BL and SL change, and LBL and LSL are utilized to effectively detect this. Additionally, by applying coupling capacitors (C1, C2) to couple the voltage changes of BL and SL to LBL and LSL, the voltage changes necessary for termination determination can be sensed.

[0049] As shown in Fig. 5, voltage changes in BL and SL are reflected in LBL and LSL through C1 and C2, thereby enabling more precise termination. This reduces unnecessary power consumption and improves the write reliability of the MRAM.

[0050] FIG. 6 is a diagram showing the operation process of a bitline-source line voltage sensing circuit for optimizing write termination of an MRAM according to one embodiment of the present invention.

[0051] Regarding the initial state and voltage changes due to MTJ switching, in the circuit of FIG. 4, in the initial state, the LSL voltage is set to the threshold voltage (VTHN) of M3, and the LBL voltage is set to the VTRIP of the M1 and M2 inverters. Subsequently, as shown in FIG. 6, when MTJ switching occurs, the BL voltage decreases and the SL voltage increases, and this change is coupled to and reflected in LBL and LSL through C1 and C2. Through this, the LBL voltage gradually decreases, and termination is performed when it falls below VTRIP.

[0052] Figure 6 shows the detailed process of the WRITE TERMINATION operation. In the initial state, LBL is set to 0V and LSL is also set to 0V. Subsequently, LBL is charged through the operation of M1, and the LSL voltage is set to VTHN through M3. At this time, the initial states of BL and SL maintain the set voltages, respectively, and form a standby state for termination.

[0053] When MTJ switching occurs, the BL voltage decreases and the SL voltage increases, and this voltage change is coupled to LBL and LSL through C1 and C2. During this process, the LBL voltage gradually decreases and the LSL voltage increases to adjust the reference value through M3. The moment the LBL voltage drops below VTRIP, termination is performed and the OUT_D signal is activated.

[0054] Regarding the performance of termination through the integration of the detection paths of BL and SL, the circuit operates by integrating two paths that detect BL and SL, respectively, to perform termination. In FIG. 4, voltage changes in BL and SL are detected through LBL and LSL, respectively, and information from the two detection paths is combined to generate a termination signal.

[0055] In the final step of Fig. 6, the output of the comparator changes when the LBL voltage becomes lower than VTRIP, and the VOUT_D signal rises. This signal activates the Write Done (WD) signal to perform termination, which enables more accurate termination than the conventional method and reduces unnecessary power consumption.

[0056] FIG. 7 is a diagram showing the write pulse waveform when the bitline-source line voltage sensing circuit for optimizing write termination of an MRAM according to one embodiment of the present invention is not applied and when it is applied.

[0057] Figure 7 shows a comparison of write pulse durations with and without a termination circuit. In the absence of a termination circuit, a preset write pulse is maintained even after MTJ switching, resulting in unnecessary power consumption. On the other hand, when a termination circuit is applied, voltage changes between BL and SL are detected in real time, and termination is performed immediately after MTJ switching, causing the write pulse to terminate early. This prevents unnecessary write pulses, thereby improving power efficiency.

[0058] FIG. 8 is a table comparing the performance of a bitline-source line voltage sensing circuit for optimizing write termination of an MRAM according to one embodiment of the present invention with and without application.

[0059] Figure 8 shows the results of comparing the retention yield, termination yield, energy consumption, and energy reduction of the proposed circuit with the VT-VEW and SDWT methods. Retention yield is an indicator used to evaluate data retention characteristics, and the proposed circuit recorded superior values ​​of 10.6σ and 9.62σ at Write '0' and Write '1', respectively, compared to the existing methods, confirming that data stability has been improved.

[0060] Termination yield is an indicator that evaluates the accuracy of termination, and the proposed circuit showed higher values ​​than the existing method, with 30.05σ at Write '0' and 4.63σ at Write '1', confirming that more precise termination is possible.

[0061] In terms of energy consumption, the proposed circuit consumes 1.86 pJ and 2.87 pJ of energy in Write '0' and Write '1', respectively, showing much lower power consumption than the VT-VEW method (1.92 pJ) and SDWT method (5.09 pJ and 10.4 pJ). In particular, the energy reduction analysis results showed a power saving effect of 59.2% in Write '0' and 4.4% in Write '1', confirming high energy efficiency compared to the existing SDWT method (346% in Write '1').

[0062] The present invention is a circuit that performs accurate termination by detecting voltage changes between the BL and SL in real time during MTJ switching in an MRAM write operation. Conventional termination methods had limitations in that a fixed write pulse was maintained, resulting in unnecessary power consumption and low termination reliability. By simultaneously detecting voltage changes between the BL and SL and optimizing the termination timing, this circuit can prevent unnecessary current application and minimize power consumption. This improves the reliability of the write operation and enhances the termination yield, enabling more precise write termination compared to conventional methods. Furthermore, by improving the write speed of the MRAM and maximizing power efficiency through optimized termination, excellent performance is expected even in memory environments requiring high-speed operation.

[0063] This technology can be applied to high-performance, low-power memory applications such as MRAM-based cache memory and low-power embedded systems. In particular, it plays a role in maximizing power efficiency and improving reliability in systems requiring fast data access, and can be utilized in various fields demanding high-speed computation and real-time data processing.

[0064] Furthermore, this technology has the potential to be partially applied to various advanced devices, such as smartphones, wireless earphones, IoT home appliances, high-performance computers, and autonomous vehicles. In these products, it is crucial to maintain high performance while minimizing power consumption; utilizing MRAM's optimized write termination technology can contribute to extending battery life and enhancing system stability.

[0065] Recently, the utilization of non-volatile memory (MRAM) has been increasing due to the proliferation of cutting-edge systems, including high-performance computers and smartphones. Furthermore, alongside the advancement of AI and edge computing, the demand for low-power, high-speed MRAM is expanding. In particular, the practicality of MRAM in AI accelerators and autonomous driving systems is garnering attention, and it is emerging as a next-generation memory technology to complement the limitations of existing DRAM and NAND memory. Consequently, the importance of write termination technology, which guarantees low power consumption and high reliability, is growing.

[0066] Although it is described that all components constituting the embodiments of the present invention described above are combined or operate in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all such components may be selectively combined in one or more ways to operate. Furthermore, while all such components may each be implemented as a single independent piece of hardware, they may also be implemented as a computer program having a program module that performs some or all of the combined functions in one or more pieces of hardware by selectively combining some or all of the components. Additionally, such a computer program may be stored on a computer-readable media such as a USB memory, CD disk, or flash memory, and read and executed by a computer to implement the embodiments of the present invention. Magnetic recording media, optical recording media, etc., may be included as recording media for the computer program.

[0067] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications, changes, and substitutions within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention and the accompanying drawings are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments and accompanying drawings. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0068] 100: Bitline-Sourceline Voltage Sensing Circuit 111: First capacitor 112: Second capacitor 121: Node 1 122: Node 2

Claims

Claim 1 A bitline-sourceline voltage sensing circuit comprising: a first capacitor connected to a bitline of the MRAM to capacitively couple a voltage change of the bitline to a first node; and a second capacitor connected to a sourceline of the MRAM to capacitively couple a voltage change of the sourceline to a second node. Claim 2 A bitline-source line voltage sensing circuit according to claim 1, further comprising a first switch element connected to a first node and charging the first node according to operation. Claim 3 A bitline-source line voltage sensing circuit according to claim 2, further comprising: a second switch element connected between a third node and ground (GND) which is connected to the first switch element and provides an output signal of the voltage sensing circuit to the outside. Claim 4 A bitline-source line voltage sensing circuit characterized by further including, in paragraph 3, a sixth switch element connected between the first node and the third node. Claim 5 A bitline-source line voltage sensing circuit according to claim 1, further comprising a third switch element connecting between the first node and ground and connected to the second node. Claim 6 A bitline-source line voltage sensing circuit characterized by further including, in claim 1, a fourth switch element connecting the first node and the second node. Claim 7 A bitline-source line voltage sensing circuit according to claim 1, further comprising a fifth switch element connecting the second node and ground. Claim 8 A bitline-source line voltage sensing circuit according to claim 3, characterized in that when the voltage of the first node drops below the trip voltage (VTRIP) of the first switch element or the second switch element, an output signal from the third node is activated. Claim 9 A resistive memory device comprising: a resistive memory cell; a source line connected to one end of the resistive memory cell; a bit line connected to the other end of the resistive memory cell; and a bit line-source line voltage sensing circuit connected to the source line and the bit line, wherein the bit line-source line voltage sensing circuit comprises: a first capacitor connected to the bit line to capacitively couple a voltage change of the bit line to a first node; and a second capacitor connected to the source line to capacitively couple a voltage change of the source line to a second node. Claim 10 A resistive memory device according to claim 9, wherein the resistive memory cell comprises a Magnetic Random Access Memory (MRAM) cell. Claim 11 A resistive memory device according to claim 9, further comprising a first switch element connected to a first node and charging the first node according to operation. Claim 12 A resistive memory device according to claim 11, further comprising: a second switch element connected between a third node and ground (GND) which is connected to the first switch element and provides an output signal of the voltage sensing circuit to the outside. Claim 13 A resistive memory device characterized by further including, in claim 12, a sixth switch element connected between the first node and the third node. Claim 14 A resistive memory device according to claim 12, characterized in that when the voltage of the first node drops below the trip voltage (VTRIP) of the first switch element or the second switch element, an output signal from the third node is activated. Claim 15 A resistive memory device according to claim 9, further comprising a third switch element that connects the first node and ground and is connected to the second node.

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