Display apparatus

Abstract

A display device according to the present specification may include a display area disposed on a substrate and comprising a plurality of pixels, a first area disposed in the display area and comprising a hole, a second area disposed in the inner side of the hole and comprising a plurality of dummy pixels comprising an organic pattern, a first insulating layer disposed below the organic pattern, a second insulating layer disposed above the organic pattern, a reflection pattern disposed on the second insulating layer corresponding to each dummy pixel, and a plurality of signal link wires extending from one side of the hole through the second area to the other side of the hole area.

Description

Technology Field

[0001] This specification relates to a display device. Background Technology

[0002] Display devices are applied to various electronic devices such as TVs, smartphones, laptops, and tablets. To this end, research is continuously being conducted to develop thinner, lighter, and lower power consumption display devices.

[0003] Examples of display devices include Liquid Crystal Display apparatus (LCD), Field Emission Display apparatus (FED), and Organic Light Emitting Display apparatus (OLED).

[0004] The bezel area of ​​a display device may include an area surrounding the outer edge of the display area on the display panel. The bezel area can protect the edges of the display panel and internal electronic components from external shock, pressure, or damage. Meanwhile, the bezel area is visible to the user and may be a factor that reduces the sense of immersion regarding the image emitted from the display area.

[0005] Accordingly, there has recently been an increasing demand for display devices that implement a narrow bezel, which reduces the bezel area where the screen is not displayed, or a zero bezel, which has the effect of having virtually no bezel area. The problem to be solved

[0006] The problem to be solved according to the embodiments of the present specification is to provide a display device capable of preventing a decrease in transmittance caused by gate link wiring and data link wiring introduced into a hole area.

[0007] The problem to be solved according to the embodiments of the present specification is to provide a display device that prevents only the hole area from being visible during the operation of turning the display panel on or off, thereby preventing a decrease in the immersion of the screen.

[0008] In addition, the problem to be solved according to the embodiments of the present specification is to provide a display device capable of preventing an external light source from being reflected and emitted from the display device.

[0009] In addition, the problem to be solved according to the embodiments of the present specification is to provide a display device that can reduce signal transmission distance to prevent signal delay and enable low-power operation, thereby reducing power consumption.

[0010] The problems solved according to one embodiment of this specification are not limited to the purposes mentioned above, and other unmentioned purposes and advantages of the present invention may be understood from the following description and will be more clearly understood by the embodiments of this specification. Furthermore, it will be readily apparent that the purposes and advantages of this specification can be realized by the means and combinations thereof set forth in the claims. means of solving the problem

[0011] A display device according to one embodiment of the present specification may include a display area disposed on a substrate and comprising a plurality of pixels, a first area disposed in the display area and comprising a hole, a second area disposed in the inner side of the hole and comprising a plurality of dummy pixels comprising an organic pattern, a first insulating layer disposed below the organic pattern, a second insulating layer disposed above the organic pattern, a reflection pattern disposed on the second insulating layer corresponding to each dummy pixel, and a plurality of signal link wires extending from one side of the hole through the second area to the other side of the hole area. Effects of the invention

[0012] In the display device according to the embodiment of the present specification, dummy subpixels having the same shape as the subpixels on the display area may be disposed in the hole area. Accordingly, since the hole area is not visible during the operation of turning the display panel on or off, a decrease in screen immersion can be prevented.

[0013] In a display device according to an embodiment of the present specification, gate link wiring and data link wiring may be arranged to overlap with dummy subpixels placed in a hole area in the upper and lower directions. Accordingly, the display device according to an embodiment of the present specification can prevent a reduction in transmittance in the hole area.

[0014] In a display device according to an embodiment of the present specification, gate link wiring and data link wiring may be arranged to cross a hole area without bypassing it. As a result, the signal transmission path of the gate link wiring and data link wiring may be reduced. Accordingly, the hole bezel area in a display device according to an embodiment of the present specification may be further reduced or eliminated.

[0015] In the display device according to the embodiment of the present specification, external light reflection can be reduced by means of an extinction interference effect, etc., by placing a reflection pattern in the hole area.

[0016] In the display device according to the embodiment of the present specification, the signal transmission path can be shortened by arranging the gate link wiring and the data link wiring to cross the hole area. Accordingly, the display device according to the embodiment of the present specification can be operated at low power by reducing signal delay. As a result, the display device according to the embodiment of the present specification has the effect of reducing power consumption.

[0017] The effects of this specification are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below. Brief explanation of the drawing

[0018] FIG. 1 is a plan view of a display panel according to embodiments of the present specification. FIG. 2 is a drawing showing a wearable display device including a display panel according to embodiments of the present specification. Figure 3 is a drawing showing an enlarged view of area I of Figure 1. Figure 4 is a cross-sectional view along line II-II' of Figure 3. FIGS. 5 to 8 are drawings according to an embodiment of the present specification. FIG. 9 is a drawing according to another embodiment of the present specification. FIGS. 10 to 12 are drawings according to another embodiment of the present specification. FIG. 13 is a drawing according to another embodiment of the present specification. FIG. 14 is a diagram showing the operation of a display panel according to an embodiment of the present specification. Specific details for implementing the invention

[0019] The advantages and features of this specification and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below but may be implemented in various different forms, and these embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention.

[0020] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary and are not limited to the depicted items. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing this specification, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of this specification, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0021] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0022] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0023] In the case of an explanation of a temporal relationship, for example, when a temporal sequence is explained using 'after', 'following', 'next', 'before', etc., it may include cases where the sequence is not continuous unless 'immediately' or 'directly' is used.

[0024] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this specification.

[0025] The features of each of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0026] Hereinafter, a display device according to each embodiment of the present invention will be described with reference to the attached drawings.

[0028] FIG. 1 is a plan view of a display panel according to embodiments of the present specification.

[0029] Referring to FIG. 1, a display device according to an embodiment of the present specification may include a display panel (200), a printed circuit board (104), a driving circuit chip (103), and a control circuit chip (105), etc.

[0030] The display panel (200) may include a display area (AA) and a non-display area (NAA). The display area (AA) is an area where an image is displayed, and a plurality of pixels (P), data lines (DL), and gate lines (GL) may be arranged therein. The non-display area (NAA) may be an area where an image is not displayed. The non-display area (NAA) may be located in the peripheral area (or border area) of the display panel (200), but is not limited thereto. For example, the remaining area on the display area (AA), excluding the light-emitting area where light is emitted outwardly, may be referred to as the non-display area (NAA). The bezel area of ​​the display device may be defined by the non-display area (NAA). The bezel area may surround the outer side of the display area (AA).

[0031] Wiring may be arranged in the non-display area (NAA) to provide an electrical signal to the display area (AA) or to receive an electrical signal from the display area (AA). For example, a gate driver (101) that supplies a gate signal to a plurality of subpixels (SP1, SP2, SP3) of the display area (AA) may be arranged in the non-display area (NAA). The gate driver (101) may be arranged at the right and left edges of the non-display area (NAA) in a GIP (Gate In Panel) manner. The gate driver (101) may transmit the gate signal through gate wiring (GL).

[0032] A pad area in which a driving circuit chip (103) and a plurality of pads are disposed may be included in one edge portion of the non-display area (NAA). The driving circuit chip (103) can transmit data signals to a plurality of subpixels (SP1, SP2, SP3) through a plurality of data lines (DL) of the display area (AA). For example, the driving circuit chip (103) may be a data driving circuit chip, but is not limited thereto.

[0033] Gate wiring (GL) can be extended in a first direction (X) of the display panel (200), and data wiring (DL) can be extended in a second direction (Y) of the display panel (200) intersecting with gate wiring (GL).

[0034] The display panel (200) may be composed of a flexible material. Accordingly, a portion of the display panel (200) may be bent so that the printed circuit board (104) on which the control circuit chip (105) is placed faces the back of the display area (AA) of the display panel (200). Accordingly, the lower non-display area of ​​the display device (1) perceived from the front of the display device (1) is reduced, and the bezel area may be further reduced. The control circuit chip (105) can control the driving circuit chip (103) and the gate driver.

[0035] The display area (AA) may include a plurality of pixels (P) and a hole area (H). The hole area (H) may be an area where electronic components are placed. For example, the electronic components may include a camera module for taking photos or videos in a smartphone or watch phone, or various sensor devices for detecting external objects. The sensor devices may include at least one of a proximity sensor, a gesture sensor, a color sensor, a biometric sensor, and an infrared sensor, but are not limited thereto.

[0036] A single pixel (P) may be composed of multiple subpixels (SP1, SP2, SP3). An image can be displayed in a display area (AA) through the multiple subpixels (SP1, SP2, SP3). The multiple subpixels (SP1, SP2, SP3) may be arranged in an array on the display area (AA). In one example, the multiple subpixels (SP1, SP2, SP3) may be arranged in a matrix-type array spaced apart from each other in a first direction of the display area (AA) and a second direction intersecting the first direction. The first direction may be a horizontal direction, an X-axis direction, or a row direction, and the second direction may be a vertical direction, a Y-axis direction, or a column direction. However, this is not limited thereto, and the arrangement shape, arrangement order, and arrangement direction of the subpixels (SP1, SP2, SP3) may be varied. The subpixels (SP1, SP2, SP3) will be described later in FIG. 3.

[0037] In this specification, one embodiment is described in which a pixel (P) is composed of a first subpixel (SP1), a second subpixel (SP2), and a third subpixel (SP3), but is not limited thereto. For example, additional subpixels may be included in the pixel (P).

[0038] Each subpixel (SP1, SP2, SP3) may be implemented to emit light of the same color for each subpixel, such as white light, or may be implemented to emit light of a different color for each subpixel, such as red, green, or blue light. For example, the first subpixel (SP1) may be implemented as red, the second subpixel (SP2) as green, and the third subpixel (SP3) as blue.

[0039] FIG. 2 is a drawing showing a wearable device including a display panel according to an embodiment of the present specification.

[0040] Referring to FIG. 2, a wearable device (100) according to an embodiment of the present specification may include a display panel (200), a frame portion (20), and a strap portion (30). In one example, the wearable device (100) may include a smart watch phone. The frame portion (20) may be a structure assembled to form the exterior of the wearable device (100). The display portion may be placed in the space formed by the frame portion (20). The display portion may include a display panel (200) including a display area (AA) and a hole area (H). The display area (AA) may be visible from the front of the wearable device (100). The display area (AA) may include a plurality of pixels (P) and a hole area (H). The hole area (H) may be an area where electronic components are placed. For example, the electronic components may include a camera or a sensor device. The strap portion (30) may be a part for wearing and securing the wearable device (100).

[0041] FIG. 3 is a drawing showing an enlarged view of region I of FIG. 1. FIG. 3 may be a region including a hole region (H).

[0042] Referring to FIGS. 1 and 3, the display area (AA) of the display panel (200) may include a first area surrounding the hole area (H), the hole area (H), and a second area disposed inside the hole area (H). The hole area (H) may have a closed curve shape when viewed from a plane. For example, the hole area (H) may have a circular shape.

[0043] A first region surrounding a hole area (H) may be arranged with pixels (P) including a plurality of subpixels (SP1, SP2, SP3). A single pixel (P) may include a first subpixel (SP1), a second subpixel (SP2), and a third subpixel (SP3). For example, when viewed from a plane, the first subpixels (SP1) may be arranged spaced apart from each other in a first direction (X), which is the horizontal direction of the display area (AA). The second subpixels (SP2) may be spaced apart from each other in a second direction (Y), which is the vertical direction of the plurality of first subpixels (SP1), and arranged in the same row direction. Additionally, the third subpixels (SP3) may be arranged spaced apart from each other in a second direction (Y), which is the vertical direction of the display area (AA), and spaced apart from each other in a first direction (X), which is the horizontal direction of the plurality of first subpixels (SP1). The pixels (P) can be electrically connected to the gate link wiring (400) and the data link wiring (300).

[0044] A plurality of dummy pixels (DP) may be disposed in the second region. A single dummy pixel (DP) may include a plurality of dummy subpixels (DSP-1, DSP-2, DSP-3). The plurality of dummy subpixels (DSP-1, DSP-2, DSP-3) may include a first dummy subpixel (DSP-1), a second dummy subpixel (DSP-2), and a third dummy subpixel (DSP-3). Each of the first dummy subpixel (DSP-1), the second dummy subpixel (DSP-2), and the third dummy subpixel (DSP-3) may be configured with the same shape as the first subpixel (SP1), the second subpixel (SP2), and the third subpixel (SP3), respectively. Accordingly, a single dummy pixel (DP) may be configured with the same shape as a single pixel (P).

[0045] For example, when viewed from a plane, the first dummy subpixels (DSP-1) may be arranged spaced apart from each other in the first direction (X), which is the horizontal direction of the display area (AA). The second dummy subpixels (DSP-2) may be spaced apart from each other in the second direction (Y), which is the vertical direction of the plurality of first dummy subpixels (DSP-1), and arranged in the same row direction. Additionally, the third dummy subpixels (DSP-3) may be arranged spaced apart from each other in the second direction (Y), which is the vertical direction of the display area (AA), and spaced apart from each other in the first direction (X), which is the horizontal direction of the plurality of first dummy subpixels (DSP-1).

[0046] A first area in which a plurality of pixels (P) are arranged may be a display area (AA) in which an image is displayed when a driving current is applied. A second area in which a plurality of dummy pixels (DP) are arranged may be a non-display area (NAA) in which an image is not displayed because no light is emitted even when a driving current is applied.

[0047] A plurality of gate link wirings (400) and a plurality of data link wirings (300) may be disposed on a first region surrounding a hole region (H), the hole region (H), and a second region disposed inside the hole region (H). For example, the first region may include a first-1 region disposed on one side with the hole region (H) in between and a first-2 region disposed on the other side.

[0048] A plurality of gate link wires (400) may include a first gate link wire (400-1), a second gate link wire (400-2), a third gate link wire (400-3), and an nth gate link wire (400-n) (n is a natural number). Each gate link wire (400-1, 400-2, 400-3, 400-n) (n is a natural number) may extend along a horizontal direction (or horizontal direction), which is the first direction (X) of the display area (AA). A plurality of data link wires (300) may extend in a direction intersecting the plurality of gate link wires (400). For example, each data link wire (300-1, 300-2, 300-3, 300-n) (n is a natural number) may extend along a vertical direction (or vertical direction), which is the second direction (Y) of the display area (AA).

[0049] For example, a plurality of gate link wires (400) may extend from the first-1 region across the hole to the first-2 region. Since the plurality of gate link wires (400) do not bypass the hole region (H), they may be arranged in a straight line shape. For example, a plurality of data link wires (300) may extend from the first-1 region across the hole to the first-2 region. Since the plurality of data link wires (300) do not bypass the hole region (H), they may be arranged in a straight line shape. As the plurality of gate link wires (400) and data link wires (300) are configured in a straight line shape, the signal path can be simplified. Accordingly, the signal transmission path is shortened, and signal delay can be reduced. Reducing signal delay prevents unnecessary power consumption and allows the display panel to be driven at low power. Therefore, a display device capable of reducing power consumption can be provided. In addition, since the plurality of gate link wires (400) and data link wires (300) are configured in a straight line shape without bypassing the hole area (H), the bezel area in the hole area can be further reduced. Furthermore, since the plurality of gate link wires (400) and data link wires (300) are configured in a straight line shape, the signal transmission path is shortened, which can reduce signal loss. Accordingly, since the signal transmission path is stably formed, the operational stability of the display device can be improved.

[0050] A plurality of gate link wirings (400) and data link wirings (300) may be arranged to overlap with at least one of the plurality of dummy subpixels (DSP-1, DSP-2, DSP-3) among the plurality of dummy subpixels (DSP-1, DSP-2, DSP-3) arranged inside the hole region (H) so as to prevent a decrease in transmittance. For example, a plurality of gate link wirings (400) and data link wirings (300) may be arranged to overlap in the upper and lower directions with organic patterns arranged corresponding to each of the plurality of dummy subpixels (DSP-1, DSP-2, DSP-3) so as to prevent a decrease in transmittance.

[0051] FIG. 4 is a cross-sectional view along line II-II' of FIG. 3. FIG. 4 schematically shows one subpixel. For convenience of explanation, one subpixel is described as an example in this specification, but is not limited thereto.

[0052] Referring to FIG. 4, the display panel (200) may include a pixel driving circuit comprising a plurality of transistors (220, 240) disposed on a substrate (201), a light-emitting element (260), and a touch sensor unit (287).

[0053] A single subpixel may include a light-emitting element (260) and a pixel driving circuit that applies a driving current to the light-emitting element (260). The pixel driving circuit is disposed on a substrate (201), and the light-emitting element (260) is disposed on the pixel driving circuit. The pixel driving circuit may include a plurality of transistors (220, 240) and a storage capacitor (230). In one example, the plurality of transistors (220, 240) may include a first transistor (220) and a second transistor (240).

[0054] The substrate (201) may be a flexible plastic substrate. If the substrate (201) is a plastic film, it may include multiple layers of insulating material. For example, the substrate (201) may include a first base layer (202), a second base layer (203), and a support layer (204). The first base layer (202) and the second base layer (203) may be spaced apart from each other at the top and bottom, and the support layer (204) may be placed between them.

[0055] A multi-buffer layer (207) may be disposed on a substrate (201). The multi-buffer layer (207) may be a structure in which a first buffer layer (205) and a second buffer layer (206) are disposed above and below. The first buffer layer (205) and the second buffer layer (206) may cover the surface of the substrate (201). The first buffer layer (205) and the second buffer layer (206) may reduce or prevent the penetration of moisture, oxygen, or impurities through the substrate (201). The first buffer layer (205) and the second buffer layer (206) may be a single layer or a multi-layer made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0056] A light-shielding layer (209) may be disposed on the multi-buffer layer (207). The light-shielding layer (209) can block external light incident on the transistor. To this end, the light-shielding layer (209) may include an opaque metallic material. A first metal pattern (209a) may be disposed on the multi-buffer layer (207) spaced apart from the light-shielding layer (209). The first metal pattern (209a) may be formed from the same material as the light-shielding layer (209) in the same process.

[0057] A third buffer layer (212) may be disposed on the light-shielding layer (209). The third buffer layer (212) may protect the transistor from moisture, oxygen, or impurities. The third buffer layer (212) may be a single layer or a multilayer made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. The third buffer layer (212) may cover the entire surface of the substrate (201).

[0058] A first transistor (220) may be disposed on the third buffer layer (212). The first transistor (220) may include a first semiconductor layer (221), a first gate insulating layer (222), a first gate electrode (223), and a first source / drain electrode (224). In one example, the first transistor (220) may be a switching transistor.

[0059] The first semiconductor layer (221) may include a channel region and a source / drain region. The region of the first semiconductor layer (221) that overlaps with the first gate electrode (223) in the upper and lower directions may be a channel region. The source / drain region may be disposed on each side of the channel region. For example, among the source / drain regions, the region disposed on one side of the channel region may be a source region, and the region disposed on the other side of the channel region may be a drain region. The first semiconductor layer (221) may be composed of one of a polysilicon semiconductor layer and a low-temperature polysilicon semiconductor layer, or a combination thereof. In one example, the first semiconductor layer (221) may include an oxide semiconductor layer. For example, the first semiconductor layer (221) may include at least one oxide semiconductor material such as indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO).

[0060] If the first semiconductor layer (221) is an oxide semiconductor layer, the first transistor (220) may be an oxide thin film transistor. In this case, the first transistor (220) may include a material identical to the functional structure constituting the second transistor (240). For example, it may include a material identical to each of the second semiconductor layer (241), second gate insulating layer (242), second gate electrode (243), and second source / drain electrode (245) constituting the second transistor (240). The first semiconductor layer (221) may be arranged to overlap the light shielding layer (209) in the upper and lower directions. The light shielding layer (209) can block external light incident on the first semiconductor layer (221). To this end, the light shielding layer (209) may be at least the same width as or greater than that of the first semiconductor layer (221).

[0061] A first gate insulating layer (222) may be disposed between the first semiconductor layer (221) and the first gate electrode (223). The first gate insulating layer (222) may extend outwardly while covering the first semiconductor layer (221). The first gate insulating layer (222) may be composed of a single layer or multiple layers of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0062] The first gate electrode (223) may be disposed on the first gate insulating layer (222). The first source / drain electrode (224) may be electrically connected to the first semiconductor layer (221) of the first transistor (220). In one example, the first source / drain electrode (224) may be referred to as the first input / output electrode. The first source / drain electrode (224) may be disposed on both sides with the first gate electrode (223) in between and may come into contact with the source region or drain region of the first semiconductor layer (221). For example, one of the first source / drain electrodes (224) may be a source electrode that comes into contact with the source region of the first semiconductor layer (221). For example, the other of the first source / drain electrodes (224) may be a drain electrode that comes into contact with the drain region of the first semiconductor layer (221). If the first transistor (220) is a switching transistor, the source electrode may be an input electrode into which a data signal provided from data lines (DL, see FIG. 1) is input. The drain electrode may transmit the data signal to the second transistor (240). The drain electrode may be an output electrode that transmits the data signal. A second metal pattern (223a) may be disposed on the first gate insulating layer (222) spaced apart from the first gate electrode (223). The second metal pattern (223a) may be formed in the same process with the same material as the first gate electrode (223). The second metal pattern (223a) may be disposed overlapping the first metal pattern (209a) in the upper and lower directions. A portion of the second metal pattern (223a) may penetrate the first gate insulating layer (222) and the third buffer layer (212) to be in direct contact with the first metal pattern (209a).

[0063] A lower interlayer insulating structure (215) may be disposed on the first gate electrode (223). The lower interlayer insulating structure (215) may include a first interlayer insulating layer (213) and a second interlayer insulating layer (214) disposed on the first interlayer insulating layer (213). The first interlayer insulating layer (213) may cover the first gate electrode (223). The first interlayer insulating layer (213) and the second interlayer insulating layer (214) may be a single layer or a multilayer made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0064] A third interlayer insulating layer (216) may be disposed on the second interlayer insulating layer (214). A third metal pattern (225) may be disposed at a different location spaced apart from the first transistor (220). The third metal pattern (225) may be disposed between the second interlayer insulating layer (214) and the third interlayer insulating layer (216). The third metal pattern (225) may include a transition metal material having hydrogen-friendly properties that have a hydrogen capture effect. For example, the third metal pattern (225) may include titanium (Ti). The third metal pattern (225) can prevent hydrogen from flowing into the second semiconductor layer (241) which contains an oxide semiconductor material. To this end, it is preferable that the third metal pattern (225) be formed with a size larger than the width of the second semiconductor layer (241). The threshold voltage characteristic of the second transistor (240) can be negatively shifted by the third metal pattern (225), thereby preventing current from flowing at a low gate voltage.

[0065] A fourth buffer layer (217) may be disposed on the third interlayer insulating layer (216). The fourth buffer layer (217) may protect the transistor from moisture, oxygen, or impurities. The fourth buffer layer (217) may be a single layer or a multilayer made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0066] A second transistor (240) may be disposed on the fourth buffer layer (217) at a different location spaced apart from the first transistor (220). The second transistor (240) may be electrically connected to the first transistor (220). For example, the second transistor (240) may include a second semiconductor layer (241), a second gate insulating layer (242), a second gate electrode (243), and a second source / drain electrode (245). In one example, the second transistor (220) may be a driving transistor electrically connected to the light-emitting element (260). However, FIG. 4 illustrates connection relationships, etc., to explain an example of a method of supplying driving current to the light-emitting element (260), and is not limited thereto. For example, another switching transistor or another light-emitting transistor may be further disposed between the light-emitting element (260) and the second transistor (240).

[0067] The second semiconductor layer (241) may include a channel region and a source / drain region. The region of the second semiconductor layer (241) that overlaps with the second gate electrode (243) in the up and down directions may be the channel region. The source / drain region may be disposed on each side of the channel region. The second semiconductor layer (241) may be composed of an oxide semiconductor layer. For example, the second semiconductor layer (241) may include at least one oxide semiconductor material such as indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO). In one example, the second semiconductor layer (241) may be disposed to overlap with the first metal pattern (209a), the second metal pattern (223a), and the third metal pattern (225) in the up and down directions. Accordingly, external light incident from outside the substrate (201) to the second semiconductor layer (241) can be blocked by the metal patterns (209a, 223a, 225). Thus, it is possible to prevent the characteristics of the second transistor (240) from changing due to external light.

[0068] A second gate insulating layer (242) may be disposed between the second semiconductor layer (241) and the second gate electrode (243). The second gate insulating layer (242) may be composed of a single layer or multiple layers of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0069] The first gate electrode (223) or the second gate electrode (243) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, it is not limited to these materials.

[0070] An upper interlayer structure (218, 219) may be disposed on the second gate electrode (243). The upper interlayer structure (218, 219) may include a fourth interlayer insulating layer (218) and a fifth interlayer insulating layer (219). The fourth interlayer insulating layer (218) and the fifth interlayer insulating layer (219) may be a single layer or a multilayer made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0071] The fourth interlayer insulating layer (218) may cover the second gate electrode (243). The storage capacitor (230) may include a first storage electrode (231) and a second storage electrode (233). For example, the first storage electrode (231) may be located on the same layer as the second gate electrode (243). For example, the first storage electrode (231) may be made of the same material as the second gate electrode (243). The first storage electrode (231) may be placed on the second gate insulating layer (242) at a different location spaced apart from the second gate electrode (243). The second storage electrode (233) may be placed on the fourth interlayer insulating layer (218) so as to overlap the first storage electrode (231) in the upper and lower directions.

[0072] The first storage electrode (231) and the second storage electrode (233) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, they are not limited to these materials. The second storage electrode (232) may be covered with a fifth interlayer insulating layer (219).

[0073] A first source / drain electrode (224) and a second source / drain electrode (245) may be disposed on the fifth interlayer insulating layer (219). The first source / drain electrode (224) may be connected by directly contacting the source / drain region of the first semiconductor layer (221) by penetrating the upper interlayer structure (218, 219), the fourth buffer layer (217), the third interlayer insulating layer (216), the lower interlayer structure (215), and the first gate insulating layer (222). The first source / drain electrode (224) may be disposed on both sides with the first gate electrode (223) in between.

[0074] The second source / drain electrode (245) can be connected by penetrating the upper interlayer structure (218, 219) and directly contacting the source / drain region of the second semiconductor layer (241), respectively. A portion of the second source / drain electrode (245) of the second transistor (240) can be electrically connected to the third metal pattern (225). For example, a portion of the second source / drain electrode (245) can be connected by penetrating the upper interlayer structure (218, 219), the second gate insulating layer (242), the fourth buffer layer (217), and the third interlayer insulating layer (216) and directly contacting the third metal pattern (225). In one example, the second source / drain electrode (245) may be referred to as the second input / output electrode. The second source / drain electrode (245) may be positioned on both sides with the second gate electrode (243) in between and may come into contact with the source region or drain region of the second semiconductor layer (241). For example, one of the second source / drain electrodes (245) may be a source electrode that comes into contact with the source region of the second semiconductor layer (241). For example, the other of the second source / drain electrodes (245) may be a drain electrode that comes into contact with the drain region of the second semiconductor layer (241). If the second transistor (2240) is a driving transistor, the source electrode may be an input electrode into which a data signal provided from the data lines (DL, see FIG. 1) is input. The drain electrode may deliver a driving current to the light-emitting element (260). The drain electrode may be an output electrode from which the driving current is emitted.

[0075] The first source / drain electrode (224) or the second source / drain electrode (245) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof, but is not limited thereto.

[0076] A passivation layer (247) may be disposed on the first source / drain electrode (224) or the second source / drain electrode (245). The passivation layer (247) may be a single layer or a multilayer, comprising an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride. The passivation layer (247) may protect the pixel driving circuit disposed underneath.

[0077] A flattening layer (250) may be disposed on the passivation layer (247). The flattening layer (250) can flatten the step difference caused by the lower pixel driving circuit. The flattening layer (250) may be disposed in a structure in which a plurality of flattening layers are stacked from bottom to top. For example, in the drawing, the flattening layer (250) is shown as having a structure in which a first flattening layer (251) and a second flattening layer (252) are stacked in the upper and lower directions, but it is not limited thereto. For example, a multilayer structure may be included in which a third flattening layer (not shown) is further stacked on the second flattening layer (252). For example, the flattening layer (250) may include an organic insulating material such as polyimide or acrylic resin.

[0078] A pixel contact electrode (255) may be disposed on the first flattening layer (250). The pixel contact electrode (255) may penetrate the first flattening layer (250) and the passivation layer (247) and directly contact the second source / drain electrode (245) of the second transistor (240).

[0079] A light-emitting element (260) may be formed on the flattening layer (250). For example, a light-emitting element (260) may be disposed on the second flattening layer (252). The light-emitting element (260) may include a first electrode (261), a light-emitting layer (263), and a second electrode (265).

[0080] The light-emitting element (260) can be electrically connected to a pixel driving circuit through a first electrode (261). For example, the first electrode (261) can penetrate the second planarization layer (252) and come into direct contact with the pixel contact electrode (255). Accordingly, the first electrode (261) can be electrically connected to the second transistor (240) through the pixel contact electrode (255). However, FIG. 2 is intended to illustrate an example of a method of supplying current to the first electrode and is not limited to physical contact between the second transistor (240), which is a driving transistor, and the first electrode (261). In one example, the switching transistor electrically connected to the first electrode (261) may be a light-emitting transistor. For example, the light-emitting transistor can control the turn-on and turn-off states of the light-emitting element (260). The pixel contact electrode (255) may include a conductive material. For example, the pixel contact electrode (255) may include metallic materials such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). In one example, the pixel contact electrode (255) may have a multilayer structure of titanium / aluminum / titanium (Ti / Al / Ti).

[0081] The first electrode (261) may include a transparent conductive film. For example, the first electrode (261) may include indium tin oxide (ITO) or indium zinc oxide (IZO). Alternatively, the first electrode (261) may include a single-layer or multi-layer structure comprising a reflective metal film formed of one of silver (Ag), aluminum (Al), gold (Au), nickel (Ni), and chromium (Cr), or an alloy thereof. The first electrode (261) may also be referred to as an anode electrode or a pixel electrode.

[0082] A bank (262) may be disposed on the first electrode (261). The bank (262) may be disposed to cover the edge of the first electrode (261). A portion of the bank (262) may extend to the second flattening layer (252). The upper surface of the first electrode (261) exposed and not covered by the bank (262) may become a light-emitting region. The bank (262) may include a black material, a light-blocking material, and a light-absorbing material. The bank (262) may include a material that absorbs light within a specific wavelength range. The bank (262) may be composed of a stacked structure of at least two different colored filters among a red color filter, a green color filter, and a blue color filter. The bank (262) may be composed of an organic insulating material. Bank (262) may contain, for example, photosensitive polyimide, photoacrylic or benzocyclobutene (BCB).

[0083] A light-emitting layer (263) may be disposed on the first electrode (261). The light-emitting layer (263) may include a hole transport layer (HTL), an organic light-emitting layer (EML), an electron transport layer (ETL), a hole blocking layer (HBL), a hole injection layer (HIL), an electron blocking layer (EBL), and an electron injection layer (EIL) as components. The light-emitting layer (263) may have a multi-stack structure in which two or more organic light-emitting layers (EML) are stacked. Among the components of the light-emitting layer (263), the electron injection layer (EIL), the electron blocking layer (EBL), the hole injection layer (HTL), and the hole blocking layer (HBL) may be disposed as a common layer in the entire area of ​​the display area (AA) and a part of the non-display area (AA). Additionally, the organic light-emitting layer (EML) may be disposed only in the pixels of the display area (AA). Alternatively, the organic light-emitting layer (EML) may be disposed as a common layer on the display area (AA) and the non-display area (AA).

[0084] A second electrode (265) may be disposed on the light-emitting layer (263). The second electrode (265) may be commonly connected to the light-emitting layer (263) formed on all pixels. Thus, the second electrode (265) may also be referred to as a cathode electrode or a common electrode. The second electrode (265) may include a semi-transparent conductive material. For example, the second electrode (265) may be formed from a metallic material such as magnesium (Mg), silver (Ag), or an alloy of silver (Ag) and magnesium (Mg) (Ag-Mg). In one example, the second electrode (265) may include a transparent conductive film such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). Although not shown in the drawing, in one example, the display area (AA) may include a plurality of transmission areas. If a transparent portion exists within the display area (AA), the second electrode (265) may be placed within the display area (AA) so as not to overlap with the transparent portion. For example, the transparent portion may be an area where no opaque or reflective material is placed.

[0085] A capping layer (267) may be disposed on the second electrode (265). The capping layer (267) can improve light extraction efficiency by preventing light generated from the light-emitting layer (263) from being lost.

[0086] A sealing portion (270) may be disposed on the light-emitting element (260). The sealing portion (270) may protect the light-emitting element (260) from external oxygen or moisture. The sealing portion (270) may cover the display area (AA) and extend to the non-display area (NAA) outside the display area (AA).

[0087] The bag portion (270) may include a multilayer structure in which a first bag layer (271), a second bag layer (273), and a third bag layer (275) are arranged. The second bag layer (273) may be configured to be arranged between the first bag layer (271) and the third bag layer (275).

[0088] A first encapsulation layer (271) may be placed on the capping layer (267). A second encapsulation layer (273) may be placed on the first encapsulation layer (271). The second encapsulation layer (273) may have sufficient thickness to cover the first encapsulation layer (271) and have a flat surface. The second encapsulation layer (273) may prevent foreign substances from penetrating into the light-emitting element (260). A third encapsulation layer (275) may be placed on the second encapsulation layer (273).

[0089] The first encapsulation layer (271) and the third encapsulation layer (275) may contain an inorganic insulating material, and the second encapsulation layer (273) may contain an organic insulating material. For example, each of the first encapsulation layer (271) and the third encapsulation layer (275) may contain at least one material selected from silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). The second encapsulation layer (273) may contain at least one material selected from epoxy, polyimide, polyethylene, and acrylate.

[0090] A touch portion may be disposed on the packaging portion (270). The touch portion may include a touch buffer layer (277), a touch sensor portion (287), an inter-touch layer insulating layer (282), and a touch protection layer (290).

[0091] A touch buffer layer (277) may be disposed on the third encapsulation layer (275). The touch buffer layer (277) can relieve stress between the encapsulation portion (270) and the touch sensor portion (287) layer, thereby preventing damage to the encapsulation portion (270) and the light-emitting element (260). The touch buffer layer (277) may include an inorganic insulating material. For example, the touch buffer layer (277) may include silicon nitride (SiNx), but is not limited thereto.

[0092] The touch sensor portion (287) may include a plurality of touch electrodes (285) and bridge electrodes (281). The plurality of touch electrodes (285) and bridge electrodes (281) may be disposed on different layers. For example, the bridge electrode (281) may be disposed on a touch buffer layer (277). The plurality of touch electrodes (287) may be disposed on a touch interlayer insulating layer (282). The plurality of touch electrodes (287) may include a first touch electrode (283) and a second touch electrode (284). The bridge electrode (281) may electrically connect adjacent first touch electrodes (283). To this end, the first touch electrode (283) may penetrate the touch interlayer insulating layer (282) and be connected to the bridge electrode (281). The touch interlayer insulating layer (282) may include an inorganic insulating material. For example, the interlayer insulating layer (282) may include silicon nitride (SiNx), but is not limited thereto.

[0093] A conductive material may be included in the first touch electrode (283), the second touch electrode (284), or the bridge electrode (281). Each of the first touch electrode (283), the second touch electrode (284), or the bridge electrode (281) may include a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0094] The touch buffer layer (277) and the touch layer insulation layer (282) may be in contact in the upper and lower directions to form a touch insulation structure (280). A touch protection layer (290) may be placed on the touch sensor part (287). The touch protection layer (290) can prevent damage to the touch sensor part (287) caused by external impact and moisture. The touch protection layer (290) may contain an organic insulating material. For example, the touch protection layer (290) may contain a photosensitive acrylic or polyimide-based organic material. The touch protection layer (290) may extend into a non-display area (NAA).

[0095] FIGS. 5 to 8 are drawings according to an embodiment of the present specification. FIG. 5 is a partial enlarged view showing region III of FIG. 3. FIG. 6 is a cross-sectional view along line IV-IV' of FIG. 5. FIG. 7 is a cross-sectional view along line VV' of FIG. 5. For example, FIG. 5 may show patterns of dummy pixels (DP) placed within a hole region (H). In FIG. 5, for convenience of explanation, only the dummy pixels (DP), a plurality of gate link wires (400), and a plurality of data link wires (400) are shown.

[0096] Referring to FIG. 5, a plurality of gate link wires (400) may include a first gate link wire (400-1), a second gate link wire (400-2), and a third gate link wire (400-3). Each gate link wire (400-1, 400-2, 400-3, 400-n) (n is a natural number) may extend along the horizontal direction (or horizontal direction) of the display area (AA). A plurality of data link wires (300) may extend in a direction intersecting the plurality of gate link wires (400). For example, each data link wire (300-1, 300-2, 300-3, 300-n) (n is a natural number) may extend along the vertical direction (or vertical direction) of the display area (AA).

[0097] Referring to FIGS. 5 and 6, a multi-buffer layer (207) and a third buffer layer (212) may be disposed on a substrate (201) of a hole region (H). Wiring patterns (223-1, 243-1, 233-1) constituting gate link wiring (400) may be disposed on the third buffer layer (212).

[0098] Wiring patterns (223-1, 243-1, 233-1) may be placed overlappingly in an area corresponding to the first dummy subpixel (DSP-1). Wiring patterns (223-1, 243-1, 233-1) may include a first wiring pattern (223-1), a second wiring pattern (243-1), and a third wiring pattern (233-1). The first wiring pattern (223-1) is placed between the third buffer layer (212) and the first gate insulating layer (222) and may be formed in the same process with the same material as the first gate electrode (223). The second wiring pattern (243-1) is placed between the second gate insulating layer (242) and the fourth interlayer insulating layer (218) and may be formed in the same process with the same material as the second gate electrode (243). The third wiring pattern (233-1) is placed between the fourth interlayer insulating layer (218) and the fifth interlayer insulating layer (219) and can be formed in the same process with the same material as the second storage electrode (233).

[0099] The gate link wiring (400) can be configured using one or more of the first wiring pattern (223-1), the second wiring pattern (243-1), or the third wiring pattern (233-1).

[0100] The third wiring pattern (233-1) and the light-emitting layer (263) may be spaced apart from each other in the upper and lower directions. Multilayer insulating layers may be stacked in the upper and lower directions between the third wiring pattern (233-1) and the light-emitting layer (263). For example, the fifth interlayer insulating layer (219), the passivation layer (247), the first flattening layer (251), the second flattening layer (252), and the bank (262) may be stacked from the bottom. The first organic pattern (263-1) and the second organic pattern (263-2) constituting the dummy light-emitting layer (263d) may be disposed on the bank (262). The first organic pattern (263-1) and the second organic pattern (263-2) may be formed in the same material and the same process as the light-emitting layer (263) of the display area (AA). The lower surface of each of the first organic pattern (263-1) and the second organic pattern (263-2) may be in contact with a bank (262), which is an organic insulating material, and the upper surface may be in contact with a first encapsulation layer (271), which is an inorganic insulating material. Accordingly, since no driving current is supplied to the dummy light-emitting layer (263d), it may not emit light even when a driving current is supplied to the pixel area (P). The dummy light-emitting layer (263d) may be positioned corresponding to the first dummy subpixel (DSP-1) and the second dummy subpixel (DSP-2).

[0101] One or more reflection patterns (285-1) may be positioned spaced apart from the dummy light-emitting layer (263d) in the upper and lower directions. The reflection patterns (285-1) may be formed from the same material and in the same process as the touch electrode (285) of the display area (AA). Multilayer insulating layers may be stacked in the upper and lower directions between the dummy light-emitting layer (263d) and the reflection patterns (285-1). For example, a first encapsulation layer (271), a second encapsulation layer (273), a third encapsulation layer (275), and a touch insulating structure (280) may be stacked from the bottom. In one example, the reflection patterns (285-1) may extend in the same direction overlapping with the gate link wiring (400). Accordingly, in one example, the reflection pattern (285-1) may be placed overlapping the area corresponding to the first dummy subpixel (DSP-1) on which the wiring patterns (223-1, 243-1, 233-1) are placed.

[0102] Referring to FIGS. 5 and 7, the data link wiring (300) may be arranged to overlap with the area corresponding to a plurality of third dummy subpixels (DSP-3). For example, the data link wiring (300) may be extended to overlap with a plurality of third dummy subpixels (DSP-3) arranged along the column direction.

[0103] A multi-buffer layer (207) and a third buffer layer (212) may be disposed on the substrate (201) of the hole region (H). A first wiring pattern (223-1), a second wiring pattern (243-1), and a third wiring pattern (233-1) constituting a gate link wiring (400) may be disposed on the third buffer layer (212). The first wiring pattern (223-1), the second wiring pattern (243-1), and the third wiring pattern (233-1) may be disposed on different layers with insulating layers in between.

[0104] The third wiring pattern (233-1) may be covered by the fifth interlayer insulation layer (219). Data link wiring (300) may be placed on the fifth interlayer insulation layer (219). The data link wiring (300) may include a first data link pattern (245-1) and a second data pattern (255-1). The first data pattern (245-1) and the second data pattern (255-1) may be placed on different layers.

[0105] The first data pattern (245-1) and the second data pattern (255-1) can be positioned in correspondence with the third dummy subpixel (DSP-3) positioned on both sides with the first dummy subpixel (DSP-1) in between, as shown in FIG. 7.

[0106] The first data pattern (245-1) may be placed on the upper surface of the fifth interlayer insulating layer (219). The first data pattern (245-1) may be formed in the same process with the same material as the second source / drain electrode (245). The first data pattern (245-1) may be covered with a passivation layer (247). A first flattening layer (251) may be placed on the passivation layer (247). A second data pattern (255-1) may be placed on the first flattening layer (251). The second data pattern (255-1) may be formed in the same process with the same material as the pixel contact electrode (255).

[0107] A second flattening layer (251) and a bank (262) may be arranged sequentially on a second data pattern (255-1). A first organic pattern (263-1) and a third organic pattern (263-3) constituting a dummy light-emitting layer (263d) may be arranged on the bank (262). Since no driving current is supplied to the dummy light-emitting layer (263d), the dummy light-emitting layer (263d) may not emit light even when a driving current is supplied to the pixel area (P). The dummy light-emitting layer (263d) may be arranged at a position corresponding to the first dummy subpixel (DSP-1) and the third dummy subpixel (DSP-3).

[0108] The first data pattern (245-1) and the second data pattern (255-1) can each overlap the third dummy subpixel (DSP-3) in the up and down directions. The third organic pattern (263-3) may have at least the same width as or a larger size than each of the first data pattern (245-1) and the second data pattern (255-1).

[0109] One or more reflection patterns (285-1) may be positioned spaced apart from the dummy light-emitting layer (263d) in the upper and lower directions. Multilayer insulating layers may be stacked in the upper and lower directions between the dummy light-emitting layer (263d) and the reflection pattern (285-1). For example, a first encapsulation layer (271), a second encapsulation layer (273), a third encapsulation layer (275), and a touch insulating structure (280) may be stacked from the bottom. In one example, the reflection pattern (285-1) may extend in the same direction as the gate link wiring (400), as shown in FIG. 5. The reflection pattern (285-1) may overlap with the gate link wiring (400) in the upper and lower directions. In one example, the reflection pattern (285-1) may extend along the first direction (X) of the display panel (200). The first direction (X) may be referred to as the horizontal direction.

[0110] A reflection pattern (285-1) placed in the second region of the hole region (H) can further reduce external light reflection. For example, referring to FIG. 8, external light (O_L) can be incident on each dummy subpixel (DSP-1, DSP-2, DSP-3). The incident external light (O_L) can reach the reflection pattern (285-1) by passing through the first organic pattern (263-1), the second organic pattern (263-2), and the third organic pattern (263-3) that constitute the dummy light-emitting layer (263d). Then, the external light (O_L) can be canceled out by destructive interference effects, etc., occurring in the reflection pattern (285-1), thereby reducing external light reflection.

[0111] According to an embodiment of the present specification, the gate link wiring (400) and the data link wiring (300) are arranged to overlap the dummy light-emitting layer (263d) in the upper and lower directions, thereby preventing the gate link wiring (400) and the data link wiring (300) from being visually perceived. Accordingly, a decrease in transmittance in the hole area (H) can be prevented. Additionally, the gate link wiring (400) or the data link wiring (300) can be arranged in a straight line shape that crosses the hole area (H). Since the signal transmission path through the gate link wiring (400) or the data link wiring (300) does not bypass the hole area (H), the unnecessary bezel area can be reduced. Therefore, the bezel area of ​​the hole area (H) can be further reduced or a zero bezel can be implemented.

[0112] FIG. 9 is a drawing according to another embodiment of the present specification. FIG. 9 is identical to the configuration of FIG. 5 except for the location where the gate link wiring (400) is arranged. Referring to FIG. 9, a plurality of data link wirings (300) may be arranged in an overlapping manner along the column direction of the third dummy subpixel (DSP-3).

[0113] As illustrated in FIG. 6, the gate link wiring (400) may include a first wiring pattern (223-1), a second wiring pattern (243-1), and a third wiring pattern (233-1). The gate link wiring (400) may be arranged in a direction that crosses the third dummy subpixel (DSP-3) and the second dummy subpixel (DSP-2). For example, a third organic pattern (263-3) may be arranged on the third dummy subpixel (DSP-3), and a second organic pattern (263-2) may be arranged on the second dummy subpixel (DSP-2). Accordingly, the gate link wiring (400) may be arranged to overlap the third organic pattern (263-3) and the second organic pattern (263-2) in the upper and lower directions, respectively.

[0114] The gate link wiring (400) or data link wiring (300) can be arranged to overlap the lower portion of the plurality of organic patterns (263-1, 263-2, 263-3) constituting the dummy light-emitting layer (263d), respectively. Accordingly, the reduction of transmittance by the gate link wiring (400) or data link wiring (300) can be prevented.

[0115] FIGS. 10 to 12 are drawings according to another embodiment of the present specification. FIG. 10 is a partial enlarged view showing region III of FIG. 3. FIG. 11 is a cross-sectional view along line VI-VI' of FIG. 10. FIG. 12 is a cross-sectional view along line VII-VII' of FIG. 10. Components identical to those in FIGS. 5 to 7 in FIGS. 10 to 12 may have the same reference numerals. Accordingly, redundant descriptions will be omitted or briefly described, and parts that differ will be described.

[0116] FIG. 10 may show dummy subpixel patterns (DSP-1, DSP-2, DSP-3) of a dummy pixel (DP) placed within a hole region (H). For convenience of explanation, FIG. 10 only shows the dummy pixel (DP), a plurality of gate link wires (400), and a plurality of data link wires (400).

[0117] Referring to FIGS. 10 to 12, the dummy light-emitting layer (263d) may include a first organic pattern (263-1), a second organic pattern (263-2), and a third organic pattern (263-3). The dummy light-emitting layer (263d) can be formed through a process of depositing organic material using an open mask. The open mask may include a metal material. Accordingly, a support spacer (500) for supporting the open mask made of a metal material may be further included. For example, the support spacer (500) may be positioned between adjacent organic patterns and may be positioned overlapping a plurality of gate link wirings (400) and a plurality of data link wirings (300).

[0118] A plurality of gate link wires (400) may include a first gate link wire (400-1), a second gate link wire (400-2), and a third gate link wire (400-3). Each gate link wire (400-1, 400-2, 400-3, 400-n) (n is a natural number) may extend along the horizontal direction (or horizontal direction) of the display area (AA). A plurality of data link wires (400) may extend in a direction intersecting the plurality of gate link wires (400). For example, each data link wire (300-1, 300-2, 300-3, 300-n) (n is a natural number) may extend along the vertical direction (or vertical direction) of the display area (AA).

[0119] Each of the gate link wires (400-1, 400-2, 400-3, 400-n) and data link wires (300-1, 300-2, 300-3, 300-n) may be placed overlappingly on the lower part of the first organic pattern (263-1) or the third organic pattern (263-3). For example, each of the gate link wires (400-1, 400-2, 400-3, 400-n) and data link wires (300-1, 300-2, 300-3, 300-n) may be placed so as not to extend beyond the width of each of the first organic pattern (263-1) or the third organic pattern (263-3).

[0120] A support spacer (500) may be positioned between adjacent organic patterns and may be positioned overlapping a plurality of gate link wirings (400) and a plurality of data link wirings (300). For example, referring to FIGS. 10 and FIGS. 12, a support spacer (500) may be positioned in each first space between a first organic pattern (263-1) and a third organic pattern (263-3) in a first direction (X). Additionally, a support spacer (500) may be positioned in each second space between a third organic pattern (263-3) positioned corresponding to a third dummy subpixel (DSP-3) in a second direction (Y).

[0121] The support spacer (500) may be configured in a semicircular or elliptical shape, but is not limited thereto. The support spacer (500) may have a shape that protrudes beyond the organic patterns (263-1, 263-2, 263-3) so as to support an open mask made of metal material. The thickness of the support spacer (500) may be greater than the thickness of each organic pattern (263-1, 263-2, 263-3). Accordingly, the support spacer (500) can prevent the organic patterns (263-1, 263-2, 263-3) from being damaged by the open mask.

[0122] FIG. 13 is a drawing according to another embodiment of the present specification. FIG. 13 differs from FIG. 10 in the location where the gate link wiring (400) is placed. In FIG. 13, components identical to those in FIG. 10 through FIG. 12 may have the same reference numerals.

[0123] Referring to FIG. 13, a plurality of data link wires (300) may be arranged in an overlapping manner along the column direction of the third dummy subpixel (DSP-3). For example, each of the data link wires (300-1, 300-2, 300-3, 300-n) may be arranged so as not to exceed the width of each of the third organic pattern (263-3). The gate link wires (300) may be arranged in a direction that crosses the third dummy subpixel (DSP-3) and the second dummy subpixel (DSP-2). Accordingly, they may be arranged to overlap the third organic pattern (263-3) and the second organic pattern (263-2) in the upper and lower directions. The gate link wires (400) may be arranged to overlap the lower portion of the plurality of organic patterns constituting the dummy light-emitting layer (263d). Therefore, the exposure of the gate link wiring (400) can be reduced, so a decrease in transmittance in the hole area (H) can be prevented. Additionally, as the data link wiring (300) overlaps along the column direction of the third dummy subpixel (DSP-3), it can be arranged to overlap the third organic pattern (263-3) in the upper and lower directions. Therefore, the exposure of the data link wiring (300) can be reduced, so a decrease in transmittance in the hole area (H) can be prevented.

[0124] The support spacer (500) may be positioned between adjacent organic patterns and may overlap with a plurality of data link wirings (300). For example, the support spacer (500) may be positioned in each first space between the first organic pattern (263-1) and the third organic pattern (263-3) in the first direction (X). The first organic pattern (264-1) may be positioned corresponding to the first dummy subpixel (DSP-1), and the third organic pattern (263-3) may be positioned corresponding to the third dummy subpixel (DSP-3). Additionally, the support spacer (500) may be positioned in each second space between adjacent third organic patterns (263-3) in the second direction (Y).

[0125] FIG. 14 is a diagram illustrating the operation of a display panel according to an embodiment of the present specification. Referring to FIG. 14, the first hole (H1) of the comparative example (REF) may be configured to be open, penetrating the first display panel (200a) without dummy pixels. In the comparative example (REF), only the first hole (H1) may be visible when the first display panel (200a) is turned on by applying current or turned off by cutting off current. Additionally, a hole bezel area may be placed around the first hole (H1). Accordingly, the immersion of the screen of the first display panel (200a) may be reduced by the hole bezel area. In contrast, dummy pixels (DP) may be placed in the second hole (H2) of the second display panel (200b) according to the embodiment (REF) of the present specification, as shown in FIG. 3. Accordingly, the second hole (H2) may not be visible during the operation of turning off the second display panel (200b). Additionally, even when turning on the second display panel (200), the second hole (H2) may be relatively less visible to the user than the first hole (H1). Furthermore, the display area may be expanded because the hole bezel area around the second hole (H2) can be removed.

[0126] A display device according to various embodiments of the present specification may be described as follows.

[0127] A display device according to an embodiment of the present specification may include a display area disposed on a substrate and comprising a plurality of pixels, a first area disposed in the display area and comprising a hole, a second area disposed in the inner side of the hole and comprising a plurality of dummy pixels comprising an organic pattern, a first insulating layer disposed below the organic pattern, a second insulating layer disposed above the organic pattern, a reflection pattern disposed on the second insulating layer corresponding to each dummy pixel, and a plurality of signal link wires extending from one side of the hole through the second area to the other side of the hole area.

[0128] According to various embodiments of the present specification, a plurality of pixels may emit light and a plurality of dummy pixels may not emit light.

[0129] According to various embodiments of the present specification, a plurality of dummy pixels may have the same shape as the pixel.

[0130] According to various embodiments of the present specification, a plurality of pixels comprises: a plurality of first subpixels arranged spaced apart from each other in the horizontal direction of a display area; a plurality of second subpixels arranged in the same row direction, spaced apart from each other in the vertical direction of the plurality of first subpixels; and a plurality of third subpixels arranged spaced apart from each other in the vertical direction of the display area, spaced apart from each other in the horizontal direction of the plurality of first subpixels, and each of the plurality of first subpixels, the plurality of second subpixels, and the plurality of third subpixels may each include a light-emitting element composed of a first electrode, a light-emitting layer, and a second electrode.

[0131] According to various embodiments of the present specification, a plurality of dummy pixels comprises: a plurality of first dummy subpixels arranged spaced apart from each other in the horizontal direction of a display area; a plurality of second dummy subpixels arranged in the same row direction, spaced apart from each other in the vertical direction of the plurality of first dummy subpixels; and a plurality of third dummy subpixels arranged spaced apart from each other in the vertical direction of the display area, spaced apart from each other in the horizontal direction of the plurality of first dummy subpixels, and the plurality of first dummy subpixels, the plurality of second dummy subpixels, and the plurality of third dummy subpixels may each include an organic pattern.

[0132] According to various embodiments of the present specification, a plurality of signal link wires include gate link wires or data link wires, and each of the gate link wires or data link wires can extend straight from one side of the hole through a second region to the other side of the hole.

[0133] According to various embodiments of the present specification, each gate link wiring may be arranged along a horizontal direction from one side of the hole to the other side of the hole, and each data link wiring may be arranged along a vertical direction intersecting the gate link wiring.

[0134] According to various embodiments of the present specification, the gate link wiring may be arranged to overlap the organic pattern of a plurality of first dummy subpixels in the upper and lower directions.

[0135] According to various embodiments of the present specification, data link wiring may be arranged to overlap with the organic pattern of a number of third dummy subpixels in the upper and lower directions.

[0136] According to various embodiments of the present specification, the width of the gate link wiring may be smaller than the width of the organic pattern of the first dummy subpixel.

[0137] According to various embodiments of the present specification, the width of the data link wiring may be smaller than the width of the organic pattern of the third dummy subpixel.

[0138] According to various embodiments of the present specification, a first space disposed along a horizontal direction between an organic pattern of a first dummy subpixel and an organic pattern of a third dummy subpixel; and a second space between adjacent organic patterns of third dummy subpixels, and may further include support spacers disposed in the first space and the second space.

[0139] According to various embodiments of this specification, the thickness of the support spacer may be greater than the thickness of the organic patterns.

[0140] Although the embodiments of this specification have been described in more detail with reference to the attached drawings, this specification is not necessarily limited to these embodiments and may be modified in various ways within the scope of the technical spirit of this specification. Accordingly, the embodiments disclosed in this specification are intended to explain, not limit, the technical spirit of this specification, and the scope of the technical spirit of this specification is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0141] 1: Display device 200: Display panel AA: Display area NAA: Non-display area H: Hole area 300: Data Link Wiring 400: Gate link wiring P: Pixel DP: Dummy pixel 500: Support Spacer 263-1: First organic pattern 263-2: Second Organic Pattern 263-3: Third Organic Pattern

Claims

Claim 1 A display device comprising: a display area disposed on a substrate and including a plurality of pixels; a first area disposed on the display area and including a hole; a second area disposed on the inner side of the hole and including a plurality of dummy pixels including an organic pattern; a first insulating layer disposed on the lower side of the organic pattern; a second insulating layer disposed on the upper side of the organic pattern; a reflection pattern disposed on the second insulating layer corresponding to each dummy pixel; and a plurality of signal link wires extending from one side of the hole through the second area to the other side of the hole area. Claim 2 A display device according to claim 1, wherein the plurality of pixels emit light and the plurality of dummy pixels do not emit light. Claim 3 A display device according to claim 1, wherein the plurality of dummy pixels have the same shape as the pixels. Claim 4 A display device according to claim 1, wherein the plurality of pixels comprises: a plurality of first subpixels arranged spaced apart from each other in the horizontal direction of the display area; a plurality of second subpixels arranged in the same row direction, spaced apart from each other in the vertical direction of the plurality of first subpixels; and a plurality of third subpixels arranged spaced apart from each other in the vertical direction of the display area, spaced apart from each other in the horizontal direction of the plurality of first subpixels, and wherein the plurality of first subpixels, the plurality of second subpixels, and the plurality of third subpixels each comprise a light-emitting element composed of a first electrode, a light-emitting layer, and a second electrode. Claim 5 A display device according to claim 1, wherein the plurality of dummy pixels comprises: a plurality of first dummy subpixels arranged spaced apart from each other in the horizontal direction of the display area; a plurality of second dummy subpixels arranged in the same row direction, spaced apart from each other in the vertical direction of the plurality of first dummy subpixels; and a plurality of third dummy subpixels arranged spaced apart from each other in the vertical direction of the display area, spaced apart from each other in the horizontal direction of the plurality of first dummy subpixels, and wherein the plurality of first dummy subpixels, the plurality of second dummy subpixels, and the plurality of third dummy subpixels each comprise an organic pattern. Claim 6 A display device according to claim 5, wherein the plurality of signal link wires includes gate link wires or data link wires, and the gate link wires or the data link wires each extend in a straight line from one side of the hole through the second region to the other side of the hole. Claim 7 A display device according to claim 6, wherein each gate link wiring is arranged along a horizontal direction from one side of the hole to the other side of the hole, and each data link wiring is arranged along a vertical direction intersecting the gate link wiring. Claim 8 A display device according to claim 7, wherein the gate link wiring is arranged to overlap the organic pattern of the plurality of first dummy subpixels in the upper and lower directions. Claim 9 In claim 7, the display device wherein the data link wiring is arranged to overlap the organic pattern of the plurality of third dummy subpixels in the upper and lower directions. Claim 10 A display device according to claim 7, wherein the width of the gate link wiring is smaller than the width of the organic pattern of the first dummy subpixel. Claim 11 A display device according to claim 7, wherein the width of the data link wiring is smaller than the width of the organic pattern of the third dummy subpixel. Claim 12 A display device according to claim 5, comprising: a first space arranged along a horizontal direction between the organic pattern of the first dummy subpixel and the organic pattern of the third dummy subpixel; and a second space between adjacent organic patterns of the third dummy subpixel, and further comprising support spacers arranged in the first space and the second space. Claim 13 In paragraph 12, a display device wherein the thickness of the support spacer is greater than the thickness of the organic patterns.

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