Heat pipe, semiconductor device including heat pipe, and method of manufacturing thereof

Abstract

A semiconductor device according to one embodiment of the present disclosure comprises a stack, a heat sink, and a heat pipe, wherein the stack comprises a first semiconductor layer and a second semiconductor layer stacked in a first direction on the first semiconductor layer, the heat sink is stacked in the first direction on the second semiconductor layer, and the heat pipe may extend in the first direction within the first semiconductor layer, the second semiconductor layer, and the heat sink.

Description

Technology Field

[0001] This application claims priority to U.S. provisional application No. 63 / 763,081 filed on February 25, 2025, the full contents of which are referenced herein.

[0002] The technical concept of the present invention relates to a heat pipe, a semiconductor device including a heat pipe, and a method for manufacturing the heat pipe and the semiconductor device. Background Technology

[0003] In a stacked structure of semiconductor dies (e.g., semiconductor chips) contained within a semiconductor package, heat buildup occurring between the dies can be a factor limiting the performance of the semiconductor package. For instance, a problem of heat accumulation in the center of the semiconductor package may occur.

[0004] The information disclosed in the background art of the present invention is technical information that has already been recognized or derived by the inventors of the present invention prior to or during the process of deriving the embodiments of the present disclosure, or that was obtained during the process of deriving the embodiments. Accordingly, the information described in the background art of the present invention is not known prior art. The problem to be solved

[0005] The problem that the technical concept of the present invention aims to solve is to provide a heat pipe and a semiconductor device that prevent heat accumulation that limits the performance of a semiconductor package.

[0006] Furthermore, the problems that the technical concept of the present invention aims to solve are not limited to those mentioned above, and other problems can be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0007] A semiconductor device according to an exemplary embodiment of the present disclosure comprises a stack, a heat sink, and a heat pipe, wherein the stack comprises a first semiconductor layer and a second semiconductor layer stacked in a first direction on the first semiconductor layer, the heat sink is stacked in the first direction on the second semiconductor layer, and the heat pipe may extend in the first direction within the first semiconductor layer, the second semiconductor layer, and the heat sink.

[0008] A semiconductor device according to an exemplary embodiment of the present disclosure comprises a stack and a heat sink, wherein the stack comprises a first semiconductor chip comprising a first via having a first internal space and a second semiconductor chip stacked in a first direction on the first semiconductor chip and comprising a second via having a second internal space, and the heat sink comprises a third internal space stacked in the first direction on the second semiconductor chip, wherein the first internal space, the second internal space and the third internal space overlap each other in the first direction and fluidly communicate with each other and may be provided as a heat pipe. Brief explanation of the drawing

[0009] FIG. 1 is a schematic perspective view illustrating a heat pipe according to one embodiment of the present disclosure. FIG. 2 is a schematic side view illustrating the heat pipe of FIG. 1 according to one embodiment of the present disclosure. FIG. 3a is a cross-sectional view of a heat pipe according to one embodiment of the present disclosure, cut along the line A-A' of FIG. 2. FIG. 3b is a cross-sectional view of a heat pipe according to one embodiment of the present disclosure, cut along the line B-B' of FIG. 2. FIG. 3c is a cross-sectional view of a heat pipe according to one embodiment of the present disclosure, cut along the line C-C' of FIG. 2. FIG. 4a is a cross-sectional view illustrating the cross-sectional shape of a heat pipe according to one embodiment of the present disclosure. FIG. 4b is a cross-sectional view illustrating the cross-sectional shape of a heat pipe according to one embodiment of the present disclosure. FIG. 4c is a cross-sectional view illustrating the cross-sectional shape of a heat pipe according to one embodiment of the present disclosure. FIG. 5 is a cross-sectional view of a semiconductor device including a heat pipe and a semiconductor layer according to one embodiment of the present disclosure. FIG. 6 is a cross-sectional view of a semiconductor device comprising a plurality of semiconductor layers according to one embodiment of the present disclosure. FIG. 7 is a flowchart illustrating a method for manufacturing a semiconductor device including a heat pipe according to one embodiment of the present disclosure. Specific details for implementing the invention

[0010] The embodiments of the present disclosure are exemplary embodiments and are not limited thereto, and may be implemented in various other forms. Each embodiment provided in the following description is not excluded from being associated with or combined with one or more features of other embodiments provided or not provided in the present disclosure, provided that such association is consistent with the present disclosure. For example, even if a matter described in a particular embodiment is not explicitly described in another embodiment, such matter may be understood to be associated with or combined with other embodiments unless otherwise noted. Furthermore, all descriptions regarding the principles, aspects, examples, and embodiments of the present disclosure should be understood to include their structural and functional equivalents. In addition, such equivalents should be understood to include not only currently known equivalents but also equivalents to be developed in the future, that is, all devices that perform the same function regardless of structure.

[0011] Where any component, part, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an “element”) of a semiconductor device (or semiconductor package) is described as being “on,” “connected to,” or “coupled to” another element, this means that the element may be directly located on or directly connected or coupled to the other element, or that one or more intervening elements may exist between them. On the other hand, where any element of the semiconductor device is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, no intervening elements exist between them. Throughout this specification, the same reference numerals refer to the same elements.

[0012] Spatial relative terms such as "over," "above," "on," "upper," "below," "under," "lower," "left," "right," "lower-left," "lower-right," "upper-left," "upper-right," "central," and "middle" may be used for convenience to describe the relationships between elements as illustrated in the drawings. These spatial relative terms should be understood to include not only the directions illustrated in the drawings but also other orientations of the semiconductor device during use or operation. For example, if the semiconductor device illustrated in the drawings is flipped, an element described as being "below" or "below" another element may be placed "above." Therefore, the term "below" may include both upper and lower orientations. The semiconductor device may also be rotated 90 degrees or oriented in other directions, and spatial relative terms used in this disclosure should be interpreted accordingly. Additionally, elements referred to as the "left" element and the "right" element may be interchanged depending on the orientation of the device or structure. Accordingly, in the following description, the "left" element and the "right" element may be referred to as the "first" element and the "second" element, respectively, as long as their structural relationship is clearly understood. Likewise, the "bottom" element and the "top" element may also be referred to as the "first" element and the "second" element, respectively.

[0013] In this disclosure, terms such as "first," "second," "third," "fourth," "fifth," "sixth," etc., may be used to describe various elements, but such elements should not be limited by these terms. These terms are merely for distinguishing one element from another; for example, the first element described below may be named the second element without departing from the scope of this disclosure.

[0014] In this disclosure, when the expression “at least one of” is used before a list of elements, it modifies the entire list and does not modify each individual element included in the list. For example, the expression “at least one of a, b, and c” means including only a, including only b, including only c, including a and b, including a and c, including b and c, or including all of a, b, and c. Additionally, when the terms “same” or “equal” are used when comparing the dimensions of two or more elements, they may include “substantially same” or “substantially equal” dimensions.

[0015] Where a method for manufacturing a device or structure is described as comprising a plurality of steps or processes, even if a step or process is described as being performed later than another step or process, it may be performed earlier or simultaneously unless it is specified that such step or process must necessarily be performed before the preceding step or process. Additionally, the manufacturing method may further comprise additional steps or processes not mentioned in this disclosure.

[0016] In this disclosure, a number of embodiments are described with reference to schematic cross-sectional views of the embodiments (and intermediate structures). Accordingly, it is expected that shape variations may occur, for example, due to manufacturing techniques and / or process tolerances. Therefore, the embodiments of this disclosure should not be limited to the specific shapes of the regions depicted herein, and should be understood to include shape variations, for example, caused by the manufacturing process. The various regions depicted in the drawings are schematic and are not intended to represent the actual region shapes of the device, nor are they intended to limit the scope of this disclosure. Additionally, the size and relative size of layers and regions may be exaggerated in the drawings for clarity.

[0017] For the sake of brevity, detailed descriptions of conventional elements, structures, or layers included in a semiconductor package, such as connection pads, adhesive layers, insulating layers, barrier metal patterns, seed layers, etc., may be omitted from this disclosure. For example, a description of a specific connection pad of a semiconductor chip connected to a solder ball or bump in a semiconductor package may be omitted if it is not relevant to the features of a specific embodiment. Additionally, a description of a material forming a known structural element may be omitted if it is not relevant to the features of a specific embodiment. In this disclosure, "connection" between two structures or elements may mean an electrical connection. For example, a connection between a semiconductor chip, a semiconductor package, and / or a semiconductor device may mean an electrical connection between two or more corresponding elements. The terms "coupled" and "connected" have the same meaning and may be used interchangeably in this disclosure. Additionally, "isolation" between two structures or elements means electrical isolation or separation. For example, isolation between wiring patterns may mean that said wiring patterns are not electrically connected to each other.

[0018] Various embodiments of the present disclosure will be described in detail below with reference to FIGS. 1, 2, FIGS. 3a to 3c, FIGS. 4a to 4c, and FIGS. 5 to 7.

[0019] According to exemplary embodiments of the present disclosure, a heat pipe, a semiconductor device including the heat pipe (e.g., a semiconductor package), and a method for manufacturing the heat pipe and the semiconductor device may be provided.

[0020] In some embodiments, the heat pipe may be a micro heat pipe.

[0021] In some embodiments, a heat pipe (e.g., a micro heat pipe) may be implemented using a Through Silicon Via (TSV) process for at least a portion. Therefore, the heat pipe may be referred to as a TSV heat pipe. The TSV heat pipe may be included in a semiconductor device (e.g., a semiconductor package) and may be configured to transfer heat from the internal layers of the semiconductor device to the outside. For example, the TSV heat pipe may be configured to prevent heat accumulation in a certain region of the semiconductor device (e.g., a central region). For example, the TSV heat pipe may be configured to directly remove heat from the center of an individual semiconductor die (e.g., a semiconductor chip) and / or from the center of a stack of semiconductor dies (e.g., semiconductor chips).

[0022] For example, a TSV heat pipe may be configured to transfer heat from an intermediate layer of a semiconductor device to an upper layer (e.g., top layer) and / or a lower layer (e.g., bottom layer) of the semiconductor device. Alternatively, the TSV heat pipe may be configured to transfer heat from an upper layer to a lower layer of the semiconductor device, or conversely, to transfer heat from a lower layer to an upper layer. In some embodiments, the lower layer, intermediate layer, and / or upper layer of the semiconductor device may be a semiconductor die (e.g., a semiconductor chip) or may comprise a semiconductor die. The TSV heat pipe may be provided within or perpendicular to the lower layer, intermediate layer, and / or upper layer of the semiconductor device.

[0023] In some embodiments, the lower layer, intermediate layer and / or upper layer of the semiconductor device may be a semiconductor die (e.g., a semiconductor chip) or may include a semiconductor die.

[0024] In some embodiments, at least one heat pipe (e.g., TSV heat pipe) may be provided, said heat pipe may include a TSV having a hollow structure and may be connected to a corresponding hole of a heat sink. said heat sink may be part of a semiconductor device (e.g., semiconductor package) and may be, for example, an upper layer and / or a lower layer of the semiconductor device.

[0025] In some embodiments, the heat pipe (e.g., TSV heat pipe) may be composed of a vertical heat pipe penetrating one or more stacked semiconductor dies in a vertical direction.

[0026] In some embodiments, the TSV included in the heat pipe may have a larger size than the TSV configured to perform only electrical connection functions.

[0027] In some embodiments, the TSV heat pipe may be configured to perform both heat transfer and electrical connection functions. For example, the TSV heat pipe may be configured to transfer heat from the semiconductor device to the outside of the semiconductor device and simultaneously electrically connect at least two components of the semiconductor device (e.g., semiconductor dies) or electrically connect at least one component of the semiconductor device (e.g., semiconductor dies) to at least one component outside the semiconductor device.

[0028] In some embodiments, the semiconductor device (e.g., semiconductor package) may be a 2.5D+ semiconductor device (e.g., 2.5D+ semiconductor package). For example, the 2.5D+ semiconductor device may include a 2.5D semiconductor device (e.g., 2.5D semiconductor package), a 3D semiconductor device (e.g., 3D semiconductor package), etc.

[0029] In some embodiments, a semiconductor system including a semiconductor device (e.g., a semiconductor package) may be provided.

[0030] In some embodiments, the semiconductor device may include High Bandwidth Memory (HBM). For example, a TSV heat pipe included in the semiconductor device may be configured to transfer heat from the center of an individual semiconductor die (e.g., a semiconductor chip) of the HBM and / or from the center of a stack of semiconductor dies to the outside of the semiconductor die or the stack of semiconductor dies. For example, the semiconductor die may be a Dynamic Random Access Memory (DRAM) chip.

[0031] In some embodiments, thermal problems occurring in stacked semiconductor dies of various configurations (e.g., semiconductor chips) can be reduced or prevented.

[0032] Referring to FIGS. 1, FIGS. 2, FIGS. 3a to 3c and FIGS. 4a to 4c, embodiments of the present disclosure may include a heat pipe (100).

[0033] FIG. 1 is a schematic perspective view illustrating a heat pipe (100) according to one embodiment of the present disclosure. FIG. 2 is a schematic side view illustrating the heat pipe (100) of FIG. 1 according to one embodiment of the present disclosure. FIG. 3a is a cross-sectional view of the heat pipe (100) according to one embodiment of the present disclosure, cut along the line A-A' of FIG. 2. FIG. 3b is a cross-sectional view of the heat pipe (100) according to one embodiment of the present disclosure, cut along the line B-B' of FIG. 2. FIG. 3c is a cross-sectional view of the heat pipe (100) according to one embodiment of the present disclosure, cut along the line C-C' of FIG. 2.

[0034] A heat pipe (100) may be a sealed pipe configured to transfer heat through the evaporation and condensation of a working fluid (W) inside the heat pipe (100). For example, as shown in FIG. 2, one end of the heat pipe (100) in the first direction (Z direction) may be located adjacent to a heat source and may receive heat (B1) from the heat source. The one end of the heat pipe (100) may be referred to as the "hot side of the heat pipe (100)." Specifically, the working fluid (W) located at the one end of the heat pipe (100) may receive heat (B1), and the working fluid (W) located at the one end may evaporate due to the heat (B1). For example, the working fluid (W) may be in a steam (A1) state. The steam (A1) may move from one end of the heat pipe (100) along the first direction (Z direction) to the other end opposite to the one end. At the other end, the steam (A1) can condense back into liquid (A2) and release heat (B2) from the other end of the heat pipe (100) to the outside of the heat pipe (100). The other end of the heat pipe (100) may be referred to as the "cool side of the heat pipe (100)." After condensation, the liquid (A2) can flow back to one end of the heat pipe (100) by capillary action. According to some embodiments, the process in which the working fluid (W) at one end of the heat pipe (100) receives heat (B1), evaporates and moves to the other end of the heat pipe (100), condenses to release heat (B2), and then moves back to the other end by capillary action can be repeated continuously. Accordingly, the heat pipe is a closed system that does not require pumping compared to a liquid cooling system and has a structure that transfers most of the heat by relying on the phase change of the fluid.

[0035] Referring to FIG. 1, the heat pipe (100) may extend in a first direction (Z direction) and may include an evaporation region (191), an adiabatic region (192), and a condensation region (193) arranged sequentially along the first direction (Z direction). The evaporation region (191) may be a region of the heat pipe (100) where the working fluid (W) receives heat (B1) and evaporates. For example, one end of the heat pipe (100) may include at least a portion of the evaporation region (191). An exemplary cross-section of the evaporation region (191) is shown in FIG. 3a. The adiabatic region (192) may be a region of the heat pipe (100) located between the evaporation region (191) and the condensation region (193), and may be a region where the working fluid (W) moves between the evaporation region (191) and the condensation region (193). An exemplary cross-section of the adiabatic region (192) is shown in FIG. 3b. The condensation region (193) may be a region of the heat pipe (100) in which heat (B2) is released as the working fluid (W) condenses. For example, the other end of the heat pipe (100) may include at least a partial condensation region (193). An exemplary cross-section of the condensation region (193) is shown in FIG. 3C.

[0036] In some embodiments, the heat pipe (100) may have various cross-sectional shapes. For example, the cross-sectional shape of the internal space of the heat pipe (100) may be various closed shapes including at least one internal edge (C1) configured to allow the working fluid (W) to move by capillary action. For example, each of the at least one internal edge (C1) may function as a capillary. For example, the internal edge (C1) may be defined by two inner surfaces of the heat pipe (100) that define at least a portion of the internal space of the heat pipe (100). For example, the two inner surfaces may meet at an acute angle. For example, the internal edge (C1) may have a sharp polygonal cross-section.

[0037] In some embodiments, with reference to FIGS. 1, FIGS. 2 and FIGS. 3a through 3c, the internal space of the heat pipe (100) may have a triangular cross-sectional shape, and the triangular cross-sectional shape may include three inner corners (C1) configured to allow the working fluid (W) to move by capillary action. For example, the working fluid (W) in a liquid state (A2) may move along the inner corners (C1) from the condensation region (193) through the adiabatic region (192) to the evaporation region (191).

[0038] However, the embodiments of the present disclosure are not limited thereto. For example, the heat pipe (100) and its internal space may have various cross-sectional shapes. For example, referring to FIGS. 4a through 4c, the cross-sectional shape may be a shape containing only straight lines (i.e., a polygonal shape) (e.g., FIGS. 4a and 4b), or may include a shape combining straight lines and curves (e.g., the curve L1 in FIG. 4c). In some embodiments, FIG. 4a illustrates a substantially square cross-sectional shape of the heat pipe (100), and FIGS. 4b and 4c illustrate a substantially rectangular cross-sectional shape of the heat pipe (100). In some embodiments, the cross-sectional shape of the internal space of the heat pipe (100) may include any number of internal corners (C1) configured to allow the working fluid (W) to move by capillary action. Additionally, the internal corners (C1) may have various shapes. In some embodiments, the shape and / or size of the cross-sectional shape of the internal space of the heat pipe (100) may vary depending on the position in the first direction (Z direction).

[0039] In some embodiments, the lengths of the evaporation region (191), the adiabatic region (192), and the condensation region (193) in the first direction (Z direction) can be varied and are not limited to the relative lengths shown in FIG. 1.

[0040] According to some embodiments, the heat pipe (100) may be a micro heat pipe and may have various hydraulic diameters. For example, the hydraulic diameter of the heat pipe (100) may be 5 μm. However, the embodiments of the present disclosure are not limited thereto. For example, the hydraulic diameter of the heat pipe (100) may be smaller or larger than 5 μm. In some embodiments, the hydraulic diameter of the heat pipe (100) may be substantially larger than 5 μm.

[0041] In some embodiments, the working fluid (W) may be deionized water (DI water), hydrofluoroether (HFE), perfluorinated compounds (PFCs) and derivatives thereof, or may include them. However, the embodiments of the present disclosure are not limited thereto.

[0042] Referring to FIGS. 5 and 6, a semiconductor device (1) (e.g., a semiconductor package) may include a heat pipe (100). FIG. 5 is a cross-sectional view of a semiconductor device (1) according to one embodiment of the present disclosure. FIG. 6 is a cross-sectional view of an exemplary embodiment of a semiconductor device (1) including a plurality of semiconductor layers. In FIGS. 5 and 6, the size and relative size of the layers and regions may be exaggerated for clarity of explanation.

[0043] In some embodiments, the semiconductor device (1) may include a heat pipe (100), at least one semiconductor layer (200), and a heat sink (300). The at least one semiconductor layer (200) may generate heat, for example, as a byproduct of normal electrical operation performed therein. The heat pipe (100) may be configured to receive heat from the at least one semiconductor layer (200) and transfer the heat to the heat sink (300), and the heat sink (300) may be configured to remove heat from the semiconductor device (1) by releasing the heat to an external environment of the semiconductor device (1), for example.

[0044] In some embodiments, at least one semiconductor layer (200) may each be a semiconductor die (e.g., a semiconductor chip). For example, at least one semiconductor layer (200) may include at least one of a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a memory, etc. In some embodiments, at least one semiconductor layer (200) may be semiconductor dies of the same type (e.g., a semiconductor chip) or semiconductor dies of different types (e.g., a semiconductor chip).

[0045] In some embodiments, as illustrated in FIG. 5, when only a single semiconductor layer (200) is provided, the first bonding structure (410) may be configured to extend in a horizontal direction (e.g., X direction or Y direction) from the lower surface (200_L) of the semiconductor layer (200) (e.g., inside the lower surface (200_L) or on the lower surface (200_L)) to seal the bottom of the first internal space (S1) to be described below.

[0046] In some embodiments, referring to FIG. 6, a plurality of semiconductor layers (200) may be provided. For example, the plurality of semiconductor layers (200) may be stacked sequentially along a vertical direction (Z direction). For example, the plurality of semiconductor layers (200) may overlap each other in a vertical direction (Z direction). However, the embodiments of the present disclosure are not limited thereto. For example, only a single semiconductor layer (200) may be provided.

[0047] In some embodiments, the heat sink (300) may be disposed on the upper surface (200_U) of the at least one semiconductor layer (200), and at least a portion of the heat pipe (100) may be located within the at least one semiconductor layer (200) and the heat sink (300), or the heat pipe (100) may extend to penetrate the at least one semiconductor layer (200) and the heat sink (300). For example, the heat pipe (100) may extend in a vertical direction (Z direction) within the at least one semiconductor layer (200) and the heat sink (300).

[0048] According to one embodiment, the heat pipe (100) may be extended upward in a vertical direction (e.g., Z direction) from the lower surface (200_L) of the semiconductor layer (200) located at the bottom of the plurality of semiconductor layers (200), and may be extended through the upper surface (200_U) of the semiconductor layer (200) located at the top of the semiconductor layers and the lower surface (300_L) of the heat sink (300) to the upper region of the heat sink (300). For example, referring to FIG. 6, a heat sink (300) may be provided on the upper surface (200_U) of a semiconductor layer (200C) located at the top of a plurality of semiconductor layers (200), and a heat pipe (100) may be extended in a vertical direction (Z direction) from the lower surface (200_L) of a semiconductor layer (200A) located at the bottom of the plurality of semiconductor layers (200), penetrate at least one intermediate semiconductor layer (200B), pass through the upper surface (200_U) of the top semiconductor layer (200C) and the lower surface (300_L) of the heat sink (300), and extend to the upper region of the heat sink (300). However, embodiments of the present disclosure are not limited thereto. For example, the lowest portion of the heat pipe (100) may be defined by the upper surface of a semiconductor layer (e.g., the lowest semiconductor layer (200A)), or it may be located inside the semiconductor layer (e.g., the lowest semiconductor layer (200A)) and spaced apart from the lower surface of the semiconductor layer.

[0049] In some embodiments, the heat sink (300) may have various configurations for transferring heat. For example, the heat sink (300) may be a body comprising a thermally conductive material. For example, the thermally conductive material may comprise copper. However, the embodiments of the present disclosure are not limited thereto.

[0050] In some embodiments, the heat pipe (100) may include at least one via (110). For example, one or more of the plurality of vias (110) may be through-silicon vias (TSVs). For example, the via (110) may penetrate the semiconductor layer (200) in a vertical direction from the lower surface (200_L) of the semiconductor layer (200) to the upper surface (200_U). For example, the via (110) may be provided within a via hole (150) formed in the semiconductor layer (200). The via hole (150) may penetrate the semiconductor layer (200) in a vertical direction from the lower surface (200_L) of the semiconductor layer (200) to the upper surface (200_U). In some embodiments, the via (110) may include a liner composed of an electrically conductive material that coats the inner surface of the via hole (150) in a horizontal direction (e.g., X direction or Y direction). According to these embodiments, the via (110) may be a hollow structure. For example, the inner walls of the via (110) may define at least a portion of the first internal space (S1) formed within the via (110).

[0051] In some embodiments, the plurality of vias (110) may have various cross-sectional shapes, including cross-sectional shapes as described above with reference to FIGS. 1, FIG. 2, FIGS. 3a to 3c and FIGS. 4a to 4c. However, the embodiments of the present disclosure are not limited thereto.

[0052] In some embodiments, the semiconductor device (1) may further include bonding structures that bond the semiconductor layer (200) and / or the top semiconductor layer (200) and the heat sink (300) to each other. For example, the bonding structures may include at least one first bonding structure (410) provided between two vertically adjacent semiconductor layers (200) and a second bonding structure (420) provided between the top semiconductor layer (200) and the heat sink (300). The first bonding structure (410) may connect (e.g., bond) two vertically adjacent semiconductor layers (200) to each other. The second bonding structure (420) may connect (e.g., bond) the top semiconductor layer (200) and the heat sink (300) to each other.

[0053] In some embodiments, bonding structures (e.g., a first bonding structure (410) and / or a second bonding structure (420)) may bond semiconductor layers (200) to each other in vias (110) that penetrate them. In some exemplary embodiments, the bonding structures (e.g., a first bonding structure (410) and / or a second bonding structure (420)) may have an annular shape with a hole formed extending in a vertical direction, and the hole may have a size and / or cross-sectional shape substantially corresponding to the size and / or cross-sectional shape of the vias (110).

[0054] In some embodiments, the first bonding structure (410) may extend horizontally (e.g., in the X direction or Y direction) on the lower surface (200_L) or upper surface (200_U) of the semiconductor layer (200) (e.g., on the interior or surface). Additionally, the second bonding structure (420) may extend horizontally (e.g., in the X direction or Y direction) on the upper surface (200_U) of the uppermost semiconductor layer (200) (e.g., on the interior or surface).

[0055] For example, the second bonding structure (420) may be vertically overlapped with the via (110) and the first bonding structure (410) in the vertical direction (Z direction). For example, at least one via (110) may be located between two first bonding structures (410) (e.g., directly between them) and may connect the two first bonding structures (410) to each other (e.g., directly connected).

[0056] Alternatively or additionally, at least one via (110) may be located between one first bonding structure (410) and one second bonding structure (420) (e.g., directly between them) and may connect the first bonding structure (410) and the second bonding structure (420) to each other (e.g., directly connected). Alternatively or additionally, at least one via (110) may be located between one first bonding structure (410) and one sealing structure (430) to be described below (e.g., directly between them) and may connect the first bonding structure (410) and the sealing structure (430) to each other (e.g., directly connected). Alternatively or additionally, at least one via (110) may be located between the second bonding structure (420) and the sealing structure (430) (e.g., directly between them) and may connect them to each other (e.g., directly connected).

[0057] In some embodiments, the material of the first bonding structure (410) may be the same as or different from the material of the second bonding structure (420). Additionally, in some embodiments, the material of at least one first bonding structure (410) may be the same as or different from the material of at least one other first bonding structure (410). For example, at least one of the bonding structures (e.g., the first bonding structure (410) or the second bonding structure (420)) may comprise an electrically conductive material, and at least one other bonding structure (e.g., the first bonding structure (410) or the second bonding structure (420)) may comprise an electrically nonconductive material.

[0058] According to some embodiments, when N semiconductor layers (200) are stacked with reference to FIG. 6, N vias (110) may be provided in each of the N semiconductor layers (200). Additionally, N-1 first bonding structures (410) may be provided so as to be placed between two semiconductor layers (200) adjacent in the vertical direction. For example, when three semiconductor layers (200) are stacked as shown in FIG. 6, one first bonding structure (410) may be provided between the bottom semiconductor layer (200A) and the middle semiconductor layer (200B) in the vertical direction (Z direction), and another first bonding structure (410) may be provided between the middle semiconductor layer (200B) and the top semiconductor layer (200C). The first bonding structures (410) may connect the vias (110) formed in two semiconductor layers (200) adjacent in the vertical direction. However, the embodiments of the present disclosure are not limited thereto. For example, one or more semiconductor layers (200) may not include vias (110), and / or the lowest portion of a via (110) formed in any one semiconductor layer (200) may be closed and spaced apart from the lower surface of the semiconductor layer, so that the heat pipe (100) may not penetrate the entire stack composed of a plurality of semiconductor layers (200).

[0059] In some embodiments, the first bonding structure (410) and / or the second bonding structure (420) may be implemented as various types of bonding structures. For example, the first bonding structure (410) and / or the second bonding structure (420) may be bonding structures formed through thermal compression bonding (TCB), copper hybrid bonding (HCB), etc. In some embodiments, the first bonding structure (410) and / or the second bonding structure (420) may include copper-to-copper bonding (Cu to Cu bonding). In some embodiments, the first bonding structure (410) and / or the second bonding structure (420) may include an electrically conductive material (e.g., copper). However, the embodiments of the present disclosure are not limited thereto. For example, the first bonding structure (410) and / or the second bonding structure (420) can be formed through various bonding processes and may include various materials that are electrically conductive or non-conductive.

[0060] In some embodiments, one or more (e.g., some or all) of the first bonding structure (410) may comprise an electrically conductive material, and the second bonding structure (420) may comprise an electrically nonconductive material. Additionally, the working fluid (W) may be electrically nonconductive. For example, the second bonding structure (420) may comprise an electrically nonconductive material such as Parylene C. For example, the working fluid (W) may comprise perfluorocompounds (PFCs) or hydrofluorocarbons (HFCs). According to these embodiments, one or more vias (110) may be configured to form part of the heat pipe (100) while simultaneously performing an electrical connection function (e.g., signal or power transmission). For example, one or more semiconductor layers (200) (e.g., semiconductor die) can be electrically connected to each other through a conductive liner of a via (110) and a first bonding structure (410).

[0061] In some embodiments, a through hole or gap may be provided in the first bonding structure (410) so that the hollow spaces of vias (110) formed in two vertically adjacent semiconductor layers (200) can fluidly communicate with each other. For example, the through hole or gap of the first bonding structure (410) may overlap vertically with the hollow spaces of the vias (110). For example, the through hole or gap of the first bonding structure (410) may define a part of the first internal space (S1).

[0062] In some embodiments, the cross-section of the through hole or gap of each of the first bonding structure (410) and the second bonding structure (420) and the cross-section of the hollow space of the via (110) may be aligned and may have a size and / or shape to ensure capillary flow of the working fluid (W). For example, the cross-section may have a shape and / or size as described with reference to FIGS. 1, 2, FIGS. 3a to 3c and FIGS. 4a to 4c. However, the embodiments of the present disclosure are not limited thereto.

[0063] In some embodiments, the hollow space of the via (110) and the through hole or gap of the first bonding structure (410) and the second bonding structure (420) may define a single through hole extending in a vertical direction (Z direction) through one or more semiconductor layers (200). The single through hole may partially define a first internal space (S1). In some embodiments, the first internal space (S1) may include a portion of the working fluid (W) of the heat pipe (100). For example, the via (110) and the first internal space (S1) may be a portion of the heat pipe (100) configured to receive heat (B1 in FIG. 2). For example, a portion of the via (110) and the first internal space (S1) may be composed of an evaporation region (191) of the heat pipe (100), where the working fluid (W) may absorb and evaporate heat (B1). In some embodiments, at least a portion of the first internal space (S1) may be composed of at least a portion of the insulating region (192 in FIG. 2) of the heat pipe (100), in which the working fluid (W) may move between the evaporation region (191) and the condensation region (193).

[0064] In some embodiments, the heat pipe (100) may further include a condenser (130) fluidically connected to the first internal space (S1). For example, the heat sink (300) may define a second internal space (S2) by including a hole extending from the lower surface (300_L) of the heat sink (300) to the upper region of the heat sink (300). For example, the hole of the heat sink (300) may define a condenser (130), and the condenser (130) may include part or all of the second internal space (S2). In some embodiments, if the lower region of the second internal space (S2) is composed of part of an insulating region (192) or an evaporation region (191 in FIG. 1), at least a portion of the working fluid (W) may evaporate in the lower region of the second internal space (S2).

[0065] In some embodiments, the cross-section of the condenser (130) may be aligned with the cross-section of the through hole or gap of the first bonding structure (410) and the second bonding structure (420), and the cross-section of the hollow space of the via (110), and may have a size and / or shape that can ensure capillary flow of the working fluid (W). For example, the cross-section may have the shape and / or size described with reference to FIGS. 1, FIGS. 2, FIGS. 3a to 3c and FIGS. 4a to 4c. However, the embodiments of the present disclosure are not limited thereto.

[0066] In some embodiments, a condenser (130) including a second internal space (S2) may be part of a heat pipe (100) configured to release heat (B2 in FIG. 2) to a heat sink (300). For example, at least a portion of the condenser (130) including the second internal space (S2) may be composed of a condensation region (193) of the heat pipe (100) where the working fluid (W) is condensed to release heat (B2). In some embodiments, at least a portion of the second internal space (S2) may include a portion of an insulating region (192 in FIG. 2) of the heat pipe (100), in which the working fluid (W) may move between the evaporation region (191) and the condensation region (193).

[0067] In some embodiments, the plurality of via holes (150), the hollow spaces of the plurality of vias (110) (e.g., a first internal space (S1) defined at least partially by the plurality of vias (110)) and / or the condenser (130) (e.g., a second internal space (S2) defined at least partially by the condenser (130)) may have various cross-sectional shapes as described with reference to FIGS. 3a to 3c and FIGS. 4a to 4c. For example, the cross-sectional shape of the plurality of via holes (150), the hollow spaces of the plurality of vias (110) (e.g., a first internal space (S1)), and / or the condenser (130) (e.g., a second internal space (S2)) may be a shape containing only straight lines (i.e., a polygonal shape) or may include a shape combining straight lines and curves. Additionally, the cross-sectional shapes may include any number of inner edges (C1) (see FIGS. 3a to 3c and FIGS. 4a to 4c) configured to induce movement of the working fluid (W) by capillary action in the vertical direction (Z direction), and the inner edges (C1) may have various shapes.

[0068] In some embodiments, the cross-sectional shape and / or size of the plurality of via holes (150), the hollow spaces of the plurality of vias (110) (e.g., first internal space (S1)), and / or the condenser (130) (e.g., second internal space (S2)) may vary depending on the position in the vertical direction (Z direction). For example, referring to FIGS. 5 and 6, the horizontal width (e.g., X direction or Y direction) of the first internal space (S1) may be kept constant along the vertical direction (Z direction), while the horizontal width (e.g., X direction or Y direction) of the second internal space (S2) may increase along the vertical direction (Z direction). In some embodiments, at one or more (e.g., some or all) vertical levels of the condenser (130), the width of the second internal space (S2) may be greater than the width of the first internal space (S1) (e.g., maximum width). However, the present disclosure is not limited to the shapes, sizes, and widths described above. According to some embodiments, the hollow space of a plurality of vias (110) may follow the shape of the via hole (150) when the vias (110) are formed within the via hole (150).

[0069] In some embodiments, as illustrated in FIG. 6, a sealing structure (430) may be provided. For example, the sealing structure (430) may include a body that seals the bottom of the first internal space (S1). For example, the sealing structure (430) may extend horizontally (e.g., in the X direction or the Y direction) from the bottom surface (200_L) of the bottom semiconductor layer (200A). The sealing structure (430) may define the bottom of the first internal space (S1). For example, the sealing structure (430) may seal the bottom of the heat pipe (100) to prevent the working fluid (W) from leaking out of the semiconductor device (1) through the bottom. For example, the sealing structure (430) may not include a hole or a through hole.

[0070] In some embodiments, the sealing structure (430) may be a bonding structure that bonds the bottom semiconductor layer (200A) to other components of the semiconductor device (1). For example, the sealing structure (430) may be a bonding structure formed through thermal compression bonding (TCB), hybrid bonding (HCB), etc. In some embodiments, the sealing structure (430) may include copper-copper bonding. In some embodiments, the sealing structure (430) may include an electrically conductive material, for example, said electrically conductive material may include copper. However, the embodiments of the present disclosure are not limited thereto. For example, the sealing structure (430) may be formed through various types of bonding processes and may include a conductive or non-conductive material. Alternatively, the sealing structure (430) may not be a bonding structure.

[0071] In some embodiments, a plurality of vias (110), a first bonding structure (410), a second bonding structure (420), and a sealing structure (430) may be connected to each other and may overlap each other in a vertical direction (Z direction).

[0072] According to some embodiments, the heat pipe (100) may be configured to receive heat from one or more semiconductor layers (200) by means of a first internal space (S1) that extends vertically through one or more (e.g., some or all) semiconductor layers (200) that generate heat (B1 in FIG. 2). For example, at least a portion of the first internal space (S1) may be configured as an evaporation region (191 in FIG. 1), and the working fluid (W) within the first internal space (S1) may evaporate due to the heat. Additionally, at least a portion of the first internal space (S1) and / or the second internal space (S2) may be composed of an adiabatic region (192) through which steam (A1 in FIG. 2) travels between an evaporation region (191) and a condensation region (193), and at least a portion of the second internal space (S2) may be composed of a condensation region (193) of a heat pipe (100) so that heat (B2 in FIG. 2) can be released to a heat sink (300) as the working fluid (W) condenses. After condensation, the working fluid may return to the first internal space (S1) through capillary action by an internal corner (C1) formed in one or more (e.g., some or all) of the condenser (130) and a plurality of vias (110).

[0073] In some embodiments, the height (H1) from the lower surface of the sealing structure (430) to the upper surface (200_U) of the uppermost semiconductor layer (200C), or the height (H1) from the lower surface of the lowest semiconductor layer (200A) to the upper surface (200_U) of the uppermost semiconductor layer (200C), may be set to various values. According to some embodiments, the height (H1) may be the height of the first internal space (S1). For example, the height (H1) may be about 1 mm.

[0074] In some embodiments, the height (H2) from the upper surface (200_U) of the top semiconductor layer (200C) to the upper surface (300_U) of the heat sink (300) can be set to various values. In some embodiments, the height (H2) may be the height of the condenser (130). For example, the height (H2) may be about 9 mm.

[0076] In some embodiments, with reference to FIGS. 5 to 7, a method (500) for manufacturing a semiconductor device (e.g., semiconductor device 1) including a heat pipe (100) may be provided.

[0077] For example, the above method (S500) may include the step S510 of forming a plurality of via holes (150) in a plurality of semiconductor layers (200), the step S520 of forming vias (110) in the plurality of via holes (150), the step S530 of stacking a plurality of semiconductor layers (200), the step S540 of preparing a heat sink (300), the step S550 of connecting the uppermost semiconductor layer (200) and the heat sink (300), the step S560 of injecting an operating fluid (W) into a heat pipe (100), and the step S570 of sealing the heat pipe.

[0078] In some embodiments, at step S510, via holes (150) may be formed in each of one or more semiconductor layers (200). For example, via holes (150) may be formed to penetrate vertically from the lower surface (200_L) to the upper surface (200_U) of the semiconductor layer (200). In some embodiments, via holes (150) may be formed simultaneously for each of the plurality of semiconductor layers (200), or may be formed at different times.

[0079] In some embodiments, at step S520, a via (110) may be formed by filling a material within the via hole (150). For example, at step S520, a copper deposition process may be performed within the via hole (150) to form the via (110). For example, the material of the via (110) (e.g., copper) may coat the inner surface of the via hole (150) in a horizontal direction (e.g., X direction or Y direction), and the via (110) may have a hollow structure to define a portion of the first internal space (S1) of the heat pipe (100) to be formed thereafter. At step S520, a pad may also be formed. For example, the pad may be a portion used to form the first bonding structure (410) and / or the second bonding structure (420).

[0080] In some embodiments, at step S530, the semiconductor layer (200) can be bonded by stacking the semiconductor layer (200) in a vertical direction (Z direction) and forming a first bonding structure (410). For example, at step S530, the vias (110) of the semiconductor layer (200) can be aligned in a vertical direction. For example, the capillaries (e.g., inner corners (C1)) of the hollow space of the vias (110) can be aligned (or overlapped) perpendicularly to each other. According to some embodiments, the bonding may include performing thermal compression bonding (TCB) or copper hybrid bonding (HCB) between the semiconductor layers (200). For example, the bonding may include copper-copper bonding, and the first bonding structure (410) may be composed of copper formed by the copper-copper bonding. In some embodiments, the semiconductor layers (200) are vertically aligned and bonded to each other so that a single through hole is formed that penetrates the semiconductor layers (200) in a vertical direction (Z direction), thereby defining a first internal space (S1).

[0081] In some embodiments, at step S540, a condenser (130) may be formed in the heat sink (300). For example, at step S540, at least one void may be formed in the heat sink (300), and said at least one void may define a condenser (130) that includes a second internal space (S2) of the heat pipe (100) to be formed thereafter. For example, said at least one void (and condenser (130)) may include a hole extending from the lower surface (300_L) of the heat sink (300) to the upper portion of the heat sink (300), thereby defining the second internal space (S2).

[0082] In some embodiments, step S550 may include providing a heat sink (300) on the upper surface (200_U) of the top semiconductor layer (200C) and bonding the heat sink (300) to the top semiconductor layer (200C). For example, in step S550, the condenser (130) may be aligned perpendicularly to the via (110) of the top semiconductor layer (200C). For example, the capillary of the condenser (130) (e.g., inner corner C1) and the hollow space of the via (110) may be aligned perpendicularly to each other (or overlap). In some embodiments, the bonding may include performing thermal compression bonding (TCB) or hybrid bonding between the top semiconductor layer (200C) and the heat sink (300). For example, in one embodiment, the bonding may include copper-copper bonding, and the second bonding structure (420) may be composed of copper formed by the copper-copper bonding. Alternatively, the second bonding structure (420) may be formed in a different way. In some embodiments, the heat sink (300) and the top semiconductor layer (200C) may be vertically aligned and bonded to each other so that the first internal space (S1) and the second internal space (S2) overlap each other in the vertical direction (e.g., Z direction) and are formed to be in a state of fluid communication with each other.

[0083] In some embodiments, at step S560, a working fluid (W) may be injected into the first internal space (S1) and / or the second internal space (S2) of the heat pipe (100). For example, a predetermined amount of the working fluid (W) may be injected to have a predetermined pressure. For example, the working fluid (W) may be injected into the semiconductor device through the hollow space of the via (110) of the bottom semiconductor layer (200A). For example, at the time step S560 is performed, the bottom portion of the hollow space of the via (110) of the bottom semiconductor layer (200A) may be exposed to the outside of the semiconductor device. In some embodiments, step S560 may be performed before step S540 and / or step S550, or simultaneously with them.

[0084] In some embodiments, at step S570, the heat pipe (100) can be sealed using a sealing structure (430). For example, the sealing structure (430) may be provided to extend horizontally (e.g., in the X direction or Y direction) on (or within) the lower surface (200_L) of the bottom semiconductor layer (200A). By sealing the bottom portion of the first internal space (S1), the sealing structure (430) can prevent the working fluid (W) from leaking out of the semiconductor device (1). In some embodiments, at step S560, the internal space of the heat pipe (100) (e.g., the first internal space (S1) and the second internal space (S2)) may be made to have a vacuum state. For example, at step S570, air may be removed from the heat pipe (100) through the vacuum. Accordingly, the heat pipe (100) can be sealed under a vacuum state.

[0085] In some embodiments, the step of providing a sealing structure (430) on (or within) the lower surface (200_L) of the lowest semiconductor layer (200A) may be performed prior to steps S530, S540, S550, S560 and / or S570. For example, after the sealing structure (430) is provided, the heat pipe (100) may be sealed by connecting a heat sink (300) containing a working fluid (W) to the top semiconductor layer (200C) (steps S550–S570).

[0086] In some embodiments, when the bottom of the heat pipe (100) is located inside the semiconductor layer (e.g., bottom semiconductor layer (200A)) and the bottom of the heat pipe (100) is spaced apart from the bottom surface of the semiconductor layer (200), a sealing structure (430) may not be provided. For example, sealing of the heat pipe (100) (step S570) can be performed by connecting a heat sink (300) containing a working fluid (W) to the top semiconductor layer (200C).

[0087] The present disclosure is presented to enable those skilled in the art to manufacture and use the disclosed information and to apply it in the context of specific applications. Although the foregoing has been described with respect to specific embodiments, other embodiments and additional embodiments may be derived without departing from the scope of the present disclosure.

[0088] Various variations and different modes of use in different applications will be obvious to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Accordingly, this disclosure is not limited to the exemplary embodiments presented herein, but should be given the maximum scope consistent with the principles and novel features disclosed herein.

[0089] In the description of this specification, numerous specific details are described to provide a more comprehensive understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without being limited to these specific details. Furthermore, in other cases, known structures and devices are illustrated in the form of block diagrams instead of detailed descriptions so as not to unnecessarily obscure the present disclosure.

[0090] All features disclosed herein (including the appended claims, summary, and drawings) may be replaced by alternative features that perform the same, equivalent, or similar purposes, unless otherwise expressly stated. Accordingly, unless otherwise expressly stated, each disclosed feature is merely an example of one of a general category of equivalent or similar features.

[0091] Various features are described in this disclosure with reference to the drawings. However, the drawings are intended only to facilitate the description of the features and are not intended to provide a comprehensive description of the disclosure or to limit the scope of the disclosure. Furthermore, the illustrated examples are not required to include all aspects or all advantages. Any aspects or advantages described in relation to a particular example are not limited to that example and may be similarly implemented in other embodiments even if they are not illustrated in the drawings or explicitly described.

[0092] Furthermore, any component in a claim that does not explicitly state "means for" or "step for" to perform a specific function shall not be interpreted as a "means" or "step" provision of 35 USC §112(f) of the United States Patent Act. In particular, expressions such as "step of" or "act of" used in the claims of this specification are not intended to invoke the provisions of 35 USC §112(f).

[0093] When terms such as "left," "right," "front," "back," "top," "bottom," "forward," "reverse," "clockwise," and "counterclockwise" are used, they are for convenience of explanation only and are not intended to imply a specific fixed direction. Rather, these terms are used to indicate the relative position and / or orientation between various parts of an object.

[0094] Although the embodiments have been described based on circuit functions, the embodiments of the present disclosure are not limited thereto. Possible embodiments may be implemented in the form of a single integrated circuit, a multi-chip module, a single card, a system-on-a-chip, or a multi-card circuit package. As will be obvious to those skilled in the art, various embodiments may be implemented as part of a larger system. For example, these embodiments may be used in combination with a digital signal processor, a microcontroller, a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a general-purpose computer.

[0095] For the sake of brevity, known components relating to semiconductor devices may not be described in detail or may be omitted in this specification. However, even if a specific component is described or illustrated as being included in a semiconductor device in this disclosure, it is not necessarily included in the claimed semiconductor device unless such component is explicitly stated to be included in the claim. Furthermore, it will be understood that even if a specific deposition or etching method used in the manufacture of a semiconductor device is not mentioned or is not mentioned in this specification, a conventional deposition or etching method may be applied in such manufacturing steps.

[0096] Although non-limiting exemplary embodiments have been described in relation to the drawings above, it will be apparent to those skilled in the art that various modifications and variations are possible without departing from the scope of the present disclosure. Explanation of the symbols

[0097] 1: Semiconductor device, 100: Heat pipe, 191: Evaporation region, 192: Insulation region, 193: Condensation region, 200: Semiconductor layer, 300: Heat sink

Claims

Claim 1 A semiconductor device comprising: a stack; a heat sink; and a heat pipe; wherein the stack comprises: a first semiconductor layer; and a second semiconductor layer stacked in a first direction on the first semiconductor layer; the heat sink is stacked in the first direction on the second semiconductor layer; and the heat pipe extends in the first direction within the first semiconductor layer, the second semiconductor layer and the heat sink. Claim 2 A semiconductor device according to claim 1, wherein the heat pipe is configured to transfer heat from the stack toward the heat sink through a working fluid inside the heat pipe. Claim 3 A semiconductor device according to claim 1, wherein the heat pipe is configured to move a working fluid toward the stack through capillary action. Claim 4 A semiconductor device according to claim 1, wherein the heat pipe comprises: a first via located inside the first semiconductor layer; and a second via located inside the second semiconductor layer; and each of the first via and the second via comprises an internal space that moves a working fluid through capillary action. Claim 5 A semiconductor device according to claim 1, comprising: a first via located inside the first semiconductor layer; a second via located inside the second semiconductor layer; and a bonding structure connecting the first semiconductor layer and the second semiconductor layer, wherein the first via and the second via include an internal space for moving a working fluid through capillary action, and the heat pipe moves the working fluid through the bonding structure. Claim 6 A semiconductor device according to claim 1, further comprising: a bonding structure connecting the heat sink and the second semiconductor layer; and an operating fluid inside the heat pipe, wherein the bonding structure and the operating fluid are electrically non-conductive. Claim 7 A semiconductor device according to claim 1, wherein the heat pipe comprises: a via located inside the second semiconductor layer; a first bonding structure located between the first semiconductor layer and the second semiconductor layer; a second bonding structure connecting the second semiconductor layer and the heat sink and being electrically nonconductive; and an electrically nonconductive working fluid; wherein the internal space of the via and the internal space of the first bonding structure are configured to move the working fluid through capillary action, and the first semiconductor layer and the second semiconductor layer are electrically connected by the via and the first bonding structure. Claim 8 A semiconductor device according to claim 1, wherein the heat pipe comprises: a first via located inside the first semiconductor layer; and a second via located inside the second semiconductor layer; wherein the first via and the second via comprise an internal space for moving a working fluid through capillary action, the first semiconductor layer is connected to the second semiconductor layer by a bonding structure, and the first via is fluidly connected to the second via through the bonding structure. Claim 9 A semiconductor device according to claim 1, wherein the first semiconductor layer comprises a first semiconductor chip and the second semiconductor layer comprises a second semiconductor chip. Claim 10 A semiconductor device according to claim 1, wherein the heat pipe comprises a condenser for a working fluid; and at least a portion of the condenser is located inside the heat sink. Claim 11 A semiconductor device comprising: a stack; and a heat sink; wherein the stack comprises: a first semiconductor chip comprising a first via having a first internal space; and a second semiconductor chip stacked in a first direction on the first semiconductor chip and comprising a second via having a second internal space; and wherein the heat sink is stacked in the first direction on the second semiconductor chip and comprises a third internal space, and the first internal space, the second internal space and the third internal space overlap each other in the first direction, fluidly communicate with each other, and are provided as heat pipes. Claim 12 A semiconductor device according to claim 11, wherein the heat pipe is configured to transfer heat from the stack toward the heat sink through a working fluid inside the heat pipe. Claim 13 In claim 11, the semiconductor device is configured such that the heat pipe moves the working fluid toward the stack through capillary action. Claim 14 A semiconductor device according to claim 11, further comprising: a bonding structure connecting the second semiconductor chip and the heat sink, which is electrically nonconductive; and an electrically nonconductive working fluid. Claim 15 In claim 11, the heat pipe further comprises: a first bonding structure located between the first semiconductor chip and the second semiconductor chip; a second bonding structure connecting the heat sink and the second semiconductor chip and being electrically nonconductive; and an electrically nonconductive working fluid; wherein the first internal space of the first via, the second internal space of the second via, and the internal space of the first bonding structure are configured to move the working fluid through capillary action, and the first semiconductor chip and the second semiconductor chip are electrically connected through the first via, the second via, and the first bonding structure, a semiconductor device. Claim 16 A semiconductor device according to claim 11, wherein at least a portion of the first internal space or at least a portion of the second internal space is provided as an evaporator for a working fluid. Claim 17 A semiconductor device according to claim 11, wherein at least a portion of the third internal space is provided as a condenser for a working fluid. Claim 18 A semiconductor device comprising, in claim 11, a sealing structure that seals the bottom of the first internal space. Claim 19 In paragraph 18, the above-mentioned sealing structure is a semiconductor device comprising copper. Claim 20 In paragraph 18, the above-mentioned sealing structure is an electrically non-conductive semiconductor device.

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