Semiconductor device and method of controlling underfill overflow

Abstract

A semiconductor device has a substrate and an interconnection structure formed on a die attachment area of ​​the substrate. An insulating layer is formed on the surface of the substrate. A trench is formed within the insulating layer between the die attachment area and the interconnection structure and extends around the perimeter of the die attachment area. A semiconductor die is placed on the die attachment area. Underfill material is deposited beneath the semiconductor die. The trench prevents or obstructs excess underfill material from reaching the interconnection structure. A T-bar structure is formed between the die attachment area and the interconnection structure and extends around the perimeter of the die attachment area. The trench and / or T-bar structure function as an overflow structure that obstructs the flow of underfill material. Multiple trenches and / or multiple T-bar structures may be alternately arranged around the perimeter of the die attachment area.

Description

Technology Field

[0001] The present invention generally relates to a semiconductor device, and more specifically to an underfill overflow control method and a semiconductor device. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmission and reception of electromagnetic signals, control of electronic devices, and the generation of visual images for optoelectronic and television displays. Semiconductor devices are used in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. They can also be found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor dies and / or semiconductor wafers may be stacked for space efficiency. FIG. 1 illustrates a conventional semiconductor wafer or die (50) having a conductive layer (52) and a bump (54). A semiconductor die (60) is mounted on the semiconductor wafer / die (50) in a die attachment area (62) having a bump (64) connecting the conductive layer (62) and a contact pad (68). The semiconductor wafer / die (50) may be referred to as a mother die, and the semiconductor die (60) may be referred to as a child die in a stacked arrangement. An underfill material (70) is deposited under the semiconductor die (60) for structural support and environmental protection. The distribution of the underfill material (70) is generally difficult to control depending on the manufacturing process. Excess underfill material (70) may flow out or overflow from the die attachment area (62) depending on the underfill material and reach the bump (54), causing electrical insulation or short circuit conditions of the interconnect structure as well as other inspection and manufacturing defects. Brief explanation of the drawing

[0004] FIG. 1 illustrates a conventional underfill overflow for a nearby bump; FIGS. 2a-2f illustrate a semiconductor wafer having a plurality of semiconductor dies separated by a top street; FIGS. 3a-3l illustrate a process of forming an overflow structure as a trench between a die attachment area and an interconnection structure formed on a substrate; FIGS. 4a-4f illustrate another process for forming an overflow structure as a T-bar structure between a die attachment area and an interconnection structure formed on a substrate; FIG. 5 illustrates an embodiment having a higher T-bar structure; FIG. 6 illustrates an embodiment having a trench and a T-bar structure; FIGS. 7a-7b illustrate an embodiment in which trench and T-bar structures are arranged alternately; FIG. 8 illustrates a printed circuit board (PCB) with different types of packages placed on the surface of the PCB. Specific details for implementing the invention

[0005] The present invention is described in the following description with reference to the drawings by one or more embodiments, in which similar numbers indicate identical or similar elements. Although the present invention is described in the best mode for achieving the purposes of the invention, it will be understood by those skilled in the art that alternative embodiments, modifications, and equivalents that may be included within the spirit and scope of the invention are intended by the invention defined by the appended claims and the equivalents supported by the following disclosure and drawings. As used herein, the term "semiconductor die" means both singular and plural, and may refer to both a single semiconductor device and multiple semiconductor devices.

[0006] Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. Active electrical components, such as transistors and diodes, function to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, generate the relationship between voltage and current necessary to perform the electrical circuit function.

[0007] Back-end manufacturing refers to cutting or singulating a finished wafer into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. To singulate semiconductor dies, the wafer is cut and fractured along a non-functional area of ​​the wafer called a saw street or scribe. The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are mounted on a package substrate containing pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor dies are connected to contact pads within the package. Electrical connections can be made using conductive layers, bumps, stud bumps, conductive paste, or bond wires. An encapsulant or other molding material is deposited on the package to provide physical support and electrical insulation. Subsequently, the finished package is inserted into an electrical system, allowing the functions of the semiconductor device to be utilized by other system components.

[0008] FIG. 2a illustrates a semiconductor wafer (100a) having a base substrate material (102) such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials for structural support. A plurality of semiconductor dies or components (104a) are formed on the wafer (100a) separated by a non-active, inter-die wafer region or a top street (106a). The top street (106a) provides a cutting region for singulating the semiconductor wafer (100a) into individual semiconductor dies (104a). In one embodiment, the semiconductor wafer (100a) has a diameter of 100 to 450 millimeters (mm). The semiconductor wafer (100a) may be rectangular or any other geometric shape.

[0009] FIG. 2b illustrates a cross-sectional view of a portion of a semiconductor wafer (100a). Each semiconductor die (104a) has a back surface or non-active surface (108a) and an active layer (110a) and includes an analog or digital circuit implemented by an active device, a passive device, a conductive layer, and a dielectric layer formed inside the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements, which are formed within the active layer (110) to implement the analog or digital circuit, such as a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a memory, or other signal processing circuit. The semiconductor die (104a) may also include an IPD, such as an inductor, a capacitor, and a resistor, and other circuits for RF signal processing.

[0010] An electrically conductive layer (112) is formed within the active layer (110a) using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer (112) may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive materials. The conductive layer (112) acts as a contact pad or redistribution layer (RDL) electrically connected to the circuit of the active layer (110). A portion of the conductive layer (112) may be electrically common or electrically insulated depending on the design and function of the semiconductor die (104a) and other electrical components within the semiconductor wafer (100a).

[0011] An insulating or dielectric layer (114) is formed on an active surface (110a) and a conductive layer (112) using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer (114) comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials having similar insulating and structural properties.

[0012] In FIG. 2c, a semiconductor wafer (100a) is singulated into individual semiconductor dies (104a) via a saw street (106a) using a saw blade or laser cutting tool (118). After singulation, the individual semiconductor dies (104a) can be inspected and electrically tested for identification of known superior dies or units (KGD / KGU).

[0013] In another case, FIG. 2d illustrates a semiconductor wafer (100b) manufactured similarly to a semiconductor wafer (100a). A plurality of semiconductor dies or components (104b) are formed on the wafer (100b) separated by a non-active, inter-die wafer area or a top street (106b). The top street (106b) provides a cutting area for singulating the semiconductor wafer (100b) into individual semiconductor dies (104b). In one embodiment, the semiconductor wafer (100b) has a diameter of 100-450 mm. The semiconductor wafer (100b) may be rectangular or any other geometric shape.

[0014] FIG. 2e illustrates a cross-sectional view of a portion of a semiconductor wafer (100b). Each semiconductor die (104b) has a back surface or a non-active surface (108b) and an active layer (110b) and includes an analog or digital circuit implemented by an active device, a passive device, a conductive layer, and a dielectric layer formed inside the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active layer (110) to implement an analog circuit or a digital circuit, such as a DSP, ASIC, memory, or other signal processing circuit. The semiconductor die (104b) may also include an IPD, such as an inductor, capacitor, and resistor, and other circuits for RF signal processing. The semiconductor die (104b) may have different electrical functions than the semiconductor die (104a).

[0015] An electrically conductive layer (120) is formed within the active layer (110b) using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer (120) may be one or more layers made of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive materials. The conductive layer (120) functions as a contact pad or redistribution layer (RDL) electrically connected to the circuit of the active layer (110b).

[0016] An electrically conductive bump material is deposited onto a conductive layer (120) using an evaporation, electroplating, electroless plating, ball drop, or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and there are optional flux solutions. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer (120) using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump (122). In one embodiment, the bump (122) is formed on an Under Bump Metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. The bump (122) may also be compression bonded or thermally compressed to the conductive layer (120). The bump (122) represents a type of interconnection structure that can be formed on the conductive layer (120). The interconnection structure may also use bond wire, conductive paste, stud bumps, microbumps, or other electrical interconnections.

[0017] In FIG. 2f, a semiconductor wafer (100b) is singulated into individual semiconductor dies (104b) through a saw street (106b) using a saw blade or laser cutting tool (118). After singulation, the individual semiconductor dies (104b) can be inspected and electrically tested for identification of known superior dies or units (KGD / KGU).

[0018] FIG. 3a illustrates a more detailed view of a portion of the semiconductor wafer (100a) prior to singulation, or a portion of the semiconductor die (104a) after singulation. In one embodiment, the insulating layer (114) has a thickness (T1) of 10.0 μm. A portion of the insulating layer (114) is removed by a laser direct ablation (LDA) or etching process using a laser (131) to form openings or trenches (130a-130f). The openings (130a, 130d, 130e, and 130f) extend to and expose the conductive layer (112). The location of the openings (130a, 130d, 130e, and 130f) is selected to be aligned with the conductive layer (112). The trenches (130b and 130c) extend from the insulating layer (114) to the active surface (110a) or to a level above the active surface. For example, FIG. 3b illustrates in more detail the trenches (130b and 130c) of the region (132) extending to the insulating layer (114) above the active surface (110a) with a depth (D1) of less than 10.0 μm and a width (W1) of at least 50.0 μm. FIG. 3C is a top view of a semiconductor die (104a) having openings (130a, 130d, 130e, and 130f) exposing the conductive layer (112) and trenches (130b and 130c) extending around the outer periphery of the die attachment region (134). As described, the trenches (130b and 130c) function as overflow structures that absorb, block, hinder, or otherwise suppress the overflow of the underfill material from reaching other interconnected structures.

[0019] In FIG. 3d, a photoresist layer (140) is deposited on a semiconductor wafer (100a) or a semiconductor die (104a). In FIG. 3e, the photoresist layer (140) is LDA or patterned and etched on a conductive layer (112) to form an opening (142). In FIG. 3f, the opening (142) within the photoresist layer (140) is filled with Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material to form a conductive pillar (144).

[0020] In FIG. 3g, an electrically conductive bump material is deposited onto a conductive pillar (144) using an evaporation, electroplating, electroless plating, ball drop, or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and there are optional flux solutions. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive pillar (144) using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump (146). In one embodiment, the bump (146) is formed on an Under Bump Metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. The bump (146) may also be compression bonded or thermally bonded to the conductive pillar (144). A bump (146) represents a type of interconnect structure that can be formed on a conductive pillar (144). The interconnect structure may also use bond wire, conductive paste, stud bumps, microbumps, or other electrical interconnects. A combination of the conductive pillar (144) and the bump (146) forms a vertical interconnect structure (148).

[0021] In FIG. 3h, the photoresist layer (140) is removed to leave an interconnect structure (148) on the conductive layer (112) of the semiconductor die (104a). One or more electrical components (150) are placed on the die attachment area (134) using a pick-and-place process with bumps (122) oriented toward the conductive layer (112). In one embodiment, the electrical component (150) may be the semiconductor die (104b) of FIG. 2f. Alternatively, the electrical component (150) may include another semiconductor die, a semiconductor package, a surface mount device, an individual electrical device, an interconnect structure, or an IPD. In this case, the semiconductor die (104a) is considered as a parent die, i.e., a larger semiconductor die, and the semiconductor die (104b) is considered as a child die smaller than the semiconductor die (104a) in a stacked semiconductor array. While the semiconductor die (104a) may have large dimensions of 2.0 x 2.0 mm, the semiconductor die (104b) may generally be smaller than the semiconductor die (104a) at 1.0 x 1.0 mm. FIG. 3i illustrates an electrical component (150) mounted on the semiconductor die (104a) with a bump (122) electrically and mechanically bonded to a conductive layer (112) within the die attachment area (134).

[0022] In FIG. 3j, the underfill material (156) is deposited under the electrical component (150). The distribution of the underfill material (156) can be difficult to control. Excess underfill material (156) flows outward from the perimeter of the electrical component (150). Since defects may occur, the underfill material (156) must not reach the interconnect structure (148). When the underfill material (156) reaches the trench (130c), the trench acts as an overflow structure that absorbs, blocks, hinders, or otherwise suppresses further progression of the underfill material. That is, the excess underfill material (156) flows into the trench (130c) and blocks the outward flow of the underfill material toward the interconnect structure (148). FIG. 3k illustrates a top view of trenches (130b and 130c) placed around the outer periphery of an electrical component (150) to surround all sides of the electrical component (150). The underfill material (156) is shown being obstructed by the trenches (130c) within the stacked semiconductor package (158).

[0023] If the capacity of the trench (130c) is insufficient to block the outward flow of the underfill material (156), the trench (130b) acts as a secondary overflow structure to provide an additional protective layer that absorbs, blocks, hinders, or otherwise suppresses further progression of the underfill material. When the underfill material (156) reaches the trench (130b), the trench acts as an overflow structure that absorbs, blocks, hinders, or otherwise suppresses further progression of the underfill material. That is, excess underfill material (156) flows into the trench (130c) and blocks the outward flow of the underfill material toward the interconnection structure (148). FIG. 3L illustrates a top view of the underfill material (156) being hindered by the trench (130b).

[0024] The trenches (130b and 130c) control the overflow of excess underfill material (156) flowing out from under the semiconductor die (104b). This embodiment illustrates two trenches (103b and 130c). There may be only one trench or there may be two or more trenches. In any case, depending on the control of the underfill material (156), one or more trenches are placed around the outer periphery of the die attachment area (134) and the electrical component (150) to prevent or hinder the underfill material from reaching the interconnect structure (148).

[0025] In another embodiment continuing from FIG. 3h, trenches (130b and 130c) are filled with a solid material such as metal, polymer, or epoxy to form T-bar structures (160a and 160b) as shown in FIG. 4a. Components having similar functions are indicated by the same reference numerals. The trenches (130b and 130c) may have a width (W2) of at least 20.0 μm. The T-bar structures (160a-160b) have a width (W3) of at least 30.0 μm.

[0026] One or more electrical components (150) are placed on a die attachment area (134) using a pick-and-place process with bumps (122) oriented toward a conductive layer (112). In one embodiment, the electrical component (150) may be a semiconductor die (104b) of FIG. 2f. Alternatively, the electrical component (150) may include another semiconductor die, a semiconductor package, a surface mount device, an individual electrical device, an interconnect structure, or an IPD. In this case, the semiconductor die (104a) is considered a parent die, i.e., a larger semiconductor die, and the semiconductor die (104b) is considered a child die smaller than the semiconductor die (104a) in a stacked arrangement. FIG. 4b illustrates an electrical component (150) mounted on a semiconductor die (104a) with bumps (122) electrically and mechanically bonded to a conductive layer (112) within the die attachment area (134).

[0027] FIG. 4c is a top view of a semiconductor die (104a) having a T-bar structure (160a and 160b) extending around the outer periphery of the bump (146) of the interconnect structure (148) and the die attachment area (134). The T-bar structure (160a and 160b) can be formed within the same photomask as the conductive layer (112), that is, before forming the interconnect structure (148). As illustrated, the T-bar structure (160a and 160b) functions as an overflow structure that absorbs, blocks, hinders, or otherwise suppresses the overflow of the underfill material from reaching the interconnect structure (148).

[0028] In FIG. 3d, the underfill material (164) is deposited beneath the electrical component (150). The distribution of the underfill material (164) can be difficult to control. Excess underfill material (164) flows outward from the perimeter of the electrical component (150). Since defects may occur, the underfill material (164) must not reach the interconnect structure (148). When the underfill material (164) reaches the T-bar structure (160a), the T-bar structure acts as an overflow structure that absorbs, blocks, hinders, or otherwise suppresses further progression of the underfill material. That is, the excess underfill material (164) flows outward from the T-bar structure (160a) and, if possible, over its upper surface, thereby blocking the flow of the underfill material outward toward the interconnect structure (148) within the stacked semiconductor package (166). FIG. 4e shows a top view of T-bar structures (160a and 160b) placed around the outer circumference of an electrical component (150) to surround all sides of the electrical component. The underfill material (164) is shown being obstructed by the T-bar structure (160a) within the stacked semiconductor package (166).

[0029] If the capacity of the T-bar structure (160a) is insufficient to block the outward flow of the underfill material (164), the T-bar structure (160b) acts as a secondary overflow structure to provide an additional protective layer that absorbs, blocks, hinders, or otherwise suppresses further progression of the underfill material. When the underfill material (164) reaches the T-bar structure (160b), the T-bar structure acts as a secondary overflow structure that absorbs, blocks, hinders, or otherwise suppresses further progression of the underfill material. That is, excess underfill material (164) flows out toward the T-bar structure (160a) and, if possible, over its upper surface, thereby blocking the outward flow of the underfill material toward the interconnect structure (148). FIG. 4f illustrates the underfill material (164) being hindered by the T-bar structure (160b).

[0030] T-bar structures (160a and 160b) control the overflow of excess underfill material (164) flowing out from under the semiconductor die (104b). This embodiment illustrates two T-bar structures (160a and 160b). There may be only one T-bar structure or there may be two or more T-bar structures. In any case, depending on the control of the underfill material (164), one or more T-bar structures are placed around the outer periphery of the die attachment area (134) and the electrical component (150) to prevent or hinder the underfill material from reaching the interconnect structure (148).

[0031] In another embodiment continuing from FIG. 4d, trenches (130b and 130c) are filled with a solid material such as metal, polymer, or epoxy to form T-bar structures (160a and 160b) as shown in FIG. 5. In this case, the height (H1) above the surface (128) of the T-bar structures (160a and 160b) is at least 20.0 μm, which is greater than that shown in FIG. 4d. The T-bar structures (160a and 160b) of FIG. 5 function as overflow structures that absorb, block, hinder, or otherwise suppress further progression of the underfill material within the stacked semiconductor package (168), similar to FIG. 4d-4f. The T-bar structures (160a and 160b) can be formed within the same photomask as the conductive layer (112), that is, before forming the interconnect structure (148).

[0032] In another embodiment continuing from FIG. 3i, the trench (130b) is filled with a solid material such as metal, polymer, or epoxy to form a T-bar structure (170) as shown in FIG. 6. The trench (130c) is kept open. Alternatively, the trench (130c) is filled with a solid material such as metal, polymer, or epoxy to form a T-bar structure (170), and the trench (130b) is kept open. The T-bar structure (170) can be formed within the same photomask as the conductive layer (112), that is, before forming the interconnect structure (148).

[0033] Similar to FIG. 4d, an underfill material (174) is deposited under an electrical component (150). The distribution of the underfill material (174) can be difficult to control. Excess underfill material (174) flows outward from the perimeter of the electrical component (150). Since defects may occur, the underfill material (174) must not reach the interconnect structure (148). When the underfill material (174) reaches the trench (130c), the trench acts as an overflow structure that absorbs, blocks, hinders, or otherwise suppresses further progression of the underfill material. That is, the excess underfill material (174) flows into the trench (130c) and blocks the outward flow of the underfill material toward the interconnect structure (148) within the stacked semiconductor package (176).

[0034] If the capacity of the trench (130c) is insufficient to block the outward flow of the underfill material (174), the T-bar structure (170) acts as an overflow structure to provide an additional protective layer that absorbs, blocks, hinders, or otherwise suppresses further progression of the underfill material. When the underfill material (174) reaches the T-bar structure (170), the T-bar structure acts as an overflow structure that absorbs, blocks, hinders, or otherwise suppresses further progression of the underfill material. That is, excess underfill material (164) flows out toward the T-bar structure (170) and, if possible, over its upper surface, blocking the outward flow of the underfill material toward the interconnect structure (148) within the stacked semiconductor package (176), similar to FIGS. 3k-3l and 4e-4f.

[0035] The trench (130c) and T-bar structure (170) control the overflow of excess underfill material (174) flowing out from under the semiconductor die (104b). This embodiment illustrates one trench (103c) and one T-bar structure (170). Any combination of trenches and T-bar structures may exist. For example, FIG. 7a illustrates T-bar structures (180a), trenches (180b), T-bar structures (180c), and trenches (180d) alternately arranged between the die attachment area (134) and the interconnection structure (148). The T-bar structures (180a and 180c) may be formed similarly to the T-bar structures (160a-160b). T-bar structures (180a and 180c) can be formed within the same photomask as the conductive layer (112), that is, before forming the interconnect structure (148). In any case, depending on the control of the underfill material (174), one or more trenches and one or more T-bar structures are arranged around the outer periphery of the die attachment area (134) and the electrical component (150), and if possible, alternately arranged so as to prevent the underfill material from reaching the interconnect structure (148) within the stacked semiconductor package (180). FIG. 7b illustrates a top view of excess underfill material (174) blocking between the trench (180b) and the T-bar structure (180a) within the stacked semiconductor package (180).

[0036] FIG. 8 illustrates an electronic device (400) having a chip carrier substrate or a PCB (402) having a plurality of semiconductor packages disposed on the surface of the PCB (402), including stacked semiconductor packages (158, 166, 168, 176, and 180). Depending on the application, the electronic device (400) may have one type of semiconductor package or a plurality of types of semiconductor packages.

[0037] The electrical device (400) may be a standalone system using a semiconductor package to perform one or more electrical functions. Alternatively, the electrical device (400) may be a subcomponent of a larger system. For example, the electrical device (400) may be part of a tablet, mobile phone, digital camera, communication system, or other electrical device. Alternatively, the electrical device (400) may be a graphics card, a network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package may include a microprocessor, memory, ASIC, logic circuit, analog circuit, RF circuit, discrete device, or other semiconductor die or electrical component. Miniaturization and lightweighting are essential for the product to be accepted in the market. To achieve high density, the distance between semiconductor devices can be reduced.

[0038] In FIG. 8, the PCB (402) provides a general substrate for structural support and electrical interconnection of semiconductor packages placed on the PCB. Conductive signal traces (404) are formed on the surface of or within a layer of the PCB (402) using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces (404) provide electrical communication between each semiconductor package, mounted components, and other external system components. The traces (404) also provide power and ground connections for each semiconductor package.

[0039] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level packaging includes a process for mechanically and electrically attaching an intermediate substrate to a PCB. In other embodiments, a semiconductor device may have a first level packaging in which the die is directly mechanically and electrically placed on a PCB.

[0040] For the purpose of illustration, various types of first-level packaging, including bond wire packages (406) and flip-chip (408), are illustrated on the PCB (402). Additionally, various types of second-level packaging, including ball grid arrays (BGA) (410), bump chip carriers (BCC) (412), land grid arrays (LGA) (416), multi-chip modules (MCM) or SIP modules (418), quad flat lead-free packages (QFN) (420), quad flat packages (422), embedded wafer-level ball grid arrays (eWLB) (424), and wafer-level chip scale packages (WLCSP) (426), are illustrated on the PCB (402). In one embodiment, the eWLB (424) is a fan-out wafer-level package (Fo-WLP) and the WLCSP (426) is a fan-in wafer-level package (Fi-WLP). Depending on system requirements, any combination of semiconductor packages consisting of any combination of first and second level packaging styles, as well as other electrical components, may be connected on the PCB (402). In some embodiments, the electrical device (400) comprises a single attached semiconductor, but other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, the manufacturer can integrate pre-fabricated components into the electrical device and system. Because the semiconductor package contains sophisticated functions, the electrical device can be manufactured using less expensive components and a simplified manufacturing process. Accordingly, the device is less likely to fail and is cheaper to manufacture, resulting in reduced consumer costs.

[0041] Although one or more embodiments of the present invention have been illustrated in detail, those skilled in the art will understand that modifications and adaptations to these embodiments may be made without departing from the scope of the present invention as described in the following claims.

Claims

Claim 1 A semiconductor device comprising: a substrate including a die attachment region; an interconnection structure formed on the substrate; a trench formed between the die attachment region and the interconnection structure; a semiconductor die disposed on the die attachment region; and an underfill material deposited beneath the semiconductor die, wherein the trench prevents excess underfill material from reaching the interconnection structure. Claim 2 A semiconductor device according to claim 1, further comprising an insulating layer formed on the surface of a substrate, wherein a trench is formed within the insulating layer. Claim 3 A semiconductor device according to claim 1, further comprising a T-bar structure formed between a die attachment area and an interconnection structure. Claim 4 In paragraph 3, the semiconductor device, wherein the T-bar structure extends around the perimeter of the die attachment area. Claim 5 A semiconductor device according to claim 1, further comprising a plurality of T-bar structures and a plurality of trenches alternately arranged around the perimeter of a die attachment area. Claim 6 A semiconductor device comprising: a substrate; an overflow structure formed around a die attachment area of ​​the substrate; a semiconductor die disposed above the die attachment area; and an underfill material deposited below the semiconductor die, wherein the overflow structure obstructs the underfill material. Claim 7 A semiconductor device according to claim 6, further comprising an insulating layer formed on the surface of a substrate. Claim 8 A semiconductor device according to claim 7, wherein the overflow structure comprises a trench formed within an insulating layer around a die attachment region. Claim 9 A semiconductor device according to claim 6, wherein the overflow structure further comprises a T-bar structure formed around a die attachment region. Claim 10 A semiconductor device according to claim 6, further comprising an interconnection structure formed on a substrate, wherein the overflow structure prevents excess underfill material from reaching the interconnection structure. Claim 11 A method for manufacturing a semiconductor device comprising: providing a substrate including a die attachment region; forming an interconnection structure on the substrate; forming an overflow structure between the die attachment region and the interconnection structure; placing a semiconductor die on the die attachment region; and depositing an underfill material under the semiconductor die, wherein the overflow structure prevents excess underfill material from reaching the interconnection structure. Claim 12 A method according to claim 11, further comprising the step of forming an insulating layer on the surface of a substrate. Claim 13 A method according to claim 12, wherein the step of forming an overflow structure includes the step of forming a trench within an insulating layer around a die attachment area. Claim 14 In claim 11, the step of forming an overflow structure further comprises the step of forming a T-bar structure around a die attachment area. Claim 15 The method according to claim 11, wherein the step of forming an overflow structure further comprises the step of forming a plurality of T-bar structures and a plurality of trenches alternately arranged around the perimeter of a die attachment area.

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