Display device and electronic device including the same
Patent Information
- Application Number
- KR1020250023432
- Authority / Receiving Office
- KR · KR
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2026-09-02
Smart Images
Figure PAT00014_ABST
Abstract
Description
Technology Field
[0001] The present invention relates to a display device and an electronic device including the same, and more specifically, to a display device capable of improving display quality and an electronic device including the same. Background Technology
[0002] Among display devices, light-emitting displays display images using light-emitting diodes (LEDs) that generate light through the recombination of electrons and holes. Such light-emitting displays have the advantage of fast response speeds and low power consumption.
[0003] The display device includes a display panel for displaying images, a gate driver for sequentially supplying scan signals to scan lines provided on the display panel, a data driver for supplying data signals to data lines provided on the display panel, and a voltage generator for providing voltages to voltage lines provided on the display panel. The problem to be solved
[0004] The present invention aims to provide a display device capable of improving display quality and an electronic device including the same. means of solving the problem
[0005] A display device according to one feature of the present invention comprises a plurality of pixels, each comprising a light-emitting element and a pixel circuit connected to the light-emitting element; a plurality of data lines connected to the plurality of pixels; a plurality of voltage lines connected to the plurality of pixels; a data driver connected to the plurality of data lines; and a voltage generator providing a plurality of voltages to the plurality of voltage lines. The plurality of pixels each include a first pixel and a second pixel, each comprising a first subpixel, a second subpixel, and a third subpixel arranged sequentially in a first direction. The plurality of data lines include a first data line connected to the first subpixel, a second data line connected to the second subpixel, and a third data line connected to the third subpixel. The first data line, the second data line, and the third data line are positioned between the first subpixel and the third subpixel. The plurality of voltage lines are spaced apart from the first data line, the second data line, and the third data line with the first subpixel or the third subpixel in between.
[0006] The first data line is positioned between the first subpixel and the second subpixel, and the second data line and the third data line are positioned between the second subpixel and the third subpixel.
[0007] The third subpixel is symmetrical to the second subpixel with respect to the second data line and the third data line.
[0008] The first and second data lines are positioned between the first subpixel and the second subpixel, and the third data line is positioned between the second subpixel and the third subpixel.
[0009] The first subpixel is symmetrical to the second subpixel with respect to the first data line and the second data line.
[0010] The plurality of data lines and the plurality of voltage lines are arranged on the same layer.
[0011] It further includes a plurality of horizontal voltage lines and a light-blocking pattern, wherein the plurality of horizontal voltage lines and the light-blocking pattern are arranged on the same layer, and the plurality of voltage lines are each connected to the plurality of horizontal voltage lines.
[0012] The above display panel further includes an insulating pattern that partially covers a semiconductor pattern and has a gate disposed thereon, and a first insulating layer that covers the semiconductor pattern and the gate.
[0013] The plurality of data lines and the plurality of voltage lines are disposed on the first insulating layer.
[0014] The plurality of voltage lines include a first driving voltage line, a second driving voltage line, a reference voltage line, and an initialization voltage line, wherein the second driving voltage line, the initialization voltage line, and the reference voltage line are spaced apart from the first data line with the first subpixel in between, and the first driving voltage line is spaced apart from the third data line with the third subpixel in between.
[0015] The pixel circuit comprises a plurality of transistors, each including a semiconductor pattern and a gate, and each of the plurality of transistors comprises a first transistor connected between the first driving voltage line and the light-emitting element, a second transistor connected between one of the plurality of data lines and the first transistor, and a third transistor connected to the reference voltage line.
[0016] The semiconductor pattern of the first transistor is connected to a light-blocking pattern that overlaps with the semiconductor pattern of the first transistor.
[0017] The pixel circuit further includes a first capacitor formed by the light-blocking pattern and the gate of the first transistor, and a second capacitor formed by the light-blocking pattern and the capacitor electrode, wherein the capacitor electrode is disposed on the same layer as the semiconductor pattern of the first transistor.
[0018] The pixel circuit further includes a third transistor connected between the initialization voltage line and the light-emitting element, a fifth transistor connected between the first driving voltage line and the first transistor, and a sixth transistor connected between the first transistor and the second driving voltage line.
[0019] The above reference voltage line includes a first reference voltage line connected to the third transistor and a second reference voltage line connected to the second capacitor.
[0020] Each of the first pixel and the second pixel is arranged repeatedly in a first direction, and the first pixel and the second pixel are arranged alternately in a second direction.
[0021] The first driving voltage line and the second driving voltage line are positioned between the first pixel and the second pixel, the first reference voltage line is adjacent to the first pixel, and the second reference voltage line is positioned between the first pixel and the second pixel.
[0022] An electronic device according to one feature of the present invention includes a display device and a processor that controls the operation of the display device. The display device includes a display panel comprising a plurality of pixels, each comprising a light-emitting element and a pixel circuit connected to the light-emitting element, a plurality of data lines connected to the plurality of pixels, and a plurality of voltage lines connected to the plurality of pixels, a data driver connected to the plurality of data lines, and a voltage generator that provides a plurality of voltages to the plurality of voltage lines. The plurality of pixels each include a first pixel and a second pixel, each comprising a first subpixel, a second subpixel, and a third subpixel arranged sequentially in a first direction. The plurality of data lines include a first data line connected to the first subpixel, a second data line connected to the second subpixel, and a third data line connected to the third subpixel. The first data line, the second data line, and the third data line are disposed between the first subpixel and the third subpixel, and the plurality of voltage lines are spaced apart from the first data line, the second data line, and the third data line with the first subpixel or the third subpixel in between.
[0023] The first data line is positioned between the first subpixel and the second subpixel, the second data line and the third data line are positioned between the second subpixel and the third subpixel, and the third subpixel is symmetrical with respect to the second subpixel and the second data line and the third data line.
[0024] The plurality of data lines and the plurality of voltage lines are arranged on the same layer. Effects of the invention
[0025] According to the present invention, each pixel may include subpixels. The subpixels may be connected to voltage lines and data lines extending in a first direction. Here, the data lines may be placed between the subpixels, and the voltage lines may be placed outside the subpixels so that the data lines and voltage lines are not adjacent to each other. Accordingly, the interaction between the data lines and voltage lines is reduced, thereby providing a display device with improved display quality. Brief explanation of the drawing
[0026] FIG. 1 is a perspective view of a display device according to one embodiment of the present invention. FIG. 2a is an exploded perspective view of a display device according to one embodiment of the present invention. FIG. 2b is a cross-sectional view of a display device according to one embodiment of the present invention. FIG. 3 is a block diagram of a display device according to one embodiment of the present invention. FIG. 4a is an equivalent circuit diagram of a pixel according to one embodiment of the present invention. FIG. 4b is a waveform diagram of driving signals for driving the pixel shown in FIG. 4a. FIG. 5 is a cross-sectional view of a display panel according to one embodiment of the present invention. FIG. 6a is a plan view of a plurality of conductive patterns according to one embodiment of the present invention. FIG. 6b is a plan view of semiconductor patterns and gates according to one embodiment of the present invention. FIG. 6c is a plan view of voltage lines and data lines according to one embodiment of the present invention. FIG. 7 is a plan view of subpixels according to one embodiment of the present invention. FIG. 8 is a plan view of a plurality of pixels according to one embodiment of the present invention. FIG. 9 is a block diagram of an electronic device according to one embodiment. FIG. 10 is a schematic diagram of an electronic device according to various embodiments. Specific details for implementing the invention
[0027] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them.
[0028] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. "And / or" includes all one or more combinations that the associated components may define.
[0029] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.
[0030] Additionally, terms such as "below," "lower side," "on," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.
[0031] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.
[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.
[0033] Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0034] FIG. 1 is a perspective view of a display device according to an embodiment of the present invention. FIG. 2a is an exploded perspective view of a display device according to an embodiment of the present invention. FIG. 2b is a cross-sectional view of a display device according to an embodiment of the present invention.
[0035] Referring to FIG. 1 and FIG. 2a, a display device (DD) according to one embodiment of the present invention may have a rectangular shape having short sides parallel to a first direction (DR1) and long sides parallel to a second direction (DR2) intersecting the first direction (DR1). However, it is not limited thereto, and the display device (DD) may have various shapes such as a circle and a polygon.
[0036] The display device (DD) may be a device that is activated according to an electrical signal. The display device (DD) may include various embodiments. For example, the display device (DD) may be applied to electronic devices such as smartwatches, tablets, laptops, computers, and smart televisions.
[0037] Hereinafter, the normal direction substantially perpendicular to the plane defined by the first direction (DR1) and the second direction (DR2) is defined as the third direction (DR3). In this specification, the meaning of "when viewed in a plane" may mean the state viewed from the third direction (DR3).
[0038] The upper surface of the display device (DD) can be defined as a display surface (IS) and may be parallel to a plane defined by a first direction (DR1) and a second direction (DR2). Images (IM) generated by the display device (DD) can be provided to a user through the display surface (IS).
[0039] The display surface (IS) can be divided into a transparent area (TA) and a bezel area (BZA). The transparent area (TA) may be an area where images (IM) are displayed. The user perceives the images (IM) through the transparent area (TA). In this embodiment, the transparent area (TA) is depicted as a square shape with rounded vertices. However, this is illustrated as an example, and the transparent area (TA) may have various shapes and is not limited to any single embodiment.
[0040] The bezel region (BZA) is adjacent to the transparent region (TA). The bezel region (BZA) may have a specific color. The bezel region (BZA) may surround the transparent region (TA). Accordingly, the shape of the transparent region (TA) may be substantially defined by the bezel region (BZA). However, this is illustrated as an example, and the bezel region (BZA) may be adjacent to only one side of the transparent region (TA) or may be omitted.
[0041] The display device (DD) can detect external inputs applied from the outside. The external input may include various forms of inputs provided from outside the display device (DD). For example, the external input may include contact by a part of the body, such as the user's hand (US_F), or contact by a separate device (e.g., an active pen or digitizer), as well as external inputs applied in close proximity to the display device (DD) or at a predetermined distance (e.g., hovering). Additionally, the external input may have various forms such as force, pressure, temperature, light, etc.
[0042] The display device (DD) may include a window (WM), a display module (DM), and a housing (EDC). In this embodiment, the window (WM) and the housing (EDC) are combined to form the exterior of the display device (DD).
[0043] The front surface of the window (WM) defines the display surface (IS) of the display device (DD). The window (WM) may include an optically transparent insulating material. For example, the window (WM) may include glass or plastic. The window (WM) may have a multilayer structure or a single layer structure. For example, the window (WM) may include a plurality of plastic films bonded by an adhesive, or a glass substrate and a plastic film bonded by an adhesive.
[0044] The display module (DM) may include a display panel (DP) and an input sensing layer (ISL). The display panel (DP) displays an image according to an electrical signal, and the input sensing layer (ISL) can detect an external input applied from the outside. The external input may be provided in various forms.
[0045] A display panel (DP) according to one embodiment of the present invention may be a light-emitting display panel and is not particularly limited. For example, the display panel (DP) may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of an inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel.
[0046] Referring to FIG. 2b, the display panel (DP) includes a base layer (BL), a circuit layer (DP_CL), a device layer (DP_ED), and an encapsulation layer (TFE). The display panel (DP) according to the present invention may be a flexible display panel. However, the present invention is not limited thereto. For example, the display panel (DP) may be a foldable display panel or a rigid display panel that folds along a folding axis.
[0047] The base layer (BL) may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, and the material is not particularly limited. Additionally, the base layer (BL) may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc.
[0048] A circuit layer (DP_CL) is disposed on a base layer (BL). The circuit layer (DP_CL) is disposed between the base layer (BL) and the device layer (DP_ED). The circuit layer (DP_CL) includes at least one insulating layer and a circuit element. Hereinafter, the insulating layer included in the circuit layer (DP_CL) is referred to as an intermediate insulating layer. The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit element may include a pixel driving circuit included in each of a plurality of pixels for displaying an image and a sensor driving circuit included in each of a plurality of sensors for recognizing external information. The external information may be biometric information. As an example of the present invention, the sensor may be a fingerprint recognition sensor, a proximity sensor, an iris recognition sensor, a blood pressure measurement sensor, or an illuminance sensor. Additionally, the sensor may be an optical sensor that recognizes biometric information in an optical manner. The circuit layer (DP_CL) may further include signal lines connected to the pixel driving circuit and / or the sensor driving circuit.
[0049] The device layer (DP_ED) may include a light-emitting element included in each pixel and a light-receiving element included in each sensor. In one example of the present invention, the light-receiving element may be a photodiode. The light-receiving element may be a sensor that detects light reflected by a user's fingerprint or responds to light.
[0050] The encapsulation layer (TFE) seals the device layer (DP_ED). The encapsulation layer (TFE) may include at least one organic film and at least one inorganic film. The inorganic film may include an inorganic material and can protect the device layer (DP_ED) from moisture / oxygen. The inorganic film may include, but is not particularly limited to, a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer may include an organic material and can protect the device layer (DP_ED) from foreign substances such as dust particles.
[0051] An input sensing layer (ISL) may be formed on a display panel (DP). The input sensing layer (ISL) may be placed directly on an encapsulation layer (TFE). According to one embodiment of the present invention, the input sensing layer (ISL) may be formed on the display panel (DP) by a continuous process. That is, when the input sensing layer (ISL) is placed directly on the display panel (DP), an adhesive film is not placed between the input sensing layer (ISL) and the encapsulation layer (TFE). Alternatively, an adhesive film may be placed between the input sensing layer (ISL) and the display panel (DP). In this case, the input sensing layer (ISL) is not manufactured by a continuous process with the display panel (DP), but is manufactured through a separate process from the display panel (DP) and then fixed to the upper surface of the display panel (DP) by an adhesive film.
[0052] The input sensing layer (ISL) can detect an external input (e.g., a user's touch), convert it into a predetermined input signal, and provide the input signal to the display panel (DP). The input sensing layer (ISL) may include a plurality of sensing electrodes for detecting external input. The sensing electrodes can detect external input in a capacitive manner. The display panel (DP) receives the input signal from the input sensing layer (ISL) and can generate an image corresponding to the input signal.
[0053] The display module (DM) may further include an anti-reflective layer (RPL). The anti-reflective layer (RPL) can reduce the reflectivity of external light incident from above the display device (DD) toward the display panel (DP). External light may not be visible to the user due to the anti-reflective layer (RPL). In one example of the present invention, the anti-reflective layer (RPL) may be placed on an input sensing layer (ISL). However, the present invention is not limited thereto. The anti-reflective layer (RPL) may also be placed between the display panel (DP) and the input sensing layer (ISL). The anti-reflective layer (RPL) may include a plurality of color filters placed corresponding to each pixel. The color filters may filter external light to the same color as the pixels. In this case, external light may not be visible to the user. However, the present invention is not limited thereto, and the anti-reflective layer (RPL) may include a phase retarder and / or a polarizer to reduce the reflectivity of external light.
[0054] A display device (DD) according to one embodiment of the present invention may further include an adhesive layer (AL). A window (WM) may be attached to an anti-reflective layer (RPL) by the adhesive layer (AL). The adhesive layer (AL) may include an optically clear adhesive, an optically clear adhesive resin, or a pressure-sensitive adhesive (PSA).
[0055] Referring again to FIG. 2a, the display module (DM) may further include a driving chip (DIC). In one example of the present invention, the driving chip (DIC) may be mounted on the display panel (DP) adjacent to one end of the display panel (DP). However, alternatively, the driving chip (DIC) may be mounted on a flexible circuit film coupled to one side of the display panel (DP).
[0056] The housing (EDC) is combined with the window (WM). The housing (EDC) is combined with the window (WM) to provide a predetermined internal space. The display module (DM) can be accommodated in the internal space. The housing (EDC) may include a material having relatively high rigidity. For example, the housing (EDC) may include glass, plastic, or metal, or may include multiple frames and / or plates composed of a combination thereof. The housing (EDC) can reliably protect the components of the display device (DD) accommodated in the internal space from external impact. Although not illustrated, a battery module or the like that supplies power necessary for the overall operation of the display device (DD) may be placed between the display module (DM) and the housing (EDC).
[0057] FIG. 3 is a block diagram of a display device according to one embodiment of the present invention.
[0058] Referring to FIG. 3, the display device (DD) includes a display panel (DP), a panel driver, and a driving controller (100). In one example of the present invention, the panel driver includes a data driver (200), a first driving driver (300), a second driving driver (400), and a voltage generator (500).
[0059] The driving controller (100) receives a video signal (RGB) and a control signal (CTRL). The driving controller (100) generates video data (I_DATA) by converting the data format of the video signal (RGB) to match the interface specifications with the data driver (200). The driving controller (100) outputs a first control signal (SCS1), a second control signal (SCS2), and a third control signal (DCS).
[0060] The data driver (200) receives a third control signal (DCS) and image data (I_DATA) from the driving controller (100). The data driver (200) converts the image data (I_DATA) into data signals and outputs the data signals to a plurality of data lines (DL1~DLm) described below. The data signals are analog voltages corresponding to the grayscale values of the image data (I_DATA). As an example of the present invention, the data driver (200) may be embedded in the driving chip (DIC) shown in FIG. 2a.
[0061] The first drive driver (300) receives a first control signal (SCS1) from the drive controller (100), and the second drive driver (400) receives a second control signal (SCS2) from the drive controller (100). The first drive driver (300) and the second drive driver (400) can output scan signals to scan lines in response to the first control signal (SCS1) and the second control signal (SCS2), respectively.
[0062] The voltage generator (500) generates voltages required for the operation of the display panel (DP). In this embodiment, the voltage generator (500) generates a first driving voltage (ELVDD), a second driving voltage (ELVSS), an initialization voltage (Vint), a first reference voltage (Vref1), and a second reference voltage (Vref2).
[0063] The display panel (DP) may include a display area (DA) corresponding to a transparent area (TA) (shown in FIG. 1) and a non-display area (NDA) corresponding to a bezel area (BZA) (shown in FIG. 1).
[0064] The display panel (DP) may include a plurality of pixels (PX) disposed in a display area (DA). The display panel (DP) further includes initialization scan lines (GIL1~GILn), reset scan lines (GRL1~GRLn), write scan lines (GWL1~GWLn), first light emission control lines (EML1~EMLn), second light emission control lines (EMBL1~EMBLn), and data lines (DL1~DLm). The initialization scan lines (GIL1~GILn), reset scan lines (GRL1~GRLn), write scan lines (GWL1~GWLn), first light emission control lines (EML1~EMLn), and second light emission control lines (EMBL1~EMBLn) extend in a first direction (DR1) and are spaced apart from each other in a second direction (DR2). Data lines (DL1~DLm) extend in the second direction (DR2) and are spaced apart from each other in the first direction (DR1). Here, n and m are natural numbers greater than or equal to 1.
[0065] Multiple pixels (PX) are each electrically connected to initialization scan lines (GIL1~GILn), reset scan lines (GR1~GRLn), write scan lines (GWL1~GWLn), first light emission control lines (EML1~EMLn), second light emission control lines (EMBL1~EMBLn), and data lines (DL1~DLm). For example, each of the multiple pixels (PX) may be electrically connected to three scan lines. However, the number of scan lines connected to each pixel (PX) is not limited to this and may be changed. FIG. 3 illustrates a pixel (PX) that is connected to the i-th initial scan line (GILi, hereinafter referred to as the initial scan line) among the initial scan lines (GIL1~GILn), connected to the i-th reset scan line (GRLi, hereinafter referred to as the reset scan line) among the reset scan lines (GR1~GRLn), connected to the i-th write scan line (GWLi, hereinafter referred to as the write scan line) among the write scan lines (GWL1~GWLn), connected to the i-th first light emission control line (EMLi, hereinafter referred to as the first light emission control line) among the first light emission control lines (EML1~EMLn), connected to the i-th second light emission control line (EMBLi, hereinafter referred to as the second light emission control line) among the second light emission control lines (EMBL1~EMBLn), and connected to the j-th data line (DLj, hereinafter referred to as the data line) among the data lines (DL1~DLm).
[0066] The first driving driver (300) and the second driving driver (400) may be placed in the non-display area (NDA) of the display panel (DP). The first driving driver (300) receives a first control signal (SCS1) from the driving controller (100). In response to the first control signal (SCS1), the first driving driver (300) may output initialization scan signals to the initialization scan lines (GIL1~GILn), output reset scan signals to the reset scan lines (GRL1~GRLn), and output write scan signals to the write scan lines (GWL1~GWLn). The second driving driver (400) may output first light emission control signals to the first light emission control lines (EML1~EMLn) and output second light emission control signals to the second light emission control lines (EMLB1~EMLBn) in response to the second control signal (SCS2).
[0067] FIG. 4a is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. FIG. 4b is a waveform diagram of driving signals for driving the pixel shown in FIG. 4a.
[0068] FIG. 4a illustrates an exemplary equivalent circuit diagram of one pixel (PXij) among the plurality of pixels (PX) shown in FIG. 3. Since each of the plurality of pixels (PX) has the same circuit structure, a detailed description of the remaining pixels is omitted in the description of the circuit structure for the pixel (PXij).
[0069] In this embodiment, the pixel circuit may include first to fifth transistors (T1 to T6), a first capacitor (C1) to a third capacitor (C3), and a light-emitting element (OLED). In this embodiment, the first to fourth transistors (T1 to T4) are described as N-type, and the fifth and sixth transistors (T5, T6) are described as P-type. In one embodiment of the present invention, the third capacitor (C3) may be omitted.
[0070] In this embodiment, the first transistor (T1) is shown to include two gates, and each of the second to sixth transistors (T2 to T6) is shown to include one gate, but is not limited thereto. At least one of the second to sixth transistors (T2 to T6) may include two gates.
[0071] In this embodiment, the first transistor (T1) may be a driving transistor, and the second transistor (T2) may be a switching transistor. The node connected to the gate (G1-1, hereinafter the first gate) of the first transistor (T1) is defined as the first node (ND1), and the node connected to the source (S1) of the first transistor (T1) may be defined as the second node (ND2).
[0072] A first transistor (T1) is electrically connected between a first voltage line (VL1) (which may be referred to as the first driving voltage line) receiving a first driving voltage (ELVDD) and a second node (ND2). The first transistor (T1) may include a source (S1, hereinafter referred to as the first source), a drain (D1, hereinafter referred to as the first drain), a channel region (or semiconductor region), and a first upper gate (G1-1) connected to the second node (ND2). The first transistor (T1) may further include a gate (G1-2, hereinafter referred to as the lower gate) connected to the second node (ND2). The first transistor (T1) controls the driving current of the light-emitting element (OLED) based on the charge capacity of the first capacitor (C1).
[0073] The second transistor (T2) is electrically connected between the data line (DLj) and the first node (ND1). The second transistor (T2) may include a source (S2, hereinafter referred to as the second source) connected to the first node (ND1), a drain (D2, hereinafter referred to as the second drain) connected to the data line (DLj), a channel region, and a gate (G2) connected to the write scan line (GWLi). The second transistor (T2) outputs a data voltage. The first capacitor (C1) receives the data voltage.
[0074] A third transistor (T3) is electrically connected between a first node (ND1) and a fourth voltage line (VL4) (which may be referred to as the first reference voltage line) that receives a first reference voltage (Vref1). The third transistor (T3) may include a drain (D3, hereinafter referred to as the third drain) connected to the first node (ND1), a source (S3, hereinafter referred to as the third source) connected to the fourth voltage line (VL4), a channel region, and a third gate (G3) connected to a reset scan line (GRLi).
[0075] The fourth transistor (T4) is electrically connected between a third voltage line (VL3) (which may be referred to as the initialization voltage line) that receives an initialization voltage (Vint) and a light-emitting element (OLED). The fourth transistor (T4) may include a drain (D4, hereinafter referred to as the fourth drain) connected to the first electrode of the light-emitting element (OLED), a source (S4, hereinafter referred to as the fourth source) connected to the third voltage line (VL3), a channel region, and a fourth gate (G4) connected to the initialization scan line (GILi).
[0076] The fifth transistor (T5) is electrically connected between the first voltage line (VL1) and the first drain (D1). In this embodiment, the fifth transistor (T5) may include a source (S5, hereinafter referred to as the fifth source) connected to the first voltage line (VL1), a drain (D5, hereinafter referred to as the fifth drain) connected to the first drain (D1), a channel region, and a fifth gate (G5) connected to the first light emission control line (EMLi).
[0077] The sixth transistor (T6) is electrically connected between the second node (ND2) and the first electrode of the light-emitting element (OLED). In this embodiment, the sixth transistor (T6) may include a source (S6, hereinafter referred to as the sixth source) connected to the second node (ND2), a drain (D6, hereinafter referred to as the sixth drain) connected to the first electrode of the light-emitting element (OLED), a channel region, and a sixth gate (G6) connected to the second light-emitting control line (EMBLi).
[0078] A light-emitting element (OLED) is electrically connected between a sixth drain (D6) and a second voltage line (VL2) (which may be referred to as a second driving voltage line) that receives a second power supply voltage. The light-emitting element (OLED) includes a first electrode connected to the sixth drain (D6) and a second electrode connected to the second voltage line (VL2).
[0079] The first capacitor (C1) is electrically connected between the first node (ND1) and the second node (ND2). The first capacitor (C1) includes a first electrode (E1-1) connected to the first node (ND1) and a second electrode (E1-2) connected to the second node (ND2).
[0080] The second capacitor (C2) is electrically connected between a fifth voltage line (VL5) (which may be referred to as the second reference voltage line) receiving a second reference voltage (Vref2) and a second node (ND2). The second capacitor (C2) includes a first electrode (E2-1) connected to the fifth voltage line (VL5) and a second electrode (E2-2) connected to the second node (ND2).
[0081] The third capacitor (C3) is electrically connected between the first electrode and the second electrode of the light-emitting element (OLED). The third capacitor (C3) includes a first electrode (E3-1) connected to the first electrode of the light-emitting element (OLED) and a second electrode (E3-2) connected to the second electrode of the light-emitting element (OLED).
[0082] The operation of the pixel (PXij) is described in more detail with reference to FIGS. 4a and 4b. A display device (DD, see FIG. 3) displays an image for each frame interval. Each of the initialization scan lines, reset scan lines, write scan lines, first light emission control lines, and second light emission control lines is scanned sequentially during the frame interval. FIG. 4b illustrates a portion of the frame interval and shows the timing diagram of the first light emission control signal (EMi) output from the first light emission control line (EMLi), the second light emission control signal (EMBi) output from the second light emission control line (EMBLi), the reset scan signal (GRi) output from the reset scan line (GRLi), the write scan signal (GWi) output from the write scan line (GWLi), and the initialization scan signal (GIi) output from the initialization scan line (GILi).
[0083] Referring to FIG. 4b, each of the signals (EMi, EMBi, GRi, GWi, GIi) may have a high level (V-HIGH) for a portion of the time and a low level (V-LOW) for a portion of the time. The N-type first to fourth transistors (T1 to T4) described above are turned on when the corresponding control signal has a high level (V-HIGH), and the P-type fifth and sixth transistors (T5, T6) are turned on when the corresponding control signal has a low level (V-LOW).
[0084] During the initialization period (IP), the reset scan signal (GRi) and the initialization scan signal (GIi) have a high level (V-HIGH), so the third transistor (T3) and the fourth transistor (T4) are turned on, and the second light emission control signal (EMBi) has a low level (V-LOW), so the sixth transistor (T6) is turned on. When the third transistor (T3) is turned on, the first node (ND1) is initialized to the first reference voltage (Vref1), and when the fourth transistor (T4) is turned on, the first electrode of the light-emitting element (OLED) can be initialized to the initialization voltage (Vint). When the sixth transistor (T6) is turned on, the second node (ND2) can be initialized to the initialization voltage (Vint). The first capacitor (C1) can be initialized to the difference between the first reference voltage (Vref1) and the initialization voltage (Vint). The second capacitor (C2) can be initialized with the difference between the second reference voltage (Vref2) and the initialization voltage (Vint). The third capacitor (C3) can be initialized with the difference between the second driving voltage (ELVSS) and the initialization voltage (Vint). In one example of the present invention, the second reference voltage (Vref2) may be the first driving voltage (ELVDD).
[0085] During the compensation period (CPP), the third transistor (T3) is turned on because the reset scan signal (GRi) has a high level (V-HIGH), and the fifth transistor (T5) is turned on because the first light emission control signal (EMi) has a low level (V-LOW). The first capacitor (C1) is compensated with a voltage corresponding to the threshold voltage of the first transistor (T1).
[0086] During the write interval (WP), the write scan signal (GWi) has a high level (V-HIGH), so the second transistor (T2) is turned on. The second transistor (T2) outputs a voltage (or data voltage) corresponding to the data signal (DS). As a result, the first capacitor (C1) is charged with a voltage level corresponding to the data signal (DS). The first capacitor (C1) is charged with the data signal (DS) compensated for the threshold voltage of the first transistor (T1). Although the threshold voltages of the driving transistors may differ for each of the multiple pixels (PX, see FIG. 3), the pixel (PXij) shown in FIG. 4a can supply a current of a magnitude proportional to the data signal (DS) to the light-emitting element (OLED) regardless of the deviation in the threshold voltages of the driving transistors.
[0087] During the EL initialization period (EIP), the fourth transistor (T4) is turned on because the initialization scan signal (GIi) has a high level (V-HIGH), and the sixth transistor (T6) is turned on because the second light emission control signal (EMBi) has a low level (V-LOW). The first electrode and the second node (ND2) of the light-emitting element (OLED) can be initialized to an initialization voltage (Vint).
[0088] Subsequently, during the light emission period, the first light emission control signal (EMi) and the second light emission control signal (EMBi) have a low level (V-LOW), so the fifth transistor (T5) and the sixth transistor (T6) are turned on. The first transistor (T1) provides a current to the light-emitting element (OLED) corresponding to the charge capacity stored in the first capacitor (C1). The light-emitting element (OLED) can emit light with a brightness corresponding to the data signal (DS).
[0089] FIG. 5 is a cross-sectional view of a display panel according to one embodiment of the present invention.
[0090] Referring to FIG. 5, the display panel (DP) may include a base layer (BL), a circuit layer (DP_CL), and a device layer (DP_ED).
[0091] The base layer (BL) may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide-based resin layer, and the material thereof is not particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylate resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, the base layer may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc.
[0092] A buffer layer (BFL) comprising at least one inorganic layer is disposed on the upper surface of a base layer (BS). The buffer layer (BFL) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in multiple layers. The buffer layer (BFL) can prevent foreign substances from entering from the outside. The buffer layer (BFL) improves the bonding strength between the base layer (BS) and a semiconductor pattern and / or a conductive pattern disposed on the upper side.
[0093] A plurality of conductive patterns may be disposed on the upper surface of the base layer (BL). In FIG. 5, a light-blocking pattern (BML) among the plurality of conductive patterns is illustrated as an example. In an example of the present invention, the light-blocking pattern (BML) may correspond to a lower gate (G1-2) and a second electrode (E2-2) of a second capacitor (C2). The light-blocking pattern (BML) may define a capacitor electrode (CE) disposed on the upper side and a second capacitor (C2, see FIG. 4a).
[0094] Semiconductor patterns (SP1, SP2), capacitor electrodes (CE), and connection signal lines (CSL) may be disposed on the buffer layer (BFL). The semiconductor patterns (SP1, SP2) may include polysilicon. However, they are not limited thereto, and the semiconductor patterns (SP1, SP2) may include amorphous silicon.
[0095] In FIG. 5, only the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2) are illustrated, but additional semiconductor patterns (SP1, SP2) may be placed in other areas of the pixel (PXij, see FIG. 4a). The electrical properties of the semiconductor patterns (SP1, SP2) differ depending on whether they are doped. The semiconductor patterns (SP1, SP2) may include a doped region and a non-doped region. The doped region may be doped with an N-type dopant or a P-type dopant. A P-type transistor includes a doped region doped with a P-type dopant, and an N-type transistor includes a doped region doped with an N-type dopant.
[0096] The doped region has greater conductivity than the undoped region and effectively functions as an electrode or signal line. The undoped region effectively corresponds to the active (or channel) of the transistor. In other words, a portion of the semiconductor pattern may be the active of the transistor, another portion may be the source or drain, and yet another portion may be the connecting signal line (or connecting electrode).
[0097] The first source (S1), first drain (D1), and channel region described with reference to FIG. 4a can be formed from the first semiconductor pattern (SP1). The first source (S1), first drain (D1), and channel region shown in FIG. 4a may correspond to the first source (S1), first drain (D1), and first channel region (A1) of FIG. 5. The first source (S1) and the first drain (D1) may extend in opposite directions from the first channel region (A1). In this embodiment, the first drain (D1) may be defined as the first input region, and the first source (S1) may be defined as the first output region. Although an N-type first transistor (T1) has been described as an example, if the nature of the first transistor (T1) is P-type, it may be defined in the opposite way.
[0098] The second source (S2), second drain (D2), and channel region described with reference to FIG. 4a can be formed from the second semiconductor pattern (SP2). The second source (S2), second drain (D2), and channel region shown in FIG. 4a may correspond to the second source (S2), second drain (D2), and second channel region (A2) of FIG. 5. The second source (S2) and the second drain (D2) may extend in opposite directions from the second channel region (A2). In this embodiment, the second drain (D2) may be defined as the second input region, and the second source (S2) may be defined as the first output region. Although an N-type second transistor (T2) has been described as an example, if the nature of the second transistor (T2) is P-type, it may be defined in the opposite way.
[0099] The capacitor electrode (CE) may be positioned to partially overlap with the lower light-blocking pattern (BML). In one example of the present invention, the capacitor electrode (CE) may correspond to the first electrode (E2-1) of the second capacitor (C2, see FIG. 4a). The capacitor electrode (CE) may define the second capacitor (C2, see FIG. 4a) together with the lower light-blocking pattern (BML).
[0100] Insulating patterns (IP1, IP2) can be disposed on semiconductor patterns (SP1, SP2). Insulating patterns (IP1, IP2) silicon dioxide (SiO2) ), silicon nitride (Si N₄), aluminum oxide (Al O₃), titanium dioxide (TiO₂) It may include ). Insulating patterns (IP1, IP2) may partially cover the upper surface of semiconductor patterns (SP1, SP2). For example, the first insulating pattern (IP1) may be arranged to cover the first channel region (A1) of the first semiconductor pattern (SP1), and the second insulating pattern (IP2) may be arranged to cover the second channel region (A2) of the second semiconductor pattern (SP2).
[0101] A first gate (G1-1) and a second gate (G2) may be disposed on an insulating pattern (IP1, IP2). The first gate (G1-1) corresponds to the first gate (G1-1) of the first transistor (T1) described with reference to FIG. 4a, and the second gate (G2) corresponds to the second gate (G2) of the second transistor (T2) described with reference to FIG. 4a. The first gate (G1-1) and the second gate (G2) may include polycrystalline silicon (Polysilicon), titanium nitride (TiN), tungsten (W), molybdenum (Mo), and aluminum (Al). Each of the first gate (G1-1) and the second gate (G2) may overlap the first channel region (A1) and the second channel region (A2).
[0102] A first insulating layer (IL1) may be placed to overlap a plurality of pixels (PX, see FIG. 3) in common and to cover semiconductor patterns (SP1, SP2) and gates (G1-1, G2). The first insulating layer (IL1) may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The first insulating layer (IL1) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer (IL1) may be a single-layer silicon oxide layer.
[0103] Connecting electrodes (CNE1, CNE2, CNE3) may be disposed on the first insulating layer (IL1). The first connecting electrode (CNE1) may be connected to a connecting signal line (CSL) through a first contact hole (CNT1) penetrating the first insulating layer (IL1) and connected to an anode electrode (AE) through a second contact hole (CNT2) penetrating the second insulating layer (IL2). The second connecting electrode (CNE2) may be connected to a first source (S1) and a light-blocking pattern (BML). The third connecting electrode (CNE3) may be connected to a capacitor electrode (CE) and a fifth voltage line (VL5, see FIG. 4a).
[0104] A second insulating layer (IL2) may be disposed on the first insulating layer (IL1). The second insulating layer (IL2) may cover the connecting electrodes (CNE1, CNE2, CNE3). In this embodiment, the sixth insulating layer (60) may be an organic layer and may have a single-layer structure, but is not particularly limited.
[0105] A third insulating layer (IL3) may be disposed on the second insulating layer (IL2). In this embodiment, the third insulating layer (IL3) may be an organic layer and may have a single-layer structure, but is not particularly limited.
[0106] The device layer (DP_ED) is disposed on the circuit layer (DP_CL). The device layer (DP_ED) may include an anode electrode (AE). The anode electrode (AE) may be connected to a first connecting electrode (CNE1) through a second contact hole (CNT2) that penetrates the third insulating layer (IL3).
[0107] The device layer (D(P_ED)) further includes a pixel definition layer (PDL) disposed on the circuit layer (DP_CL). The pixel definition layer (PDL) may include an opening (OP) defined corresponding to a light-emitting element (OLED, see FIG. 4a). The opening (OP) exposes at least a portion of the anode electrode (AE).
[0108] A light-emitting layer (EL) is disposed corresponding to an opening (OP) defined in a pixel definition layer (PDL). In this embodiment, a patterned light-emitting layer (EL) is illustrated exemplarily, but the present invention is not limited thereto. Alternatively, a common light-emitting layer may be disposed in common across a plurality of pixels (PX, see FIG. 3). In this case, the common light-emitting layer may generate white light or blue light. A cathode electrode (CE) is disposed on the light-emitting layer (EL). The cathode electrode (CE) is disposed in common across a plurality of pixels (PX, see FIG. 3).
[0109] FIG. 6a is a plan view of a plurality of conductive patterns according to an embodiment of the present invention. FIG. 6b is a plan view of semiconductor patterns and gates according to an embodiment of the present invention. FIG. 6c is a plan view of voltage lines and data lines according to an embodiment of the present invention.
[0110] Referring to FIGS. 5 and 6a, a plurality of conductive patterns may be formed simultaneously on a base layer (BL). The plurality of conductive patterns may include a first horizontal voltage line (VL1_h) outputting a first driving voltage (ELVDD), a second horizontal voltage line (VL2_h) outputting a second driving voltage (ELVSS), a third horizontal voltage line (VL3_h) outputting an initialization voltage (Vint), a fourth horizontal voltage line (VL4_h) outputting a first reference voltage (Vref1), a fifth horizontal voltage line (VL5_h) outputting a second reference voltage (Vref2), and a light-blocking pattern (BML). The first to fifth horizontal voltage lines (VL1_h to VL5_h) may extend in a first direction (DR1) and be spaced apart in a second direction (DR2).
[0111] The first to fifth horizontal voltage lines (VL1_h-VL5_h) are directly connected to the pixel (PX, see FIG. 6c) and can provide voltages to the pixel (PX, see FIG. 6c).
[0112] Referring to FIGS. 5, 6a, and 6b, a plurality of semiconductor patterns and a plurality of gates may be disposed on a plurality of conductive patterns described with reference to FIG. 6a. A plurality of semiconductor patterns may be formed simultaneously, and a plurality of gates may be formed simultaneously. In FIG. 5, only two semiconductor patterns (SP1, SP2) and gates (G1-1, G2) defining a first transistor (T1) and a second transistor (T2) are shown, but in FIG. 6b, a plurality of semiconductor patterns and a plurality of gates defining first to sixth transistors (T1-T6) are shown.
[0113] The gates may be part of an initialization scan line (GILi), a reset scan line (GRLi), a first light emission control line (EMLi), and a second light emission control line (EMBLi). The initialization scan line (GILi), the reset scan line (GRLi), the first light emission control line (EMLi), and the second light emission control line (EMBLi) extend in a first direction (DR1) and may be spaced apart in a second direction (DR2).
[0114] The gate (G1-1) of the first transistor (T1) can define the first capacitor (C1) by overlapping with the light-blocking pattern (BML). The capacitor electrode (CE) can define the second capacitor (C2) by overlapping with the light-blocking pattern (BML).
[0115] The third gate (G3) of the third transistor (T3) may be part of the reset scan line (GRLi), and the fourth gate (G4) of the fourth transistor (T4) may be part of the initialization scan line (GILi). The fifth gate (G5) of the fifth transistor (T5) may be part of the first light emission control line (EMLi), and the sixth gate (G6) of the sixth transistor (T6) may be part of the second light emission control line (EMBLi).
[0116] Referring to FIGS. 5 and 6c, the first to third data lines (DL1-DL3) and the first to fourth voltage lines (VL1-VL4) may be placed on a plurality of semiconductor patterns and a plurality of gates as described with reference to FIG. 6b. The first to third data lines (DL1-DL3) and the first to fourth voltage lines (VL1-VL4) may be placed on the same layer. That is, the first to third data lines (DL1-DL3) and the first to fourth voltage lines (VL1-VL4) may be placed on a first insulating layer (IL1).
[0117] A pixel (PX) may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3). Each of the first to third subpixels (SPX1-SPX3) may have a configuration similar to the pixel (PXij) described with reference to FIG. 4a. The first to third subpixels (SPX1-SPX3) may be arranged sequentially along a first direction (DR1). In one example of the present invention, the first subpixel (SPX1) and the second subpixel (SPX2) may be arranged identically to each other, but the third subpixel (SPX3) may be symmetrical to the second subpixel (SPX2) or the third subpixel (SPX3) with respect to the second data line (DL2) and / or the third data line (DL3).
[0118] The first to third data lines (DL1-DL3) extend in a second direction (DR2) and can each be spaced apart in a first direction (DR1). The first to third data lines (DL1-DL3) can be positioned between the first to third subpixels (SPX1-SPX3). The first data line (DL1) can be connected to the first subpixel (SPX1), the second data line (DL2) can be connected to the second subpixel (SPX2), and the third data line (DL3) can be connected to the third subpixel (SPX3). In one example of the present invention, each of the first to third data lines (DL1-DL3) can be connected to the second transistor (T2) of the first to third subpixels (SPX1-SPX3).
[0119] The first to third data lines (DL1-DL3) may be positioned between the first subpixel (SPX1) and the third subpixel (SPX3). In one example of the present invention, the first data line (DL1) may be positioned between the first subpixel (SPX1) and the second subpixel (SPX2), and the second data line (DL2) may be positioned between the second subpixel (SPX2) and the third subpixel (SPX3). Since the third subpixel (SPX3) is symmetrical with respect to the first subpixel (SPX1) or the second subpixel (SPX2) with respect to the second data line (DL2) and / or the third data line (DL3), the third data line (DL3) may be positioned between the second subpixel (SPX2) and the third subpixel (SPX3). Accordingly, the first data line (DL1) is spaced apart from the second data line (DL2) and the second subpixel (SPX2), but the second data line (DL2) may be adjacent to the third data line (DL3).
[0120] The first to fourth voltage lines (VL1-VL4) extend in a second direction (DR2) and can be spaced apart in a first direction (DR1). In one example of the present invention, the second voltage line (VL2), the third voltage line (VL3), and the fourth voltage line (VL4) can be spaced apart from the first data line (DL1) with the first subpixel (SPX1) in between, and the first voltage line (VL1) can be spaced apart from the third data line (DL3) with the third subpixel (SPX3) in between. That is, the first to third data lines (DL3) are placed between the first and third subpixels (SPX1, SPX3), but the first to fourth voltage lines (VL1-VL4) are not placed between the first and third subpixels (SPX1, SPX3) but can be placed outside the first and third subpixels (SPX1, SPX3).
[0121] The first voltage line (VL1) can be connected to the pixel (PX) through the first horizontal voltage line (VL1_h) to provide the first driving voltage (ELVDD) to the pixel (PX). The second voltage line (VL2) can be connected to the pixel (PX) through the second horizontal voltage line (VL2_h) to provide the second driving voltage (ELVSS) to the pixel (PX). The third voltage line (VL3) can be connected to the pixel (PX) through the third horizontal voltage line (VL3_h) to provide the initialization voltage (Vint) to the pixel (PX). The fourth voltage line (VL4) can be connected to the pixel (PX) through the fourth horizontal voltage line (VL4_h) to provide the first reference voltage (Vref1) to the pixel (PX).
[0122] According to the present invention, the first to third data lines (DL1-DL3) are positioned between the first and third subpixels (SPX1, SPX3), but the first to fourth voltage lines (VL1-VL5) may be positioned outside the first and third subpixels (SPX1, SPX3). That is, the first to third data lines (DL1-DL3) may not be immediately adjacent to the first to fourth voltage lines (VL1-VL4). Accordingly, a display device (DD, see FIG. 1) with improved display quality can be provided, in which coupling between the first to third data lines (DL1-DL3) and the first to fourth voltage lines (VL1-VL4) is reduced.
[0123] FIG. 7 is a plan view of subpixels according to one embodiment of the present invention.
[0124] Referring to FIG. 7, a pixel (PXa) may include a first subpixel (SPX1a), a second subpixel (SPX2a), and a third subpixel (SPX3a). Each of the first to third subpixels (SPX1a-SPX3a) may have a configuration similar to the pixel (PXij) described with reference to FIG. 4a. The first to third subpixels (SPX1a-SPX3a) may be arranged sequentially along a first direction (DR1). In one example of the present invention, the second subpixel (SPX2a) and the third subpixel (SPX3a) may be arranged identically to each other, but the first subpixel (SPX1a) may be symmetrical to the second subpixel (SPX2a) or the third subpixel (SPX3a) with respect to the first data line (DL1a) and / or the second data line (DL2a).
[0125] The first to third data lines (DL1a-DL3a) may be positioned between the first subpixel (SPX1a) and the third subpixel (SPX3a). In one example of the present invention, since the first subpixel (SPX1a) is symmetrical with respect to the second subpixel (SPX2a) or the third subpixel (SPX3a) with respect to the first data line (DL1a) and / or the second data line (DL2a), the first data line (DL1a) may be positioned between the first subpixel (SPX1a) and the second subpixel (SPX2a). The second data line (DL2a) may be positioned between the first subpixel (SPX1a) and the second subpixel (SPX2a), and the third data line (DL3a) may be positioned between the second subpixel (SPX2a) and the third subpixel (SPX3a). Accordingly, the second data line (DL2a) is spaced apart from the third data line (DL3a) and the second subpixel (SPX2a), but the first data line (DL1a) can be adjacent to the second data line (DL2a).
[0126] FIG. 8 is a plan view of a plurality of pixels according to one embodiment of the present invention.
[0127] Referring to FIG. 8, the first pixel (PX1) and the second pixel (PX2) are each arranged repeatedly in the second direction (DR2), and the first pixel (PX1) and the second pixel (PX2) may be arranged alternately in the first direction (DR1). The configuration of the first pixel (PX1) and the second pixel (PX2) is the same as the configuration of the pixel (PX) described with reference to FIG. 6c.
[0128] The first pixel (PX1) and the second pixel (PX2) may be connected to the first to fifth voltage lines (VL1-VL5). Each of the first voltage line (VL1) and the second voltage line (VL2) may be alternately arranged between the first pixel (PX1) and the second pixel (PX2).
[0129] One of the first voltage line (VL1) and the second voltage line (VL2) may be positioned between the first pixel (PX1) and the second pixel (PX2), and the other may be adjacent to the second pixel (PX2). In one example of the present invention, the first voltage line (VL1) may be positioned between the first pixel (PX1) and the second pixel (PX2), and the second voltage line (VL2) may be more adjacent to the second pixel (PX2) among the two pixels (PX1, PX2).
[0130] One of the fourth voltage line (VL4) outputting the first reference voltage (Vref1) and the fifth voltage line (VL5) outputting the second reference voltage (Vref2) may be closer to the first pixel (PX1), and the other may be placed between the first pixel (PX1) and the second pixel (PX2). In one example of the present invention, the fourth voltage line (VL4) may be closer to the first pixel (PX1) among two pixels (PX1, PX2), and the fifth voltage line (VL5) may be closer to the second pixel (PX2) among two pixels (PX1, PX2). The fifth voltage line (VL5) may be formed simultaneously with the first to fourth voltage lines (VL1-VL4) described with reference to FIG. 6c and placed on the same layer.
[0131] However, the arrangement relationship of the first to fifth voltage lines (VL1-VL5) in the present invention is not limited thereto, and the present invention includes various configurations in which the first to fifth voltage lines (VL1-VL5) are arranged outside the first and third subpixels (SPX1, SPX3) so as not to be adjacent to the first to third data lines (DL1-DL3, see FIG. 6c).
[0132] The display device according to the embodiment can be applied to various electronic devices. An electronic device according to one embodiment includes the display device described above and may further include a module or device having other additional functions in addition to the display device.
[0133] FIG. 9 is a block diagram of an electronic device according to one embodiment. Referring to FIG. 9, an electronic device (10) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14).
[0134] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. The processor (12) may control the operation of a display device according to embodiments of the present invention.
[0135] The memory (15) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (15), a video data signal and / or an input control signal is transmitted to the display module (11), and the display module (11) can process the received signal and output video information through a display screen.
[0136] The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (10).
[0137] The electronic device (10) described above includes a display device according to the embodiments described above, and at least one of each component of the electronic device (10) may be included within the display device. Additionally, some of the individual modules functionally included within a single module may be included within the display device, while others may be provided separately from the display device. For example, the display device may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device.
[0138] FIG. 10 is a schematic diagram of an electronic device according to various embodiments.
[0139] Referring to FIG. 10, various electronic devices to which a display device according to the embodiments is applied may include not only image display electronic devices such as a smartphone (10_1a), tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), head-mounted display (10_2b), and smart watch (10_2c), and automotive electronic devices (10_3) including display modules such as a CID (Center Information Display) and room mirror display placed on the instrument panel, center fascia, and dashboard of a car.
[0140] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the relevant technical field will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as set forth in the claims below. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols
[0141] DL1: 1st data line VL1: First voltage line SPX1: 1st subpixel VL1_h: 1st horizontal voltage line BML: Light-blocking pattern SP1: First semiconductor pattern G1-1: Gate 1 T1: First transistor T2: Second transistor C1: First capacitor C2: Second capacitor
Claims
Claim 1 A display device comprising: a plurality of pixels, each including a light-emitting element and a pixel circuit connected to the light-emitting element; a plurality of data lines connected to the plurality of pixels; and a plurality of voltage lines connected to the plurality of pixels; a data driver connected to the plurality of data lines; and a voltage generator providing a plurality of voltages to the plurality of voltage lines, wherein the plurality of pixels each include a first pixel and a second pixel including a first subpixel, a second subpixel, and a third subpixel arranged sequentially in a first direction, and the plurality of data lines include a first data line connected to the first subpixel, a second data line connected to the second subpixel, and a third data line connected to the third subpixel, wherein the first data line, the second data line, and the third data line are disposed between the first subpixel and the third subpixel, and the plurality of voltage lines are spaced apart from the first data line, the second data line, and the third data line with the first subpixel or the third subpixel in between. Claim 2 A display device according to claim 1, wherein the first data line is positioned between the first subpixel and the second subpixel, and the second data line and the third data line are positioned between the second subpixel and the third subpixel. Claim 3 In paragraph 2, the third subpixel is a display device that is symmetrical to the second subpixel with respect to the second data line and the third data line. Claim 4 A display device according to claim 1, wherein the first and second data lines are disposed between the first subpixel and the second subpixel, and the third data line is disposed between the second subpixel and the third subpixel. Claim 5 In paragraph 4, the first subpixel is a display device that is symmetrical to the second subpixel with respect to the first data line and the second data line. Claim 6 In claim 1, the plurality of data lines and the plurality of voltage lines are arranged on the same layer in a display device. Claim 7 A display device according to claim 1, wherein the display panel further comprises a plurality of horizontal voltage lines and a light-blocking pattern, wherein the plurality of horizontal voltage lines and the light-blocking pattern are arranged on the same layer, and the plurality of voltage lines are each connected to the plurality of horizontal voltage lines. Claim 8 A display device according to claim 1, wherein the display panel comprises: an insulating pattern that partially covers a semiconductor pattern and has a gate disposed thereon; and a first insulating layer that covers the semiconductor pattern and the gate. Claim 9 In claim 8, the plurality of data lines and the plurality of voltage lines are a display device disposed on the first insulating layer. Claim 10 A display device according to claim 1, wherein the plurality of voltage lines include a first driving voltage line, a second driving voltage line, a reference voltage line, and an initialization voltage line, wherein the second driving voltage line, the initialization voltage line, and the reference voltage line are spaced apart from the first data line with the first subpixel in between, and the first driving voltage line is spaced apart from the third data line with the third subpixel in between. Claim 11 In claim 10, the pixel circuit comprises a plurality of transistors, each comprising a semiconductor pattern and a gate, and each of the plurality of transistors comprises: a first transistor connected between the first driving voltage line and the light-emitting element; a second transistor connected between one of the plurality of data lines and the first transistor; and a third transistor connected to the reference voltage line. Claim 12 In claim 11, the semiconductor pattern of the first transistor is a display device connected to a light-blocking pattern that overlaps with the semiconductor pattern of the first transistor. Claim 13 In claim 12, the pixel circuit further comprises: a first capacitor formed by the light-blocking pattern and the gate of the first transistor; and a second capacitor formed by the light-blocking pattern and a capacitor electrode, wherein the capacitor electrode is disposed on the same layer as the semiconductor pattern of the first transistor. Claim 14 In claim 13, the pixel circuit further comprises: a third transistor connected between the initialization voltage line and the light-emitting element; a fifth transistor connected between the first driving voltage line and the first transistor; and a sixth transistor connected between the first transistor and the second driving voltage line. Claim 15 In paragraph 13, the reference voltage line comprises a first reference voltage line connected to the third transistor; and a second reference voltage line connected to the second capacitor, in a display device. Claim 16 A display device according to claim 15, wherein each of the first pixel and the second pixel is repeatedly arranged in a first direction, and the first pixel and the second pixel are alternately arranged in a second direction. Claim 17 A display device according to claim 16, wherein the first driving voltage line and the second driving voltage line are positioned between the first pixel and the second pixel, the first reference voltage line is adjacent to the first pixel, and the second reference voltage line is positioned between the first pixel and the second pixel. Claim 18 An electronic device comprising: a display device; and a processor for controlling the operation of the display device, wherein the display device comprises a plurality of pixels each comprising a light-emitting element and a pixel circuit connected to the light-emitting element, a plurality of data lines connected to the plurality of pixels, and a plurality of voltage lines connected to the plurality of pixels; a data driver connected to the plurality of data lines; and a voltage generator for providing a plurality of voltages to the plurality of voltage lines, wherein the plurality of pixels each comprises a first pixel and a second pixel including a first subpixel, a second subpixel, and a third subpixel arranged sequentially in a first direction, and the plurality of data lines include a first data line connected to the first subpixel, a second data line connected to the second subpixel, and a third data line connected to the third subpixel, wherein the first data line, the second data line, and the third data line are disposed between the first subpixel and the third subpixel, and the plurality of voltage lines are spaced apart from the first data line, the second data line, and the third data line with the first subpixel or the third subpixel in between. Claim 19 A display device according to claim 18, wherein the first data line is positioned between the first subpixel and the second subpixel, the second data line and the third data line are positioned between the second subpixel and the third subpixel, and the third subpixel is symmetrical to each other with respect to the second subpixel and the second data line and the third data line. Claim 20 In paragraph 18, the plurality of data lines and the plurality of voltage lines are a display device disposed on the same layer.