Electronic apparatus

Abstract

An electronic device according to the present invention comprises a pixel including a base layer, a gate line extending along one direction, a data line insulatingly intersecting the gate line, a pixel driver connected to the gate line and the data line, and a light-emitting element connected to the pixel driver, wherein the light-emitting element comprises an anode, a cathode, and a light-emitting layer, and the pixel driver comprises a first transistor including a first semiconductor pattern and a first gate electrode, a second transistor including a second semiconductor pattern and a second gate electrode connected to the data line and spaced apart from the first semiconductor pattern, a first capacitor connected between the second transistor and the data line, and a second capacitor connected to the first transistor, wherein the first semiconductor pattern is disposed between the first capacitor and the second capacitor.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to an electronic device with improved resolution. Background Technology

[0002] Display devices such as televisions, monitors, smartphones, and tablets that provide images to users include display panels that display images. Various display panels are being developed as display panels, such as liquid crystal display panels, organic light emitting display panels, electro-wetting display panels, and electrophoretic display panels.

[0003] A display panel includes a plurality of pixels for generating an image. It includes a gate driver that applies gate signals to the pixels and a data driver that applies data voltages to the pixels. The pixels receive data voltages in response to the gate signals and generate an image using the data voltages. Each pixel includes a light-emitting element and a plurality of transistors connected to the light-emitting element.

[0004] Light-emitting elements are driven by transistors to generate light. Among the transistors, the driving transistor is connected to the light-emitting element through a connecting electrode. The connecting electrode is connected to the driving transistor through a contact hole defined in the insulating layer. Since the area occupied by the contact hole in each pixel is limited, the development of technology to precisely manufacture the contact hole is required. The problem to be solved

[0005] The present invention has the objective of providing an electronic device with improved resolution by distributing two capacitors for each pixel on the upper and lower parts of the transistor active layer, respectively, thereby securing the capacitor area and controlling the depth of the contact hole. means of solving the problem

[0006] An electronic device according to the present invention comprises a pixel including a base layer, a gate line disposed on the base layer and extending along one direction, a data line insulatingly intersecting the gate line, a pixel driver connected to the gate line and the data line, and a light-emitting element disposed on the pixel driver and connected to the pixel driver, wherein the light-emitting element comprises an anode, a cathode disposed on the anode, and a light-emitting layer disposed between the anode and the cathode, and wherein the pixel driver comprises a first transistor including a first semiconductor pattern and a first gate electrode overlapping the first semiconductor pattern, a second transistor including a second semiconductor pattern connected to the data line and spaced apart from the first semiconductor pattern and a second gate electrode overlapping the second semiconductor pattern, a first capacitor connected between the second transistor and the data line, and a second capacitor connected to the first transistor, wherein the first semiconductor pattern is disposed between the first capacitor and the second capacitor.

[0007] The first capacitor may include a first lower capacitor electrode and a second lower capacitor electrode disposed on the first lower capacitor electrode, and may be characterized in that the area of ​​each of the first and second lower capacitor electrodes on a plane is larger than the area of ​​the anode.

[0008] The first lower capacitor electrode may be characterized by having a shape that is integral with the data line.

[0009] The second lower capacitor electrode may be characterized by having a shape that is integral with the data line.

[0010] The ratio of the area of ​​each of the first and second lower capacitor electrodes to the area of ​​the anode may be 1.4 or more.

[0011] An electronic device according to the present invention may further include a lower conductive pattern disposed between the first capacitor and the first transistor and a buffer layer disposed on the lower conductive pattern, wherein the lower conductive pattern overlaps with the first semiconductor pattern.

[0012] The short-range surface roughness of the buffer layer may be less than 10 nm, and the long-range surface roughness may be less than 200 nm.

[0013] The first transistor may be characterized by including a silicon semiconductor, and the second transistor may be characterized by including an oxide semiconductor.

[0014] The separation distance from the first semiconductor pattern to the anode is 1.5 It can be characterized as follows.

[0015] An electronic device according to the present invention may further include an upper electrode connecting the first capacitor and the second transistor, wherein the upper electrode is disposed on the first capacitor and the second transistor.

[0016] The upper electrode may be characterized by comprising the same material as at least one of the electrodes constituting the second capacitor.

[0017] An electronic device according to the present invention comprises a base layer, a gate line disposed on the base layer and extended along one direction, a data line including a line portion insulatingly intersecting the gate line and a protrusion protruding from the line portion, a pixel driving unit connected to the gate line and the data line, and a pixel including a light-emitting element disposed on the pixel driving unit and connected to the pixel driving unit, wherein the light-emitting element includes an anode, a cathode disposed on the anode, and a light-emitting layer disposed between the anode and the cathode, and the pixel driving unit comprises a first transistor including a first semiconductor pattern and a first gate electrode overlapping with the first semiconductor pattern, a second transistor including a second semiconductor pattern connected to the data line and spaced apart from the first semiconductor pattern and a second gate electrode overlapping with the second semiconductor pattern, and a capacitor electrode disposed below the first semiconductor pattern and overlapping with the protrusion on a plane, wherein the protrusion overlaps with the anode on a plane.

[0018] The area of ​​each of the above protrusion and the above capacitor electrode may be larger than the area of ​​the above anode.

[0019] The capacitor electrode may be characterized by being positioned on the upper part of the protrusion.

[0020] The capacitor electrode may be characterized by being positioned at the lower part of the protrusion.

[0021] The electronic device according to the present invention may further include a lower conductive pattern disposed between the capacitor electrode and the first transistor and a buffer layer disposed on the lower conductive pattern, wherein the lower conductive pattern overlaps with the first semiconductor pattern.

[0022] The first transistor may be characterized by including a silicon semiconductor, and the second transistor may be characterized by including an oxide semiconductor.

[0023] The electronic device according to the present invention may further include an upper electrode connecting the capacitor electrode and the second transistor, and the upper electrode may be characterized by being disposed on the capacitor electrode and the second transistor.

[0024] An electronic device according to the present invention comprises a display module for displaying an image and a processor for providing image data to the display module. The display module comprises a pixel including a base layer, a gate line disposed on the base layer and extending along one direction, a data line insulatingly intersecting the gate line, a pixel driver connected to the gate line and the data line, and a light-emitting element disposed on the pixel driver and connected to the pixel driver. The light-emitting element comprises an anode, a cathode disposed on the anode, and a light-emitting layer disposed between the anode and the cathode. The pixel driver comprises a first transistor including a first semiconductor pattern and a first gate electrode overlapping the first semiconductor pattern, a second transistor including a second semiconductor pattern connected to the data line and spaced apart from the first semiconductor pattern and a second gate electrode overlapping the second semiconductor pattern, a first capacitor connected between the second transistor and the data line, and a second capacitor connected to the first transistor. The first semiconductor pattern is disposed between the first capacitor and the second capacitor.

[0025] The first capacitor may include a first lower capacitor electrode and a second lower capacitor electrode disposed on the first lower capacitor electrode, and may be characterized in that the area of ​​each of the first and second lower capacitor electrodes on a plane is larger than the area of ​​the anode. Effects of the invention

[0026] According to the present invention, by distributing capacitors on the upper and lower parts of the active layer, respectively, the minimum distance between the source and drain of a transistor can be reduced. As a result, the number of transistors disposed in the same area can be increased, thereby providing an electronic device with improved resolution.

[0027] In addition, by placing some of the capacitors below the active layer, it becomes easier to secure the capacitor electrode area, thereby providing an electronic device with improved reliability. Brief explanation of the drawing

[0028] FIG. 1a is a perspective view of an electronic device according to one embodiment of the present invention. FIG. 1b is a block diagram of an electronic device according to one embodiment of the present invention. FIGS. 2a and FIGS. 2b are perspective views of an electronic device according to one embodiment of the present invention. FIG. 3 is a diagram illustrating an exemplary cross-section of the electronic device shown in FIG. 1a. FIG. 4 is a drawing exemplarily illustrating a cross-section of the display panel shown in FIG. 3. FIG. 5 is a plan view of a display panel according to one embodiment of the present invention. Figure 6 is a diagram illustrating the equivalent circuit of any one of the pixels shown in Figure 4. Figure 7 is a timing diagram of signals for operating the pixel shown in Figure 6. Figure 8 is a cross-sectional view of a display panel cut along the I-I' cutting line of Figure 5. Figure 9 is a cross-sectional view of a display panel cut along the I-I' cutting line of Figure 5. FIGS. 10a to 10n are plan views showing a part of a display panel according to one embodiment of the present invention. FIGS. 11a to 11j are cross-sectional views showing some of the steps of a method for manufacturing a display panel according to one embodiment of the present invention. FIGS. 12a to 12c are cross-sectional views showing some of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. Specific details for implementing the invention

[0029] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them.

[0030] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. "And / or" includes all one or more combinations that the associated components may define.

[0031] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0032] Additionally, terms such as "below," "lower side," "on," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0033] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0034] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0035] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0036] FIG. 1a is a perspective view of an electronic device according to one embodiment of the present invention. FIG. 1b is a block diagram of an electronic device according to one embodiment of the present invention.

[0037] Referring to FIG. 1a, the electronic device (ED) may include long sides extending parallel to a first direction (DR1) and short sides extending parallel to a second direction (DR2) intersecting the first direction (DR1). However, this is illustrated as an example, and the electronic device (ED) may include sides of equal length for each of the first direction (DR1) and the second direction (DR2), and is not limited to any one embodiment.

[0038] Hereinafter, the direction that intersects substantially perpendicularly with the plane defined by the first direction (DR1) and the second direction (DR2) is defined as the third direction (DR3). Additionally, in this specification, the meaning of "when viewed on a plane" is defined as the state viewed from the third direction (DR3).

[0039] The front surface of the electronic device (ED) can be defined as a display surface (DS) and may have a plane defined by a first direction (DR1) and a second direction (DR2). Images (IM) generated by the electronic device (ED) can be provided to the user through the display surface (DS).

[0040] The display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) is an area where an image is displayed, and the non-display area (NDA) may be an area where an image is not displayed. The non-display area (NDA) may be adjacent to at least one side of the display area (DA). In the present embodiment, the non-display area (NDA) may have a frame shape that surrounds the display area (DA). However, this is illustrated as an example, and in one embodiment of the present invention, the non-display area (NDA) may be omitted, in which case the display surface (DS) may consist only of the display area (DA).

[0041] The electronic device (ED) may detect inputs applied from outside the electronic device (ED). For example, the electronic device (ED) may detect a first input by touch (TC) and a second input by touch pen (PEN). The first input by touch (TC) may include various forms of external inputs, such as a part of the user's body, light, heat, or pressure. The touch pen (PEN) may be an active pen or an electromagnetic pen, and is not limited to any one embodiment. The touch pen (PEN) may be defined as an input device, and the display area (DA) may provide the user with a sensing area capable of detecting input in addition to displaying an image.

[0042] In one embodiment, the electronic device (ED) may be a large electronic device such as a television, a monitor, or an external billboard. Additionally, the electronic device (ED) may be a small to medium-sized electronic device such as a personal computer, a laptop computer, a personal digital terminal, an automotive navigation unit, a game console, a smartphone, a tablet, and a camera. However, this is exemplary and may be adopted as other display devices without departing from the concept of the present invention. In FIGS. 1a and 1b, the electronic device (ED) is exemplarily illustrated as a tablet device.

[0043] Referring to FIG. 1b, the electronic device (ED) can output various information through a display module (DM) within the operating system. When the processor (110) executes an application stored in memory (120), the display module (DM) can provide application information to the user through a display panel (DP).

[0044] The processor (110) can acquire an external input through the input module (130) or the sensor module (161) and execute an application corresponding to the external input. For example, if a user selects a camera icon displayed on the display panel (DP), the processor (110) can acquire user input through the input sensor (161-2) and activate the camera module (171). The processor (110) can transmit image data corresponding to the captured image acquired through the camera module (171) to the display module (DM). The display module (DM) can display an image corresponding to the captured image through the display panel (DP).

[0045] The operation of the electronic device (ED) has been briefly described above. The configuration of the electronic device (ED) will be described in detail below. Some of the configurations of the electronic device (ED) described below may be integrated and provided as a single configuration, or a single configuration may be separated into two or more configurations.

[0046] Referring to FIG. 1b, the electronic device (ED) can communicate with an external electronic device (ED-A) through a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to one embodiment, the electronic device (ED) may include a processor (110), memory (120), an input module (130), a display module (DM), a power module (150), an embedded module (160), and an external module (170). According to one embodiment, at least one of the above-described components may be omitted, or one or more other components may be added to the electronic device (ED). According to one embodiment, some of the above-described components (e.g., a sensor module (161), an antenna module (162), or an acoustic output module (163)) may be integrated into another component (e.g., a display module (DM)).

[0047] The processor (110) can execute software to control at least one other component (e.g., a hardware or software component) of an electronic device (ED) connected to the processor (110) and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (110) stores commands or data received from other components (e.g., an input module (130), a sensor module (161), or a communication module (173)) in a volatile memory (121), processes the commands or data stored in the volatile memory (121), and the resulting data can be stored in a non-volatile memory (122).

[0048] The processor (110) may include a main processor (111) and an auxiliary processor (112). The main processor (111) may include one or more of a central processing unit (111-1, CPU) or an application processor (AP). The main processor (111) may further include one or more of a graphic processing unit (111-2, GPU), a communication processor (CP), and an image signal processor (ISP). The main processor (111) may further include a neural processing unit (111-3, NPU). The neural processing unit is a processor specialized for processing artificial intelligence models, and the artificial intelligence model may be generated through machine learning. The artificial intelligence model may include a plurality of artificial neural network layers. An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially. At least two of the processing unit and processor described above may be implemented as a single integrated configuration (e.g., a single chip), or each may be implemented as an independent configuration (e.g., multiple chips).

[0049] The auxiliary processor (112) may include a controller (112-1). The controller (112-1) may include an interface conversion circuit and a timing control circuit. The controller (112-1) receives a video signal from the main processor (111), converts the data format of the video signal to match the interface specifications with the display module (DM), and outputs video data. The controller (112-1) may output various control signals required for driving the display module (DM).

[0050] The auxiliary processor (112) may further include a data conversion circuit (112-2), a gamma correction circuit (112-3), a rendering circuit (112-4), etc. The data conversion circuit (112-2) receives image data from the controller (112-1) and can compensate the image data so that the image is displayed at a desired brightness according to the characteristics of the electronic device (ED) or the user's settings, etc., or can convert the image data to reduce power consumption or compensate for afterimages, etc. The gamma correction circuit (112-3) can convert image data or gamma reference voltage, etc. so that the image displayed on the electronic device (ED) has desired gamma characteristics. The rendering circuit (112-4) receives image data from the controller (112-1) and can render the image data by considering the pixel arrangement of the display panel (DP) applied to the electronic device (ED). At least one of the data conversion circuit (112-2), gamma correction circuit (112-3), and rendering circuit (112-4) may be integrated into another component (e.g., main processor (111) or controller (112-1)). At least one of the data conversion circuit (112-2), gamma correction circuit (112-3), and rendering circuit (112-4) may also be integrated into the data driving unit (DDV) described later.

[0051] The memory (120) can store various data used by at least one component of the electronic device (ED) (e.g., a processor (110) or a sensor module (161)) and input or output data for related commands. The memory (120) may include at least one of a volatile memory (121) and a non-volatile memory (122).

[0052] The input module (130) can receive commands or data to be used for components of the electronic device (ED) (e.g., processor (110), sensor module (161) or sound output module (163)) from outside the electronic device (ED) (e.g., user or external electronic device (ED-A)).

[0053] The input module (130) may include a first input module (131) into which commands or data are input from a user, and a second input module (132) into which commands or data are input from an external electronic device (ED-A). The first input module (131) may include a microphone, a mouse, a keyboard, a key (e.g., a button), or a pen (e.g., a passive pen or an active pen). The second input module (132) may support a specified protocol that can be connected to the external electronic device (ED-A) via a wired or wireless connection. According to one embodiment, the second input module (132) may include a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface. The second input module (132) may include a connector that can be physically connected to the external electronic device (ED-A), such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0054] The display module (DM) provides information visually to the user. The display module (DM) may include a display panel (DP), a scan driver (SDC), and a data driver (DDV). The display module (DM) may further include a window, a chassis, and a bracket for protecting the display panel (DP).

[0055] The display panel (DP) may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of the display panel (DP) is not particularly limited. The display panel (DP) may be a rigid type, or a flexible type that is rollable or foldable. The display module (DM) may further include a supporter, a bracket, or a heat dissipation member that supports the display panel (DP).

[0056] The scan driver (SDC) can be mounted on the display panel (DP) as a driver chip. Additionally, the scan driver (SDC) can be integrated into the display panel (DP). For example, the scan driver (SDC) may include an ASG (Amorphous Silicon TFT Gate driver circuit), an LTPS (Low Temperature Polycrystalline Silicon) TFT Gate driver circuit, or an OSG (Oxide Semiconductor TFT Gate driver circuit) embedded in the display panel (DP). The scan driver (SDC) receives a control signal from the controller (112-1) and outputs scan signals to the display panel (DP) in response to the control signal.

[0057] The display panel (DP) may further include a light-emitting driver. The light-emitting driver outputs a light-emitting control signal to the display panel (DP) in response to a control signal received from the controller (112-1). The light-emitting driver may be formed separately from the scan driver (SDC) or may be integrated into the scan driver (SDC).

[0058] The data driver (DDV) receives a control signal from the controller (112-1), converts the image data into an analog voltage (e.g., data voltage) in response to the control signal, and then outputs the data voltages to the display panel (DP).

[0059] The data driver (DDV) may be integrated into other components (e.g., controller (112-1)). The functions of the interface conversion circuit and timing control circuit of the controller (112-1) described above may also be integrated into the data driver (DDV).

[0060] The display module (DM) may further include a light-emitting driver and a voltage generation circuit. The voltage generation circuit can output various voltages required to drive the display panel (DP).

[0061] The power module (150) supplies power to the components of the electronic device (ED). The power module (150) may include a battery that charges the power voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. The power module (150) may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the modules described above and the modules described below. The power module (150) may include a wireless power transceiver electrically connected to the battery. The wireless power transceiver may include a plurality of coil-shaped antenna radiators.

[0062] The electronic device (ED) may further include an internal module (160) and an external module (170). The internal module (160) may include a sensor module (161), an antenna module (162), and an acoustic output module (163). The external module (170) may include a camera module (171), a light module (172), and a communication module (173).

[0063] The sensor module (161) can detect input by the user's body or input by a pen of the first input module (131) and generate an electrical signal or data value corresponding to the input. The sensor module (161) may include at least one of a fingerprint sensor (161-1), an input sensor (161-2), and a digitizer (161-3).

[0064] The fingerprint sensor (161-1) can generate a data value corresponding to the user's fingerprint. The fingerprint sensor (161-1) may include either an optical or capacitive fingerprint sensor.

[0065] The input sensor (161-2) can generate a data value corresponding to coordinate information of input by the user's body or input by a pen. The input sensor (161-2) generates a data value of the amount of change in capacitance due to the input. The input sensor (161-2) can detect input by a passive pen or transmit and receive data with an active pen.

[0066] The input sensor (161-2) may measure biosignals such as blood pressure, water content, or body fat. For example, if a user contacts a part of their body with the sensor layer or sensing panel and does not move for a certain period of time, the input sensor (161-2) may detect biosignals based on changes in the electric field caused by the part of the body and output information desired by the user to the display module (DM).

[0067] The digitizer (161-3) can generate a data value corresponding to the coordinate information of the input by the pen. The digitizer (161-3) generates the amount of electromagnetic change caused by the input as a data value. The digitizer (161-3) can detect input by a passive pen or transmit and receive data with an active pen.

[0068] At least one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be implemented as a sensor layer formed on a display panel (DP) through a continuous process. The fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be positioned on the upper side of the display panel (DP), and any one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3), such as the digitizer (161-3), may be positioned on the lower side of the display panel (DP).

[0069] At least two of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) can be formed to be integrated into a single sensing panel through the same process. When integrated into a single sensing panel, the sensing panel can be positioned between a display panel (DP) and a window positioned above the display panel (DP). According to one embodiment, the sensing panel may be positioned on the window, and the position of the sensing panel is not particularly limited.

[0070] At least one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be embedded in the display panel (DP). That is, at least one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be formed simultaneously through a process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel (DP).

[0071] Additionally, the sensor module (161) may generate an electrical signal or data value corresponding to an internal or external state of the electronic device (ED). The sensor module (161) may further include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0072] The antenna module (162) may include one or more antennas for transmitting a signal or power to the outside or receiving it from the outside. According to one embodiment, the communication module (173) may transmit a signal to an external electronic device or receive it from an external electronic device through an antenna suitable for a communication method. The antenna pattern of the antenna module (162) may be integrated into one component of the display module (DM) (e.g., a display panel (DP)) or an input sensor (161-2), etc.

[0073] The sound output module (163) is a device for outputting a sound signal to the outside of an electronic device (ED), and may include, for example, a speaker used for general purposes such as multimedia playback or recording playback, and a receiver used exclusively for telephone reception. According to one embodiment, the receiver may be formed integrally with or separately from the speaker. The sound output pattern of the sound output module (163) may be integrated with the display module (DM).

[0074] The camera module (171) can capture still images and video. According to one embodiment, the camera module (171) may include one or more lenses, image sensors, or image signal processors. The camera module (171) may further include an infrared camera capable of measuring the presence or absence of a user, the location of the user, the user's gaze, etc.

[0075] The light module (172) can provide light. The light module (172) may include a light-emitting diode or a xenon lamp. The light module (172) may operate in conjunction with the camera module (171) or operate independently.

[0076] The communication module (173) can support the establishment of a wired or wireless communication channel between an electronic device (ED) and an external electronic device (ED-A), and the performance of communication through the established communication channel. The communication module (173) may include one or all of a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a GNSS (global navigation satellite system) communication module, and a wired communication module such as a LAN (local area network) communication module or a power line communication module. The communication module (173) can communicate with the external electronic device (ED-A) through a short-range communication network such as Bluetooth, WiFi Direct, or IrDA (infrared data association), or a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., LAN or WAN). The various types of communication modules (173) described above may be implemented as a single chip or each as a separate chip.

[0077] The input module (130), sensor module (161), camera module (171), etc. can be used to control the operation of the display module (DM) in conjunction with the processor (110).

[0078] The processor (110) outputs commands or data to the display module (DM), sound output module (163), camera module (171), or light module (172) based on input data received from the input module (130). For example, the processor (110) may generate image data in response to input data applied via a mouse or active pen, and output it to the display module (DM), or generate command data in response to input data and output it to the camera module (171) or light module (172). If the processor (110) does not receive input data from the input module (130) for a certain period of time, it may switch the operating mode of the electronic device (ED) to a low-power mode or sleep mode to reduce the power consumed by the electronic device (ED).

[0079] The processor (110) outputs commands or data to the display module (DM), sound output module (163), camera module (171), or light module (172) based on the sensing data received from the sensor module (161). For example, the processor (110) can compare the authentication data authorized by the fingerprint sensor (161-1) with the authentication data stored in the memory (120) and then execute an application based on the comparison result. The processor (110) can execute commands or output corresponding image data to the display module (DM) based on the sensing data detected by the input sensor (161-2) or the digitizer (161-3). If the sensor module (161) includes a temperature sensor, the processor (110) receives temperature data regarding the temperature measured from the sensor module (161) and can further perform brightness correction, etc., on the image data based on the temperature data.

[0080] The processor (110) can receive measurement data regarding the presence or absence of a user, the location of the user, the user's gaze, etc. from the camera module (171). The processor (110) can further perform brightness correction on the image data based on the measurement data. For example, the processor (110), having determined the presence or absence of a user through input from the camera module (171), can output the image data with corrected brightness to the display module (DM) through the data conversion circuit (112-2) or the gamma correction circuit (112-3).

[0081] Some of the above components may be connected to each other via a communication method between peripheral devices, such as a bus, GPIO (general purpose input / output), SPI (serial peripheral interface), MIPI (mobile industry processor interface), or UPI (Ultra path interconnect) link, to exchange signals (e.g., commands or data) with each other. The processor (110) may communicate with the display module (DM) via an interface agreed upon with each other, and may, for example, use any of the communication methods described above, but is not limited to the communication methods described above.

[0082] The electronic device (ED) according to the various embodiments disclosed in this document may be of various forms. The electronic device (ED) may include, for example, at least one of a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronics device. The electronic device (ED) according to the embodiments of this document is not limited to the devices described above.

[0083] FIGS. 2a and FIGS. 2b are perspective views of an electronic device according to one embodiment of the present invention.

[0084] Referring to FIG. 2a, an electronic device (ED') according to another embodiment of the present invention may be defined as a head-mounted display device. The electronic device (ED') may be worn on the head of a user (USR).

[0085] The electronic device (ED') can provide images to the user (USR) by blocking the user's (USR) peripheral vision. The electronic device (ED') can provide virtual reality to the user (USR).

[0086] The electronic device (ED') may include a case part (CAS), a cushion part (CUP), and a strap part (STP1, STP2). The case part (CAS) may be worn by a user (USR). Inside the case part (CAS), a display panel (DP) for displaying images and an accelerometer (not shown), etc., may be housed.

[0087] The accelerometer can detect the movement of the user (USR) and transmit a predetermined signal to the display panel (DP). Accordingly, the display panel (DP) can provide an image corresponding to changes in the user's (USR) gaze. As a result, the user (USR) can experience a virtual reality that is similar to actual reality.

[0088] The cushion portion (CUP) may be positioned between the case portion (CAS) and the user (USR). The cushion portion (CUP) may include a material that is freely deformable. For example, the cushion portion (CUP) may include a polymer resin (e.g., polyurethane (PU), polycarbonate (PC), polypropylene, and polyethylene (PE). Additionally, the cushion portion (CUP) may include a foam-molded sponge made of a rubber liquid, a urethane-based material, or an acrylic-based material.

[0089] The cushion portion (CUP) allows the case portion (CAS) to adhere closely to the user (USR), thereby improving the user's (USR) wearing comfort. The cushion portion (CUP) can be detached from the case portion (CAS).

[0090] The strap portion (STP1, STP2) can be combined with the case portion (CAS) to allow the case portion (CAS) to be easily worn by the user (USR). The strap portion (STP1, STP2) may include a first strap (STP1) and a second strap (STP2).

[0091] The first strap (STP1) can be worn along the circumference of the user's (USR) head. The first strap (STP1) can secure the case part (CAS) to the user (USR) so that the case part (CAS) can be closely fitted to the user's (USR) head.

[0092] The second strap (STP2) can connect the case part (CAS) and the first strap (STP1) along the top of the user's (USR) head. The second strap (STP2) can prevent the case part (CAS) from sliding down.

[0093] Referring to FIG. 2b, the case portion (CAS) may include a first case (CAS1) and a second case (CAS2). The first case (CAS1) and the second case (CAS2) may be separated from each other.

[0094] The display panel (DP) may be positioned between the first case (CAS1) and the second case (CAS2). The display panel (DP) may be accommodated inside a case portion (CAS) formed by combining the first case (CAS1) and the second case (CAS2). For example, the display panel (DP) may provide a left-eye image and a right-eye image to the user. Thus, the display panel (DP) may provide a stereoscopic image to the user.

[0095] An optical system (OTP) may be placed inside the first case (CAS1). The optical system (OTP) can magnify an image provided from a display panel (DP). The optical system (OTP) may be placed between the display panel (DP) and the user's (USR) eye. The optical system (OTP) may include a left eye optical system (OTP1) and a right eye optical system (OTP2). The left eye optical system (OTP1) may magnify and provide an image to the user's (USR) left pupil, and the right eye optical system (OTP2) may magnify and provide an image to the user's (USR) right pupil.

[0096] FIG. 3 is a cross-sectional view of an electronic device illustrated in FIG. 1a. FIG. 4 is a cross-sectional view of a display panel illustrated in FIG. 3.

[0097] Referring to FIG. 3, the electronic device (ED) may include a display panel (DP), an input sensing unit (ISP), an anti-reflective layer (RPL), a window (WIN), a panel protection film (PPF), and first and second adhesive layers (AL1, AL2). The display panel (DP) corresponds to the display panel (DP, see FIG. 1b) described above, and the input sensing unit (ISP) may correspond to the sensor module (161, see FIG. 1b) described above.

[0098] A display panel (DP) according to one embodiment of the present invention may be a light-emitting display panel. For example, the display panel (DP) may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots or quantum rods, etc. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel by way of example.

[0099] Referring to FIG. 4, the display panel (DP) may include a base layer (BS), a circuit element layer (DP-CL), a display element layer (DP-OLED), and a thin film encapsulation layer (TFE). The circuit element layer (DP-CL), the display element layer (DP-OLED), and the thin film encapsulation layer (TFE) may be sequentially arranged on the base layer (BS).

[0100] The base layer (BS) may include glass or a flexible plastic material such as polyimide (PI).

[0101] Multiple pixels may be disposed in the circuit element layer (DP-CL) and the display element layer (DP-OLED). Each pixel may include a transistor disposed in the circuit element layer (DP-CL) and a light-emitting element disposed in the display element layer (DP-OLED) and connected to the transistor.

[0102] A thin film encapsulation layer (TFE) may be disposed on a circuit element layer (DP-CL) to cover a display element layer (DP-OLED). The thin film encapsulation layer (TFE) can protect pixels from moisture, oxygen, and external foreign substances. Meanwhile, although the thin film encapsulation layer (TFE) is illustrated as covering the entire area of ​​the base layer (BS) in this embodiment, in one embodiment of the present invention, the base layer (BS) may include a portion of the area exposed from the thin film encapsulation layer (TFE). Alternatively, the area exposed from the thin film encapsulation layer (TFE) may be formed along the edge of the base layer (BS), and is not limited to any one embodiment.

[0103] Referring to FIG. 3, an input sensing unit (ISP) may be placed on a display panel (DP). The input sensing unit (ISP) may include a plurality of sensing units (not shown) for sensing external inputs in a capacitive manner. The input sensing unit (ISP) may be formed directly on the display panel (DP) during the manufacture of the electronic device (ED). Specifically, a conductive pattern or insulating layer constituting the input sensing unit (ISP) may be directly deposited or patterned on the display panel (DP). However, one embodiment is not limited thereto, and the input sensing unit (ISP) may be manufactured as a separate panel from the display panel (DP) and attached to the display panel (DP) through an adhesive layer.

[0104] Referring to FIG. 3, an anti-reflection layer (RPL) may be placed on an input sensing unit (ISP). The anti-reflection layer (RPL) can reduce the external light reflectivity of the electronic device (ED), thereby improving the visibility of the image displayed on the electronic device (ED). The anti-reflection layer (RPL) may include a phase delayer, a polarizer, a black matrix, a color filter, etc., and is not limited to any one embodiment. The anti-reflection layer (RPL) may be formed directly on the input sensing unit (ISP) through a coating or deposition process, or may be provided in the form of a film and attached to the input sensing unit (ISP) through an adhesive layer, and is not limited to any one embodiment.

[0105] The window (WIN) can be placed on the anti-reflective layer (RPL). The window (WIN) can protect the display panel (DP), the input sensing unit (ISP), and the anti-reflective layer (RPL) from external scratches and impacts.

[0106] A panel protection film (PPF) may be placed under a display panel (DP). The panel protection film (PPF) may support the display panel (DP) and protect the lower part of the display panel (DP). The panel protection film (PPF) may have insulating properties. For example, the panel protection film (PPF) may include resins such as polyethyleneterephthalate (PET), polyimide, and polypropylene (PP), but one embodiment is not limited thereto.

[0107] A first adhesive layer (AL1) is placed between a display panel (DP) and a panel protection film (PPF), and the display panel (DP) and the panel protection film (PPF) can be bonded together by the first adhesive layer (AL1). A second adhesive layer (AL2) is placed between a window (WIN) and an anti-reflection layer (RPL), and the window (WIN) and the anti-reflection layer (RPL) can be bonded together by the second adhesive layer (AL2).

[0108] FIG. 5 is a plan view of a display panel according to an embodiment of the present invention. FIG. 5 briefly illustrates some components of the display panel (DP) for easy explanation.

[0109] Referring to FIG. 5, the display panel (DP) may include pixels (PX), signal lines (SGL), a driving circuit (GDC), and a pad portion (PLD). The display panel (DP) may include pixels (PX), signal lines (SGL) electrically connected to the pixels (PX), a driving circuit (GDC), and a pad portion (PLD).

[0110] Pixels (PX) may be placed in a display area (DA). Pixels (PX) may be arranged in a first direction (DR1) and a second direction (DR2). Pixels (PX) may include a plurality of pixel rows extending in the first direction (DR1) and arranged in the second direction (DR2), and a plurality of pixel columns extending in the second direction (DR2) and arranged in the first direction (DR1).

[0111] Each of the pixels (PX) may include a light-emitting element and a pixel circuit that drives the light-emitting element. The light-emitting element may include an organic light-emitting diode, and the pixel circuit may include at least one transistor and a capacitor connected to the light-emitting element.

[0112] The signal lines (SGL) may include gate lines (GL), data lines (DL), power lines (PL), and control signal lines (CSL). Each of the gate lines (GL) may be connected to a corresponding pixel among the pixels (PX), and each of the data lines (DL) may be connected to a corresponding pixel among the pixels (PX). The power line (PL) may be electrically connected to the pixels (PX). The control signal line (CSL) may be connected to a driving circuit (GDC) to provide control signals to the driving circuit (GDC).

[0113] The driving circuit (GDC) may include a gate driving circuit. The gate driving circuit may generate gate signals and sequentially output the generated gate signals to gate lines (GL). The gate driving circuit may further output another control signal to the pixel driving circuit.

[0114] The pad portion (PLD) may be a portion to which a circuit board (not shown) is connected. The pad portion (PLD) may include pixel pads (D-PD), and the pixel pads (D-PD) may be pads for connecting a flexible circuit board to a display panel (DP). Each pixel pad (D-PD) may be connected to a corresponding signal line among the signal lines (SGL). One of the pixel pads (D-PD) may be connected to a control signal line (CSL) to transmit a control signal to a driving circuit (GDC). Some of the pixel pads (D-PD) may be connected to a data line (DL) to transmit data signals to each of the pixels (PX).

[0115] Additionally, the pad section (PLD) may further include input pads. The input pads may be pads for connecting the circuit board to the input detection section (ISP, see FIG. 3). However, not limited thereto, the input pads may be placed in the input detection section (ISP, see FIG. 3) and connected to a circuit board separate from the pixel pads (D-PD). Alternatively, the input detection section (ISP, see FIG. 3) may be omitted and may not further include input pads.

[0116] Figure 6 is a diagram illustrating the equivalent circuit of any one of the pixels shown in Figure 5.

[0117] Referring to FIG. 6, the pixel (PX) may include a first transistor (TR1), a second transistor (TR2), a third transistor (TR3), a light-emitting element (OLED), and a storage capacitor (CST).

[0118] A gate line (GL) may include a write gate line (GWL) and a compensation gate line (GCL). The write gate line (GWL) receives a write gate signal (GW), and the compensation gate line (GCL) receives a compensation gate signal (GC).

[0119] A parasitic capacitor (CPR, or first capacitor) may be formed between the second node (N2) and the data line (DL) between the second transistor (TR2) and the third transistor (TR3). By utilizing the capacitance formed through the parasitic capacitor (CPR), the necessary capacitor capacity can be provided without forming an additional separate capacitor. This simplifies the circuit design and reduces manufacturing costs. In the present invention, by placing the parasitic capacitor (CPR) on a different layer from the storage capacitor (CST, or second capacitor) with the transistors in between, the area of ​​the electrode constituting the parasitic capacitor (CPR) can be sufficiently secured. Accordingly, an electronic device with increased resolution can be provided. A detailed explanation thereof will be provided later.

[0120] A light-emitting device (OLED) can be defined as an organic light-emitting device. The light-emitting device (OLED) may include an anode (AE) and a cathode (CE). The anode (AE) may be connected to a first power line (PL1) through a first transistor (TR1). The cathode (CE) may be connected to a second power line (PL2). The first power line (PL1) may receive a first voltage (ELVDD). The second power line (PL2) may receive a second voltage (ELVSS) having a level lower than that of the first voltage (ELVDD).

[0121] Each of the first transistor (TR1) to the third transistor (TR3) may be a PMOS transistor. The first transistor (TR1) may include a silicon semiconductor, and the second and third transistors (TR2, TR3) may include an oxide semiconductor. However, one embodiment is not limited thereto, and each of the second and third transistors (TR2, TR3) may be an NMOS transistor.

[0122] Each of the first, second, and third transistors (TR1, TR2, TR3) may include a source electrode, a drain electrode, and a gate electrode. Hereinafter, for convenience in FIG. 7, either the source electrode or the drain electrode is defined as the first electrode and the other as the second electrode. Additionally, the gate electrode is defined as the control electrode.

[0123] The first transistor (TR1) can be defined as a driving transistor, and the second transistor (TR2) can be defined as a switching transistor. The third transistor (TR3) can be defined as a compensation transistor.

[0124] The first transistor (TR1) is connected to the first power line (PL1) and the anode (AE) of the light-emitting element (OLED), and can be switched according to the voltage of the first node (N1). The first transistor (TR1) may include a first electrode connected to the first power line (PL1), a second electrode connected to the anode (AE) of the light-emitting element (OLED), and a control electrode connected to the first node (N1). The first transistor (TR1) can be turned on by the voltage of the first node (N1). The first node (N1) can substantially be defined as the control electrode of the first transistor (TR1).

[0125] The second transistor (TR2) can be connected to the first node (N1) and the second node (N2). Specifically, the second transistor (TR2) can be connected to the gate electrode of the first transistor (TR1) and the data line (DL). The second transistor (TR2) can be switched by a write gate signal (GW).

[0126] The second transistor (TR2) may include a first electrode connected to the first node (N1), a second electrode connected to the second node (N2), and a control electrode connected to the write gate line (GWL). The second transistor (TR2) may be turned on by a write gate signal (GW) applied through the write gate line (GWL).

[0127] The third transistor (TR3) is connected to the second node (N2) and the anode (AE) of the light-emitting element (OLED) and can be switched by a compensation gate signal (GC). The third transistor (TR3) may include a first electrode connected to the second node (N2), a second electrode connected to the anode (AE) of the light-emitting element (OLED), and a control electrode connected to a compensation gate line (GCL). The third transistor (T3) can be turned on by a compensation gate signal (GC) applied through the compensation gate line (GCL).

[0128] The data line (DL) can be connected to the second node (N2). Accordingly, the data line (DL) can be connected to the second electrode of the second transistor (TR2) and the first electrode of the third transistor (TR3). The data line (DL) can receive a data signal (DATA).

[0129] The anode (AE) of the light-emitting element (OLED) can be connected to the first power line (PL1) through the first transistor (TR1), and the cathode (CE) of the light-emitting element (OLED) can be connected to the second power line (PL2).

[0130] The storage capacitor (CST) may include a first electrode connected to the initialization line (VIL) and a second electrode connected to the first node (N1). The initialization line (VIL) may receive an initialization voltage (VINT).

[0131] The write gate signal (GW) applied to the control electrode of the second transistor (TR2) may be a global clock signal for simultaneous light emission driving. For example, when a display device operates in a simultaneous light emission driving mode, the write gate signal (GW), which is a global clock signal, may be applied commonly to the pixels (PX).

[0132] Figure 7 is a timing diagram of signals for operating the pixel shown in Figure 6.

[0133] Referring to FIGS. 6 and 7, the operating period of the pixel (PX) may include an on-bias period (OBP), an initialization period (IP), a compensation period (CP), a data writing period (DWP), and an emission period (EMP).

[0134] The pixel (PX) can perform an on-bias operation in the on-bias period (OBP) and an initialization operation in the initialization period (IP). The pixel (PX) can perform a threshold voltage compensation operation in the compensation period (CP), a data write operation in the data write period (DWP), and a light emission operation in the light emission period (EMP).

[0135] In the on-bias period (OBP), the first voltage (ELVDD) has a high voltage level, the second voltage (ELVSS) has a high voltage level, and the initialization voltage (VINT) may have a low voltage level. In the on-bias period (OBP), the write gate signal (GW) and the compensation gate signal (GC) have a low level (e.g., disabled level), and the data signal (DATA) may have a reference voltage (VR) having a preset level.

[0136] In this case, an on-bias operation is performed for the pixel (PX), and accordingly, the voltage characteristic curve of the first transistor (TR1) can be initialized to an on-bias state regardless of the data signal (DATA) supplied in the previous frame. As a result, the pixel (PX) can generate a desired brightness regardless of the data signal (DATA) supplied in the previous frame.

[0137] In the on-bias period (OBP), an initialization voltage (VINT) having a low voltage level is delivered to the gate terminal of the first transistor (TR1), but since both the first voltage (ELVDD) and the second voltage (ELVSS) have high voltage levels, the first transistor (TR1) may not be turned on. Depending on the disabled write gate signal (GW) and the disabled compensation gate signal (GC), the second and third transistors (TR2, TR3) may be turned off.

[0138] Subsequently, during the initialization period (IP), the first voltage (ELVDD) has a low voltage level, the second voltage (ELVSS) has a high voltage level, and the initialization voltage (VINT) may have a low voltage level. During the initialization period (IP), the write gate signal (GW) transitions from a low level to a high level (e.g., an activation level), the compensation gate signal (GC) has a high level (e.g., an activation level), and the data signal (DATA) may have a reference voltage (VR).

[0139] Accordingly, the second transistor (TR2) can be turned off and then turned on, and the third transistor (TR3) can be turned on. Since the second and third transistors (TR2, TR3) are turned on, the first node (N1) can be connected to the second node (N2), and the second node (N2) can be connected to the anode (AE) of the light-emitting element (OLED). Depending on the initialization voltage (VINT), the first node (i.e., the control electrode of the first transistor (TR1)) can be initialized, the second node (N2) connected to the first node (N1) can be initialized, and the anode (AE) of the light-emitting element (OLED) connected to the second node (N2) can be initialized.

[0140] Subsequently, during the compensation interval (CP), the first voltage (ELVDD) has a high voltage level, the second voltage (ELVSS) has a high voltage level, and the initialization voltage (VINT) may have a high voltage level. During the compensation interval (CP), the write gate signal (GW) has a high level, the compensation gate signal (GC) has a high level, and the data signal (DATA) may have a reference voltage (VR).

[0141] The first transistor (TR1), the second transistor (TR2), and the third transistor (TR3) can be connected in the form of diodes. In this case, a voltage reflecting the threshold voltage of the first transistor (TR1) is stored at the first node (N1), and accordingly, characteristic deviations due to the threshold voltage of the first transistor (TR1) can be eliminated. The operation of connecting the first transistor (T1) in the form of diodes can be defined as a threshold voltage compensation operation.

[0142] Subsequently, in the data writing period (DWP), the first voltage (ELVDD) may have a low voltage level and the second voltage (ELVSS) may have a high voltage level. In the data writing period (DWP), after the initialization voltage (VINT) transitions from a high voltage level to a low voltage level, it may transition from a low voltage level to a high voltage level after a predetermined time has elapsed.

[0143] In the data writing period (DWP), the write gate signal (GW) can transition from a low level to a high level after a predetermined time (e.g., data writing operation time) has elapsed. In the data writing period (DWP), the compensation gate signal (GC) has a low level, and the data signal (DATA) can have a data voltage (VD) having a level corresponding to a predetermined grayscale.

[0144] The second transistor (TR2) can be turned on during the activation period (e.g., high level) of the write gate signal (GW), and the third transistor (TR3) can be turned off. During the data write operation time when the second transistor (TR2) is turned on, a data signal (DATA) can be stored in the storage capacitor (CST).

[0145] Subsequently, during the emission phase (EMP), the first voltage (ELVDD) has a high voltage level, the second voltage (ELVSS) has a low voltage level, and the initialization voltage (VINT) may have a high voltage level. The write gate signal (GW) has a low level, the compensation gate signal (GC) has a low level, and the data signal (DATA) may have a reference voltage (VR).

[0146] In this case, the first transistor (TR1) can be turned on based on the data signal (DATA) stored in the storage capacitor (CST). Thus, current flows through the light-emitting element (OLED), and the light-emitting element (OLED) can emit light.

[0147] Figure 8 is a cross-sectional view of a display panel cut along the II' cutting line of Figure 5.

[0148] Referring to FIG. 8, the display panel (DP) may include a base layer (BS), a circuit element layer (DP-CL), a display element layer (DP-OLED), and a thin film encapsulation layer (TFE).

[0149] A display panel (DP) may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. Insulating layers, semiconductor layers, and conductive layers are formed by methods such as coating or deposition. Subsequently, insulating layers, semiconductor layers, and conductive layers can be selectively patterned by photolithography and etching. In this way, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer (DP-CL) and the display element layer (DP-OLED) can be formed.

[0150] The base layer (BS) may include a glass substrate, a sapphire substrate, a plastic film, or an organic / inorganic laminated film. The base layer (BS) may have a multilayer or single-layer structure. For example, the base layer (BS) may have a laminated structure of multiple plastic films bonded by an adhesive, or a laminated structure of a glass substrate and a plastic film bonded by an adhesive. The base layer (BS) may have flexibility. For example, the base layer (BS) may include polyimide. However, this is described by way of example, and the base layer (BS) may be provided in a rigid state and is not limited to any one embodiment.

[0151] The circuit element layer (DP-CL) may include pixel drivers, lower conductive patterns (BMP), buffer layers (BFL1, BFL2), and first to sixth insulating layers (10, 20, 30, 40, 50, 60).

[0152] Referring to FIG. 8, the circuit element layer (DP-CL) can be placed on the base layer (BS). FIG. 8 illustrates two transistors (TR1, TR2), two capacitors (CPR, CST), an upper electrode (UE), and a plurality of connecting electrodes (CNa, CNb, CNc) among the pixel driving units, and sequentially stacked first to sixth insulating layers (10, 20, 30, 40, 50, 60). Meanwhile, this is illustrated as an example, and the configuration or arrangement relationship of the pixel driving units constituting the circuit element layer (DP-CL) can be varied and is not limited to any one embodiment.

[0153] A buffer layer (BFL) may be disposed on a base layer (BS). The buffer layer (BFL) can improve the bonding strength between the base layer (BS) and the semiconductor pattern. The buffer layer (BFL) may include a silicon oxide layer and / or a silicon nitride layer. If the buffer layer (BFL) includes a silicon oxide layer and a silicon nitride layer, the two layers may be stacked alternately.

[0154] Referring to FIG. 8, the buffer layer (BFL) may be provided with a plurality of layers. The buffer layer (BFL) may include a first buffer layer (BFL1) and a second buffer layer (BFL2). The first buffer layer (BFL1) may cover a first capacitor (CPR). The second buffer layer (BFL2) may cover lower conductive patterns (BMP). However, one embodiment is not limited thereto, and the buffer layer (BFL) may be a single layer.

[0155] The lower conductive patterns (BMP) may be placed on the base layer (BS). The lower conductive patterns (BMP) may be placed between the first capacitor (CPR) and the first transistor (TR1). The lower conductive patterns (BMP) may constitute a pixel (PX). The lower conductive patterns (BMP) may include a conductive material and may include a metal. Alternatively, the lower conductive patterns (BMP) may include a light-blocking material. The lower conductive patterns (BMP) may include the same material, but are not limited thereto and may include different materials and are not limited to any one embodiment. The lower conductive patterns (BMP) may be placed to overlap with the transistors (TR1, TR2), etc., to protect the semiconductor patterns of the transistors (TR1, TR2), etc. The lower conductive patterns (BMP) may be placed below the transistors (TR1, TR2) to block the electrical potential from affecting the transistors (TR1, TR2) or to block external light from reaching the transistors (TR1, TR2).

[0156] Each of the lower conductive patterns (BMP) can overlap with the semiconductor patterns (AC1, AC2). One of the lower conductive patterns (BMP) can overlap with the first semiconductor pattern (AC1), and another of the lower conductive patterns (BMP) can overlap with the second semiconductor pattern (AC2). By arranging the lower conductive patterns (BMP) to overlap with the semiconductor patterns (AC1, AC2) of each of the transistors (TR1, TR2), electrical interference exerted by the conductive layers placed beneath the transistors (TR1, TR2) on the transistors (TR1, TR2) can be minimized.

[0157] The insulating layers (10, 20, 30, 40, 50, 60) may include first to sixth insulating layers (10, 20, 30, 40, 50, 60) sequentially stacked on the base layer (BS), but this is illustrated as an example and the number of insulating layers constituting the circuit element layer (DP-CL) can be varied and is not limited to any one embodiment.

[0158] Transistors (TR1, TR2) may be placed on buffer layers (BFL1, BFL2). The transistors (TR1, TR2) may include a first transistor (TR1) and a second transistor (TR2). In this case, the first transistor (TR1) may correspond to the first transistor (TR1) of FIG. 6, and the second transistor (TR2) may correspond to the second transistor (TR2) of FIG. 6. The first transistor (TR1) may be defined as a driving transistor, and the second transistor (TR2) may be defined as a switching transistor. However, one embodiment is not limited thereto.

[0159] The first transistor (TR1) may include a first semiconductor pattern (AC1) and a first gate electrode (GE1). The second transistor (TR2) may be placed on the same layer as the first transistor (TR1). The second transistor (TR2) may include a second semiconductor pattern (AC2) and a second gate electrode (GE2). In this case, the first semiconductor pattern (AC1) may be placed between the first capacitor (CPR) and the second capacitor (CST).

[0160] Semiconductor patterns (AC1, AC2) may be disposed on buffer layers (BFL1, BFL2). Each of the semiconductor patterns (AC1, AC2) may be disposed overlapping with a lower conductive pattern (BMP). The semiconductor patterns (AC1, AC2) may include polysilicon. However, they are not limited thereto, and the semiconductor patterns (AC1, AC2) may include amorphous silicon or metal oxide. FIG. 8 illustrates only some of the semiconductor patterns (AC1, AC2) as examples, and at least one additional semiconductor pattern may be disposed within a plurality of light-emitting regions. The semiconductor patterns (AC1, AC2) may include a plurality of regions distinguished by conductivity.

[0161] Each of the semiconductor patterns (AC1, AC2) may include a source region (SE1, SE2), an active region (AA1, AA2), and a drain region (DE1, DE2). The active region (AA1, AA2) may be a region having relatively lower electrical conductivity compared to the source region (SE1, SE2) and the drain region (DE1, DE2). The source region (SE1, SE2) and the drain region (DE1, DE2) may be spaced apart from each other with the active region (AA1, AA2) in between.

[0162] The gate electrodes (GE1, GE2) may be placed between the second insulating layer (20) and the third insulating layer (30). The gate electrodes (GE1, GE2) may be placed overlapping the active regions (AA1, AA2) among the semiconductor patterns (AC1, AC2). In this embodiment, the transistors (TR1, TR2) are illustrated as having a top-gate structure. However, this is illustrated as an example, and the gate electrodes (GE1, GE2) may be placed below the semiconductor patterns (AC1, AC2) and are not limited to any one embodiment.

[0163] The source region (SE1, SE2), active region (AA1, AA2), and drain region (DE1, DE2) of the transistor (TR1, TR2) can be covered by the second insulating layer (20). The transistor (TR1, TR2) can be covered by the third insulating layer (30).

[0164] The first capacitor (CPR) may be placed on the base layer (BS) and positioned below the first and second transistors (TR1, TR2). The first capacitor (CPR) may include a first lower capacitor electrode (LCE1) and a second lower capacitor electrode (LCE2). The first lower capacitor electrode (LCE1) and the second lower capacitor electrode (LCE2) may be positioned below the semiconductor patterns (AC1, AC2). A detailed description of the first capacitor (CPR) will be provided later.

[0165] The first capacitor (CPR) can be connected to the second transistor (TR2) through the upper electrode (UE). The upper electrode (UE) can be placed on the first capacitor (CPR) and the second transistor (TR2). The upper electrode (UE) can have a bridge shape in cross-section.

[0166] The upper electrode (UE) can be connected to the first capacitor (CPR) and the second transistor (TR2) through a contact hole (CNT1-1) penetrating the first to fourth insulating layers (10, 20, 30, 40) and a contact hole (CNT1-2) penetrating the second to fourth insulating layers (20, 30, 40). That is, the upper electrode (UE) can connect the first capacitor (CPR) and the second transistor (TR2). The upper electrode (UE) can be connected to the first lower capacitor electrode (LCE1) of the first capacitor (CPR). The upper electrode (UE) may include the same material as at least one of the electrodes constituting the first capacitor (CPR).

[0167] When the upper electrode (UE) is connected to the first lower capacitor electrode (LCE1) of the first capacitor (CPR), the distance between the transistor and the capacitor electrode connected to the transistor can be increased compared to when it is connected to the second lower capacitor electrode (LCE2). Accordingly, electrical interference occurring between the transistor and the first capacitor (CPR) can be reduced, and voltage accumulation can be achieved stably.

[0168] The first lower capacitor electrode (LCE1) can be connected between the second node (N2) and the data line (DL, see FIG. 5). The first lower capacitor electrode (LCE1) may have an integral shape with the data line (DL). That is, in one embodiment, the first lower capacitor electrode (LCE1) may be utilized as the data line (DL). Accordingly, additional wiring may not be required, and space within the circuit may be saved. Additionally, the degree of freedom in circuit design may be increased, enabling efficient layout design. However, one embodiment is not limited thereto, and the first lower capacitor electrode (LCE1) may have an integral shape with the gate line (GL, see FIG. 5).

[0169] The second capacitor (CST) may be placed on the base layer (BS). The second capacitor (CST) may be placed on top of the first and second transistors (TR1, TR2). The second capacitor (CST) may include a first upper capacitor electrode (UCE1, or first gate electrode), a second upper capacitor electrode (UCE2, or second gate electrode), and a third upper capacitor electrode (UCE3, or third gate electrode). The second upper capacitor electrode (UCE2) may be placed on the first upper capacitor electrode (UCE1), and the third upper capacitor electrode (UCE3) may be placed on the second upper capacitor electrode (UCE2). In this case, the first upper capacitor electrode (UCE1) may correspond to the first gate electrode (GE1) of the first transistor (TR1). That is, the first transistor (TR1) and the second capacitor (CST) may share at least one electrode.

[0170] A capacitance (CST1) may be formed between the second upper capacitor electrode (UCE2) and the third upper capacitor electrode (UCE3). A capacitance (CST2) may be formed between the first upper capacitor electrode (UCE1) and the second upper capacitor electrode (UCE2). That is, the second capacitor (CST) may have a dual capacitor structure.

[0171] The second capacitor (CST) can be connected to the first transistor (TR1). The third upper capacitor electrode (UCE3) of the second capacitor (CST) can be connected to the first transistor (TR1) and the second transistor (TR2), respectively, through a contact hole (CNT3-1) penetrating the second to fourth insulating layers (20, 30, 40) and a contact hole (CNT3-2) penetrating the third and fourth insulating layers (30, 40). The first capacitor (CPR) can correspond to the parasitic capacitor (CPR) of FIG. 6, and the second capacitor (CST) can correspond to the capacitor (CST) of FIG. 6. However, one embodiment is not limited thereto.

[0172] The first insulating layer (10) disposed between the first lower capacitor electrode (LCE1) and the second lower capacitor electrode (LCE2) insulates the first lower capacitor electrode (LCE1) and the second lower capacitor electrode (LCE2) and can function as a dielectric of the first capacitor (CPR) between the first lower capacitor electrode (LCE1) and the second lower capacitor electrode (LCE2).

[0173] A third insulating layer (30) disposed between the first upper capacitor electrode (UCE1) and the second upper capacitor electrode (UCE2), and a fourth insulating layer (40) disposed between the second upper capacitor electrode (UCE2) and the third upper capacitor electrode (UCE3), can each insulate the first upper capacitor electrode (UCE1) and the second upper capacitor electrode (UCE2), and the second upper capacitor electrode (UCE2) and the third upper capacitor electrode (UCE3). Additionally, the third insulating layer (30) disposed between the first upper capacitor electrode (UCE1) and the second upper capacitor electrode (UCE2), and the fourth insulating layer (40) disposed between the second upper capacitor electrode (UCE2) and the third upper capacitor electrode (UCE3), can each function as a dielectric of the second capacitor (CST) between the first upper capacitor electrode (UCE1) and the second upper capacitor electrode (UCE2), and between the second upper capacitor electrode (UCE2) and the third upper capacitor electrode (UCE3).

[0174] The first connecting electrode (CNa) may be disposed between the third insulating layer (30) and the fourth insulating layer (40). The first connecting electrode (CNa) may be connected to the second gate electrode (GE2) through a contact hole (CNT2) penetrating the third insulating layer (30). The second connecting electrode (CNb) may be connected to the first connecting electrode (CNa) through a contact hole (CNT4) penetrating the fourth and fifth insulating layers (40, 50). The third connecting electrode (CNc) may be connected to the first semiconductor pattern (AC1) through a contact hole (CNT5) penetrating the second to fifth insulating layers (20, 30, 40, 50). A driving signal may be transmitted to the display element layer (DP-OLED) through the third connecting electrode (CNc).

[0175] Referring to FIG. 8, in one embodiment of the present invention, the display panel (DP) may further include a shielding electrode (SSE). The shielding electrode (SSE) may be positioned between the first gate electrode (GE1) of the first transistor (TR1) and the second gate electrode (GE2) of the second transistor (TR2) with respect to the first direction (DR1). The shielding electrode (SSE) may be positioned between the first gate electrode (GE1) and the second gate electrode (GE2) to perform a shielding function.

[0176] A display element layer (DP-OLED) can be disposed on a circuit element layer (DP-CL). The display element layer (DP-OLED) may include a pixel definition film (PDL) and a light-emitting element (OLED).

[0177] A pixel defining film (PDL) may be disposed on the sixth insulating layer (60) of the circuit element layer (DP-CL). A light-emitting opening (PDL-OP) may be defined in the pixel defining film (PDL) (or may have). The light-emitting opening (PDL-OP) may correspond to an anode (AE), and the pixel defining film (PDL) may expose at least a portion of the anode (AE) through the light-emitting opening (PDL-OP).

[0178] The pixel defining layer (PDL) may include an inorganic insulating material. For example, it may include silicon nitride (SiNx, or silicon nitride).

[0179] The light-emitting element (OLED) may include an anode (AE), a light-emitting pattern (EP), and a cathode (CE).

[0180] An anode (AE) may be disposed on the sixth insulating layer (60) of the circuit element layer (DP-CL). The anode (AE) may be a transparent electrode, a semi-transparent electrode, or a reflective electrode. The anode (AE) may include a single layer or a multilayer structure. The anode (AE) may include a plurality of layers including ITO and Ag. For example, the anode (AE) may include a layer including ITO (hereinafter, lower ITO layer), a layer including Ag disposed on the lower ITO layer (hereinafter, Ag layer), and a layer including ITO disposed on the Ag layer (hereinafter, upper ITO layer). However, it is not limited thereto, and the anode (AE) may be provided as a single layer.

[0181] The light-emitting layer (EML) may be placed on the anode (AE). The light-emitting layer (EML) may also be referred to as an 'organic layer' or an 'intermediate layer'. The light-emitting layer (EML) may cover a portion of the upper surface of the pixel defining film (PDL).

[0182] The light-emitting element (OLED) may further include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between an anode (AE) and a light-emitting layer (EML), and may further include an electron transport layer (ETL) and an electron injection layer (EIL) disposed on the light-emitting layer (EML).

[0183] The cathode (CE) can be placed on the light-emitting layer (EML). The cathode (CE) can cover the light-emitting layer (EML). The cathode (CE) can be placed on the electronic control layer (ECL). The cathode (CE) can be placed commonly on the pixels (PX, see FIG. 5). That is, the cathode (CE) can be placed commonly on the light-emitting layers (EML) of the pixels (PX).

[0184] A thin film encapsulation layer (TFE) can be disposed on a light-emitting device (OLED). The thin film encapsulation layer (TFE) may include sequentially stacked inorganic layers, organic layers, and inorganic layers. The inorganic layers may contain inorganic materials and can protect pixels from moisture / oxygen. The organic layers may contain organic materials and can protect pixels (PX) from foreign substances such as dust particles.

[0185] In the present invention, the first capacitor (CPR) may be placed below the first and second transistors (TR1, TR2). The first capacitor (CPR) may be a parasitic capacitor formed between the second node (N2, see FIG. 6) and the data line (DL, see FIG. 6). That is, the first capacitor (CPR) may include a first lower capacitor electrode (LCE1) connected to the data line and a second lower capacitor electrode (LCE2) connected to the second node (N2). In this embodiment, the second lower capacitor electrode (LCE2) may be placed on the first lower capacitor electrode (LCE1) and connected to the source region of the second transistor (TR2) to be connected to the second node (N2). However, this is illustrated as an example, and the first lower capacitor electrode (LCE1) may be placed on the second lower capacitor electrode (LCE2), and is not limited to any one embodiment.

[0186] According to the present invention, the first capacitor (CPR) is positioned below the first and second transistors (TR1, TR2), thereby allowing it to be placed on a different layer from the second capacitor (CST) with the first and second transistors (TR1, TR2) in between. Since the formation of the first capacitor (CPR) is not affected by the electrodes of the transistors and the wiring design connected thereto, the area of ​​the first lower capacitor electrode (LCE1) and the second lower capacitor electrode (LCE2) constituting the first capacitor (CPR) can be easily secured. Accordingly, interference with other components constituting the driving circuit is prevented, and the capacitance of the first capacitor (CPR) can be sufficiently secured without increasing the area occupied by the driving circuit. Therefore, a larger number of driving circuits can be placed within a given area, and an electronic device with increased resolution can be provided. That is, design flexibility for the capacitor and driving circuit can be increased, the process can be simplified, and the integration density of the source electrode and drain electrode can be relaxed.

[0187] At this time, the area of ​​each of the first lower capacitor electrode (LCE1) and the second lower capacitor electrode (LCE2) constituting the first capacitor (CPR) may be larger than the area of ​​the anode (AE). The ratio of the area of ​​each of the first and second lower capacitor electrodes (LCE1, LCE2) to the area of ​​the anode (AE) may be 1.4 or greater. The area of ​​each of the first and second lower capacitor electrodes (LCE1, LCE2) may be 140% or greater of the area of ​​the anode (AE). By forming the area of ​​each electrode of the first capacitor (CPR) to be larger than that of the anode (AE), current and voltage changes caused by the driving signal can be absorbed or mitigated by the capacitor. Accordingly, stable pixel driving can be achieved by minimizing signal fluctuations. In addition, increasing the electrode area of ​​the first capacitor (CPR) can reduce interference between adjacent pixels or circuits. While the anode (AE) is operating, the first capacitor (CPR) can maintain a stable voltage, enabling clearer and more accurate image representation in high-resolution electronic devices.

[0188] The first capacitor (CPR) and the second capacitor (CST) can be distributed below and above the first and second transistors (TR1, TR2), respectively. In this case, compared to the case where the capacitors (CPR, CST) are all placed above the transistors (TR1, TR2), spatial constraints on the formation of the electrodes constituting the capacitors (CPR, CST) can be reduced. That is, as the area occupied by the electrodes of the capacitors (CPR, CST) is efficiently distributed, extra space can be secured to place other components or wiring within the circuit.

[0189] In addition, as the first capacitor (CPR) and the second capacitor (CST) are distributed below and above the first and second transistors (TR1, TR2), respectively, the source electrode and drain electrode connected to each of the transistors can be placed on different layers. Accordingly, as the current flows through various paths, the resistance can be distributed and the Drain-Source Resistance (D / R) can be mitigated.

[0190] also, Compared to the case where all capacitors (CPR, CST) are placed on top of the transistors (TR1, TR2), the number of layers stacked on the transistors (TR1, TR2) can be reduced. That is, the distance (SD) from the semiconductor patterns (AC1, AC2) of the transistors (TR1, TR2) to the anode (AE) can be reduced. Specifically, referring to FIG. 8, the distance (SD) from the first semiconductor pattern (AC1) to the anode (AE) is 1.5 It may be less than.

[0191] FIG. 9 is a cross-sectional view of a display panel cut along the II' cutting line of FIG. 5. In the following description with reference to FIG. 9, the same or similar reference numerals are used for configurations identical or similar to those described in FIG. 8, and redundant descriptions are omitted.

[0192] Referring to FIG. 9, the first capacitor (CPR) can be connected to the second transistor (TR2) through an upper electrode (UE). The upper electrode (UE) can be placed on the first capacitor (CPR) and the second transistor (TR2). The upper electrode (UE) can have a bridge shape in cross-section.

[0193] The upper electrode (UE) can be connected to the first capacitor (CPR) and the second transistor (TR2), respectively, through a contact hole (CNT1-1) penetrating the first to fourth insulating layers (10, 20, 30, 40) and a contact hole (CNT1-2) penetrating the second to fourth insulating layers (20, 30, 40). That is, the upper electrode (UE) can connect the first capacitor (CPR) and the second transistor (TR2). The upper electrode (UE) can be connected to the second lower capacitor electrode (LCE2) of the first capacitor (CPR). The upper electrode (UE) may include the same material as at least one of the electrodes constituting the first capacitor (CPR).

[0194] When the upper electrode (UE) is connected to the second lower capacitor electrode (LCE2) of the first capacitor (CPR), the distance between the transistor and the capacitor electrode connected to the transistor can be reduced compared to when it is connected to the first lower capacitor electrode (LCE1). Accordingly, electrical changes occurring in the transistor can be transmitted to the capacitor at a faster speed, and the switching speed, accuracy, and power efficiency of the circuit can be improved.

[0195] FIGS. 10a to 10n are plan views showing a part of a display panel according to one embodiment of the present invention.

[0196] Referring to FIGS. 10a and 10b, a second lower capacitor electrode (LCE2) may be disposed on a first lower capacitor electrode (LCE1). The second lower capacitor electrode (LCE2) may overlap with the first lower capacitor electrode (LCE1) in a plane. The first lower capacitor electrode (LCE1) may form a first capacitor (CPR, see FIG. 8) together with the second lower capacitor electrode (LCE2).

[0197] The first lower capacitor electrode (LCE1) may have an integral shape with the data line (DL). That is, in one embodiment, the first lower capacitor electrode (LCE1) may be utilized as the data line (DL). Accordingly, additional wiring may not be required, and space within the circuit may be saved. Additionally, the degree of freedom in circuit design may be increased, enabling efficient layout design. However, one embodiment is not limited thereto, and the first lower capacitor electrode (LCE1) may have an integral shape with the gate line (GL, see FIG. 5).

[0198] In one embodiment of the present invention, the data line (DL) may include a line portion extended with respect to a second direction (DR2) and a portion protruding from the line portion. In this case, the line portion may be a portion that intersects insulatingly with the gate line (GL, see FIG. 5). The second lower capacitor electrode (LCE2) may overlap with the protruding portion of the data line in a plane. That is, the protruding portion of the data line (DL) may form a capacitor together with the second lower capacitor electrode (LCE2). The protruding portion of the data line (DL) may overlap with the anode (AE) in a plane.

[0199] In FIG. 10a and FIG. 10b, the first lower capacitor electrode (LCE1) is shown having a shape that is integral with the data line (DL), but one embodiment is not limited thereto. For example, a second lower capacitor electrode (LCE2) disposed on the first lower capacitor electrode (LCE1) may have a shape that is integral with the data line (DL) and may form a capacitor together with the first lower capacitor electrode (LCE1).

[0200] Referring to FIG. 10c, a lower conductive pattern (BMP) may be placed on the lower capacitor electrodes (LCE1, LCE2). The lower conductive pattern (BMP) may overlap with the lower capacitor electrodes (LCE1, LCE2) in a plane.

[0201] Referring to FIG. 10d, the active layer (ACT) of a transistor can be placed on the lower conductive pattern (BMP). The active layer (ACT) may correspond to the layer on which the first and second semiconductor patterns (AC1, AC2) shown in FIG. 8 are placed. The active layer (ACT) may overlap with the lower conductive pattern (BMP) in a plane. By placing the lower conductive pattern (BMP) so as to overlap with the active layer (ACT) of each transistor, electrical interference exerted by the conductive layers placed below the transistor on the transistor can be minimized.

[0202] Referring to FIGS. 10e to 10j, gate electrodes (UCE1, UCE2, UCE3) may be disposed on an active layer (ACT), and contact holes (CNTa, CNTb, CNTc) for connecting the gate electrodes (UCE1, UCE2, UCE3) and other conductive layers may be defined. At this time, the gate electrodes (UCE1, UCE2, UCE3) may correspond to the first to third upper capacitor electrodes (UCE1, UCE2, UCE3) shown in FIG. 8, and the contact holes (CNTa, CNTb, CNTc) may correspond to the contact holes (CNT1-1 to CNT5) shown in FIG. 8.

[0203] Referring to FIG. 10f, among the contact holes (CNTa, CNTb, CNTc), the first contact hole (CNTa) can be formed by penetrating the insulating layer (INS1) formed on the first gate electrode (UCE1). At this time, the insulating layer (INS1) corresponds to the third insulating layer (30) of FIG. 8, and the first contact hole (CNTa) can correspond to the contact hole (CNT2) penetrating the third insulating layer (30) of FIG. 8.

[0204] Referring to FIG. 10h, among the contact holes (CNTa, CNTb, CNTc), the second contact hole (CNTb) can be formed by penetrating the insulating layer (INS2) formed on the second gate electrode (UCE2). At this time, the insulating layer (INS2) corresponds to the fourth insulating layer (40) of FIG. 8, and the second contact hole (CNTb) can correspond to the contact holes (CNT1-1, CNT1-2, CNT3-1, CNT3-2) penetrating the fourth insulating layer (40) of FIG. 8.

[0205] Referring to FIG. 10j, among the contact holes (CNTa, CNTb, CNTc), the third contact hole (CNTc) can be formed by penetrating the insulating layer (INS3) formed on the third gate electrode (UCE3). At this time, the insulating layer (INS3) corresponds to the fifth insulating layer (50) of FIG. 8, and the third contact hole (CNTc) can correspond to the contact holes (CNT4, CNT5) penetrating the fifth insulating layer (50) of FIG. 8.

[0206] Referring to FIG. 10k and FIG. 10l, driving voltage lines (VL), initialization voltage lines (RL1, RL2), and connecting electrodes (SD1, SD2) may be disposed on gate electrodes (UCE1, UCE2, UCE3), and contact holes (CNTd) for connecting the lines (VL, RL1, RL2) and connecting electrodes (SD1, SD2) to an OLED may be defined.

[0207] Referring to FIG. 10, a contact hole (CNTd) can be formed by penetrating an insulating layer (INS4) formed on a driving voltage line (VL), initialization voltage lines (RL1, RL2), and connecting electrodes (SD1, SD2). At this time, the insulating layer (INS4) corresponds to the sixth insulating layer (60) of FIG. 8, and the contact hole (CNTd) can correspond to the sixth insulating layer (60) of FIG. 8.

[0208] Referring to FIG. 10m, light-emitting elements (OLEDs) including an anode (AE) can be disposed on a driving voltage line (VL), initialization voltage lines (RL1, RL2), and connecting electrodes (SD1, SD2). The light-emitting elements (OLEDs) can be connected to the connecting electrodes (SD1, SD2) through a contact hole (CNTd).

[0209] Referring to FIG. 10n, the anode (AE) may overlap with the first and second lower capacitor electrodes (LCE1, LCE2) on a plane. In this case, the area of ​​each of the first and second lower capacitor electrodes (LCE1, LCE2) may be larger than the area of ​​the anode (AE). The ratio of the area of ​​each of the first and second lower capacitor electrodes (LCE1, LCE2) to the area of ​​the anode (AE) may be 1.4 or greater. The area of ​​each of the first and second lower capacitor electrodes (LCE1, LCE2) may be 140% or greater of the area of ​​the anode (AE). By forming the area of ​​each electrode of the first capacitor (CPR) larger than that of the anode (AE), current and voltage changes caused by the driving signal can be absorbed or mitigated by the capacitor. Accordingly, stable pixel driving can be achieved by minimizing signal fluctuations. In addition, increasing the electrode area of ​​the first capacitor (CPR) can reduce interference between adjacent pixels or circuits. While the anode (AE) is operating, the parasitic capacitor can maintain a stable voltage, enabling clearer and more accurate image representation in high-resolution electronic devices.

[0210] As described above, by placing the first capacitor (CPR) below the first and second transistors (TR1, TR2), the first capacitor (CPR) can be formed without being affected by the electrodes of the transistors and the wiring design connected thereto. Accordingly, the area of ​​the first lower capacitor electrode (LCE1) and the second lower capacitor electrode (LCE2) constituting the first capacitor (CPR) can be easily secured.

[0211] FIGS. 11a to 11j are cross-sectional views illustrating some of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. In the following description with reference to FIGS. 11a to 11j, the same or similar reference numerals are used for configurations identical or similar to those described in FIGS. 9 to 10m, and redundant descriptions are omitted.

[0212] Referring to FIGS. 11a and 11b, a first pre-buffer layer (BFL1-1) may be formed on a second lower capacitor electrode (LCE2) to cover the second lower capacitor electrode (LCE2). At this time, the upper surface (BFL1-US') of the formed first pre-buffer layer (BFL1-1) may not be flat. For example, the short-distance surface roughness of the upper surface (BFL1-US') of the first pre-buffer layer (BFL1-1) may be 10 nm or more, and the long-distance surface roughness may be 200 nm or more. In this specification, short-distance surface roughness may refer to surface roughness measured when the length scale is less than 1 μm, and long-distance surface roughness may refer to surface roughness measured when the length scale is 1 μm or more.

[0213] A method for manufacturing a display panel according to one embodiment of the present invention may include a step of polishing the upper surface (BFL1-US') of the first pre-buffer layer (BFL1-1) after forming the first pre-buffer layer (BFL1-1). The step of polishing the upper surface (BFL1-US') of the first pre-buffer layer (BFL1-1) may include a Chemical Mechanical Polishing (CMP) process. In this specification, polishing may comprehensively refer to a process of performing to provide a smoother surface on the upper surface (BFL1-US') of the first pre-buffer layer (BFL1-1). The upper surface may be flattened by applying a polishing solution (PT1, or polishing gas) onto the first pre-buffer layer (BFL1-1). At this time, the polishing solution (PT1) may include a slurry.

[0214] A polishing solution (PT1) may be applied to the upper surface (BFL1-US') of the first pre-buffer layer (BFL1-1) to cause a chemical reaction, thereby polishing and flattening the upper surface (BFL1-US'). Additionally, although not illustrated, a polishing pad may be utilized to flatten the upper surface (BFL1-US') of the first pre-buffer layer (BFL1-1). When the polishing pad applies pressure to the upper surface (BFL1-US') of the first pre-buffer layer (BFL1-1) to cause friction, the upper surface (BFL1-US') of the first pre-buffer layer (BFL1-1) can be flattened.

[0215] A first buffer layer (BFL1) having a flattened upper surface (BFL1-US) can be formed by polishing the upper surface (BFL1-US') of the first pre-buffer layer (BFL1-1). For example, the short-range surface roughness of the first buffer layer (BFL1) may be less than 10 nm, and the long-range surface roughness may be less than 200 nm. As the first buffer layer (BFL1) having a flattened upper surface (BFL1-US) is formed through the flattening process, when the lower conductive pattern (BMP) is subsequently formed on the first buffer layer (BFL1), the lower conductive pattern (BMP) can be formed more uniformly and accurately. In addition, the possibility of defects occurring in subsequent process steps can be reduced. However, this is described as an example, and the method for manufacturing a display panel (DP) according to one embodiment of the present invention may include various process steps as long as a first buffer layer (BFL1) having a flattened upper surface (BFL1-US) can be formed, and is not limited to any one embodiment.

[0216] Referring to FIG. 11c and FIG. 11d, a lower conductive pattern (BMP) may be formed on a first buffer layer (BFL1), and a second pre-buffer layer (BFL2-1) may be formed on the lower conductive pattern (BMP) to cover the lower conductive pattern (BMP). At this time, the upper surface (BFL2-US') of the formed second pre-buffer layer (BFL2-1) may not be flat. For example, the short-range surface roughness of the upper surface (BFL2-US') of the second pre-buffer layer (BFL2-1) may be 10 nm or more, and the long-range surface roughness may be 200 nm or more.

[0217] A method for manufacturing a display panel according to one embodiment of the present invention may include a step of polishing the upper surface (BFL2-US') of the second pre-buffer layer (BFL2-1) after forming the second pre-buffer layer (BFL2-1). The step of polishing the upper surface (BFL2-US') of the second pre-buffer layer (BFL2-1) may include a Chemical Mechanical Polishing (CMP) process. A polishing solution (PT2) may be applied to the upper surface (BFL2-US') of the second pre-buffer layer (BFL2-1) to flatten the upper surface (BFL2-US').

[0218] A second buffer layer (BFL2) having a flattened upper surface (BFL2-US) can be formed by polishing the upper surface (BFL2-US') of the second pre-buffer layer (BFL2-1). For example, the short-range surface roughness of the second buffer layer (BFL2) may be less than 10 nm, and the long-range surface roughness may be less than 200 nm. As the second buffer layer (BFL2) having a flattened upper surface (BFL2-US) is formed through the flattening process, when semiconductor patterns of transistors are subsequently formed on the second buffer layer (BFL2), the semiconductor patterns can be formed more uniformly and accurately. Accordingly, degradation of the device characteristics of the transistors can be prevented. In addition, the possibility of defects occurring in subsequent process steps can be reduced. However, this is described as an example, and the method for manufacturing a display panel (DP) according to one embodiment of the present invention may include various process steps as long as a second buffer layer (BFL2) having a flattened upper surface can be formed, and is not limited to any one embodiment.

[0219] Referring to FIG. 11e, semiconductor patterns (AC1, AC2) can be formed on a buffer layer (BFL). The semiconductor patterns (AC1, AC2) can be formed by depositing or coating a semiconductor material on the buffer layer (BFL) and then patterning it into a plurality of patterns. The semiconductor patterns (AC1, AC2) can be formed in an area that overlaps with the lower conductive patterns (BMP).

[0220] Referring to FIG. 11f, a second insulating layer (20), first and second gates (GE1, GE2), and a shielding electrode (SSE) may be formed on semiconductor patterns (AC1, AC2). The second insulating layer (20) may be formed by depositing or coating an insulating material on the semiconductor patterns (AC1, AC2). Subsequently, a conductive layer may be formed by depositing or coating a conductive material on the second insulating layer (20). Subsequently, the first and second gates (GE1, GE2) and the shielding electrode (SSE) may be formed by patterning the conductive layer. At this time, a portion of the semiconductor patterns (AC1, AC2) may be formed as a source region and a drain region. Accordingly, the boundary between the source and drain regions of each of the semiconductor patterns (AC1, AC2) may be self-aligned by the gates (GE1, GE2).

[0221] Referring to FIG. 11g thereafter, a third insulating layer (30) is formed on the second gates (GE1, GE2) and the shielding electrode (SSE), and one of the connecting electrode (CNa) and upper capacitor electrodes c (or, the second upper capacitor electrode (UCE2)) may be formed. The third insulating layer (30) may be formed by depositing or coating an insulating material on the second gates (GE1, GE2) and the shielding electrode (SSE). Subsequently, a contact hole (CNT2) may be formed in the third insulating layer (30). The connecting electrode (CNa) may be formed by depositing or coating a conductive material on the third insulating layer (30) to form a conductive layer, and then patterning it. The connecting electrode (CNa) may be filled into the contact hole (CNT2) and connected to the second transistor (TR2).

[0222] Referring to FIG. 11h thereafter, a fourth insulating layer (40) is formed on the connecting electrode (CNa) and the second upper capacitor electrode (UCE2), and another one of the upper electrodes (UE) and upper capacitor electrodes (UCE1, UCE2, UCE3) (or a third upper capacitor electrode (UCE3)) may be formed. The fourth insulating layer (40) may be formed by depositing or coating an insulating material on the connecting electrode (CNa) and the second upper capacitor electrode (UCE2). Subsequently, a plurality of contact holes (CNT1-1, CNT1-2, CNT3-1, CNT3-2) may be formed in the fourth insulating layer (40). The upper electrode (UE) and the third upper capacitor electrode (UCE3) may be formed by depositing or coating a conductive material on the fourth insulating layer (40) to form a conductive layer, and then patterning. The upper electrode (UE) and the third upper capacitor electrode (UCE3) can be filled into contact holes (CNT1-1, CNT1-2, CNT3-1, CNT3-2) and connected to the first and second transistors (TR1, TR2), respectively.

[0223] Referring to FIG. 11i thereafter, a fifth insulating layer (50) and connecting electrodes (CNb, CNc) may be formed on the upper electrode (UE) and the third upper capacitor electrode (UCE3). The fifth insulating layer (50) may be formed by depositing or coating an insulating material on the upper electrode (UE) and the third upper capacitor electrode (UCE3). Subsequently, a plurality of contact holes (CNT4, CNT5) may be formed in the fifth insulating layer (50). The connecting electrodes (CNb, CNc) may be filled into the contact holes (CNT4, CNT5) and connected to the first and second transistors (TR1, TR2), respectively.

[0224] Referring to FIG. 11j, a display element layer (DP-OLED) can be formed by forming a sixth insulating layer (60) and a light-emitting element (OLED). The anode (AE) can be formed by depositing a conductive material to form a conductive layer and then patterning it. Subsequently, an insulating material layer can be formed by depositing or coating an insulating material, and then forming an opening to form the sixth insulating layer (60). Subsequently, a light-emitting layer (EML) and a cathode (CE) can be formed sequentially to form a light-emitting element (OLED).

[0225] FIGS. 12a to 12c are cross-sectional views illustrating some of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. In the following description with reference to FIGS. 12a to 12c, the same or similar reference numerals are used for configurations identical or similar to those described in FIGS. 9 to 11j, and redundant descriptions are omitted.

[0226] Referring to FIGS. 12a and 12b, a contact hole (CNT1-1) can be formed penetrating the buffer layers (BFL1, BFL2) and the second to fourth insulating layers (20, 30, 40). Subsequently, a plurality of contact holes (CNT1-2, CNT3-1) penetrating the second to fourth insulating layers (20, 30, 40) and a contact hole (CNT3-2) penetrating the third and fourth insulating layers (30, 40) can be formed. That is, a relatively deep contact hole (CNT1-1) can be formed first, and then shallow contact holes (CNT1-2, CNT3-1, CNT3-2) can be additionally formed. In this case, the depth of each of the contact holes (CNT1-1 to CNT3-2) can be controlled more precisely, thereby reducing errors that may occur during processing. In addition, process efficiency can be increased by applying different optimized processing conditions depending on the depth of each contact hole (CNT1-1 to CNT3-2).

[0227] Referring to FIG. 12c thereafter, the upper electrode (UE) and the third upper capacitor electrode (UCE3) can be formed by depositing or coating a conductive material on the fourth insulating layer (40) to form a conductive layer and then patterning. The upper electrode (UE) and the third upper capacitor electrode (UCE3) can be filled into the contact holes (CNT1-1 to CNT3-2) as described above and connected to the first and second transistors (TR1, TR2).

[0228] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the relevant technical field will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as set forth in the claims below. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0229] ED: Electronic device AE: Anode UCE: Upper capacitor electrode LCE: Lower capacitor electrode BMP: Underlying conduction pattern CPR: First capacitor CST: Second capacitor TR1: First transistor TR2: Second transistor BFL: Buffer layer

Claims

Claim 1 An electronic device comprising: a base layer; a gate line disposed on the base layer and extending along one direction; a data line insulatingly intersecting the gate line; a pixel driver connected to the gate line and the data line; and a light-emitting element disposed on the pixel driver and connected to the pixel driver, wherein the light-emitting element comprises an anode, a cathode disposed on the anode, and a light-emitting layer disposed between the anode and the cathode, and wherein the pixel driver comprises: a first transistor comprising a first semiconductor pattern and a first gate electrode overlapping the first semiconductor pattern; a second transistor comprising a second semiconductor pattern connected to the data line and spaced apart from the first semiconductor pattern and a second gate electrode overlapping the second semiconductor pattern; a first capacitor connected between the second transistor and the data line; and a second capacitor connected to the first transistor, wherein the first semiconductor pattern is disposed between the first capacitor and the second capacitor. Claim 2 An electronic device according to claim 1, wherein the first capacitor comprises a first lower capacitor electrode and a second lower capacitor electrode disposed on the first lower capacitor electrode, and the area of ​​each of the first and second lower capacitor electrodes in a plane is larger than the area of ​​the anode. Claim 3 In claim 2, the first lower capacitor electrode is an electronic device having a shape integral with the data line. Claim 4 In claim 2, the second lower capacitor electrode is an electronic device having a shape integral with the data line. Claim 5 An electronic device according to claim 2, wherein the ratio of the area of ​​each of the first and second lower capacitor electrodes to the area of ​​the anode is 1.4 or greater. Claim 6 An electronic device according to claim 1, further comprising a lower conductive pattern disposed between the first capacitor and the first transistor and a buffer layer disposed on the lower conductive pattern, wherein the lower conductive pattern overlaps with the first semiconductor pattern. Claim 7 An electronic device according to claim 6, wherein the short-range surface roughness of the buffer layer is less than 10 nm and the long-range surface roughness is less than 200 nm. Claim 8 An electronic device according to claim 1, wherein the first transistor comprises a silicon semiconductor and the second transistor comprises an oxide semiconductor. Claim 9 In claim 1, the separation distance from the first semiconductor pattern to the anode is 1.5 Electronic device below. Claim 10 An electronic device according to claim 9, further comprising an upper electrode connecting the first capacitor and the second transistor, wherein the upper electrode is disposed on the first capacitor and the second transistor. Claim 11 An electronic device according to claim 10, wherein the upper electrode comprises the same material as at least one of the electrodes constituting the second capacitor. Claim 12 An electronic device comprising: a base layer; a gate line disposed on the base layer and extending along one direction; a data line including a line portion insulatingly intersecting the gate line and a protrusion protruding from the line portion; a pixel including a pixel driver connected to the gate line and the data line and a light-emitting element disposed on the pixel driver and connected to the pixel driver, wherein the light-emitting element includes an anode, a cathode disposed on the anode, and a light-emitting layer disposed between the anode and the cathode, and wherein the pixel driver includes a first transistor including a first semiconductor pattern and a first gate electrode overlapping with the first semiconductor pattern; a second transistor including a second semiconductor pattern connected to the data line and spaced apart from the first semiconductor pattern and a second gate electrode overlapping with the second semiconductor pattern; and a capacitor electrode disposed below the first semiconductor pattern and overlapping with the protrusion in a plane, wherein the protrusion overlaps with the anode in a plane. Claim 13 In claim 12, an electronic device in which the area of ​​each of the protrusion and the capacitor electrode is larger than the area of ​​the anode. Claim 14 In claim 12, the capacitor electrode is an electronic device positioned on the upper part of the protrusion. Claim 15 In claim 12, the capacitor electrode is an electronic device positioned at the lower part of the protrusion. Claim 16 An electronic device according to claim 12, further comprising a lower conductive pattern disposed between the capacitor electrode and the first transistor and a buffer layer disposed on the lower conductive pattern, wherein the lower conductive pattern overlaps with the first semiconductor pattern. Claim 17 An electronic device according to claim 12, wherein the first transistor comprises a silicon semiconductor and the second transistor comprises an oxide semiconductor. Claim 18 An electronic device according to claim 12, further comprising an upper electrode connecting the capacitor electrode and the second transistor, wherein the upper electrode is disposed on the capacitor electrode and the second transistor. Claim 19 An electronic device comprising: a display module for displaying an image; and a processor for providing image data to the display module, wherein the display module comprises: a base layer; a gate line disposed on the base layer and extending along one direction; a data line that is insulatedly intersecting the gate line; a pixel driver connected to the gate line and the data line; and a light-emitting element disposed on the pixel driver and connected to the pixel driver, wherein the light-emitting element comprises an anode, a cathode disposed on the anode, and a light-emitting layer disposed between the anode and the cathode, and wherein the pixel driver comprises: a first transistor comprising a first semiconductor pattern and a first gate electrode overlapping the first semiconductor pattern; a second transistor comprising a second semiconductor pattern connected to the data line and spaced apart from the first semiconductor pattern and a second gate electrode overlapping the second semiconductor pattern; a first capacitor connected between the second transistor and the data line; and a second capacitor connected to the first transistor, wherein the first semiconductor pattern is disposed between the first capacitor and the second capacitor. Claim 20 An electronic device according to claim 19, wherein the first capacitor comprises a first lower capacitor electrode and a second lower capacitor electrode disposed on the first lower capacitor electrode, and the area of ​​each of the first and second lower capacitor electrodes in a plane is larger than the area of ​​the anode.

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