Deposition apparatus, method of manufacturing the deposition apparatus, and electronic device manufactured using the deposition apparatus

Abstract

The deposition apparatus includes a stage attached to one side inside the chamber and supporting a substrate, a base substrate defining first openings, an insulating film surrounding the base substrate and defining second openings corresponding to the first openings, a mask including a piezoelectric element that generates current by a piezoelectric effect and includes a first insulating layer, a metal pattern, and a second insulating layer sequentially disposed on the base substrate, and a deposition source disposed below the mask and supplying a deposition material to the substrate.

Description

Technology Field

[0001] The present invention relates to a deposition apparatus, a method for manufacturing a deposition apparatus, and a method for manufacturing an electronic device using said deposition apparatus. More specifically, the invention relates to a deposition apparatus used in the manufacture of micro OLEDs, a method for manufacturing a deposition apparatus, and a method for manufacturing an electronic device using said deposition apparatus. Background Technology

[0002] Deposition equipment is essential in the manufacturing process of OLED panels, semiconductor devices, and other precision instruments, and deposition quality is largely determined by the alignment and adhesion between the mask and the substrate.

[0003] In conventional deposition processes, if the mask and substrate were not in close contact, there was a high likelihood of reduced precision in the deposited pattern or non-uniform deposition. This situation was particularly pronounced with large-area substrates, causing difficulties in productivity and quality control. While existing technologies provided various structural approaches to align and secure the mask and substrate, they had limitations in monitoring or controlling the degree of contact in real time.

[0004] To overcome these limitations, a piezoelectric element is placed on the mask to detect the adhesion status between the mask and the substrate in real time. The piezoelectric element converts the interaction between the substrate and the mask into an electrical signal, thereby verifying adhesion; this significantly improves the precision of the deposition process and reduces the defect rate. The problem to be solved

[0005] One objective of the present invention is to provide a deposition apparatus that minimizes deposition distortion.

[0006] Another objective of the present invention is to provide a method for manufacturing the deposition apparatus.

[0007] Another objective of the present invention is to provide an electronic device manufactured using the above deposition apparatus.

[0008] However, the objectives of the present invention are not limited to the objectives described above and may be extended in various ways without departing from the spirit and scope of the invention. means of solving the problem

[0009] To achieve one objective of the present invention as described above, a deposition apparatus according to an embodiment of the present invention may include a stage attached to one side inside a chamber and supporting a substrate, a base substrate defining first openings, an insulating film surrounding the base substrate and defining second openings corresponding to the first openings, a mask including a piezoelectric element that generates current by a piezoelectric effect and includes a first insulating layer, a metal pattern, and a second insulating layer sequentially disposed on the base substrate, and a deposition source disposed below the mask and supplying a deposition material to the substrate.

[0010] In one embodiment, the piezoelectric element may have a semicircular shape that is convex in the direction toward the stage on a cross-section.

[0011] In one embodiment, the shortest distance between the upper surface of the base substrate and the center of the lower surface of the second insulating layer may be about 7 µm or less.

[0012] In one embodiment, the insulating film may include a first insulating film in direct contact with the base substrate and a second insulating film surrounding the first insulating film.

[0013] In one embodiment, the first insulating film may comprise silicon oxide, and the second insulating film may comprise silicon nitride.

[0014] In one embodiment, the first insulating layer of the piezoelectric element may include the same material as the first insulating film, and the second insulating layer of the piezoelectric element may include the same material as the second insulating film.

[0015] In one embodiment, the thickness of the first insulating layer of the piezoelectric element may be about 0.1 µm or more and about 1 µm or less.

[0016] In one embodiment, the thickness of the base substrate may be about 725 µm or more and about 775 µm or less.

[0017] In one embodiment, the base substrate may further include a third opening defined corresponding to the piezoelectric element.

[0018] In one embodiment, a plurality of piezoelectric elements may be disposed on the base substrate.

[0019] In one embodiment, the metal pattern of the piezoelectric element may include one selected from the group consisting of aluminum and chromium.

[0020] In one embodiment, the deposition device may further include a sensing unit that is electrically connected to the piezoelectric element and detects a current applied from the piezoelectric element.

[0021] To achieve another objective of the present invention as described above, a method for manufacturing a deposition apparatus according to an embodiment of the present invention may include the steps of: forming a first insulating film surrounding a base substrate; forming a metal layer on the upper surface of the first insulating film; forming a second insulating film surrounding the first insulating film and the metal layer; forming second openings on the upper surface of the second insulating film; etching the metal layer and the first insulating film to form a piezoelectric element comprising a first insulating layer, a metal pattern, and a second insulating layer; and forming first openings corresponding to the second openings on the base substrate.

[0022] In one embodiment, in the step of forming the first openings corresponding to the second openings in the base substrate, the step of forming a third opening corresponding to the piezoelectric element in the base substrate may be performed simultaneously.

[0023] In one embodiment, after the step of forming the third opening, the piezoelectric element may have a convex semicircular shape in cross-section.

[0024] In one embodiment, the step of forming second openings on the upper surface of the second insulating film can be performed through a dry etching method.

[0025] In one embodiment, the step of forming the first openings corresponding to the second openings in the base substrate can be performed through a wet etching method.

[0026] In one embodiment, in the step of forming a first insulating film surrounding a base substrate, the first insulating film may be formed to be about 0.1 µm or more and about 1 µm or less.

[0027] In one embodiment, in the step of forming the piezoelectric element, a plurality of the piezoelectric elements may be formed on the base substrate.

[0028] To achieve another objective of the present invention as described above, an electronic device according to an embodiment of the present invention includes a display device and a processor for driving the display device, and the display device It can be manufactured by a deposition apparatus comprising: a stage attached to one side inside a chamber and supporting a substrate; a base substrate defining first openings; an insulating film surrounding the base substrate and defining second openings corresponding to the first openings; a mask disposed on the base substrate and comprising a piezoelectric element including a first insulating layer, a metal pattern, and a second insulating layer, which generates current by a piezoelectric effect; and a deposition source disposed below the mask and supplying a deposition material to the substrate. Effects of the invention

[0029] A deposition apparatus according to embodiments of the present invention may include a stage attached to one side inside a chamber and supporting a substrate, a base substrate defining first openings, an insulating film surrounding the base substrate and defining second openings corresponding to the first openings, a mask including a piezoelectric element that generates current by a piezoelectric effect and includes a first insulating layer, a metal pattern, and a second insulating layer sequentially disposed on the base substrate, and a deposition source disposed below the mask and supplying a deposition material to the substrate.

[0030] Accordingly, as the piezoelectric element and the sensing unit are positioned in the deposition apparatus, the piezoelectric element can increase the precision of the alignment of the mask and monitor the contact state between the mask and the substrate in real time. Consequently, the present invention can provide higher reliability and accuracy than existing technologies in manufacturing display devices, etc., by utilizing the inherent characteristics of the piezoelectric element.

[0031] However, the effects of the present invention are not limited to the above effects, and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0032] FIG. 1 is a cross-sectional view showing a deposition apparatus according to one embodiment of the present invention. FIG. 2 is a cross-sectional view showing an enlarged embodiment of the mask and stage illustrated in FIG. 1. Figure 3 is a cross-sectional view showing an enlarged view of area A of Figure 2. Figure 4 is a cross-sectional view showing an enlarged view of region B of Figure 2. FIGS. 5 to 14 are cross-sectional views illustrating a method for manufacturing a mask shown in FIG. 2. FIG. 15 is a block diagram showing an electronic device according to one embodiment of the present invention. FIG. 16 is a schematic diagram of an electronic device according to various embodiments of FIG. 15. Specific details for implementing the invention

[0033] With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are provided merely for the purpose of explaining the embodiments of the present invention, and the embodiments of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in the text.

[0034] The present invention is capable of various modifications and may take various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the invention to the specific disclosed forms, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0035] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component.

[0036] When it is stated that one component is "connected" to another component, it should be understood that it may be directly connected to or joined to that other component, or that there may be other components in between. Other expressions describing the relationship between components, such as "between" and "exactly between" or "adjacent to" and "directly adjacent to," should be interpreted in the same way.

[0037] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to specify the existence of the described features, numbers, steps, actions, components, parts, or combinations thereof, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0038] Terms such as “below,” “lower,” “below,” “under,” “above,” “upper,” “top,” and “on top” are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0039] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0040] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted.

[0041] In this specification, a plane may be defined by a first direction (D1) and a second direction (D2) that intersects the first direction (D1). For example, the second direction (D2) may be perpendicular to the first direction (D1). Additionally, a third direction (D3) may be a normal direction to the plane. That is, the third direction (D3) may be perpendicular to the plane formed by the first direction (D1) and the second direction (D2).

[0042] FIG. 1 is a cross-sectional view showing a deposition apparatus according to one embodiment of the present invention.

[0043] Referring to FIG. 1, the deposition apparatus (DPA) may include a chamber (CH), a stage (ST), an electrostatic chuck (ESC), a deposition source (DS), a support member (SP), a mask (MK), and a sensing unit (SS).

[0044] The chamber (CB) can protect substrates (SUB), etc., by providing a sealed environment from the outside, and can provide a space where substrates (SUB) are deposited. For example, the chamber (CB) may have a vacuum pressure (about 10 Torr to about 200 Torr) lower than atmospheric pressure (about 1 atm or about 760 Torr). However, embodiments of the present invention are not limited thereto.

[0045] The chamber (CB) may be provided with at least one gate (GT). The chamber (CH) may be opened or closed by the gate (GT). The substrate (SUB) may enter or exit through the gate (GT) provided in the chamber (CH).

[0046] The stage (ST) may be positioned on one side (e.g., the upper side) of the chamber (CH). The stage (ST) may be movable up and down or left and right. For example, the stage (ST) may position the substrate (SUB) on the mask (MK).

[0047] An electrostatic inducer, such as the electrostatic chuck (ESC), may be disposed on the stage (ST). As voltage is applied to the electrodes of the electrostatic chuck (ESC), an electrostatic force may be induced. For example, the electrostatic chuck (ESC) may support the substrate (SUB) by the electrostatic force. That is, the electrostatic chuck (ESC) may attach the substrate (SUB) to the stage (ST) while the deposition process is being carried out within the deposition apparatus (DPA). However, the electrostatic chuck (ESC) may be omitted. That is, the stage (ST) and the substrate (SUB) may be directly attached by a separate fixing member, etc.

[0048] The deposition source (DS) may include a deposition material. The deposition material is a material capable of sublimation or vaporization and may include one or more of inorganic or organic materials. The deposition material evaporated from the deposition source (DS) may pass through the grid member (GP) and the mask (MK) and be deposited on the substrate (SUB).

[0049] The support member (SP) may be placed on the deposition source (DS). The support member (SP) may support the mask (MK). The support member (SP) may be placed outside the path of the deposition material supplied from the deposition source (DS) to the substrate (SUB).

[0050] The mask (MK) may be placed on the support member (SP). The mask (MK) may define a plurality of openings so that the deposition material evaporated from the deposition source (DS) can be deposited at predetermined locations on the substrate (SUB). The openings defined in the mask (MK) will be described later with reference to FIG. 2.

[0051] A piezoelectric element (PR) may be disposed on the mask (MK). The piezoelectric element (PR) can convert physical pressure transmitted from the outside into an electrical signal. For example, when the mask (MK) comes into contact with the substrate (SUB), etc., disposed on the stage (ST), it is possible to determine whether the mask (MK) has come into contact with the substrate (SUB) due to a change in pressure transmitted to the piezoelectric element (PR).

[0052] A sensing unit (SS) capable of detecting an electrical signal generated from the piezoelectric element (PR) may be disposed in the deposition apparatus (DPA). A user of the deposition apparatus (DPA) can check the sensing unit (SS) to determine whether the mask (MK) has come into contact with the substrate (SUB). Although FIG. 1 illustrates the sensing unit (SS) being disposed inside the deposition apparatus (DPA), embodiments of the present invention are not limited thereto. The sensing unit (SS) may also be disposed outside the deposition apparatus (DPA).

[0053] As the piezoelectric element (PR) and the sensing unit (SS) are placed in the deposition apparatus (DPA), the piezoelectric element (PR) can increase the precision of alignment of the mask (MK) and monitor the contact state between the mask (MK) and the substrate (SUB) in real time. Consequently, the present invention can provide higher reliability and accuracy than existing technologies in manufacturing display devices, etc. by utilizing the unique characteristics of the piezoelectric element (PR). The piezoelectric element (PR) will be described later with reference to FIGS. 2 and FIGS. 3.

[0054] FIG. 2 is a cross-sectional view showing an enlarged embodiment of the mask and stage illustrated in FIG. 1.

[0055] Referring to FIGS. 1 and FIGS. 2, the mask (MK) may include a base substrate (SUB), an insulating film (IM), and a piezoelectric element (PR).

[0056] The base substrate (BL) may be located inside the mask (MK). The base substrate (BL) may include metals, semiconductor materials, ceramics, polymers, etc. For example, examples of the metals included in the base substrate (BL) may include iron (Fe), platinum (Pt), gold (Au), silver (Ag), indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), zinc (Zn), silicon (Si), etc. Examples of semiconductor materials included in the base substrate (SUB) may include silicon (Si), etc. These may be used alone or in combination with each other. However, embodiments of the present invention are not limited thereto.

[0057] In one embodiment, the thickness (TH-BL) of the base substrate (SUB) may be approximately 700 µm or more and approximately 800 µm or less. Preferably, the thickness (TH-BL) of the base substrate (SUB) may be approximately 725 µm or more and approximately 775 µm or less. If the thickness (TH-BL) of the base substrate (SUB) is smaller than the range described above, the durability of the base substrate (SUB) is weakened, and the mask (MK) may bend during the deposition process. If the thickness (TH-BL) of the base substrate (SUB) is larger than the range described above, the deposition material may be deposited on the inner surface of the base substrate during the deposition process. That is, by satisfying the range described above for the thickness (TH-BL) of the substrate, the deposition material supplied from the deposition source (DS) can be less affected by the inner surface of the base substrate (SUB) and can proceed in the third direction (D3).

[0058] The insulating film (IM) may be positioned to surround the base substrate (BL). The insulating film (IM) can prevent the base substrate (BL) and the substrate (SUB) from coming into direct contact. That is, the insulating film (IM) can block the flow of current between the base substrate (BL) and the substrate (SUB) by preventing the base substrate (BL) and the substrate (SUB) from coming into direct contact.

[0059] The insulating film (IM) may include a silicon oxide film, a silicon nitride film, a metal oxide film, etc. For example, the insulating film (IM) may be silicon oxide (SiO₂). x ), silicon nitride (SiN x- ), silicon nitride (SiO₂) x N yIt may include metal oxides, etc. These may be used alone or in combination with each other. However, the embodiments of the present invention are not limited thereto. The materials included in the insulating film (IM) will be described later with reference to FIGS. 3 and FIGS. 4.

[0060] In one embodiment, first openings (OP1) may be defined in the base substrate (BL). Second openings (OP2) may be defined in the insulating film (IM). The second openings (OP2) may include second-1 openings (OP2-1), second-2 openings (OP2-2), second-3 openings (OP2-3), and second-4 openings (OP2-4). For example, the second-1 openings (OP2-1) and the second-2 openings (OP2-2) may each be located on the upper surface of the base substrate (SUB) in cross-section. The second-3 openings (OP2-3) and the second-4 openings (OP2-4) may each be located on the lower surface of the base substrate (SUB) in cross-section.

[0061] In one embodiment, the first openings (OP1), the second-first openings (OP2-1), and the second-third openings (OP2-3) may overlap on a plane. That is, the first openings (OP1), the second-first openings (OP2-1), and the second-third openings (OP2-3) may be openings defined so that the deposition material can be deposited at a predetermined location on the substrate (SUB).

[0062] In one embodiment, two or more of the second-1 openings (OP2-1) may correspond to each of the first openings (OP1). That is, the deposition material passing through the first openings (OP1) may pass through a plurality of the second-1 openings (OP2-1). That is, the second-1 openings (OP2-1) may form any pattern. Accordingly, the deposition material may be deposited on the substrate (SUB) according to any pattern formed by the second-1 openings (OP2-1).

[0063] In the base substrate (SUB), third openings (OP3) spaced apart from the first openings (OP1) may be further defined. Each of the third openings (OP3) may be defined between the first openings (OP1). The cross-sectional shape of each of the third openings (OP3) may be substantially the same as the cross-sectional shape of each of the first openings (OP1). For example, the cross-sectional shapes of the first openings (OP1) and the third openings (OP3) may have a trapezoidal shape.

[0064] In one embodiment, each of the third openings (OP3) may correspond one-to-one with the piezoelectric element (PR) placed on the mask (MK). That is, each of the third openings (OP3) may overlap with the piezoelectric element (PR) in a plane. Additionally, each of the third openings (OP3) may overlap with the second-2 openings (OP2-2) and the second-4 openings (OP2-4) in a plane.

[0065] The piezoelectric element (PR) may have a shape that is convex in the third direction (D3) on a cross-section. For example, the piezoelectric element (PR) may have a semicircular shape that is convex in the direction in which the substrate (SUB) is located. Accordingly, when the piezoelectric element (PR) and the substrate (SUB) come into contact, the piezoelectric element (PR) can sensitively detect whether the mask (MK) and the substrate (SUB) have come into contact. That is, by having a shape that is convex in the third direction (D3) rather than a flat shape, the sensitivity of the piezoelectric element (PR) can be increased. However, the cross-sectional shape of the piezoelectric element (PR) is not limited to this.

[0066] In one embodiment, a plurality of piezoelectric elements (PR) may be disposed on the base substrate (SUB). For example, a plurality of piezoelectric elements (PR) may be disposed in a one-to-one correspondence with the third openings (OP3) defined on the base substrate (SUB).

[0067] Figure 3 is a cross-sectional view showing an enlarged view of area A of Figure 2.

[0068] Referring to FIGS. 1 to 3, the piezoelectric element (PR) may include a first insulating layer (IL1), a metal pattern (MP), and a second insulating layer (IL2). The insulating film (IM) may include a first insulating film (IM1) and a second insulating film (IM2). Additionally, a metal layer (ML) may be disposed between the first insulating film (IM1) and the second insulating film (IM2) in cross-section.

[0069] The first insulating layer (IL1) may be disposed on the base substrate (SUB) in a planar overlap with the third openings (OP3). The first insulating layer (IL1) may have a convex shape in the third direction (D3). For example, the first insulating layer (IL1) may have a semicircular shape in cross-section.

[0070] In one embodiment, the first insulating layer (IL1) is silicon oxide (SiO₂). x It may include ). For example, the first insulating layer (IL1) may include SiO2. The first insulating layer (IL1) may include silicon oxide (SiO2 x As it includes ), the first insulating layer (IL1) may have a convex shape in the third direction (D3) due to the tensile strength acting on the first insulating layer.

[0071] In one embodiment, the thickness (TH-IL1) of the first insulating layer (IL1) in the third direction (D3) may be about 1 µm or less. Preferably, the thickness (TH-IL1) of the first insulating layer (IL1) in the third direction (D3) may be about 0.1 µm or more and about 1 µm or less. If the thickness (TH-IL1) of the first insulating layer (IL1) is greater than the range described above, the first insulating layer (IL1) may expand excessively in the third direction (D3), and the piezoelectric element (PR) may be damaged.

[0072] In one embodiment, the separation distance (DT) formed between the center of the lower surface of the first insulating layer (IL1) and the upper surface of the base substrate (SUB) may be about 10 μm or less. The separation distance (DT) is the distance measured between the center of the lower surface of the first insulating layer (IL1) and the upper surface of the base substrate (SUB) in a direction parallel to the third direction (D3). Preferably, the separation distance (DT) formed between the center of the lower surface of the first insulating layer (IL1) and the upper surface of the base substrate (SUB) may be about 7 μm or less.

[0073] The metal pattern (MP) may be disposed on the first insulating layer (IL1). Specifically, the metal pattern (MP) may be disposed on the first insulating layer (IL1) along the profile of the first insulating layer (IL1). Accordingly, the cross-sectional shape of the metal pattern (MP) may have a semicircular shape convex in the third direction (D3).

[0074] In one embodiment, the metal pattern (MP) may include aluminum or chromium. These may be used alone or in combination with each other. However, the embodiments of the present invention are not limited thereto. The metal pattern (MP) may further include ceramics, polymers, carbon nanotubes, etc.

[0075] The second insulating layer (IL2) may be disposed on the metal pattern (MP). Specifically, the second insulating layer (IL2) may be disposed on the metal pattern (MP) along the profile of the metal pattern (MP). Accordingly, the cross-sectional shape of the second insulating layer (IL2) may have a semicircular shape convex in the third direction (D3).

[0076] In one embodiment, the second insulating layer (IL2) is silicon oxide (SiN x It may include ). For example, the second insulating layer (IL2) may include SiN2. The second insulating layer (IL2) may include silicon oxide (SiN x By including ), the second insulating layer (IL2) can stably wrap the metal pattern (MP) due to the compressive stress acting on the second insulating layer. As a result, the piezoelectric element (PR) can have a semicircular shape in cross-section.

[0077] The first insulating film (IM1) is disposed on the base substrate (SUB) and may be in direct contact with the base substrate (SUB). The first insulating film (IM1) may contain the same material as the first insulating layer (IL1). That is, the first insulating film (IM1) may be formed in the same process as the first insulating layer (IL1). Accordingly, the thickness of the first insulating film (IM1) in the third direction (D3) may also be substantially the same as the thickness (TH-IL1) of the first insulating layer (IL1).

[0078] The metal layer (ML) may be disposed on the first insulating film (IM1). The metal layer (ML) may comprise the same material as the metal pattern (MP). That is, the metal layer (ML) may be formed in the same process as the metal pattern. Accordingly, the thickness of the metal layer (ML) may be substantially the same as the thickness of the metal pattern (MP).

[0079] The second insulating film (IM2) may be disposed on the metal pattern (MP). The second insulating film (IM2) may contain the same material as the second insulating layer (IL2). That is, the second insulating film (IM2) may be formed in the same process as the second insulating layer (IL2). Accordingly, the thickness of the second insulating film (IM2) in the third direction (D3) may also be substantially the same as the thickness of the second insulating layer (IL2).

[0080] FIG. 4 is a cross-sectional view showing an enlarged view of region B of FIG. 2. Specifically, FIG. 4 may be substantially identical to FIG. 3, except for the piezoelectric element (PR). Therefore, overlapping content may be omitted or simplified.

[0081] Referring to FIGS. 1 to 4, the first openings (OP1) may be defined in the base substrate (SUB) of the mask (MK). On the upper surface of the first insulating film (IM1), the metal layer (ML), and the second insulating film (IM2), the second-first openings (OP2-1) that penetrate the first insulating film (IM1), the metal layer (ML), and the second insulating film (IM2) in the third direction (D3) may be defined. On the lower surface of the first insulating film (IM1) and the second insulating film (IM2), the second-third openings (OP2-3) that penetrate the first insulating film (IM1) and the second insulating film (IM2) in the third direction (D3) may be defined. The first openings (OP1), the second-first openings (OP2-1), and the second-third openings (OP2-3) can be superimposed on a plane. Accordingly, the deposition material can sequentially pass through the second-third openings (OP2-3), the first openings (OP1), and the second-first openings (OP2-1) along the third direction (D3).

[0082] FIGS. 5 to 14 are cross-sectional views illustrating a method for manufacturing a mask shown in FIG. 2.

[0083] Referring to FIGS. 5 and 6, the first insulating film (IM1) may be formed to surround the base substrate (SUB). The first insulating film (IM1) may be formed on the base substrate (SUB) with a uniform thickness. For example, the first insulating film (IM1) may be silicon oxide (SiO₂). x It may include ). However, embodiments of the present invention are not limited thereto.

[0084] Referring further to FIG. 7, the metal layer (ML) may be formed on one surface of the first insulating film (IM1). Specifically, the metal layer (ML) may be formed on one surface of the first insulating film (IM1) facing the third direction (D3). The metal layer (ML) may be formed on the first insulating film (IM1) with a uniform thickness. For example, the metal layer (ML) may include aluminum or chromium. However, embodiments of the present invention are not limited thereto.

[0085] Referring further to FIG. 8, the second insulating film (IM2) may be formed to surround the first insulating film (IM1) and the metal layer (ML). Specifically, the second insulating film (IM2) may surround the side and bottom surfaces of the first insulating film (IM1) and the top surface of the metal layer (ML). Accordingly, the metal layer (ML) may be disposed between the first insulating film (IM1) and the second insulating film (IM2) in cross-section. For example, the second insulating film (IM2) may include silicon nitride (SiNx). However, embodiments of the present invention are not limited thereto.

[0086] Referring further to FIG. 9, an etching process may be performed on the upper surface of the second insulating film (IM2). As the etching process is performed on the upper surface of the second insulating film (IM2), the second-1 openings (OP2-1) and the second-2 openings (OP2-2) may be formed in the second insulating film (IM2). The pattern of the second-1 openings (OP2-1) may be formed according to the pattern of the deposition material deposited on the substrate (e.g., the substrate (SUB) of FIG. 1). That is, the pattern of the second-1 openings (OP2-1) may be openings that control the deposition position of the mask (e.g., the mask (MK) of FIG. 2). Each of the second-1 openings (OP2-1) and the second-2 openings (OP2-2) may expose the upper surface of the metal layer (ML).

[0087] In one embodiment, the etching process for removing the upper surface of the second insulating film (IM2) to form the second-1 openings (OP2-1) and the second-2 openings (OP2-2) may be a dry etching process. As the etching process for forming the second-1 openings (OP2-1) and the second-2 openings (OP2-2) is performed by a dry etching process, the patterns of the second-1 openings (OP2-1) and the second-2 openings (OP2-2) can be formed precisely. However, embodiments of the present invention are not limited thereto.

[0088] Referring further to FIG. 10, the second-2 openings (OP2-2) may be further etched along the opposite direction of the third direction (D3). Specifically, the metal layer (ML) and the first insulating film (IM1) exposed by the second-2 openings (OP2-2) may be sequentially etched so that the upper surface of the base substrate (SUB) is exposed. As the etching process is performed on the second-2 openings (OP2-2) and the upper surface of the base substrate (SUB) is exposed, the first insulating film (IM1) may be formed into the first insulating layer (IL1), the metal layer (ML) may be formed into the metal pattern (MP), and the second insulating film (IM2) may be formed into the second insulating layer (IL2). That is, the above-mentioned second-2 openings (OP2-2) may be further etched to form the piezoelectric element (PR) comprising the first insulating layer (IL1), the metal pattern (MP), and the second insulating layer (IL2).

[0089] Referring further to FIG. 11, the second-third openings (OP2-3) and the second-fourth openings (OP2-4) may be formed on the lower surface of the second insulating film (IM2). The second-third openings (OP2-3) and the second-fourth openings (OP2-4) may be formed by etching a portion of the second insulating film (IM2) and exposing the lower surface of the first insulating film (IM1). For example, the second-third openings (OP2-3) may overlap in a plane with the second-first openings (OP2-1), and the second-fourth openings (OP2-4) may overlap in a plane with the piezoelectric element (PR).

[0090] Referring further to FIG. 12, an etching process may be further performed on the second-third openings (OP2-3) and the second-fourth openings (OP2-4). That is, an etching process may be further performed on the metal layer (ML) in the third direction (D3) to form openings in the first insulating film (IM1) and the base substrate (SUB). For example, an etching process may be further performed along the second-third openings (OP2-3) to form the first openings (OP1) in the base substrate (SUB). An etching process may be further performed along the second-fourth openings (OP2-4) to form the third openings (OP3) in the base substrate (SUB). The above 2-3 openings (OP2-3) can overlap in a plane with the above 2-1 openings (OP2-1), and the above 2-4 openings (OP2-4) can overlap in a plane with the above piezoelectric element (PR).

[0091] In one embodiment, the etching process for etching the first insulating film (IM1) and the base substrate (SUB) may be a wet etching process. However, the embodiments of the present invention are not limited thereto.

[0092] Referring further to FIG. 13, an etching process may be further performed on the second-1 openings (OP2-1). Specifically, an etching process is performed on the metal layer (ML) and the first insulating layer (IM1) whose upper surfaces are exposed by the second-1 openings (OP2-1), so that the second-1 openings (OP2-1) can penetrate the metal layer (ML) and the second-1 insulating layer (IL). Accordingly, the second-1 openings (OP2-1), the first openings (OP1), and the second-3 openings (OP2-3) can be connected along a third direction (D3). Consequently, as shown in FIG. 13, the deposition material can be deposited on the substrate (e.g., the substrate (SUB) of FIG. 1) by sequentially passing through the second-third openings (OP2-3), the first openings (OP1), and the second-fourth openings (OP2-4).

[0093] Referring further to FIG. 14, the lower surface of the base substrate (SUB) and the first insulating layer (IL1) may not come into contact due to the third openings (OP3). The first insulating layer (IL1) comprises silicon oxide, and the first insulating layer (IL1) may be convex in the third direction (D3) due to the tensile strength of the first insulating layer (IL1) comprising silicon oxide. That is, the first insulating layer (IL1) that does not come into contact with the base substrate (SUB) due to the third openings (OP3) may be convex in the third direction (D3). Accordingly, the piezoelectric element (PR) may be formed in a semicircular shape that is convex in the third direction (D3) on a cross-section.

[0094] FIG. 15 is a block diagram showing an electronic device according to one embodiment of the present invention.

[0095] Referring to FIG. 2 and FIG. 15, the display device (DD) according to the embodiments can be applied to various electronic devices (10). The electronic device (10) according to one embodiment includes the display device (DD) described above and may further include a module or device having additional functions other than the display device (DD).

[0096] The electronic device (10) may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0097] The above processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0098] Data information necessary for the operation of the processor (12) or the display module (11) may be stored in the memory (13). When the processor (12) executes an application stored in the memory (13), a video data signal and / or an input control signal may be transmitted to the display module (11), and the display module (11) may process the received signal and output video information through a display screen.

[0099] The power module (14) can convert power supplied by a power supply module, such as a power adapter or a battery device. Specifically, the power module (14) may include a power conversion module that generates power necessary for the operation of the electronic device (10).

[0100] At least one of each component of the electronic device (10) described above may be included in a display device according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, the display device (DD) may include the display module (11), and the processor (12), the memory (13), and the power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device (DD).

[0101] FIG. 16 is a schematic diagram of an electronic device according to various embodiments of FIG. 15.

[0102] Referring to FIGS. 15 and 16, various electronic devices (10) to which the display device (DD) according to embodiments is applied may include image display electronic devices such as a smartphone (10_1a), a tablet PC (10_1b), a laptop (10_1c), a TV (10_1d), and a desk monitor (10_1e). In addition, they may include wearable electronic devices including display modules such as smart glasses (10_2a), a head-mounted display (10_2b), and a smart watch (10_2c), and automotive electronic devices (10_3) including display modules such as a Center Information Display (CID) and a room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0103] However, this is exemplary, and the electronic device (10) according to the embodiments of the present invention is not limited thereto. For example, the electronic device (10) may be implemented as a mobile phone, video phone, smart pad, smart watch, tablet PC, vehicle display, computer monitor, laptop, head-mounted display device, etc. Additionally, the electronic device (10) may be a television, a monitor, a laptop computer, or a tablet. Additionally, the electronic device (10) may be a vehicle. Industrial applicability

[0104] The present invention may be applied to display devices and electronic devices including the same. For example, the present invention may be applied to high-resolution smartphones, mobile phones, smartpads, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer monitors, laptops, etc.

[0105] Although the present invention has been described above with reference to exemplary embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims. Explanation of the symbols

[0106] DPA: Deposition device CH: Chamber GT: Gate ST: Stage ESC: Electrostatic Chuck SUB: Substrate MK: Mask PR: Piezoelectric element SP: Support member DS: Deposition source SS: Detector BL: Base board IM: Insulating film OP1, OP2, OP3, OP4: 1st to 4th openings

Claims

Claim 1 A stage attached to one side inside the chamber and supporting a substrate; A base substrate defining first openings; An insulating film that surrounds the base substrate and defines second openings corresponding to the first openings; and A deposition apparatus comprising: a mask including a piezoelectric element that generates an electric current by a piezoelectric effect and includes a first insulating layer, a metal pattern, and a second insulating layer sequentially disposed on the base substrate; and a deposition source disposed below the mask and supplying a deposition material to the substrate. Claim 2 A deposition apparatus according to claim 1, characterized in that the piezoelectric element has a semicircular shape that is convex in a direction toward the stage on a cross-section. Claim 3 A deposition apparatus according to claim 1, characterized in that the shortest distance among the distances formed by the upper surface of the base substrate and the center of the lower surface of the second insulating layer is 7 µm or less. Claim 4 A deposition apparatus according to claim 1, wherein the insulating film comprises a first insulating film in direct contact with the base substrate; and a second insulating film surrounding the first insulating film. Claim 5 A deposition apparatus according to claim 4, wherein the first insulating film comprises silicon oxide and the second insulating film comprises silicon nitride. Claim 6 A deposition apparatus according to claim 5, wherein the first insulating layer of the piezoelectric element comprises the same material as the first insulating film, and the second insulating layer of the piezoelectric element comprises the same material as the second insulating film. Claim 7 A deposition apparatus according to claim 1, characterized in that the thickness of the first insulating layer of the piezoelectric element is 0.1 µm or more and 1 µm or less. Claim 8 A deposition apparatus according to claim 1, characterized in that the thickness of the base substrate is 725 µm or more and 775 µm or less. Claim 9 A deposition apparatus according to claim 1, wherein the base substrate further comprises a third opening defined corresponding to the piezoelectric element. Claim 10 A deposition apparatus according to claim 1, characterized in that a plurality of piezoelectric elements are arranged on the base substrate. Claim 11 A deposition apparatus according to claim 1, wherein the metal pattern of the piezoelectric element comprises one selected from the group consisting of aluminum and chromium. Claim 12 A deposition apparatus according to claim 1, further comprising a sensing unit electrically connected to the piezoelectric element and detecting a current applied from the piezoelectric element. Claim 13 A method for manufacturing a deposition apparatus comprising: a step of forming a first insulating film surrounding a base substrate; a step of forming a metal layer on the upper surface of the first insulating film; a step of forming a second insulating film surrounding the first insulating film and the metal layer; a step of forming second openings on the upper surface of the second insulating film; a step of etching the metal layer and the first insulating film to form a piezoelectric element comprising a first insulating layer, a metal pattern, and a second insulating layer; and a step of forming first openings corresponding to the second openings in the base substrate. Claim 14 A method for manufacturing a deposition apparatus according to claim 13, characterized in that, in the step of forming the first openings corresponding to the second openings in the base substrate, the step of forming the third opening corresponding to the piezoelectric element in the base substrate is performed simultaneously. Claim 15 A method for manufacturing a deposition apparatus according to claim 14, characterized in that, after the step of forming the third opening, the piezoelectric element has a convex semicircular shape in cross-section. Claim 16 A method for manufacturing a deposition apparatus according to claim 13, wherein the step of forming second openings on the upper surface of the second insulating film is performed through a dry etching method. Claim 17 A method for manufacturing a deposition apparatus according to claim 13, characterized in that the step of forming the first openings corresponding to the second openings in the base substrate is performed through a wet etching method. Claim 18 A method for manufacturing a deposition apparatus according to claim 13, characterized in that, in the step of forming a first insulating film surrounding a base substrate, the first insulating film is formed to be 0.1 µm or more and 1 µm or less. Claim 19 A method for manufacturing a deposition apparatus according to claim 13, wherein, in the step of forming the piezoelectric element, a plurality of the piezoelectric elements are formed on the base substrate. Claim 20 A display device; and a processor for driving the display device, wherein the display device A stage attached to one side inside the chamber and supporting a substrate; A base substrate defining first openings; An insulating film that surrounds the base substrate and defines second openings corresponding to the first openings; and A mask comprising a piezoelectric element disposed on the base substrate, generating an electric current by a piezoelectric effect, and including a first insulating layer, a metal pattern, and a second insulating layer; and An electronic device manufactured by a deposition apparatus comprising a deposition source that is positioned below the above mask and supplies a deposition material to the substrate.

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