Semiconductor package
Patent Information
- Application Number
- KR1020250023885
- Authority / Receiving Office
- KR · KR
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2026-09-02
Smart Images
Figure P1020250023885_ABST
Abstract
Description
Technology Field
[0001] The present invention relates to a semiconductor package, and more specifically, to a semiconductor package including an EMI shielding film. Background Technology
[0002] Recently, as the chip size of micro-devices decreases and the number of I / O terminals increases due to the miniaturization of process technology and the diversification of functions, the pitch of the electrode connection is becoming increasingly finer; furthermore, as the convergence of various functions accelerates, system-level packaging technology that integrates multiple devices within a single package is emerging.
[0003] However, as the operating speed of electronic components increases and various functions are added, electromagnetic interference (EMI) between components may occur in system-level packaging technology, and research to improve this is ongoing. The problem to be solved
[0004] The problem that the technical concept of the present invention aims to solve is to provide a semiconductor package with an enhanced electromagnetic interference blocking effect between components.
[0005] Furthermore, the problems that the technical concept of the present invention aims to solve are not limited to those mentioned above, and other problems can be clearly understood by a person skilled in the art from the description below. means of solving the problem
[0006] To achieve the technical problem, the present invention provides the following semiconductor package.
[0007] A semiconductor package according to the present invention comprises: a package substrate including a wiring pattern; an interposer substrate located on the package substrate and including a body, a through electrode penetrating the body, a redistribution pattern connected to the through electrode, a redistribution insulating layer covering at least a portion of the redistribution pattern, and an interposer substrate pad; a first chip on the interposer substrate; a second chip spaced horizontally from the first chip on the interposer substrate; and a shielding film covering an exposed surface of the first chip and an exposed surface of the second chip; wherein the through electrode includes a ground through electrode, the redistribution pattern includes a ground redistribution pattern, the interposer substrate pad includes a ground interposer substrate pad, and the shielding film is in contact with the ground interposer substrate pad.
[0008] A semiconductor package according to the present invention comprises: a package substrate including a first wiring pattern and a second wiring pattern; a first external connection terminal and a second external connection terminal located on a lower surface of the package substrate; an interposer substrate located on an upper surface of the package substrate and comprising a body, a first through-electrode penetrating the body and a second through-electrode, a first redistribution pattern electrically connected to the first through-electrode, a second redistribution pattern electrically connected to the second through-electrode, a redistribution insulating layer, a first interposer substrate pad connected to the first redistribution pattern on the redistribution insulating layer, and a second interposer substrate pad connected to the second redistribution pattern on the redistribution insulating layer; a first substrate connection bump and a second substrate connection bump located between the package substrate and the interposer substrate; a first chip on the interposer substrate; and a second chip spaced horizontally apart from the first chip on the interposer substrate. and a shielding film covering the upper surface of the interposer substrate, the upper surface and side of the first chip, and the upper surface and side of the second chip; wherein the first wiring pattern, the first external connection terminal, the first through electrode, the first redistribution pattern, the first substrate connection bump, and the first interposer substrate pad transmit a ground signal.
[0009] A semiconductor package according to the present invention comprises: a package substrate including a first wiring pattern and a second wiring pattern; a first external connection terminal and a second external connection terminal located on a lower surface of the package substrate; an interposer substrate located on an upper surface of the package substrate and comprising a body, a first through-electrode penetrating the body and a second through-electrode, a first redistribution pattern electrically connected to the first through-electrode, a second redistribution pattern electrically connected to the second through-electrode, a redistribution insulating layer, a first interposer substrate pad connected to the first redistribution pattern on the redistribution insulating layer, and a second interposer substrate pad connected to the second redistribution pattern on the redistribution insulating layer; a first substrate connection bump and a second substrate connection bump located between the package substrate and the interposer substrate; an underfill material layer surrounding the first substrate connection bump and the second substrate connection bump; a first chip on the interposer substrate; and a second chip spaced horizontally from the first chip on the interposer substrate. The invention comprises a shielding film covering the upper surface of the interposer substrate, the upper surface and side of the first chip, and the upper surface and side of the second chip; and a molding member covering the upper surface of the package substrate, the side and upper surface of the interposer substrate, and the shielding film, wherein the first wiring pattern, the first external connection terminal, the first through-electrode, the first redistribution pattern, the first substrate connection bump, and the first interposer substrate pad transmit a ground signal, and the shielding film and the molding member are located between the first chip and the second chip, and the first interposer substrate pad, the first through-electrode, the first substrate connection bump, and the first external connection terminal each do not overlap with the first chip and the second chip respectively in a vertical direction. Effects of the invention
[0010] A semiconductor package according to the technical concept of the present invention can improve the electromagnetic interference shielding effect between components within the semiconductor package through a shielding film covering the surface of a component and wiring connecting the shielding film to ground. Brief explanation of the drawing
[0011] FIG. 1a is a plan view schematically showing a semiconductor package according to embodiments of the technical concept of the present invention. FIG. 1b is a plan view schematically showing a semiconductor package according to embodiments of the technical concept of the present invention. Figure 2 is a cross-sectional view along the line A1-A1' of Figure 1b. FIG. 3 is a schematic diagram schematically showing one embodiment of the first chip of FIG. 2. FIG. 4 is a schematic diagram schematically showing one embodiment of the first chip of FIG. 2. FIG. 5 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments of the present invention. FIG. 6 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments of the present invention. FIG. 7 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments of the present invention. FIG. 8 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments of the present invention. FIG. 9 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments of the present invention. FIGS. 10 to 12 are cross-sectional views illustrating a method for manufacturing a semiconductor package of the present invention. FIGS. 13 to 15 are cross-sectional views illustrating a method for manufacturing a semiconductor package of the present invention. Specific details for implementing the invention
[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.
[0013] FIG. 1a is a schematic plan view illustrating a semiconductor package according to embodiments of the technical concept of the present invention. FIG. 1b is a schematic plan view illustrating a semiconductor package according to embodiments of the technical concept of the present invention. FIG. 2 is a cross-sectional view along the line A1-A1' of FIG. 1b.
[0014] Referring to FIGS. 1a to 2, a semiconductor package (1, 10) may include a package substrate (100), an interposer substrate (200), a first chip (300), a second chip (400), and a shielding film (500). According to exemplary embodiments, the package substrate (100) is located below the interposer substrate (200) and may be electrically connected to the interposer substrate (200) and external connection terminals (150, 160), respectively. The semiconductor package (1) shown in FIG. 1a and the semiconductor package (10) shown in FIG. 1b illustrate plan views of embodiments of a semiconductor package (1, 10) including a package substrate (100), an interposer substrate (200), a first chip (300), a second chip (400), and a shielding film (500), and the following description will be based on FIG. 1b.
[0015] In the drawings below, the X-axis direction and the Y-axis direction represent directions parallel to the surface of the package substrate (100), and the X-axis direction and the Y-axis direction can be understood as directions perpendicular to each other. The Z-axis direction may represent a direction perpendicular to the surface of the upper or lower surface of the package substrate (100), that is, a direction perpendicular to the XY plane. Additionally, in the drawings below, the first horizontal direction, the second horizontal direction, and the vertical direction can be understood as follows. The first horizontal direction can be understood as the X-axis direction, the second horizontal direction can be understood as the Y-axis direction, and the vertical direction can be understood as the Z-axis direction.
[0016] The package substrate (100) may be a substrate on which the interposer substrate (200) is mounted. In some embodiments, the package substrate (100) may be a motherboard on which various types of semiconductor chips and packages are mounted. In addition, in some embodiments, the package substrate (100) may be a substrate that acts as an intermediate bridge, receiving electrical signals from the interposer substrate (200) and transmitting them to an external device. Additionally, the package substrate (100) may also be connected to ground.
[0017] According to exemplary embodiments, the package substrate (100) may be a printed circuit board (PCB) comprising a wiring pattern (120, 130) inside and an insulating layer (110) surrounding the wiring pattern. In this case, the wiring pattern (120, 130) may be made of copper, nickel, stainless steel, or beryllium copper, and the insulating layer (110) may be made of at least one material selected from phenolic resin, epoxy resin, and polyimide. The insulating layer (110) may include at least one material selected from, for example, FR-4 (Flame Retardant 4), tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, BT (Bismaleimide triazine), Thermount, cyanate ester, polyimide, and liquid crystal polymer.
[0018] According to exemplary embodiments, the wiring pattern (120, 130) may include a first wiring pattern (120) that transmits a ground signal and a second wiring pattern (130) that transmits a power / signal signal. According to exemplary embodiments, the second wiring pattern (130) may transmit other signals in addition to power / signal. In this specification, the first wiring pattern (120) may also be referred to as a ground wiring pattern.
[0019] External connection terminals (150, 160) may be located on the lower surface of the package substrate (100). The external connection terminals (150, 160) are mounted on the lower surface of the package substrate (100) and may be configured to transmit signals received from the wiring patterns (120, 130) of the package substrate (100) to an external device. The external connection terminals (150, 160) may include a first external connection terminal (160) connected to the first wiring pattern (120) and a second external connection terminal (150) connected to the second wiring pattern (130). According to exemplary embodiments, the first external connection terminal (160) may transmit a ground signal. In some embodiments, the first external connection terminal (160) may be directly connected to ground. The second external connection terminal (150) may transmit a power / signal signal. According to exemplary embodiments, the second external connection terminal (150) may transmit other signals in addition to power / signal. According to exemplary embodiments, the second external connection terminal (150) may transmit other signals in addition to power / signal. In this specification, the first external connection terminal (160) may be referred to as a ground external connection terminal.
[0020] According to exemplary embodiments, the external connection terminal (150, 160) may be formed of a solder ball. However, according to an embodiment, the external connection terminal (150, 160) may have a structure including a pillar and solder. The external connection terminal (150, 160) may include at least one of copper (Cu), silver (Ag), gold (Au), and tin (Sb).
[0021] An interposer substrate (200) may be mounted on a package substrate (100). According to exemplary embodiments, the interposer substrate (200) may be mounted on the package substrate (100) in a flip-chip manner via substrate connection bumps (181, 183). According to exemplary embodiments, an underfill material layer (170) covering the substrate connection bumps (181, 183) may be disposed between the interposer substrate (200) and the package substrate (100). The underfill material layer (170) may be made of an epoxy resin formed, for example, by a capillary underfill method. However, in some embodiments, a molding member may be directly filled into the gap between the interposer substrate (200) and the package substrate (100) through a molded underfill process. In this case, the underfill material layer (170) may be omitted.
[0022] According to exemplary embodiments, the substrate connection bumps (181, 183) may include a first substrate connection bump (181) connected to a first wiring pattern (120) and a second substrate connection bump (183) connected to a second wiring pattern (130). The first substrate connection bump (181) may transmit a ground signal between the interposer substrate (200) and the package substrate (100). The second substrate connection bump (183) may transmit a power / signal signal between the interposer substrate (200) and the package substrate (100). According to exemplary embodiments, the second substrate connection bump (183) may transmit other signals in addition to power / signal. In this specification, the first substrate connection bump (181) may be referred to as a ground substrate connection bump.
[0023] The interposer substrate (200) is formed based on silicon and can electrically connect the first chip (300) and the second chip (400) mounted on the interposer substrate (200). That is, the interposer substrate (200) can serve as a connecting passage that electrically connects the first chip (300) and the second chip (400). According to exemplary embodiments, if the first chip (300) and the second chip (400) are each different types of chips or chip structures, the first chip (300) and the second chip (400) can exchange electrical signals with each other through the interposer substrate (200).
[0024] The interposer substrate (200) may include a body (220), through electrodes (243, 245), a redistribution insulating layer (240), and a redistribution pattern (250, 260). The body (220) may include an upper surface and a lower surface. The body (220) may include silicon (Si), for example, crystalline silicon, polycrystalline silicon, or amorphous silicon. Alternatively, the body (220) may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). Meanwhile, the first body (220) may have a silicon-on-insulator (SOI) structure. For example, the body (220) may include a buried oxide layer.
[0025] The through electrode (243, 245) may penetrate the body (220) in the vertical direction (Z). The through electrode (243, 245) may extend in the vertical direction (Z) from the upper surface of the body (220) toward the lower surface and may be electrically connected to the substrate connection bump (181, 183). According to exemplary embodiments, the through electrode (243, 245) may have a tapered shape in which the horizontal width decreases or increases as the level along the vertical direction (Z) increases. According to exemplary embodiments, the through electrode (243, 245) may include a through silicon via (TSV).
[0026] The through electrodes (243, 245) may include a first through electrode (245) connected to a first substrate connection bump (181) and a second through electrode (243) connected to a second substrate connection bump (183). The first through electrode (245) may be configured to transmit a ground signal, and the second through electrode (243) may be configured to transmit a power / signal signal. According to exemplary embodiments, the second through electrode (243) may transmit other signals in addition to power / signal. In this specification, the first through electrode (245) may also be referred to as a ground through electrode.
[0027] The redistribution insulating layer (240) may be located on the upper surface of the body (220). The redistribution insulating layer (240) may cover at least a portion of the redistribution pattern (250, 260). According to exemplary embodiments, the redistribution insulating layer (240) may be provided as a plurality of layers stacked together along the vertical direction (Z). The redistribution pattern (250, 260) may serve as an electrical connection passage penetrating the upper and lower surfaces of the redistribution insulating layer (240).
[0028] According to exemplary embodiments, the redistribution insulating layer (240) may be formed from a photo imageable dielectric (PID) or a photosensitive polyimide (PSPI).
[0029] According to exemplary embodiments, the redistribution pattern (250, 260) may be a metal or an alloy of metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc., but is not limited thereto, and in some embodiments, the redistribution pattern (250, 260) may be formed by depositing a metal or an alloy of metal on a seed layer comprising copper, titanium, titanium nitride, or titanium tungsten. The redistribution pattern (250, 260) may include a redistribution line pattern and a redistribution via pattern. The redistribution line pattern may have a shape that extends horizontally along at least one of the upper and lower surfaces of each of the plurality of redistribution insulating layers (240) stacked in the vertical direction (Z). The redistribution via pattern may have a shape that extends through the redistribution insulating layer (240) in the vertical direction (Z). The redistribution via pattern may electrically connect redistribution line patterns located at different vertical levels. In some embodiments, at least some of the redistribution line patterns may be formed together with some of the redistribution via patterns to form an integral unit.
[0030] The rewiring pattern (250, 260) may include a first rewiring pattern (260) connected to a first through electrode (245) and a second rewiring pattern (250) connected to a second through electrode (243). The first rewiring pattern (260) may be configured to transmit a ground signal, and the second rewiring pattern (250) may be configured to transmit a power / signal signal. In this specification, the first rewiring pattern (260) may also be referred to as a ground rewiring pattern.
[0031] The interposer substrate pads (271, 273) may be located on the upper surface of the interposer substrate (200). According to exemplary embodiments, the interposer substrate pads (271, 273) may be exposed vertically (Z) above the redistribution insulating layer (240). In some embodiments, at least a portion of the side of the interposer substrate pads (271, 273) may be exposed from the redistribution insulating layer (240).
[0032] According to exemplary embodiments, the interposer substrate pads (271, 273) may include a first interposer substrate pad (271) connected to a first redistribution pattern (260), and a second interposer substrate pad (273) connected to a second redistribution pattern (250). The first interposer substrate pad (271) is connected to a shielding film (500) and may be configured to transmit a ground signal. The second interposer substrate pad (273) may be connected to at least one of a first chip connection bump (390) and a second chip connection bump (490). In this specification, the first interposer substrate pad (271) may also be referred to as a ground interposer substrate pad.
[0033] The first chip (300) may be positioned on the interposer substrate (200). According to exemplary embodiments, the first chip (300) may be mounted on the interposer substrate (200) in a flip-chip manner through a first chip connection bump (390), such as a microbump, and a first chip pad (395). According to exemplary embodiments, an underfill material layer (370) covering the first chip connection bump (390) may be disposed between the first chip (300) and the interposer substrate (200). The underfill material layer (370) may be made of an epoxy resin formed, for example, by a capillary underfill method.
[0034] The first chip (300) may be a semiconductor chip or a chip stacking structure. According to exemplary embodiments, if the first chip (300) is a semiconductor chip, the first chip (300) may be a memory chip. The memory chip may be a volatile memory chip, such as, for example, DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), or a non-volatile memory chip, such as PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory).
[0035] According to exemplary embodiments, when the first chip (300) is a chip stacking structure, the chip stacking structure may be a High Bandwidth Memory (HBM) or wire bonding memory package in which a plurality of the memory chips are stacked in a vertical direction (Z). This will be explained in detail with reference to FIGS. 3 and FIGS. 4.
[0036] The second chip (400) may be mounted on the interposer substrate (200) spaced apart from the first chip (300) in the horizontal direction (X and / or Y). The second chip (400) may be mounted on the interposer substrate (200) in a flip-chip manner through a second chip connection bump (490), such as a microbump, and a second chip pad (495). According to exemplary embodiments, an underfill material layer (470) covering the second chip connection bump (490) may be disposed between the second chip (400) and the interposer substrate (200). The underfill material layer (470) may be made of an epoxy resin formed, for example, by a capillary underfill method.
[0037] According to exemplary embodiments, the second chip (400) may be a logic chip. The logic chip may be, for example, a microprocessor such as a central processing unit (CPU), a graphic processing unit (GPU), or an application processor (AP), an analog device, or a digital signal processor.
[0038] However, the first chip (300) is not limited to a memory chip, and the second chip (400) is not limited to a logic chip. In some embodiments, the first chip (300) and the second chip (400) may each be a memory chip or a logic chip, and the first chip (300) may be a logic chip and the second chip (400) may be a memory chip.
[0039] Each of the first external connection terminal (160), the first substrate connection bump (181), the first through electrode (245), and the first interposer substrate pad (271) may be provided in multiple numbers. Each of the first external connection terminal (160), the first substrate connection bump (181), the first through electrode (245), and the first interposer substrate pad (271) may be located in the lateral direction of the first chip (300), between the first chip (300) and the second chip (400), and in the lateral direction of the second chip (400). Here, the lateral direction may be understood as the direction opposite to the direction in which the first chip (300) and the second chip (400) face each other. For example, the lateral direction of the first chip (300) can be understood as the opposite side direction to the direction in which the first chip (300) and the second chip (400) face each other, and the lateral direction of the second chip (400) can be understood as the opposite side direction to the direction in which the second chip (400) and the first chip (300) face each other.
[0040] Each of the first external connection terminal (160), the first substrate connection bump (181), the first through electrode (245), and the first interposer substrate pad (271) may not overlap with each of the first chip (300) and the second chip (400) in the vertical direction (Z).
[0041] The shielding film (500) may be configured to prevent electromagnetic interference. According to exemplary embodiments, the shielding film (500) may be configured to shield Electro Magnetic Interference (EMI). The shielding film (500) may include a conductive material comprising one or more selected from the group consisting of metals and ceramics, specifically one or more selected from the group consisting of copper (Cu), gold (Au), silver (Ag), and titanium (Ti).
[0042] Additionally, the shielding film (500) may include a conductive resin. The conductive resin may be a combination in which one or more of aluminum, ceramic, or silicon are added to a carbon-based resin.
[0043] The shielding film (500) can cover the surface of the first chip (300) and the surface of the second chip (400). According to exemplary embodiments, the shielding film (500) can completely cover the surface exposed from the underfill material layer (370) in the first chip (300). Additionally, the shielding film (500) can completely cover the surface exposed from the underfill material layer (470) in the second chip (400).
[0044] The shielding film (500) can cover the upper surface and side of the first chip (300) and can cover the upper surface and side of the second chip (400).
[0045] According to exemplary embodiments, the shielding film (500) may cover the upper surface of the interposer substrate (200) in addition to the surfaces of the first chip (300) and the second chip (400), respectively. At this time, the shielding film (500) may cover the first interposer substrate pad (271). According to exemplary embodiments, the shielding film (500) covering the first interposer substrate pad (271) may be located at a higher vertical level than the shielding film (500) covering the upper surface of the redistribution insulation layer (240). Since the first interposer substrate pad (271) is located protruding in a vertical direction (Z) from the upper surface of the redistribution insulation layer (240), the shielding film (500) covering the first interposer substrate pad (271) may be located at a higher vertical level than the shielding film (500) covering the upper surface of the redistribution insulation layer (240). Since the shielding film (500) covers the side of the first interposer substrate pad (271), the shielding film (500) that contacts the first interposer substrate pad (271) in a lateral direction can be extended along the vertical direction (Z).
[0046] The shielding film (500) can cover the surface exposed from each of the interposer substrate (200), the first chip (300), and the second chip (400) by the underfill material layer (370, 470). At this time, the shielding film (500) covering the underfill material layer (370, 470) may have a slope. The slope may be a slope that forms a predetermined angle with the upper surface of the interposer substrate (200).
[0047] In the semiconductor package (10) according to the technical concept of the present disclosure, the shielding film (500) completely covers the components of the semiconductor package (10), the first chip (300) and the second chip (400) in the embodiment according to FIG. 1 and FIG. 2, thereby minimizing electromagnetic interference between the first chip (300) and the second chip (400). In addition, since the shielding film (500) is connected to the first interposer substrate pad (271) that transmits a ground signal, the first redistribution pattern (260), the first through electrode (245), the first substrate connection bump (181), the first wiring pattern (120), and the first external connection terminal (160), the shielding film (500) can be grounded without forming a separate ground pattern.
[0048] In addition, for efficient grounding of the shielding film (500), the first external connection terminal (160), the first substrate connection bump (181), the first through electrode (245), and the first interposer substrate pad (271) are each located in the lateral direction of the first chip (300), the lateral direction of the second chip (400), and between the first chip (300) and the second chip (400), so that electromagnetic interference between the first chip (300) and the second chip (400) can be efficiently prevented.
[0049] FIG. 3 is a schematic diagram illustrating an embodiment of the first chip of FIG. 2. In the following, content that overlaps with the description made with reference to FIG. 1 and FIG. 2 will be omitted, and the differences will be explained in detail.
[0050] Referring to FIG. 3, the first chip (300) may be a chip stacking structure. In this case, the first chip (300) may include a base chip (320), a first semiconductor chip (310), an adhesive layer (335), and a dummy chip (330). The base chip (320) may be a chip located at the bottom within the first chip (300). According to exemplary embodiments, at least one of the upper surface and the lower surface of the base chip (320) may have a flat shape.
[0051] According to exemplary embodiments, the base chip (320) may integrate signals from a plurality of first semiconductor chips (310) stacked on top of the base chip (320) and transmit them externally, or transmit signals and power from the outside to the first semiconductor chips (310). Accordingly, the base chip (320) may be referred to as a buffer chip or a control chip in this specification.
[0052] The base chip (320) may include various types of individual devices. The individual devices may include various microelectronics devices, such as a MOSFET (metal-oxide-semiconductor field effect transistor) such as a CMOS transistor (complementary metal-insulator-semiconductor transistor), a system LSI (large scale integration), an image sensor such as a CIS (CMOS imaging sensor), a MEMS (micro-electro-mechanical system), active devices, passive devices, etc. In some embodiments, the base chip (320) may not include memory cells. For example, the semiconductor devices included in the base chip (320) may include a serial-parallel conversion circuit, a test logic circuit such as a DFT (design for test), a JTAG (Joint Test Action Group), a MBIST (memory builtin self-test), and a signal interface circuit such as a PHY.
[0053] A through electrode (325) that penetrates the base chip (320) in a vertical direction (Z) may be located inside the base chip (320). The through electrode (325) may come into contact with a base chip pad (321) located on the upper surface of the base chip (320). The through electrode (325) may be electrically connected to the base chip pad (321).
[0054] A base chip pad (321) and a dielectric layer (323) may be located on the upper surface of the base chip (320). The dielectric layer (323) may wrap around the base chip pad (321). The dielectric layer (323) may wrap around the side of the base chip pad (321). The upper surface of the base chip pad (321) may be exposed vertically upward from the dielectric layer (323).
[0055] The first semiconductor chip (310) can be stacked in a vertical direction (Z) on the base chip (320). The first semiconductor chip (310) can be bonded onto the base chip (320) through direct bonding. The direct bonding may include dielectric-to-dielectric bonding, copper (Cu)-to-copper bonding, and hybrid bonding in which dielectric-to-dielectric bonding and metal-to-metal bonding occur together. The direct bonding may be a diffusion bonding in which two interfaces containing the same material are arranged to face each other, brought into contact, and heat is applied so that the metal atoms or dielectric materials in contact with each other become one through diffusion. The hybrid bonding may include hybrid copper bonding.
[0056] The first semiconductor chip (310) can be bonded to the base chip (320) by direct bonding. For example, the semiconductor chip pad (311) and dielectric layer (313) on the lower surface of the first semiconductor chip (310) can be in contact with the base chip pad (321) and dielectric layer (323) on the upper surface of the base chip (320) in a vertical direction (Z). Specifically, the semiconductor chip pad (311) on the lower surface of the first semiconductor chip (310) can be in contact with the base chip pad (321) on the upper surface of the base chip (320) in a vertical direction (Z), and the dielectric layer (313) on the lower surface of the first semiconductor chip (310) can be in contact with the dielectric layer (323) on the upper surface of the base chip (320) in a vertical direction (Z). At this time, the semiconductor chip pad (311) and dielectric layer (313) on the lower surface of the first semiconductor chip (310) can be bonded by direct bonding with the base chip pad (321) and dielectric layer (323) on the upper surface of the base chip (320). In FIG. 1, an interface is shown to exist between the semiconductor chip pad (311) and dielectric layer (313) on the lower surface of the first semiconductor chip (310) and the base chip pad (321) and dielectric layer (323) on the upper surface of the base chip (320), but the interface may disappear as the semiconductor chip pad (311) and dielectric layer (313) on the lower surface of the first semiconductor chip (310) are directly bonded with the base chip pad (321) and dielectric layer (323) on the upper surface of the base chip (320).
[0057] According to exemplary embodiments, a plurality of first semiconductor chips (310) may be provided. The plurality of first semiconductor chips (310) may be defined as chips located below a dummy chip (330) that are stacked in a vertical direction (Z) on a base chip (320) among the plurality of chips included in the first chip (300). According to exemplary embodiments, the first semiconductor chip (310) may be referred to as a memory chip or a core chip.
[0058] According to exemplary embodiments, the first semiconductor chip (310) may include a semiconductor chip pad (311), a dielectric layer (313), and a through electrode (315). The semiconductor chip pad (311) may be provided on the upper surface and the lower surface of the first semiconductor chip (310), respectively. The dielectric layer (313) may cover the semiconductor chip pad (311) on the upper surface and the lower surface of the first semiconductor chip (310), respectively. In this case, the dielectric layer (313) may cover the side of the semiconductor chip pad (311), and either the upper surface or the lower surface of the semiconductor chip pad (311) may be exposed along the vertical direction (Z) from the dielectric layer (313).
[0059] The first semiconductor chip (310) may include a first semiconductor substrate. The first semiconductor substrate may have a lower surface and an upper surface opposite to each other. The lower surface may be a surface facing the interposer substrate (200). The lower surface may be referred to as an active surface, and the upper surface opposite to the lower surface may be referred to as an inactive surface.
[0060] The first semiconductor substrate may include silicon (Si), for example, crystalline silicon, polycrystalline silicon, or amorphous silicon. Alternatively, the first semiconductor substrate may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). Meanwhile, the first semiconductor substrate may have a silicon-on-insulator (SOI) structure. For example, the first semiconductor substrate may include a buried oxide layer. The first semiconductor substrate may include a conductive region, for example, an impurity-doped well or an impurity-doped structure. Additionally, the first semiconductor substrate may have various device isolation structures, such as a shallow trench isolation (STI) structure.
[0061] The first semiconductor chip (310) may include a first semiconductor device layer. According to exemplary embodiments, the first semiconductor device layer may be formed on the lower surface, which is the active surface of the first semiconductor substrate. The first semiconductor device layer may include a core region and a first dummy region. Individual devices may be formed in the core region of the first semiconductor device layer. The individual devices may include various microelectronics devices, such as a MOSFET (metal-oxide-semiconductor field effect transistor) such as a CMOS transistor (complementary metal-insulator-semiconductor transistor), a system LSI (large scale integration), an image sensor such as a CIS (CMOS imaging sensor), a MEMS (micro-electro-mechanical system), active devices, passive devices, etc.
[0062] The first semiconductor chip (310) may include a first wiring layer. The first wiring layer may be spaced apart along a vertical direction from the first semiconductor substrate with the first semiconductor device layer in between. The first wiring layer may be electrically connected to the first semiconductor device layer. The first wiring layer may include a wiring pattern having a multilayer structure and vias connecting the wiring patterns to each other.
[0063] The through electrode (315) can penetrate the first semiconductor substrate of the first semiconductor chip (310) in the vertical direction (Z). The through electrode (315) can penetrate the first semiconductor device layer and the first semiconductor substrate. The through electrode (315) can be electrically connected to wiring patterns provided within the first wiring layer. The through electrode (315) may have a tapered shape in which the horizontal width decreases or increases as the level along the vertical direction increases. At least a portion of the through electrode (315) may be in the shape of a pillar. The through electrode (315) may be a through silicon via (TSV). According to exemplary embodiments, the first semiconductor chip (310_U) located at the top of a plurality of first semiconductor chips (310) may not include a through electrode (315).
[0064] According to exemplary embodiments, the surface roughness of the upper surface of the first semiconductor chip (310_U) located at the top may be rougher than the surface roughness of the upper surface of the other first semiconductor chip (310).
[0065] In some embodiments, the thickness along the vertical direction of the first semiconductor chip (310_U) located at the top of the plurality of first semiconductor chips (310) may be substantially the same as the thickness along the vertical direction (Z) of the other first semiconductor chip (310).
[0066] A plurality of first semiconductor chips (310) may be stacked in a row along the vertical direction (Z). For example, the sides of each of the plurality of first semiconductor chips (310) may be located on the same plane. However, this is not limited thereto, and the plurality of first semiconductor chips (310) may be offset stacked along one direction.
[0067] In some embodiments, a plurality of first semiconductor chips (310) may be stacked along the vertical direction (Z) through direct bonding. For example, a semiconductor chip pad (311) and a dielectric layer (313) on the upper surface of one first semiconductor chip (310) may come into contact along the vertical direction (Z) with a semiconductor chip pad (311) and a dielectric layer (313) on the lower surface of the first semiconductor chip (310) located above the first semiconductor chip (310). Specifically, a semiconductor chip pad (311) on the upper surface of one first semiconductor chip (310) may contact a semiconductor chip pad (311) on the lower surface of the first semiconductor chip (310) located above the first semiconductor chip (310) in a vertical direction (Z), and a dielectric layer (313) on the upper surface of one first semiconductor chip (310) may contact a dielectric layer (313) on the lower surface of the first semiconductor chip (310) located above the first semiconductor chip (310) in a vertical direction (Z). At this time, the semiconductor chip pad (311) and the dielectric layer (313) on the upper surface of one first semiconductor chip (310) may be bonded by direct bonding with the semiconductor chip pad (311) and the dielectric layer (313) on the lower surface of the first semiconductor chip (310) located above the first semiconductor chip (310). In FIG. 3, an interface is shown between the semiconductor chip pad (311) and dielectric layer (313) on the upper surface of one first semiconductor chip (310) and the semiconductor chip pad (311) and dielectric layer (313) on the lower surface of the first semiconductor chip (310) located above the first semiconductor chip (310). However, the interface may disappear as the semiconductor chip pad (311) and dielectric layer (313) on the upper surface of one first semiconductor chip (310) are directly bonded to the semiconductor chip pad (311) and dielectric layer (313) on the lower surface of the first semiconductor chip (310) located above the first semiconductor chip (310).
[0068] As the first semiconductor chips (310) are stacked by direct bonding, an adhesive layer and bumps may not be interposed between the plurality of first semiconductor chips (310).
[0069] According to exemplary embodiments, the first semiconductor chip (310) may include a memory chip. According to exemplary embodiments, the memory chip may be a High Bandwidth Memory (HBM) or wire bonding memory package in which a plurality of the memory chips are stacked in a vertical direction (Z). However, it is not limited thereto, and the semiconductor chip may include a microprocessor such as a central processing unit (CPU), a graphic processing unit (GPU), or an application processor (AP), an analog device, or a logic chip such as a digital signal processor.
[0070] A dummy chip (330) may be stacked in a vertical direction (Z) on a first semiconductor chip (310_U) located at the top. The dummy chip (330) may be stacked on the first semiconductor chip (310_U) located at the top through an adhesive layer (335). According to exemplary embodiments, the dummy chip (330) may not be electrically connected to the first semiconductor chip (310). In some embodiments, the thickness of the dummy chip (330) in a vertical direction (Z) may be thicker than the thickness of the first semiconductor chip (310) in a vertical direction (Z).
[0071] The adhesive layer (335) may be positioned between the dummy chip (330) and the first semiconductor chip (310_U) located at the top. In an exemplary embodiment, the adhesive layer (335) may be a layer configured to attach the dummy chip (330) onto the first semiconductor chip (310_U) located at the top. The adhesive layer (335) may be a film having adhesive properties of its own. For example, the adhesive layer (335) may be a double-sided adhesive film. According to exemplary embodiments, the adhesive layer (335) may be a tape-shaped material layer, a liquid coating curing material layer, or a combination thereof. Additionally, the adhesive layer (335) may include a thermal setting structure, thermal plastic, UV cure material, or a combination thereof. The adhesive layer (335) may be referred to as a die attach film (DAF) or a non-conductive film (NCF).
[0072] The first molding member (391) may be formed to surround the first semiconductor chips (310) and the dummy chip (330) on the upper surface of the base chip (320). The first molding member (391) may be formed from a molding material such as EMC or a photosensitive material such as PIE (photoimagable encapsulant). In some embodiments, a portion of the first molding member (391) may be made of an insulating material such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. However, it is not limited thereto, and the first molding member (391) may be formed from a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin containing reinforcing materials such as inorganic fillers, specifically ABF (Ajinomoto Build-up Film), FR-4, BT, etc. According to exemplary embodiments, the upper surface of the first molding member (391) may form a co-surface with the upper surface of the dummy chip (330).
[0073] FIG. 4 is a schematic diagram illustrating an embodiment of the first chip of FIG. 2. In the following, details that overlap with those described with reference to FIG. 3 will be omitted, and the differences will be explained in detail.
[0074] Referring to FIG. 4, the first chip (301) may be a chip stacking structure. In this case, the first chip (301) may include a base chip (320), a first semiconductor chip (310), an adhesive layer (335), and a dummy chip (330).
[0075] An underfill material layer (327) may be located between the base chip (320) and the first semiconductor chip (310), and between the first semiconductor chips (310). Additionally, the base chip (320) and the first semiconductor chip (310) may be connected via a chip connection bump (329), and adjacent first semiconductor chips (310) in a direction perpendicular to each other (Z) may be connected via a chip connection bump (319). Unlike the first chip (300) of FIG. 3, the first chip (301) of FIG. 4 may have the base chip (320) and a plurality of first semiconductor chips (310) stacked in a flip-chip manner through bumps such as microbumps.
[0076] FIG. 5 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments of the present invention. In the following description, content that overlaps with the description made with reference to FIG. 1 to 4 will be omitted, and the differences will be explained in detail.
[0077] Referring to FIG. 5, the semiconductor package (11) may include an interposer substrate (200), a first chip (300), a second chip (400), and a shielding film (501). The package substrate (100) is located below the interposer substrate (200) and may be electrically connected to the interposer substrate (200) and external connection terminals (150, 160), respectively. The package substrate (100) may include wiring patterns (120, 130) and an insulating layer (110). The wiring patterns (120, 130) may include a first wiring pattern (120) that transmits a ground signal and a second wiring pattern (130) that transmits a power / signal signal. According to exemplary embodiments, the second wiring pattern (130) may transmit other signals in addition to power / signal. An external connection terminal (150, 160) may be located on the lower surface of the package substrate (100). The external connection terminal (150, 160) may include a first external connection terminal (160) connected to a first wiring pattern (120) and a second external connection terminal (150) connected to a second wiring pattern (130).
[0078] An interposer substrate (200) may be mounted on a package substrate (100). An underfill material layer (170) covering substrate connection bumps (181, 183) may be disposed between the interposer substrate (200) and the package substrate (100). The substrate connection bumps (181, 183) may include a first substrate connection bump (181) connected to a first wiring pattern (120), and a second substrate connection bump (183) connected to a second wiring pattern (130). The interposer substrate (200) may include a body (220), through electrodes (243, 245), a redistribution insulating layer (240), and redistribution patterns (250, 260). The through electrodes (243, 245) may include a first through electrode (245) connected to a first substrate connection bump (181), and a second through electrode (243) connected to a second substrate connection bump (183).
[0079] The redistribution insulating layer (240) may be located on the upper surface of the body (220). The redistribution insulating layer (240) may cover at least a portion of the redistribution pattern (250, 260). The redistribution pattern (250, 260) may include a first redistribution pattern (260) connected to a first through electrode (245), and a second redistribution pattern (250) connected to a second through electrode (243).
[0080] According to exemplary embodiments, the interposer substrate pads (271, 273) may include a first interposer substrate pad (271) connected to a first redistribution pattern (260), and a second interposer substrate pad (273) connected to a second redistribution pattern (250).
[0081] The first chip (300) may be positioned on the interposer substrate (200). According to exemplary embodiments, the first chip (300) may be mounted on the interposer substrate (200) in a flip-chip manner through a first chip connection bump (390), such as a microbump, and a first chip pad (395). According to exemplary embodiments, an underfill material layer (370) covering the first chip connection bump (390) may be disposed between the first chip (300) and the interposer substrate (200).
[0082] The second chip (400) may be mounted on the interposer substrate (200) spaced apart from the first chip (300) in a horizontal direction (X and / or Y). The second chip (400) may be mounted in a flip-chip manner on the interposer substrate (200) through a second chip connection bump (490), such as a microbump, and a second chip pad (495). According to exemplary embodiments, an underfill material layer (470) covering the second chip connection bump (490) may be disposed between the second chip (400) and the interposer substrate (200).
[0083] The shielding film (501) can cover the upper surface of the interposer substrate (200), at least a portion of the side of the redistribution insulating layer (240), the surface exposed from the underfill material layer (470) in the first chip (300), and the surface exposed from the underfill material layer (370) in the second chip (400). The shielding film (501) can cover at least a portion of the side of the redistribution insulating layer (240). Accordingly, the shielding film (501) in contact with the side of the redistribution insulating layer (240) may have a shape extending upward in the vertical direction (Z).
[0084] The shielding film (501) can cover the first interposer substrate pad (271). Since the first interposer substrate pad (271) protrudes upward in the vertical direction (Z) from the redistribution insulation layer (240), the shielding film (501) covering the first interposer substrate pad (271) can be located at a higher vertical level than the shielding film (501) covering the upper surface of the redistribution insulation layer (240). Since the shielding film (501) covers the side of the first interposer substrate pad (271), the shielding film (501) in contact with the first interposer substrate pad (271) in the lateral direction can have a shape that extends along the vertical direction (Z).
[0085] The shielding film (501) can cover the surface exposed from each of the interposer substrate (200), the first chip (300), and the second chip (400) by the underfill material layer (370, 470). At this time, the shielding film (501) covering the underfill material layer (370, 470) may have a slope. The slope may be a slope that forms a predetermined angle with the upper surface of the interposer substrate (200).
[0086] FIG. 6 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments of the present invention. In the following description, content that overlaps with the description made with reference to FIG. 1 to 5 will be omitted, and the differences will be explained in detail.
[0087] Referring to FIG. 6, the semiconductor package (12) may include an interposer substrate (200), a first chip (300), a second chip (400), and a shielding film (502). The package substrate (100) is located below the interposer substrate (200) and may be electrically connected to the interposer substrate (200) and external connection terminals (150, 160), respectively. The package substrate (100) may include wiring patterns (120, 130) and an insulating layer (110). The wiring patterns (120, 130) may include a first wiring pattern (120) that transmits a ground signal and a second wiring pattern (130) that transmits a power / signal signal. According to exemplary embodiments, the second wiring pattern (130) may transmit other signals in addition to power / signal. An external connection terminal (150, 160) may be located on the lower surface of the package substrate (100). The external connection terminal (150, 160) may include a first external connection terminal (160) connected to a first wiring pattern (120) and a second external connection terminal (150) connected to a second wiring pattern (130).
[0088] An interposer substrate (200) may be mounted on a package substrate (100). An underfill material layer (170) covering substrate connection bumps (181, 183) may be disposed between the interposer substrate (200) and the package substrate (100). The substrate connection bumps (181, 183) may include a first substrate connection bump (181) connected to a first wiring pattern (120), and a second substrate connection bump (183) connected to a second wiring pattern (130). The interposer substrate (200) may include a body (220), through electrodes (243, 245), a redistribution insulating layer (240), and redistribution patterns (250, 260). The through electrodes (243, 245) may include a first through electrode (245) connected to a first substrate connection bump (181), and a second through electrode (243) connected to a second substrate connection bump (183).
[0089] The redistribution insulating layer (240) may be located on the upper surface of the body (220). The redistribution insulating layer (240) may cover at least a portion of the redistribution pattern (250, 260). The redistribution pattern (250, 260) may include a first redistribution pattern (260) connected to a first through electrode (245), and a second redistribution pattern (250) connected to a second through electrode (243).
[0090] According to exemplary embodiments, the interposer substrate pads (271, 273) may include a first interposer substrate pad (271) connected to a first redistribution pattern (260), and a second interposer substrate pad (273) connected to a second redistribution pattern (250).
[0091] The first chip (300) may be positioned on the interposer substrate (200). According to exemplary embodiments, the first chip (300) may be mounted on the interposer substrate (200) in a flip-chip manner through a first chip connection bump (390), such as a microbump, and a first chip pad (395). According to exemplary embodiments, an underfill material layer (370) covering the first chip connection bump (390) may be disposed between the first chip (300) and the interposer substrate (200).
[0092] The second chip (400) may be mounted on the interposer substrate (200) spaced apart from the first chip (300) in a horizontal direction (X and / or Y). The second chip (400) may be mounted in a flip-chip manner on the interposer substrate (200) through a second chip connection bump (490), such as a microbump, and a second chip pad (495). According to exemplary embodiments, an underfill material layer (470) covering the second chip connection bump (490) may be disposed between the second chip (400) and the interposer substrate (200).
[0093] The shielding film (502) can cover the upper surface and side surface of the interposer substrate (200), the surface exposed from the interposer substrate (200) and the package substrate in the underfill material layer (170), at least a portion of the side surface of the redistribution insulating layer (240), the surface exposed from the underfill material layer (470) in the first chip (300), and the surface exposed from the underfill material layer (370) in the second chip (400).
[0094] Since the shielding film (502) covers the upper surface and side of the interposer substrate (200), electromagnetic interference generated from the interposer substrate (200) can be prevented.
[0095] The shielding film (502) can cover the first interposer substrate pad (271). Since the first interposer substrate pad (271) protrudes upward in the vertical direction (Z) from the redistribution insulation layer (240), the shielding film (502) covering the first interposer substrate pad (271) can be located at a higher vertical level than the shielding film (502) covering the upper surface of the redistribution insulation layer (240). Since the shielding film (502) covers the side of the first interposer substrate pad (271), the shielding film (502) in contact with the first interposer substrate pad (271) in the lateral direction can have a shape that extends along the vertical direction (Z).
[0096] The shielding film (502) can cover the surface exposed from each of the interposer substrate (200), the first chip (300), and the second chip (400) by the underfill material layer (370, 470). At this time, the shielding film (502) covering the underfill material layer (370, 470) may have a slope. The slope may be a slope that forms a predetermined angle with the upper surface of the interposer substrate (200).
[0097] Additionally, the shielding film (502) can cover the surface of the underfill material layer (170) exposed from the interposer substrate (200) and the package substrate (100). Accordingly, the shielding film (502) can cover the side of the underfill material layer (170). At this time, the shielding film (502) covering the side of the underfill material layer (170) may be inclined with respect to the upper surface of the package substrate (100). The inclined surface may be inclined at a predetermined angle with respect to the upper surface of the package substrate (100).
[0098] FIG. 7 is a schematic cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention. In the following description, content that overlaps with the description made with reference to FIG. 1 to 6 will be omitted, and the differences will be explained in detail.
[0099] The semiconductor package (13) of FIG. 7 may include an interposer substrate (200), a first chip (300), a second chip (400), and a shielding film (503). Unlike the semiconductor package (12) of FIG. 6, the shielding film (503) may cover the upper surface of the package substrate (100). Since the shielding film (503) covers the upper surface of the package substrate (100), electromagnetic interference effects generated from the package substrate (100) can be prevented.
[0100] FIG. 8 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments of the present invention. In the following, content that overlaps with the description made with reference to FIG. 1 to 7 will be omitted.
[0101] Referring to FIG. 8, the semiconductor package (14) may include an interposer substrate (200), a first chip (300), a second chip (400), a shielding film (500), and a second molding member (690). The second molding member (690) may enclose the shielding film (500), the interposer substrate (200), and the package substrate (100). The second molding member (690) may also fill the space between the first chip (300) and the second chip (400). The shielding film (500) and the molding member (690) may be located between the first chip (300) and the second chip (400).
[0102] FIG. 9 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments of the present invention. In the following description, content that overlaps with the description made with reference to FIG. 1 to 8 will be omitted, and the differences will be explained in detail.
[0103] Referring to FIG. 9, the semiconductor package (20) may include an interposer substrate (200), a first chip (300), a second chip (400), and a shielding film (500). Each of the first chip (300) and the second chip (400) may be bonded to the interposer substrate (200) by direct bonding. Direct bonding may include dielectric-to-dielectric bonding, copper (Cu)-to-copper bonding, and hybrid bonding in which dielectric-to-dielectric bonding and metal-to-metal bonding occur together. Direct bonding may be diffusion bonding in which two interfaces containing the same material are arranged to face each other, then brought into contact with each other and heat is applied so that the metal atoms or dielectric materials in contact with each other become one through diffusion.
[0104] According to exemplary embodiments, the first chip pad (395) and the second interposer substrate pad (273) may be in contact along the vertical direction (Z). The first chip bonding insulating layer (397) may be in contact along the vertical direction (Z) with the bonding insulating layer (275) located on the redistribution insulating layer (240).
[0105] According to exemplary embodiments, the second chip pad (495) and the second interposer substrate pad (273) may be in contact along the vertical direction (Z). The second chip bonding insulating layer (497) may be in contact along the vertical direction (Z) with the bonding insulating layer (275) located on the redistribution insulating layer (240).
[0106] The bonding insulating layer (275) can surround the sides of the first interposer substrate pad (271) and the second interposer substrate pad (273). Accordingly, the upper surface of the first interposer substrate pad (271), the upper surface of the second interposer substrate pad (273), and the upper surface of the bonding insulating layer (275) can form a co-surface.
[0107] The shielding film (500) can cover the upper surface of the first chip (300), the second chip (400), and the bonding insulating layer (275). The shielding film (500) can cover the upper surface of the first interposer substrate pad (271). At this time, since the upper surface of the first interposer substrate pad (271) forms a co-surface with the upper surface of the bonding insulating layer (275), the vertical level of the shielding film (500) covering the upper surface of the first interposer substrate pad (271) can be located at the same vertical level as the shielding film (500) covering the bonding insulating layer (275).
[0108] FIGS. 10 to 12 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to the present invention. In the following, content that overlaps with the description made with reference to FIGS. 1 to 9 will be omitted, and the differences will be explained in detail.
[0109] Referring to FIG. 10, a package substrate (100) and a mounted interposer substrate (200) electrically connected to the package substrate (100) are provided. The package substrate (100) and the interposer substrate (200) may be electrically connected by substrate connection bumps (181, 183). The interposer substrate (200) may include a body (220), through electrodes (243, 245), a redistribution insulating layer (240), and a redistribution pattern (250, 260).
[0110] Referring to FIG. 11, interposer substrate pads (271, 273) are formed on an interposer substrate (200), and a first chip (300) and a second chip (400) are mounted. The first chip (300) and the second chip (400) may be mounted on the interposer substrate (200) in a flip-chip manner as shown in FIG. 11. In some embodiments, the first chip (300) and the second chip (400) may be mounted on the interposer substrate (200) by direct bonding as described with reference to FIG. 9.
[0111] Referring to FIG. 12, a shielding film (500) is formed covering the upper surface of an interposer substrate (200), a first chip (300), and a second chip (400). The shielding film (500) can be formed through a sputtering process or a spray coating process. The shielding film (500) is connected to a first interposer substrate pad (271) and can be connected to ground through the first interposer substrate pad (271), a first redistribution pattern (260), a first through electrode (245), a first substrate connection bump (181), a first wiring pattern (120), and a first external connection terminal (160).
[0112] FIGS. 13 to 15 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to the present invention. In the following, content that overlaps with the description made with reference to FIGS. 1 to 12 will be omitted, and the differences will be explained in detail.
[0113] Referring to FIG. 13, an interposer substrate (200), and a first chip (300) and a second chip (400) mounted on the interposer substrate (200) are provided. The first chip (300) and the second chip (400) may be mounted on the interposer substrate (200) by a flip-chip method or a direct bonding method.
[0114] Referring to FIG. 14, a package substrate (100) is mounted on the lower surface of an interposer substrate (200). The package substrate (100) can be mounted on the lower surface of the interposer substrate (200) through substrate connection bumps (181, 183).
[0115] Referring to FIG. 15, a shielding film (500) is formed covering the upper surface of an interposer substrate (200), a first chip (300), and a second chip (400). The shielding film (500) is connected to a first interposer substrate pad (271) and can be connected to ground through the first interposer substrate pad (271), a first redistribution pattern (260), a first through electrode (245), a first substrate connection bump (181), a first wiring pattern (120), and a first external connection terminal (160).
[0116] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims. Explanation of the symbols
[0117] 1, 10: Semiconductor package, 100: Package substrate, 200: Interposer substrate, 300: First chip, 400: Second chip, 500: Shielding film
Claims
Claim 1 A semiconductor package comprising: a package substrate including a wiring pattern; an interposer substrate located on the package substrate and including a body, a through electrode penetrating the body, a redistribution pattern connected to the through electrode, a redistribution insulating layer covering at least a portion of the redistribution pattern, and an interposer substrate pad; a first chip on the interposer substrate; a second chip spaced horizontally from the first chip on the interposer substrate; and a shielding film covering an exposed surface of the first chip and an exposed surface of the second chip; wherein the through electrode includes a ground through electrode, the redistribution pattern includes a ground redistribution pattern, the interposer substrate pad includes a ground interposer substrate pad, and the shielding film contacts the ground interposer substrate pad. Claim 2 A semiconductor package according to claim 1, wherein the shielding film covers the upper surface of an interposer substrate, and the portion of the shielding film covering the ground interposer substrate pad is located at a higher vertical level than the portion of the shielding film covering the upper surface of the redistribution insulating layer. Claim 3 A semiconductor package according to claim 1, wherein a ground substrate connection bump for transmitting a ground signal is located between the interposer substrate and the package substrate, and a ground external connection terminal for transmitting a ground signal is located on the lower surface of the package substrate, and each of the ground interposer substrate pad, ground penetration electrode, ground substrate connection bump, and ground external connection terminal is located in the lateral direction of the first chip, in the lateral direction of the second chip, and between the first chip and the second chip. Claim 4 A semiconductor package according to claim 1, wherein the first chip is located on the interposer substrate through a first chip connection bump, the second chip is located on the interposer substrate through a second chip connection bump, and an underfill material layer is located between the first chip and the interposer substrate and between the second chip and the interposer substrate. Claim 5 A semiconductor package according to claim 4, wherein the shielding film covers the underfill material layer, and the shielding film in contact with the underfill material layer has an inclination that forms a predetermined angle with the upper surface of the interposer substrate. Claim 6 A semiconductor package according to claim 1, wherein a bonding insulating layer is positioned on the upper surface of the redistribution insulating layer, the bonding insulating layer covers the side of the interposer substrate pad, a first chip pad and a first chip bonding insulating layer covering the side of the first chip pad are positioned on the lower surface of the first chip, a second chip pad and a second chip bonding insulating layer covering the side of the second chip pad are positioned on the lower surface of the second chip, and each of the first chip pad and the second chip pad contacts the interposer substrate pad in a vertical direction. Claim 7 A semiconductor package according to claim 6, wherein the upper surface of the bonding insulating layer forms a co-plane with the upper surface of the interposer substrate, and the shielding film covers the upper surface of the bonding insulating layer and the upper surface of the interposer substrate. Claim 8 A semiconductor package according to claim 1, wherein the shielding film covers the upper surface and side surface of the interposer substrate and covers the upper surface of the package substrate. Claim 9 A package substrate comprising a first wiring pattern and a second wiring pattern; a first external connection terminal and a second external connection terminal located on the lower surface of the package substrate; an interposer substrate located on the upper surface of the package substrate and comprising a body, a first through-electrode penetrating the body and a second through-electrode, a first redistribution pattern electrically connected to the first through-electrode, a second redistribution pattern electrically connected to the second through-electrode, a redistribution insulating layer, a first interposer substrate pad connected to the first redistribution pattern on the redistribution insulating layer, and a second interposer substrate pad connected to the second redistribution pattern on the redistribution insulating layer; a first substrate connection bump and a second substrate connection bump located between the package substrate and the interposer substrate; a first chip on the interposer substrate; and a second chip spaced horizontally apart from the first chip on the interposer substrate. A semiconductor package comprising: a shielding film covering the upper surface of the interposer substrate, the upper surface and side of the first chip, and the upper surface and side of the second chip; wherein the first wiring pattern, the first external connection terminal, the first through electrode, the first redistribution pattern, the first substrate connection bump, and the first interposer substrate pad transmit a ground signal. Claim 10 A package substrate comprising a first wiring pattern and a second wiring pattern; a first external connection terminal and a second external connection terminal located on the lower surface of the package substrate; an interposer substrate located on the upper surface of the package substrate and comprising a body, a first through-electrode penetrating the body and a second through-electrode, a first redistribution pattern electrically connected to the first through-electrode, a second redistribution pattern electrically connected to the second through-electrode, a redistribution insulating layer, a first interposer substrate pad connected to the first redistribution pattern on the redistribution insulating layer, and a second interposer substrate pad connected to the second redistribution pattern on the redistribution insulating layer; a first substrate connection bump and a second substrate connection bump located between the package substrate and the interposer substrate; an underfill material layer surrounding the first substrate connection bump and the second substrate connection bump; a first chip on the interposer substrate; and a second chip spaced horizontally from the first chip on the interposer substrate. A semiconductor package comprising: a shielding film covering the upper surface of the interposer substrate, the upper surface and side of the first chip, and the upper surface and side of the second chip; and a molding member covering the upper surface of the package substrate, the side and upper surface of the interposer substrate, and the shielding film, wherein the first wiring pattern, the first external connection terminal, the first through-electrode, the first redistribution pattern, the first substrate connection bump, and the first interposer substrate pad transmit a ground signal, the shielding film and the molding member are located between the first chip and the second chip, and the first interposer substrate pad, the first through-electrode, the first substrate connection bump, and the first external connection terminal each do not overlap with the first chip and the second chip respectively in a vertical direction.