Display device and electronic device having the same

Abstract

One embodiment of the present invention provides a display device comprising a substrate including a display area and a non-display area surrounding the display area, a pixel circuit including a first thin-film transistor including a first semiconductor layer and a first gate electrode that overlaps the display area, and a driving circuit including a second thin-film transistor including a second semiconductor layer and a second gate electrode that is connected to the pixel circuit and overlaps the non-display area, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor material, and the electron mobility of the second thin-film transistor is higher than the electron mobility of the first thin-film transistor.

Description

Technology Field

[0001] Embodiments of the present invention relate to a display device and an electronic device including the same. Background Technology

[0002] Among display devices, organic light-emitting diodes (OLEDs) are attracting attention as next-generation displays due to their advantages, including a wide viewing angle, excellent contrast, and fast response speed.

[0003] Generally, organic light-emitting display devices form thin-film transistors and organic light-emitting diodes as display elements on a substrate, and operate by the organic light-emitting diodes emitting light themselves. Such organic light-emitting display devices are used as display units for small products such as mobile phones, as well as for large products such as televisions. The problem to be solved

[0004] The embodiments of the present invention aim to provide a display device having excellent device characteristics and display quality, and an electronic device including the same. means of solving the problem

[0005] One embodiment of the present invention provides a display device comprising a substrate including a display area and a non-display area surrounding the display area, a pixel circuit including a first thin-film transistor including a first semiconductor layer and a first gate electrode that overlaps the display area, and a driving circuit including a second thin-film transistor including a second semiconductor layer and a second gate electrode that is connected to the pixel circuit and overlaps the non-display area, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor material, and the electron mobility of the second thin-film transistor is higher than the electron mobility of the first thin-film transistor.

[0006] In one embodiment of the present invention, the first semiconductor layer may comprise a crystalline oxide semiconductor material, and the second semiconductor layer may comprise an amorphous oxide semiconductor material.

[0007] In one embodiment of the present invention, the first semiconductor layer and the second semiconductor layer may be disposed on the same layer.

[0008] In one embodiment of the present invention, the first thin-film transistor may further include a third semiconductor layer disposed on the first semiconductor layer.

[0009] In one embodiment of the present invention, the third semiconductor layer may include the same material as the second semiconductor layer.

[0010] In one embodiment of the present invention, the third semiconductor layer may comprise an amorphous oxide semiconductor material, and the first semiconductor layer may comprise a crystalline oxide semiconductor material.

[0011] In one embodiment of the present invention, the third semiconductor layer may overlap with the first semiconductor layer.

[0012] In one embodiment of the present invention, the width of the third semiconductor layer may be smaller than the width of the first semiconductor layer.

[0013] In one embodiment of the present invention, the thickness of the third semiconductor layer may be the same as the thickness of the first semiconductor layer.

[0014] In one embodiment of the present invention, the thickness of the third semiconductor layer is the same as the thickness of the second semiconductor layer, and the thickness of the second semiconductor layer may be smaller than the thickness of the first semiconductor layer.

[0015] In one embodiment of the present invention, the width of the third semiconductor layer may be smaller than the width of the first semiconductor layer and larger than the width of the first gate electrode.

[0016] In one embodiment of the present invention, the first thin-film transistor may be a driving thin-film transistor of the pixel circuit.

[0017] In one embodiment of the present invention, the first semiconductor layer and the second semiconductor layer include indium (In), and the indium content of the first semiconductor layer may be greater than the indium content of the second semiconductor layer.

[0018] Another embodiment of the present invention provides a display device comprising a substrate including a display area and a non-display area around the display area, a pixel circuit superimposed on the display area, and a light-emitting element electrically connected to the pixel circuit to generate light, wherein the pixel circuit includes a driving transistor including a drain electrode connected to a first node, a gate electrode connected to a second node, and a source electrode connected to a third node, a switching transistor that applies a data signal to the first node in response to a scanning signal, and an initialization transistor that applies an initialization voltage to the second node in response to an initialization control signal, and wherein the driving transistor includes a first semiconductor layer comprising a crystalline oxide semiconductor material.

[0019] In another embodiment of the present invention, the first semiconductor layer comprises indium (In), and the indium content of the first semiconductor layer may be 80 at% or more.

[0020] In another embodiment of the present invention, the driving transistor further comprises a third semiconductor layer disposed on the first semiconductor layer, and the third semiconductor layer may comprise an amorphous oxide semiconductor material.

[0021] In another embodiment of the present invention, the thickness of the third semiconductor layer may be the same as the thickness of the first semiconductor layer.

[0022] In another embodiment of the present invention, the thickness of the third semiconductor layer may be smaller than the thickness of the first semiconductor layer.

[0023] In another embodiment of the present invention, the width of the third semiconductor layer may be smaller than the width of the first semiconductor layer.

[0024] In another embodiment of the present invention, a driving circuit including an output transistor that overlaps the non-display area is further included, and the output transistor may include a second semiconductor layer including an amorphous oxide semiconductor material.

[0025] Another embodiment of the present invention provides an electronic device comprising a display device, wherein the display device comprises a substrate including a display area and a non-display area surrounding the display area, a pixel circuit including a first thin-film transistor including a first semiconductor layer and a first gate electrode that overlaps the display area, and a driving circuit including a second thin-film transistor including a second semiconductor layer and a second gate electrode that overlaps the non-display area and is connected to the pixel circuit, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor material, and the electron mobility of the second thin-film transistor is higher than the electron mobility of the first thin-film transistor.

[0026] In another embodiment of the present invention, the first semiconductor layer may comprise a crystalline oxide semiconductor material, and the second semiconductor layer may comprise an amorphous oxide semiconductor material.

[0027] Another embodiment of the present invention provides an electronic device comprising a display device, wherein the electronic device comprises a substrate including a display area and a non-display area around the display area, a pixel circuit superimposed on the display area, and a light-emitting element electrically connected to the pixel circuit to generate light, wherein the pixel circuit comprises a driving transistor including a drain electrode connected to a first node, a gate electrode connected to a second node, and a source electrode connected to a third node, a switching transistor that applies a data signal to the first node in response to a scanning signal, and an initialization transistor that applies an initialization voltage to the second node in response to an initialization control signal, and wherein the driving transistor comprises a first semiconductor layer comprising a crystalline oxide semiconductor material.

[0028] Other aspects, features, and advantages other than those described above will become clear from the following drawings, claims, and detailed description of the invention. Effects of the invention

[0029] Embodiments of the present invention allow the driving thin-film transistor of the pixel circuit and the buffer transistor of the driving circuit to include different oxide semiconductor layers, thereby improving electrical characteristics and simultaneously improving the reliability of the manufacturing process.

[0030] However, the effects of the present invention are not limited to the above effects, and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0031] FIG. 1 is a schematic plan view of a display device according to one embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of a pixel according to one embodiment of the present invention. FIG. 3 is a cross-sectional view showing an example of a plane cut along AA' and B-B' of FIG. 1. FIG. 4 is a cross-sectional view of a display device according to another embodiment of the present invention. FIG. 5 is a cross-sectional view of a display device according to another embodiment of the present invention. FIG. 6 is a cross-sectional view of a display device according to another embodiment of the present invention. FIG. 7 is a cross-sectional view of a display device according to another embodiment of the present invention. FIGS. 8a to 8h are cross-sectional views illustrating a method for manufacturing a display device according to an embodiment of the present invention. FIG. 9 is a block diagram of an electronic device according to one embodiment of the present invention. FIG. 10 is a schematic diagram of an electronic device according to various embodiments of the present invention. Specific details for implementing the invention

[0032] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0033] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0034] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0035] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0036] In the following embodiments, when various components such as layers, films, regions, and plates are described as being "on" or "on" other components, this includes not only cases where they are "directly on" other components but also cases where other components are interposed between them.

[0037] In the following embodiments, terms such as "connect" or "combine" do not necessarily imply a direct and / or fixed connection or combination of two members unless the context clearly indicates otherwise, nor do they exclude the interposition of another member between the two members.

[0038] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and / or thickness of each component shown in the drawings are arbitrarily depicted for convenience of explanation, and therefore the present invention is not necessarily limited to what is illustrated.

[0039] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0040] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0041] FIG. 1 is a schematic plan view of a display device (10) according to one embodiment of the present invention.

[0042] Referring to FIG. 1, the display device (10) can be applied to various electronic devices such as tablet PCs, smartphones, car navigation units, cameras, center information displays (CID) provided in cars, wristwatch-type electronic devices, PDA (Personal Digital Assistant), PMP (Portable Multimedia Player), game consoles, small and medium-sized electronic devices, televisions, external billboards, monitors, personal computers, and laptop computers. However, these are presented as exemplary embodiments, and it is obvious that they can be adopted in other electronic devices within the scope of the concept of the present invention.

[0043] The display device (10) includes a display panel that provides a display screen. Examples of display panels include an inorganic light-emitting diode display panel, an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a plasma display panel, a field emission display panel, etc. In the following examples, an organic light-emitting diode display panel is used as an example of a display panel, but it is not limited thereto, and if the same technical concept is applicable, it can be applied to other display panels.

[0044] A display device (10) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) is an area where a screen can be displayed, and the non-display area (NDA) is an area where a screen is not displayed, and may be an area where elements and / or wiring for generating and / or transmitting various signals applied to the display area (DA) are arranged. In FIG. 1, based on the boundary line of the rectangle drawn with a dotted line, the area inside corresponds to the display area (DA), and the area outside corresponds to the non-display area (NDA). The display area (DA) may generally occupy the center of the display device (10).

[0045] The display area (DA) may include a plurality of pixels (PX). The plurality of pixels (PX) may be arranged in a matrix direction on the substrate (100). The shape of each pixel (PX) may be a flat rectangle or a square in a planar shape, but is not limited thereto, and may be a rhombus shape with each side tilted toward one direction. Each pixel (PX) may be arranged alternately in a stripe type or a pentile type. In addition, each of the pixels (PX) may include one or more light-emitting elements that emit light of a specific wavelength range to display a specific color.

[0046] In the display area (DA), signal lines such as scan lines (also called gate lines) (SL), light emission control lines (ECL), data lines (DL), and driving voltage lines (PL) are also arranged on the substrate (100). The scan lines (SL) and light emission control lines (ECL) may extend mainly in a first direction (D1), and the data lines (DL) and driving voltage lines (PL) may extend in a second direction (D2) that intersects the first direction (D1). Each pixel (PX) is connected to the scan line (SL), light emission control line (ECL), data line (DL), and driving voltage line (PL), and can receive a scan signal (also called a gate signal), a light emission control signal, a data signal, and a driving voltage (ELVDD), respectively, from these signal lines.

[0047] In the non-display area (NDA), a pad portion (PP) is located on the substrate (100) and includes pads (not shown) for receiving signals from outside the display device (10). The pad portion (PP) may be located at the lower end portion of the display device (10) as illustrated, but is not limited thereto. The pads of the pad portion (PP) are electrically connected to the wiring placed in the non-display area (NDA). A flexible printed circuit film (not shown) capable of transmitting signals and voltages from the outside may be bonded to the pad portion (PP).

[0048] A driving device that generates and / or processes various signals for driving pixels (PX) of a display area (DA) may be located in a non-display area (NDA) and may be located on a flexible printed circuit film bonded to a pad portion (PP). The driving device may include a data driver that applies a data signal to data lines (DL), a scan driver that applies a scan signal to scan lines (SL), an emission driver that applies an emission control signal to emission control lines (ECL), and a signal controller that controls the data driver, the scan driver, and the emission driver.

[0049] The scan driver and the light-emitting driver are integrated as driving circuits (DCa, DCb) in the non-display area (NDA) of the display device (10). The driving circuits (DCa, DCb) may include a driving circuit (DCa) located to the left of the display area (DA) and a driving circuit (DCb) located to the right of the display area (DA), and may be formed to be elongated in a second direction (D2). Each driving circuit (DCa, DCb) may include a scan driver and / or a light-emitting driver. Unlike what is illustrated, the driving circuits (DCa, DCb) may be located only on one side of the display area (DA). The driving circuits (DCa, DCb) may be electrically connected to scan lines (SL) and light-emitting control lines (ECL). The driving circuits (DCa, DCb) may include a shift register comprising stages connected dependently, and each stage may include a plurality of transistors and at least one capacitor. Each stage can receive driving circuit signals as input and generate and output gate signals and / or light emission control signals.

[0050] The data driver and the signal control unit may be provided as an integrated circuit chip. The integrated circuit chip may be electrically connected to the display device (10) in the form of a tape carrier package (TCP) or mounted on the display device (10). The data driver and the signal control unit may be formed as a single chip or as separate chips.

[0051] In the non-display area (NDA), driving signal lines (DSLa, DSLb) are located to transmit driving circuit signals to the driving circuit (DCa, DCb) for operating the driving circuit (DCa, DCb). The driving signal lines (DSLa, DSLb) may include driving signal lines (DSLa) located to the left of the display area (DA) and driving signal lines (DSLb) located to the right of the display area (DA). Although the driving signal lines (DSLa, DSLb) are depicted as a single line in FIG. 1 to avoid complexity of the drawing, the driving signal lines (DSLa, DSLb) may include a number of signal lines corresponding to the number of signals applied to the driving circuit (DCa, DCb), and may include a number of more or fewer signal lines. The driving signal lines (DSLa, DSLb) are electrically connected to the pad portion (PP) and may extend in a second direction (D2) parallel to the driving circuit (DCa, DCb) between the driving circuit (DCa, DCb) and the display area (DA).

[0052] Driving circuit signals transmitted from the pad section (PP) to the driving circuit (DCa, DCb) via driving signal lines (DSLa, DSLb) may include scan clock signals, light emission clock signals, gate low voltage (VGL), gate high voltage (VGH), scan frame signals (also called vertical start signals (STV)), light emission frame signals, etc. Scan clock signals, gate low voltage (VGL), and gate high voltage (VGH) may be transmitted to the scan driver of the driving circuit (DCa, DCb) and used to generate a scan signal. Light emission clock signals, gate low voltage (VGL), and gate high voltage (VGH) may be transmitted to the light emission driver of the driving circuit (DCa, DCb) and used to generate a light emission control signal. The scan frame signal may be transmitted to the scan driver to indicate the start of a frame for inputting the scan signal to the display area (DA), and the light emission frame signal may be transmitted to the light emission driver to indicate the start of a frame for inputting the light emission control signal to the display area (DA).

[0053] A common voltage transmission line (CTL) for supplying a common voltage (ELVSS) to pixels (PX) is located in the non-display area (NDA). The common voltage transmission line (CTL) can receive a common voltage (ELVSS) of a predetermined level through the pad portion (PP) and transmit it to the common electrode of the pixels (PX). The common voltage transmission line (CTL) can be formed so that one end and the other end are electrically connected to the pad portion (PP) and surround the display area (DA). On the left and right sides of the display area (DA), the common voltage transmission line (CTL) can be located between the driving circuits (DCa, DCb) and the driving signal lines (DSLa, DSLb).

[0054] A driving voltage transmission line (DTL) for supplying a driving voltage (ELVDD) to pixels (PX) is located in the non-display area (NDA). The driving voltage transmission line (DTL) can be electrically connected to the pad portion (PP) and the driving voltage line (PL), and can be located on the lower side of the display area (DA). The driving voltage (ELVDD) input through the pad portion (PP) can be applied to the pixels (PX) through the driving voltage transmission line (DTL) and the driving voltage line (PL).

[0055] The non-display area (NDA) may include a sealing area (SR). The sealing area (SR) may be spaced apart from the display area (DA). A sealing material (50) may be located in the sealing area (SR). The sealing material (50) may be formed to completely surround the display area (DA). The sealing material (50) may overlap at least partially with the driving circuits (DCa, DCb). When the sealing material (50) and the driving circuits (DCa, DCb) overlap in this way, the area of ​​the non-display area (DNA) on the left and right sides of the display area (DA) can be reduced, thereby reducing the left and right bezel width of the display device. The portion of the substrate (100) outside the sealing area (SR) at the left, right, and upper edges of the display area (DA) may be finally cut off.

[0056] Each pixel (PX) of the display device (10) includes a pixel circuit. The wiring described above may pass through each pixel (PX) or around it and apply a driving signal to each pixel circuit. The pixel circuit may include a transistor and a capacitor, and the transistor may be a thin film transistor. The number of transistors and capacitors in each pixel circuit may vary. Below, the pixel circuit is described using a 7T1C structure in which the pixel circuit includes 7 transistors and 1 capacitor as an example, but it is not limited thereto, and various other modified pixel (PX) structures such as a 2T1C structure, a 3T1C structure, and a 6T2C structure may be applied.

[0057] FIG. 2 is an equivalent circuit diagram of a pixel according to one embodiment of the present invention.

[0058] Referring to FIG. 2, a pixel (PX) located in a display area (DA) in a display device (10) according to one embodiment of the present invention includes thin-film transistors (T1-T7), a holding capacitor (Cst), and an organic light-emitting diode (OLED) connected to display signal lines (SL, SL2, ECL, BCL, DL, PL, VIL).

[0059] Thin film transistors (T1-T7) may include a driving transistor (T1), a switching transistor (T2), a compensation transistor (T3), an initialization transistor (T4), an operation control transistor (T5), a light emission control transistor (T6), and a bypass transistor (T7).

[0060] The display signal lines (SL, SL2, ECL, BCL, DL, PL, VIL) may include a scan line (SL), a front-end scan line (SL2), a light emission control line (ECL), a bypass control line (BCL), a data line (DL), a driving voltage line (PL), and an initialization voltage line (VIL). The scan line (SL) and the front-end scan line (SL2) may be connected to the scan driving unit of the aforementioned driving circuit (DCa, DCb) to receive a scan signal (Sn) and a front-end scan signal (Sn-1), respectively, and the light emission control line (ECL) may be connected to the light emission driving unit of the aforementioned driving circuit (DCa, DCb) to receive a light emission control signal (EM).

[0061] The front scan line (SL2) transmits a front scan signal (Sn-1) to the initialization transistor (T4), the light emission control line (ECL) transmits a light emission control signal (EM) to the operation control transistor (T5) and the light emission control transistor (T6), and the bypass control line (BCL) transmits a bypass signal (BP) to the bypass transistor (T7).

[0062] The data line (DL) can receive a data signal (Dm), the driving voltage line (PL) can receive a driving voltage (ELVDD), and the initialization voltage line (VIL) can receive an initialization voltage (VINT). The initialization voltage (VINT) initializes the driving transistor (T1).

[0063] The gate electrode of the driving transistor (T1) is connected to one end (Cst1) of the holding capacitor (Cst). The drain electrode of the driving transistor (T1) is connected to the driving voltage line (PL) via the operation control transistor (T5). The source electrode of the driving transistor (T1) is connected to the anode of the organic light-emitting diode (OLED) via the light emission control transistor (T6). The driving transistor (T1) controls the driving current supplied to the organic light-emitting diode (OLED) in response to the potential of the second node (N2).

[0064] The gate electrode of the switching transistor (T2) is connected to the scan line (SL). Either the source electrode or the drain electrode of the switching transistor (T2) is connected to the data line (DL). The other source electrode or the drain electrode of the switching transistor (T2) is connected to the drain electrode of the driving transistor (T1) and is connected to the driving voltage line (PL) via the operation control transistor (T5). The switching transistor (T2) is turned on by a scan signal (Sn) applied to the scan line (SL) and provides a data signal (Dm) applied to the data line (DL) to the first node (N1).

[0065] The gate electrode of the compensation transistor (T3) is connected to the scan line (SL). Either the source electrode or the drain electrode of the compensation transistor (T3) is connected to the source electrode of the driving transistor (T1) and is connected to the anode of the organic light-emitting diode (OLED) via the light-emitting control transistor (T6). The other source electrode or the drain electrode of the compensation transistor (T3) is connected together to the source electrode or the drain electrode of the initialization transistor (T4), one end (Cst1) of the holding capacitor (Cst), and the gate electrode of the driving transistor (T1).

[0066] The gate electrode of the initialization transistor (T4) is connected to the front-end scan line (SL2). Either the source electrode or the drain electrode of the initialization transistor (T4) is connected to the initialization voltage line (VIL). The other source electrode or the drain electrode of the initialization transistor (T4) is connected together to one end (Cst1) of the holding capacitor (Cst) and the gate electrode of the driving transistor (T1) via the compensation transistor (T3). The initialization transistor (T4) is turned on in response to the front-end scan signal (Sn-1) applied to the front-end scan line (SL2) and provides an initialization voltage (VINT) to the second node (N2). The second node (N2) is initialized by the initialization voltage (VINT).

[0067] The gate electrode of the operation control transistor (T5) is connected to the light emission control line (ECL). Either the source electrode or the drain electrode of the operation control transistor (T5) is connected to the driving voltage line (PL). The other of the source electrode and the drain electrode of the operation control transistor (T5) is connected to the drain electrode of the driving transistor (T1) and the source electrode or the drain electrode of the switching transistor (T2).

[0068] The gate electrode of the light-emitting control transistor (T6) is connected to the light-emitting control line (ECL). Either the source electrode or the drain electrode of the light-emitting control transistor (T6) is connected to the source electrode of the driving transistor (T1) and the source electrode or the drain electrode of the compensation transistor (T3). The other of the source electrode and the drain electrode of the light-emitting control transistor (T6) is connected to the anode of the organic light-emitting diode (OLED).

[0069] The gate electrode of the bypass transistor (T7) is connected to the bypass control line (BCL). Either the source electrode or the drain electrode of the bypass transistor (T7) is connected together to the source electrode or the drain electrode of the light emission control transistor (T6) and the anode of the organic light-emitting diode (OLED). The other source electrode or the drain electrode of the bypass transistor (T7) is connected together to the initialization voltage line (VIL) and the source electrode or the drain electrode of the initialization transistor (T4).

[0070] The other end (Cst2) of the retention capacitor (Cst) is connected to the driving voltage line (PL). The cathode of the organic light-emitting diode (OLED) is connected to the common voltage line (VSL) that delivers the common voltage (ELVSS). The common voltage line (VSL) or the cathode electrode receives the common voltage (ELVSS).

[0071] The circuit structure of the pixel (PX) is not limited to that shown in FIG. 2, and the number of transistors, the number of capacitors, and the connections between them can be varied in many ways.

[0072] Meanwhile, the thin-film transistors (T1 to T7) may include an oxide semiconductor material. In one embodiment, the thin-film transistors (T1 to T7) may all be NMOS (n-channel MOSFETs) that include an oxide semiconductor material. However, the present invention is not limited thereto, and some of the thin-film transistors (T1 to T7) may be NMOS (n-channel MOSFETs) and the rest may be PMOS (p-channel MOSFETs).

[0073] Since oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not significant even during long driving times. In other words, in the case of oxide semiconductors, the change in image color due to voltage drop is not significant even during low-frequency driving, so low-frequency driving is possible. Therefore, by including oxide semiconductor materials in the thin-film transistors (T1 to T7), it is possible to realize a display device that prevents the occurrence of leakage current while simultaneously reducing power consumption.

[0074] Meanwhile, such oxide semiconductors are sensitive to light, so fluctuations in current amount, etc. may occur due to light from the outside. Therefore, it may be considered to place a metal layer underneath the oxide semiconductor to absorb or reflect light from the outside. When viewed from a direction perpendicular to the upper surface of the substrate (100) (a direction perpendicular to DR1 and DR2), the metal layer located underneath the oxide semiconductor may overlap with the oxide semiconductor.

[0075] The stacked structure of the display device (10) will be described in detail below with reference to FIG. 3.

[0076] FIG. 3 is a cross-sectional view showing an example of a plane cut along AA' and B-B' of FIG. 1.

[0077] The pixel (PX) of the display area (DA) and the driving circuit (DCa) of the non-display area (NDA) each include a plurality of thin-film transistors, but each is described by illustrating only one thin-film transistor (TRp, TRd). For convenience, the thin-film transistor (TRp) of the pixel (PX) is referred to as the first thin-film transistor, and the thin-film transistor (TRd) of the driving circuit (DCa) is referred to as the second thin-film transistor. The illustrated first thin-film transistor (TRp) may be a driving transistor or a light emission control transistor of the pixel (PX), and the second thin-film transistor (TRd) may be an output transistor (also referred to as a buffer transistor) that outputs a scan signal or a light emission control signal from a stage.

[0078] The substrate (100) may be an insulating substrate made of glass, plastic, quartz, ceramic, etc. If the substrate (100) is plastic, it may be formed of polyimide, PET (polyethylene terephthalate), PEN (polyethylene naphthalate), or PC (polycarbonate).

[0079] A lower metal layer (BML) may be disposed on the substrate (100). The lower metal layer (BML) may be formed from a material having light-blocking properties. For example, the lower metal layer (BML) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The lower metal layer (BML) may serve to protect the semiconductor layer by blocking light incident from the outside.

[0080] In one embodiment, the lower metal layer (BML) may be electrically conductive. The lower metal layer (BML) may be electrically connected to either the source electrode (153p) or the drain electrode (154p) of the first thin-film transistor (TRp). The lower metal layer (BML) may be omitted.

[0081] A buffer layer (111) may be disposed on the lower metal layer (BML). The buffer layer (111) may cover the substrate (100) and the lower metal layer (BML). The buffer layer (111) may block impurities that may diffuse from the substrate (100) to the semiconductor layer during the process of forming the semiconductor layer and may reduce the stress on the substrate (100). The buffer layer (111) may increase the adhesion of the semiconductor layer. Although the buffer layer (111) is an insulating layer, it is referred to as a buffer layer considering its functional aspects. The buffer layer (111) may include inorganic insulating materials such as silicon oxide (SiOx) or silicon nitride (SiNx). As an example, the buffer layer (111) may be formed as a multilayer film in which a plurality of inorganic films are alternately stacked. The buffer layer (111) may be omitted.

[0082] A first thin-film transistor (TRp) and a second thin-film transistor (TRd) may be disposed on the buffer layer (111). The first thin-film transistor (TRp) may be formed in the display area (DA), and the second thin-film transistor (TRd) may be formed in the non-display area (NDA). The first thin-film transistor (TRp) may include a first semiconductor layer (120p), a first gate electrode (140p), a first source electrode (153p), and a first drain electrode (154p).

[0083] The first semiconductor layer (120p) may be formed on the buffer layer (111). The first semiconductor layer (120p) may have a thickness in the range of 100 Å to 350 Å, and preferably in the range of 150 Å to 300 Å.

[0084] The first semiconductor layer (120p) may include an oxide semiconductor material. The first semiconductor layer (120p) may include a crystalline oxide semiconductor material. For example, the oxide semiconductor material included in the first semiconductor layer (120p) may include at least one of IZO (InZnO)-based, IGO (InGaO)-based, IGZO (InGaZnO)-based, ITO (InSnO)-based, IGZTO (InGaZnSnO)-based, ITZO (InSnZnO)-based, ZnO-based, and FIZO (FeInZnO)-based oxide semiconductor materials. However, one embodiment of the present invention is not limited thereto, and the first semiconductor layer (120p) may be made of other oxide semiconductor materials having crystallinity and high mobility.

[0085] In one embodiment, the first semiconductor layer (120p) may be an indium-based oxide semiconductor material having an indium (In) content of 60 atomic percent (at%) or more based on the number of atoms among the total metal elements, and preferably, an indium-based oxide semiconductor material having an indium (In) content of 80 at percent or more may be used. For example, the first semiconductor layer (120p) may include at least one of an IGO (InGaO)-based oxide semiconductor material, an IZO (InZnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, and an ITO (InSnO)-based oxide semiconductor material having an indium (In) content of 80 at percent or more.

[0086] The first semiconductor layer (120p) contains a high concentration of indium (In), so that the channel region (131p) can have high mobility characteristics. Because the first semiconductor layer (120p) has high mobility characteristics, the first thin-film transistor (TRp) can have excellent electrical characteristics.

[0087] The first semiconductor layer (120p) can be crystallized by a heat treatment process. Specifically, the first semiconductor layer (120p) can be crystallized by heat treatment after being formed by deposition and patterning. In one embodiment, the first semiconductor layer (120p) may include a crystallization control element that facilitates patterning by preventing crystallization during the deposition process and subsequently allowing the first semiconductor layer (120p) to crystallize through a heat treatment process. The crystallization control element is an element with a strong bonding affinity with oxygen, and may include, for example, at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), and germanium (Ge).

[0088] The first semiconductor layer (120p) may include a first channel region (121p) and a first source region (122p) and a first drain region (123p) connected to both sides of the first channel region (121p). The first source region (132p) and the first drain region (133p) may be formed by selectively conducting a crystalline oxide semiconductor material. The first channel region (121p) may be a non-conducting portion. The first channel region (121p) may overlap with the first gate electrode (140p) and may overlap with the lower metal layer (BML). The first source region (122p) and the first drain region (123p) may not overlap with the first gate electrode (140p).

[0089] Since the first semiconductor layer (120p) is made of a crystalline oxide semiconductor material, the first channel region (121p) that is not conductive may have a crystalline structure. For example, the first channel region (121p) may include at least one crystal structure among a cubic crystal structure, a Bixbyte crystal structure, a cubic Bixbyte crystal structure, a spinel crystal structure, a hexagonal crystal structure, and a wurtzite crystal structure.

[0090] The first channel region (121p) can have excellent physical and chemical stability because it has a crystalline structure. That is, the first channel region (121p) can be prevented from being damaged or having its physical properties altered during the manufacturing and use processes of the display device (10). Accordingly, the first thin-film transistor (TRp), which is the driving transistor of the pixel circuit, can stably control the driving current supplied to the organic light-emitting diode (OLED), and the display device (10) including the first thin-film transistor (TRp) has excellent driving stability.

[0091] A first gate insulating layer (112p) may be disposed on the first semiconductor layer (120p). The first gate insulating layer (112p) is an insulating layer made of an insulating material and may include at least one of silicon oxide, silicon nitride, and metal-based oxide. For example, the first gate insulating layer (112p) may include an inorganic insulating layer such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. Each of the first gate insulating layers (112p) may have a single film structure or a multilayer structure.

[0092] The first gate insulating layer (112p) can be patterned in a shape corresponding to the first gate electrode (140p). The first gate insulating layer (112p) does not cover the first source region (132p) and the first drain region (133p), so that the interlayer insulating layer (113) can come into direct contact with the first source region (132p) and the first drain region (133p). Accordingly, the first source region (132p) and the first drain region (133p) can be conductive by hydrogen diffusing from the adjacent interlayer insulating layer (113).

[0093] However, the present invention is not limited thereto, and the first gate insulating layer (112p) may be formed to cover both the buffer layer (111) and the first semiconductor layer (120p).

[0094] A first gate electrode (140p) may be disposed on the first gate insulating layer (112p). The first gate electrode (140p) may overlap with the first channel region (121p) of the first semiconductor layer (120p). The first gate electrode (140p) may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The first gate electrode (140p) may have a multilayer structure comprising at least two conductive films having different physical properties.

[0095] The interlayer insulating layer (113) covers the first semiconductor layer (120p) and the first gate electrode (140p) and may be disposed on the buffer layer (111) or the substrate (100). For example, the interlayer insulating layer (113) may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0096] A first source electrode (153p) and a first drain electrode (154p) may be disposed on an interlayer insulating layer (113). The first source electrode (153p) and the first drain electrode (154p) may each include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. The first source electrode (153p) and the first drain electrode (154p) may each be made of a single layer made of a metal or an alloy of a metal, or may be made of two or more layers.

[0097] The first source electrode (153p) and the first drain electrode (154p) can each be connected to the first semiconductor layer (120p) through a contact hole. Specifically, the first source electrode (153p) and the first drain electrode (154p) can be spaced apart from each other and connected to the first source region (122p) and the first drain region (123p) of the first semiconductor layer (120p), respectively. The first source electrode (153p) and the first drain electrode (154p) can transmit an electrical signal to the first channel region (121p). In one embodiment, the first source electrode (153p) or the first drain electrode (154p) can be connected to the lower metal layer (BML) through a contact hole.

[0098] In one embodiment and drawing of the present invention, the first source electrode (153p) and the first drain electrode (154p) are distinguished only for convenience of explanation, and the first source electrode (153p) and the first drain electrode (154p) are not limited by the drawings and the descriptions above. The first source electrode (153p) and the first drain electrode (154p) may be interchangeable.

[0099] The flattening layer (114) may be positioned on the interlayer insulating layer (113) covering the first source electrode (153p) and the first drain electrode (154p). The flattening layer (114) may serve to eliminate step height and flatten the surface to increase the luminous efficiency of the organic light-emitting diode (OLED) formed thereon. The flattening layer (114) may include an organic insulating material. For example, the flattening layer (114) may include polyimide, polyamide, polyacrylate, polyphenylene ether, polyphenylene sulfide, unsaturated polyester, epoxy resin, phenolic resin, etc.

[0100] An organic light-emitting diode (OLED) may be disposed on the planarization layer (114). The organic light-emitting diode (OLED) may include a pixel electrode (210), an intermediate layer (220) including a light-emitting layer, and a counter electrode (230). Here, the pixel electrode (210) may be an anode which is a hole injection electrode, and the counter electrode (230) may be a cathode which is an electron injection electrode. Conversely, the pixel electrode (210) may be a cathode, and the counter electrode (230) may be an anode.

[0101] The pixel electrode (210) may be a (semi)transparent electrode or a reflective electrode. For example, the pixel electrode (210) may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or semitransparent electrode layer located on the reflective layer. The transparent or semitransparent electrode layer may have at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). For example, the pixel electrode (210) may have a three-layer structure of ITO / Ag / ITO.

[0102] A pixel defining film (115) may be disposed on the flattening layer (114). The pixel defining film (115) may serve to prevent arcs from occurring at the edge of the pixel electrode (210) by increasing the distance between the edge of the pixel electrode (210) and the opposing electrode (230) above the pixel electrode (210). The pixel defining film (115) may be formed by a method such as spin coating using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0103] At least a portion of the intermediate layer (220) of the organic light-emitting diode (OLED) may be located within an opening formed by the pixel defining film (115). The light-emitting region of the organic light-emitting diode (OLED) may be defined by the opening.

[0104] The intermediate layer (220) may include a light-emitting layer. The light-emitting layer may include an organic material containing a fluorescent or phosphorescent material that emits red, green, blue, or white light. The light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be optionally further disposed below and above the light-emitting layer.

[0105] The light-emitting layer may have a patterned shape corresponding to each of the pixel electrodes (210). Various variations are possible, such as the layer other than the light-emitting layer included in the intermediate layer (220) being integral across the plurality of pixel electrodes (210).

[0106] The counter electrode (230) may be a transparent electrode or a reflective electrode. For example, the counter electrode (230) may be a transparent or translucent electrode and may include a metal thin film with a low work function comprising Li, Ca, LiF, Al, Ag, Mg, and compounds thereof. Additionally, the counter electrode (230) may further include a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 located on the metal thin film. The counter electrode (230) may be integrally formed across the entire front surface of the display area (DA) and may be placed on top of the intermediate layer (220) and the pixel defining film (115).

[0107] The second thin-film transistor (TRd) is placed in the non-display area (NDA) and may include a second semiconductor layer (130d), a second gate electrode (140d), a second source electrode (151d), and a second drain electrode (152d).

[0108] The second semiconductor layer (130d) may be formed on the same layer as the first semiconductor layer (120p) of the first thin-film transistor (TRp). For example, both the first semiconductor layer (120p) and the second semiconductor layer (130d) may be formed on the buffer layer (111). The second semiconductor layer (130d) may have a thickness in the range of 50 Å to 300 Å, and preferably in the range of 100 Å to 250 Å.

[0109] The second semiconductor layer (130d) may include a second channel region (131d) and a second source region (132d) and a second drain region (133d) connected to both sides of the second channel region (131d). The second source region (132d) and the second drain region (133d) may be formed through selective conductivity of the semiconductor material, and the second channel region (131d) may be a non-conductive portion. The second channel region (131d) may overlap with the second gate electrode (140d), and the second source region (132d) and the second drain region (133d) may not overlap with the second gate electrode (140d). The second channel region (131d) may overlap with the lower metal layer (BML). The electron mobility of the second channel region (131d) may be higher than the electron mobility of the first channel region (121p) of the first semiconductor layer (120p).

[0110] The second semiconductor layer (130d) may include an oxide semiconductor material. For example, the second semiconductor layer (130d) may include at least one of an IZO (InZnO)-based, IGO (InGaO)-based, IGZO (InGaZnO)-based, ITO (InSnO)-based, IGZTO (InGaZnSnO)-based, ITZO (InSnZnO)-based, ZnO-based, and FIZO (FeInZnO)-based oxide semiconductor material.

[0111] The second semiconductor layer (130d) may include an oxide semiconductor material different from that of the first semiconductor layer (120p). For example, the first semiconductor layer (120p) may include an IGO (InGaO)-based oxide semiconductor material, and the second semiconductor layer (130d) may include an IGZTO (InGaZnSnO)-based oxide semiconductor material.

[0112] The second semiconductor layer (130d) may use an indium-based oxide semiconductor material having an indium (In) content of 50 at% or more. Preferably, the indium (In) content of the second semiconductor layer (130d) may be 60 at% or more. In one embodiment, the indium (In) content of the total metal elements in the second semiconductor layer (130d) may be lower than that of the first semiconductor layer (120p).

[0113] The second semiconductor layer (130d) may include an amorphous oxide semiconductor material. That is, the second channel region (131d) of the second semiconductor layer (130d) may be amorphous. Oxide semiconductors possess oxygen vacancies, thereby exhibiting high electron mobility characteristics even in an amorphous state. As such oxide semiconductors crystallize, oxygen vacancies decrease, and electron mobility decreases. In other words, a semiconductor layer containing a crystalline oxide semiconductor material has lower mobility characteristics than in an amorphous state.

[0114] A display device (10) according to one embodiment of the present invention can provide a high-output scan signal or light emission control signal through a thin-film transistor having a relatively higher electron mobility than the driving transistor of a pixel circuit by placing a second thin-film transistor (TRd) including a second semiconductor layer (130d) made of an amorphous oxide semiconductor material in the output transistor of a driving circuit, and the power consumption of the display device (10) can be reduced. In addition, the driving transistor of the pixel circuit can improve the driving stability of the display device (10) by having excellent stability instead of having a relatively low electron mobility.

[0115] A second gate insulating layer (112d) may be disposed on the second semiconductor layer (130d). The second gate insulating layer (112d) is an insulating layer made of an insulating material and may include at least one of silicon oxide, silicon nitride, and a metal-based oxide. The second gate insulating layer (112d) may be formed from the same material in the same manufacturing step as the first gate insulating layer (112p).

[0116] The second gate insulating layer (112d) can be patterned in a shape corresponding to the second gate electrode (140d). In this case, the interlayer insulating layer (113) can be in direct contact with the second source region (132d) and the second drain region (133d), and the second source region (132d) and the second drain region (133d) can be conductive by hydrogen diffusing from the adjacent interlayer insulating layer (113).

[0117] However, the present invention is not limited thereto, and the second gate insulating layer (112d) may be formed to cover both the buffer layer (111) and the second semiconductor layer (130d).

[0118] A second gate electrode (140d) may be disposed on the second gate insulating layer (112p). The second gate electrode (140d) may overlap with the second channel region (131d) of the second semiconductor layer (130d). The second gate electrode (140d) may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The second gate electrode (140d) may have a multilayer structure comprising at least two conductive films having different physical properties.

[0119] The interlayer insulating layer (113) covers the second semiconductor layer (130d) and the second gate electrode (140d) and may be disposed on the buffer layer (111) or the substrate (100). The interlayer insulating layer (113) may be formed integrally across the display area (DA) and the non-display area (NDA).

[0120] A second source electrode (151d) and a second drain electrode (152d) may be disposed on the interlayer insulating layer (113). The second source electrode (151d) and the second drain electrode (152d) may each comprise at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0121] The second source electrode (151d) and the second drain electrode (152d) can each be connected to the second semiconductor layer (130d) through a contact hole. Specifically, the second source electrode (151d) and the second drain electrode (152d) can be spaced apart from each other and connected to the second source region (132d) and the second drain region (133d) of the second semiconductor layer (130d), respectively. The second source electrode (151d) and the second drain electrode (152d) can transmit an electrical signal to the second channel region (131d).

[0122] Hereinafter, variations of the display device (10) are described with reference to FIGS. 4 to 7, and configurations identical to the display device (10) described with reference to FIGS. 1 to 3 are described using the same drawing number.

[0123] FIG. 4 is a cross-sectional view of a display device (10) according to another embodiment of the present invention. Compared to the display device (10) of FIG. 3, the display device of FIG. 4 differs in the first thin-film transistor (TRp). The following description focuses on the differences mentioned above, and redundant descriptions are omitted.

[0124] Referring to FIG. 4, the first thin-film transistor (TRp) may include a first semiconductor layer (120p), a third semiconductor layer (130p), a first gate electrode (140p), a first source electrode (153p), and a first drain electrode (154p).

[0125] A third semiconductor layer (130p) may be formed on the first semiconductor layer (120p). The third semiconductor layer (130p) may include an oxide semiconductor material. The third semiconductor layer (130p) may be amorphous. In one embodiment, the third semiconductor layer (130p) may be made of the same material as the second semiconductor layer (130d) of the second thin-film transistor (TRd). The second semiconductor layer (130d) and the third semiconductor layer (130p) may be formed by the same process using the same material. The thickness of the third semiconductor layer (130p) may be formed to be the same as the thickness of the first semiconductor layer (120p), but is not limited thereto.

[0126] The third semiconductor layer (130p) may overlap with the first channel region (121p) of the first semiconductor layer (120p). The width of the third semiconductor layer (130p) may be formed to correspond to the first channel region (121p) of the first semiconductor layer (120p). Here, the width refers to the length of a cross-section cut along a direction perpendicular to the upper surface of the substrate (100) (a direction perpendicular to DR1 and DR2). That is, with respect to a direction parallel to the upper surface of the substrate (100), the area of ​​the third semiconductor layer (130p) may be smaller than the area of ​​the first semiconductor layer (120p).

[0127] The width of the third semiconductor layer (130p) may be smaller than the width of the first semiconductor layer (120p) and larger than the width of the first gate electrode (140p). When the side of the third semiconductor layer (130p) is formed to be tapered, the width (d2) of the lower surface of the third semiconductor layer (130p) may be smaller than the width of the upper surface of the first semiconductor layer (120p) that the lower surface of the third semiconductor layer (130p) contacts, and may be larger than or equal to the width of the upper surface of the first channel region (121p). The width (d1) of the upper surface of the third semiconductor layer (130p) may be larger than or equal to the width of the first gate electrode (140p). The third semiconductor layer (130p) may not overlap with the first source electrode (153p) and the first drain electrode (154p).

[0128] As the width of the third semiconductor layer (130p) is formed to correspond to the first channel region (121p) of the first semiconductor layer (120p), the third semiconductor layer (130p) can serve as a protective layer that protects the first channel region (121p) of the first semiconductor layer (120p). For example, the third semiconductor layer (130p) can prevent hydrogen from directly flowing into the first channel region (121p) of the first semiconductor layer (120p) when the first gate insulating layer (112p) is formed.

[0129] In addition, a display device (10) according to another embodiment of the present invention can prevent a problem from occurring in which the length or width, etc. of the first channel region (121p) of the first semiconductor layer (120p) is formed differently from what was intended by having a side of the third semiconductor layer (130p) with an inclined surface corresponding to the side of the first gate electrode (140p) and having a lower surface of the third semiconductor layer (130p) with a larger size than the first channel region (121p).

[0130] Meanwhile, in another embodiment of the present invention, another display device (10) may have a first gate insulating layer (112p) disposed between a third semiconductor layer (130p) and a first gate electrode (140p). The first gate insulating layer (112p) may be patterned in a shape corresponding to the first gate electrode (140p), but is not limited thereto, and the first gate insulating layer (112p) may be formed to cover all of the buffer layer (111), the first semiconductor layer (120p), and the third semiconductor layer (130p).

[0131] FIG. 5 is a cross-sectional view of a display device (10) according to another embodiment of the present invention. The display device (10) of FIG. 5 differs from the display device (10) of FIG. 3 in that it has a first thin-film transistor (TRp). The following description focuses on the differences mentioned above, and redundant descriptions are omitted.

[0132] Referring to FIG. 5, the first thin-film transistor (TRp) may include a first semiconductor layer (120p), a third semiconductor layer (130p), a first gate electrode (140p), a first source electrode (153p), and a first drain electrode (154p).

[0133] A third semiconductor layer (130p) may be formed on the first semiconductor layer (120p). The third semiconductor layer (130p) may include an oxide semiconductor material. The third semiconductor layer (130p) may be amorphous. In one embodiment, the third semiconductor layer (130p) may be made of the same material as the second semiconductor layer (130d) of the second thin-film transistor (TRd). The second semiconductor layer (130d) and the third semiconductor layer (130p) may be formed by the same process using the same material.

[0134] The third semiconductor layer (130p) can be formed to overlap with the first semiconductor layer (120p). In other words, the third semiconductor layer (130p) can be formed to completely cover the first semiconductor layer (120p) on the first semiconductor layer (120p).

[0135] The third semiconductor layer (130p) may include a third channel region (131p) and a third source region (132p) and a third drain region (133p) connected to both sides of the third channel region (131p). The third source region (132p) and the third drain region (133p) may be formed by selectively conducting an amorphous oxide semiconductor material, and the third channel region (131p) may be a non-conducting portion. The third channel region (131p) may overlap the first channel region (121p), and the third source region (132p) and the third drain region (133p) may overlap the first source region (122p) and the first drain region (123p), respectively.

[0136] The third channel region (131p) of the third semiconductor layer (130p) may have a higher carrier concentration than the first channel region (121p) of the first semiconductor layer (120p).

[0137] The first gate electrode (140p) can overlap both the first channel region (121p) and the third channel region (131p). The first source electrode (153p) and the first drain electrode (154p) can be connected to the third source region (132p) and the third drain region (133p), respectively. The first source electrode (153p) and the first drain electrode (154p) can transmit electrical signals to the first channel region (121p) and the third channel region (131p).

[0138] The first gate insulating layer (112p) may be disposed between the third semiconductor layer (130p) and the first gate electrode (140p). The first gate insulating layer (112p) may be patterned in a shape corresponding to the first gate electrode (140p), but is not limited thereto, and the first gate insulating layer (112p) may be formed to cover the buffer layer (111), the first semiconductor layer (120p), and the third semiconductor layer (130p).

[0139] FIG. 6 is a cross-sectional view of a display device (10) according to another embodiment of the present invention.

[0140] Compared to the display device (10) of FIG. 5, the display device (10) of FIG. 6 has a difference in the thickness of the third semiconductor layer (130p) of the first thin-film transistor (TRp) and the second semiconductor layer (130d) of the second thin-film transistor (TRd). The following description focuses on the differences mentioned above, and redundant descriptions are omitted.

[0141] Referring to FIG. 6, the thickness (t2) of the third semiconductor layer (130p) may be smaller than the thickness (t1) of the first semiconductor layer (120p). The third semiconductor layer (130p) may be formed using the same material and process as the second semiconductor layer (130d), and the second semiconductor layer (130d) and the third semiconductor layer (130p) may have the same thickness. That is, when the second semiconductor layer (130d) is formed on the same layer as the first semiconductor layer (120p) (e.g., buffer layer (111)), the thickness of the second semiconductor layer (130d) may be smaller than the thickness of the first semiconductor layer (130p), thereby making the thickness (t2) of the third semiconductor layer (130p) smaller than the thickness (t1) of the first semiconductor layer (120p).

[0142] However, the present invention is not limited thereto, and the thickness (t2) of the third semiconductor layer (130p) may be greater than the thickness (t1) of the first semiconductor layer (120p).

[0143] FIG. 7 is a cross-sectional view of a display device (10) according to another embodiment of the present invention. The display device (10) of FIG. 7 differs from the display device (10) of FIG. 4 in that it has a gate insulating layer (112). The following description focuses on the differences mentioned above, and redundant descriptions are omitted.

[0144] Referring to FIG. 7, the gate insulating layer (112) may be formed to cover the first semiconductor layer (120p) and the third semiconductor layer (130p) of the first thin-film transistor (TRp), as well as the second semiconductor layer (130d) and the buffer layer (111) of the second thin-film transistor (TRd). In this case, the first source electrode (153p), the first drain electrode (154p), the second source electrode (151d), and the second drain electrode (152d) may each penetrate the gate insulating layer (112) and be connected to the first semiconductor layer (120p) or the second semiconductor layer (130d).

[0145] Hereinafter, a method for manufacturing a display device (10) according to an embodiment of the present invention will be described with reference to FIGS. 8a to 8h. In FIGS. 8a to 8h, the first region (I) may be a region where a second thin-film transistor (TRd) is formed and may correspond to the non-display region (NDA) of FIGS. 3 to 7. The second region (II) may be a region where a first thin-film transistor (TRp) is formed and may correspond to the display region (DA) of FIGS. 3 to 7.

[0146] First, referring to FIG. 8a, a method for manufacturing a display device (10) according to one embodiment of the present invention forms a first semiconductor material layer (120') on a substrate (100) on which a lower metal layer (BML) and a buffer layer (111) are formed. The first semiconductor material layer (120') may be formed on the buffer layer (111) and may be formed in both the first region (I) and the second region (II).

[0147] The first semiconductor material layer (120') may include a crystalline oxide semiconductor material and may be formed as a thin film. The first semiconductor material layer (120') may be formed using a vapor deposition method such as sputtering or pulsed laser deposition.

[0148] Next, as illustrated in FIG. 8b, a first semiconductor material layer (120') is patterned to form a first semiconductor pattern (120p'). The patterning can be performed by forming a photoresist pattern corresponding to the portion on the first semiconductor material layer (120') where the first semiconductor layer (120p) is to be formed, and then using a wet etching method with an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, phosphoric acid, nitric acid, and a mixture of acetic acid. Of course, dry etching can be used, or a combination of dry etching and wet etching can be used.

[0149] Next, the first semiconductor pattern (120p') is heat-treated to form a crystalline first semiconductor pattern (120p'). A temperature of 350°C or higher may be used for the heat treatment of the first semiconductor pattern (120p'), and oxygen may be injected during the heat treatment process.

[0150] Next, as illustrated in FIG. 8c, a second semiconductor material layer (130') is formed on top of the first semiconductor pattern (120p'). The second semiconductor material layer (130') can be formed in both the first region (I) and the second region (II). That is, the second semiconductor material layer (130') is formed on the buffer layer (111) in the first region (I) and can be stacked with the first semiconductor pattern (120p') in the second region (II).

[0151] Next, as illustrated in FIG. 8d, the second semiconductor material layer (130') is patterned to form a second semiconductor pattern (130d') and a third semiconductor pattern (130p'). The patterning of the second semiconductor material layer (130') can be achieved by forming a photoresist pattern corresponding to the portion where the second semiconductor layer (130d) is to be formed and the portion where the third semiconductor layer (130p) is to be formed, followed by an etching process. That is, the second semiconductor pattern (130d') and the third semiconductor pattern (130p') can be formed simultaneously.

[0152] The patterning step of the second semiconductor material layer (130') can be performed after the crystallization of the first semiconductor pattern (120p'). Accordingly, the first semiconductor pattern (120p') can be stably maintained even during the patterning of the second semiconductor material layer (130').

[0153] Meanwhile, in one embodiment, when patterning the second semiconductor material layer (130'), the third semiconductor pattern (130p') corresponding to the third semiconductor layer (130p) is not formed, so the third semiconductor layer (130p) may not be formed on the first semiconductor layer (120p).

[0154] Next, as shown in FIGS. 8e and 8f, a gate insulating material layer (112') and a gate electrode material layer (140') covering a first semiconductor pattern (120p'), a second semiconductor pattern (130d'), and a third semiconductor pattern (130p') are sequentially formed on the buffer layer (111).

[0155] The gate insulating material layer (112') may include inorganic materials such as silicon oxide, silicon nitride and / or silicon oxynitride, and may be formed through CVD or ALD (atomic layer deposition).

[0156] The gate electrode material layer (140') may include molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may be formed as a single film or a multilayer film. The gate electrode material layer (140') may be formed by a deposition method such as chemical vapor deposition, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition (ALD), but is not limited thereto.

[0157] Next, as illustrated in FIG. 8g, the gate insulating material layer (112') and the gate electrode material layer (140') are patterned to form the first gate electrode (140p), the first gate insulating layer (112p), the second gate electrode (140d), and the second gate insulating layer (112d). In one embodiment, the gate insulating material layer (112') may not be patterned when the gate electrode material layer (140') is patterned, and the gate insulating material layer (112') may form a single gate insulating layer (112) across the first region (I) and the second region (II).

[0158] Next, the first semiconductor pattern (120p') and the second semiconductor pattern (130d') are doped with impurities to form the first semiconductor layer (120p) and the second semiconductor layer (130d). The first semiconductor layer (120p) can be formed by injecting impurities into the first source region (122p) and the first drain region (123p), excluding the first channel region (121p), and the second semiconductor layer (130d) can be formed by injecting impurities into the second source region (132d) and the second drain region (133d), excluding the second channel region (131d).

[0159] The third semiconductor pattern (130p') forms the third semiconductor layer (130p). In one embodiment, the width of the third semiconductor layer (130p) may correspond to the width of the first channel region (121p). In this case, the third semiconductor layer (130p) may serve as a mask that protects the first channel region (121p) when the first semiconductor layer (120p) is doped.

[0160] Next, as illustrated in FIG. 8h, an interlayer insulating layer (113) is formed over the front surface of the buffer layer (111) on top of the first gate electrode (140p) and the second gate electrode (140d), and a first through-hole (c1) that penetrates the interlayer insulating layer (113) and exposes the first source region (122p) of the first semiconductor layer (120p), a second through-hole (c2) that exposes the first drain region (123p), a third through-hole (c3) that exposes the second source region (132d) of the second semiconductor layer (130d), and a fourth through-hole (c4) that exposes the second drain region (133d) are formed, and a first source electrode (153p), a first drain electrode (154p), a second source electrode (151d), and a second drain electrode (152d) are formed on top of the interlayer insulating layer (113).

[0161] The first source electrode (153p), the first drain electrode (154p), the second source electrode (151d), and the second drain electrode (152d) can be formed by forming a conductive material layer using various deposition methods such as chemical vapor deposition, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD), and then patterning the conductive material layer.

[0162] The display device (10) according to an embodiment of the present invention can be applied to various electronic devices. An electronic device according to one embodiment includes the display device (10) described above and may further include a module or device having other additional functions in addition to the display device (10).

[0163] FIG. 9 is a block diagram of an electronic device (1000) according to an embodiment of the present invention. Referring to FIG. 9, an electronic device (1000) according to an embodiment of the present invention may include a display module (1100), a processor (1200), a memory (1300), and a power module (1400).

[0164] The processor (1200) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0165] The memory (1300) may store data information necessary for the operation of the processor (1200) or the display module (1100). When the processor (1200) executes an application stored in the memory (1300), a video data signal and / or an input control signal is transmitted to the display module (1100), and the display module (1100) can process the received signal and output video information through a display screen.

[0166] The power module (1400) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (1000).

[0167] At least one of each component of the electronic device (1000) described above may be included within a display device according to the embodiments described above. Additionally, some of the individual modules functionally included within a single module may be included within the display device, while others may be provided separately from the display device. For example, the display device may include a display module (1100), and the processor (1200), memory (1300), and power module (1400) may be provided in the form of other devices within the electronic device (1000) other than the display device.

[0168] FIG. 10 is a schematic diagram of an electronic device according to various embodiments.

[0169] Referring to FIG. 10, various electronic devices to which a display device according to the embodiments is applied may include not only image display electronic devices such as a smartphone (1000_1a), a tablet PC (1000_1b), a laptop (1000_1c), a TV (1000_1d), and a desk monitor (1000_1e), but also wearable electronic devices including display modules such as smart glasses (1000_2a), a head-mounted display (1000_2b), and a smart watch (1000_2c), and automotive electronic devices (1000_3) including display modules such as a CID (Center Information Display) and a room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0170] As described above, the display device (10) and electronic device (1000) according to embodiments of the present invention may selectively improve the characteristics of the driving transistor of the pixel circuit and the output transistor of the driving circuit by placing a first thin-film transistor (TRp) including a first semiconductor layer (120p) made of a crystalline oxide semiconductor in the driving transistor of the pixel circuit and placing a second thin-film transistor (TRd) including a second semiconductor layer (130d) made of an amorphous oxide semiconductor in the output transistor of the driving circuit, and both electrical characteristics and driving stability may be improved.

[0171] In addition, the display device (10) and electronic device (1000) according to embodiments of the present invention may have improved process stability and may reduce process costs and time.

[0172] Each of the embodiments described above can be implemented independently, but it goes without saying that the structure of each embodiment can be applied in combination to other embodiments.

[0173] As such, the present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims.

[0174] The specific practices described in the embodiments are examples and do not limit the scope of the embodiments in any way. Furthermore, unless specifically stated as "essential," "importantly," etc., components may not be strictly necessary for the application of the invention.

[0175] In the specification of the embodiments (particularly in the claims), the use of the term "the above" and similar descriptive terms may be singular or plural. Furthermore, where a range is described in the embodiments, it is considered to include the invention with respect to individual values ​​within said range (unless otherwise stated), and is equivalent to describing each individual value constituting said range in the detailed description. Finally, regarding the steps constituting the method according to the embodiments, unless explicitly stated or otherwise stated, said steps may be performed in a suitable order. The embodiments are not necessarily limited by the order in which said steps are described. The use of any examples or exemplary terms in the embodiments is merely for the purpose of describing the embodiments in detail, and the scope of the embodiments is not limited by said examples or exemplary terms unless limited by the claims. Furthermore, those skilled in the art will understand that various modifications, combinations, and changes may be made according to design conditions and factors within the scope of the claims or equivalents to which they are added. Explanation of the symbols

[0176] 10: Display device 100 : Substrate 111 : Buffer layer 120p: First semiconductor layer 130d: Second semiconductor layer Page 130: Third semiconductor layer TRp: First thin-film transistor TRd : Second thin-film transistor 1000: Electronic device

Claims

Claim 1 A display device comprising: a substrate including a display area and a non-display area surrounding the display area; a pixel circuit including a first thin-film transistor including a first semiconductor layer and a first gate electrode that overlaps the display area; and a driving circuit including a second thin-film transistor including a second semiconductor layer and a second gate electrode that is connected to the pixel circuit and overlaps the non-display area, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor material, and the electron mobility of the second thin-film transistor is higher than the electron mobility of the first thin-film transistor. Claim 2 A display device according to claim 1, wherein the first semiconductor layer comprises a crystalline oxide semiconductor material and the second semiconductor layer comprises an amorphous oxide semiconductor material. Claim 3 A display device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are disposed on the same layer. Claim 4 A display device according to claim 1, wherein the first thin-film transistor further comprises a third semiconductor layer disposed on the first semiconductor layer. Claim 5 A display device according to claim 4, wherein the third semiconductor layer comprises the same material as the second semiconductor layer. Claim 6 A display device according to claim 4, wherein the third semiconductor layer comprises an amorphous oxide semiconductor material and the first semiconductor layer comprises a crystalline oxide semiconductor material. Claim 7 In claim 4, the display device wherein the third semiconductor layer overlaps with the first semiconductor layer. Claim 8 A display device according to claim 4, wherein the width of the third semiconductor layer is smaller than the width of the first semiconductor layer. Claim 9 A display device according to claim 4, wherein the thickness of the third semiconductor layer is the same as the thickness of the first semiconductor layer. Claim 10 A display device according to claim 4, wherein the thickness of the third semiconductor layer is the same as the thickness of the second semiconductor layer, and the thickness of the second semiconductor layer is smaller than the thickness of the first semiconductor layer. Claim 11 A display device according to claim 4, wherein the width of the third semiconductor layer is smaller than the width of the first semiconductor layer and larger than the width of the first gate electrode. Claim 12 A display device according to claim 1, wherein the first thin-film transistor is a driving thin-film transistor of the pixel circuit. Claim 13 A display device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer comprise indium (In), and the indium content of the first semiconductor layer is greater than the indium content of the second semiconductor layer. Claim 14 A display device comprising: a substrate including a display area and a non-display area surrounding the display area; a pixel circuit superimposed on the display area; and a light-emitting element electrically connected to the pixel circuit to generate light; wherein the pixel circuit comprises: a driving transistor including a drain electrode connected to a first node, a gate electrode connected to a second node, and a source electrode connected to a third node; a switching transistor applying a data signal to the first node in response to a scan signal; and an initialization transistor applying an initialization voltage to the second node in response to an initialization control signal; and wherein the driving transistor comprises a first semiconductor layer including a crystalline oxide semiconductor material. Claim 15 A display device according to claim 14, wherein the first semiconductor layer comprises indium (In), and the indium content of the first semiconductor layer is 80 at% or more. Claim 16 A display device according to claim 14, wherein the driving transistor further comprises a third semiconductor layer disposed on the first semiconductor layer, and the third semiconductor layer comprises an amorphous oxide semiconductor material. Claim 17 A display device according to claim 14, further comprising a driving circuit including an output transistor that overlaps the non-display area, wherein the output transistor includes a second semiconductor layer comprising an amorphous oxide semiconductor material. Claim 18 An electronic device comprising a display device, wherein the display device comprises: a substrate including a display area and a non-display area surrounding the display area; a pixel circuit including a first thin-film transistor including a first semiconductor layer and a first gate electrode that overlaps the display area; and a driving circuit including a second thin-film transistor including a second semiconductor layer and a second gate electrode that is connected to the pixel circuit and overlaps the non-display area, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor material, and the electron mobility of the second thin-film transistor is higher than the electron mobility of the first thin-film transistor. Claim 19 An electronic device according to claim 18, wherein the first semiconductor layer comprises a crystalline oxide semiconductor material and the second semiconductor layer comprises an amorphous oxide semiconductor material. Claim 20 An electronic device comprising a display device, wherein the display device comprises: a substrate comprising a display area and a non-display area surrounding the display area; a pixel circuit superimposed on the display area; and a light-emitting element electrically connected to the pixel circuit to generate light; wherein the pixel circuit comprises: a driving transistor comprising a drain electrode connected to a first node, a gate electrode connected to a second node, and a source electrode connected to a third node; a switching transistor that applies a data signal to the first node in response to a scanning signal; and an initialization transistor that applies an initialization voltage to the second node in response to an initialization control signal; and wherein the driving transistor comprises a first semiconductor layer comprising a crystalline oxide semiconductor material.

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