Semiconductor package and method of manufacturing the same
Patent Information
- Application Number
- KR1020250024951
- Authority / Receiving Office
- KR · KR
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-26
- Publication Date
- 2026-09-02
Smart Images
Figure PAT00001_ABST
Abstract
Description
Technology Field
[0001] The present disclosure relates to a semiconductor package and a method for manufacturing the same. Background Technology
[0002] Recently, there has been a demand for high performance, large capacity, and high reliability in semiconductor packages installed in electronic devices. Accordingly, the development of semiconductor packages containing at least one embedded semiconductor chip is underway. The problem to be solved
[0003] One of the technical problems that the technical concept of the present disclosure aims to solve is to provide a semiconductor package with improved reliability and a method for manufacturing the same. means of solving the problem
[0004] As a means of solving the aforementioned problem, one embodiment of the present disclosure provides a semiconductor package comprising: a lower redistribution structure including a lower redistribution layer; a lower chip structure on the lower redistribution structure; a sealing material covering the lower chip structure; a post penetrating the sealing material and connected to the lower redistribution layer; and external connection bumps disposed below the lower redistribution structure and electrically connected to the lower redistribution layer, wherein the post comprises: a first portion disposed on the lower redistribution layer of the lower redistribution structure and extending vertically from the lower redistribution layer; and a second portion on the first portion, wherein the width of the lower region of the second portion is smaller than the width of the upper region of the first portion, and the surface roughness of the side of the second portion is greater than the surface roughness of the side of the first portion.
[0006] Additionally, a lower redistribution structure including a lower redistribution layer; a chip structure on the lower redistribution structure; a sealant covering the chip structure; an upper redistribution structure disposed on the sealant and comprising an upper insulating layer, and an upper redistribution layer and an upper redistribution via within the upper insulating layer; a plurality of posts penetrating the sealant and electrically connecting the lower redistribution layer and the upper redistribution layer; and external connection bumps disposed below the lower redistribution structure and electrically connected to the lower redistribution layer, wherein each of the plurality of posts comprises a lower metal layer on the lower redistribution layer of the lower redistribution structure; A semiconductor package is provided that includes an upper metal layer disposed between the lower metal layer and the upper redistribution via and electrically connecting the lower metal layer and the upper redistribution via, wherein the width of the upper metal layer increases in the vertical direction, the surface of the upper metal layer has a plurality of grooves, the width of the lower region of the upper metal layer is smaller than the width of the upper region of the lower metal layer, and at least a portion of the sealant fills the plurality of grooves of the upper metal layer.
[0008] Additionally, a lower redistribution structure comprising a lower redistribution layer; a chip structure on the lower redistribution structure; an upper redistribution structure disposed on the chip structure and comprising an upper redistribution layer; at least one post electrically connecting the lower redistribution layer and the upper redistribution layer on at least one side of the chip structure; and a sealant covering the chip structure and a plurality of posts between the lower redistribution structure and the upper redistribution structure, wherein the at least one post comprises a lower metal layer on the lower redistribution layer of the lower redistribution structure; and an upper metal layer disposed between the lower metal layer and the upper redistribution layer and electrically connecting the lower metal layer and the upper redistribution layer, wherein the surface of the upper metal layer has a plurality of grooves, and the sealant comprises a first portion covering the rear surface of the chip structure; A semiconductor package is provided comprising a second portion extending horizontally from at least a portion of the first portion, filling the plurality of grooves of the upper metal layer of the post, covering the edge of the upper surface of the lower metal layer of the post, and surrounding at least a portion of the side of the lower metal layer of the post.
[0010] Additionally, the present invention provides a method for manufacturing a semiconductor package comprising: providing a lower redistribution structure including a lower redistribution layer; forming a chip structure on the lower redistribution structure; forming a post electrically connected to the lower redistribution layer of the lower redistribution structure on at least one side of the chip structure; forming a sealing material on the lower redistribution structure that surrounds the post and covers the chip structure; and forming an upper redistribution structure on the sealing material including an upper redistribution layer electrically connected to the post, wherein the post comprises a lower metal layer on the lower redistribution layer of the lower redistribution structure; and an upper metal layer between the lower metal layer and the upper redistribution layer, wherein the width of the lower surface of the upper metal layer is smaller than the width of the upper surface of the lower metal layer, and the width of the upper metal layer increases as it moves away from the upper surface of the lower metal layer.
[0012] Additionally, forming the above post comprises forming a first photoresist layer covering the lower redistribution structure and the chip structure; forming a first opening penetrating the first photoresist layer and forming the lower metal layer within the first opening; forming a second photoresist layer on the first photoresist layer and the lower metal layer; and forming a second opening penetrating the second photoresist layer and forming the upper metal layer within the second opening, thereby providing a method for manufacturing a semiconductor package.
[0014] In addition, a method for manufacturing a semiconductor package is provided, wherein the first photoresist layer comprises a negative photoresist and the second photoresist layer comprises a positive photoresist.
[0016] In addition, a method for manufacturing a semiconductor package is provided in which the surface roughness of the side wall of the second opening is greater than the surface roughness of the side wall of the first opening.
[0018] Additionally, a method for manufacturing a semiconductor package is provided, further comprising removing the first and second photoresist layers prior to forming the sealing material, wherein the edge of the upper surface of the upper metal layer is exposed by removing the first and second photoresist layers.
[0020] In addition, a method for manufacturing a semiconductor package is provided, further comprising planarizing the upper surface of the first photoresist layer and the lower metal layer prior to forming the second photoresist.
[0022] In addition, a method for manufacturing a semiconductor package is provided, wherein the ratio of the width of the upper surface of the upper metal layer to the width of the lower surface of the upper metal layer is in the range of about 1.5 to about 2.0.
[0024] In addition, a method for manufacturing a semiconductor package is provided, wherein the angle formed by the upper surface of the upper metal layer and the side surface of the upper metal layer is in the range of about 30° to about 60°.
[0026] Additionally, the chip structure comprises a base chip including connection pads electrically connected to the lower redistribution layer, upper pads facing the connection pads, and through vias electrically connecting the connection pads and the upper pads; and at least one stacked chip disposed on the base chip and electrically connected to the base chip, having a lower surface on which lower pads are disposed.
[0028] In addition, a method for manufacturing a semiconductor package is provided, further comprising forming external connection bumps on the lower portion of the lower redistribution structure. Effects of the invention
[0029] According to embodiments of the technical concept of the present disclosure, the invention provides a semiconductor package with improved reliability and a method for manufacturing the same.
[0030] Specifically, the invention provides a semiconductor package with improved reliability by means of a post having lower and upper metal layers having different widths. Additionally, the invention provides a semiconductor package with improved reliability by means of a post having lower and upper metal layers having different surface roughnesses.
[0031] The various and beneficial advantages and effects of the present disclosure are not limited to those described above and may be more easily understood in the process of describing specific embodiments of the present disclosure. Brief explanation of the drawing
[0032] FIG. 1a is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present disclosure, FIG. 1b is a plan view along line II' of FIG. 1a, and FIG. 1c is a partial enlarged view of area 'A' of FIG. 1a. FIG. 2 is a drawing for explaining a variation of an exemplary embodiment. FIG. 3a is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present disclosure, FIG. 3b is a plan view along line II' of FIG. 3a, and FIG. 3c is a partial enlarged view of area 'B' of FIG. 3a. FIG. 4 is a drawing for illustrating a variation of an exemplary embodiment. FIG. 5 is a cross-sectional view of a semiconductor package according to an exemplary embodiment. FIG. 6 is a cross-sectional view of a semiconductor package according to an exemplary embodiment. FIG. 7 is a cross-sectional view of a semiconductor package according to an exemplary embodiment. FIG. 8 is a cross-sectional view of a semiconductor package according to an exemplary embodiment. FIG. 9 is a cross-sectional view of a semiconductor package according to an exemplary embodiment. FIGS. 10a to 10g are cross-sectional views illustrating the manufacturing process of a semiconductor package according to one embodiment of the present invention. FIGS. 11a to 11g are cross-sectional views illustrating the manufacturing process of a semiconductor package according to one embodiment of the present invention. Specific details for implementing the invention
[0033] In the following, terms such as 'top', 'upper part', 'upper surface', 'lower', 'lower part', 'lower surface', 'side surface', 'top', and 'bottom' are understood to refer to the drawings, except where otherwise indicated by drawing symbols. Terms such as "upper part", "middle", and "lower part" may be replaced by other terms, such as "first", "second", and "third", to describe the components of the specification. While terms such as "first", "second", and "third" may be used to describe various components, these components are not limited by these terms, and "first component" may be named "second component".
[0035] Hereinafter, preferred embodiments of the present disclosure are described as follows with reference to the attached drawings.
[0037] FIG. 1a is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present disclosure, FIG. 1b is a plan view along line II' of FIG. 1a, and FIG. 1c is a partial enlarged view of area 'A' of FIG. 1a.
[0038] Referring to FIGS. 1a through 1c, a semiconductor package (300) of an exemplary embodiment may include a lower chip structure (100), a lower rewiring structure (310), a plurality of posts (330), a sealing material (320), and an upper rewiring structure (350). In one embodiment, the lower chip structure (100) and the lower rewiring structure (310) may be referred to as the 'chip structure' and the 'rewiring structure', respectively.
[0040] The lower chip structure (100) may include first connection terminals (100P) that are positioned on the lower redistribution structure (310) and electrically connected to the lower redistribution layer (312). The first connection terminals (100P) may be connected to the lower redistribution layer (312) through connection bumps (BP) positioned between the lower chip structure (100) and the lower redistribution structure (310). The connection bumps (BP) may include a pillar portion (PL) in contact with the first connection terminals (100P) and a solder portion (SL) positioned below the pillar portion (PL). The pillar portion (PL) may include copper (Cu) or an alloy of copper (Cu), and the solder portion (SL) may include a low-melting-point metal, for example, tin (Sn) or an alloy containing tin (Sn). According to an embodiment, the connection bumps (BP) may include only one of the pillar portion (PL) and the solder portion (SL).
[0041] The lower chip structure (100) may include a semiconductor wafer and an integrated circuit (IC) made of a semiconductor element such as silicon or germanium, or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The lower chip structure (100) may be a bare semiconductor chip without separate bumps or wiring layers formed thereon, but is not limited thereto, and may be a packaged type semiconductor chip. The integrated circuit may be a logic circuit (or 'logic chip') such as a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, or an ASIC (application-specific IC), or a memory circuit (or 'memory chip') including volatile memory such as DRAM (dynamic RAM) or SRAM (static RAM), and non-volatile memory such as PRAM (phase change RAM), MRAM (magnetic RAM), RRAM (resistive RAM), or flash memory. According to an embodiment, the lower chip structure (100) may be a package structure including a plurality of semiconductor chips, which will be described later with reference to FIGS. 6 and 7.
[0043] The lower redistribution structure (310) is a support substrate on which the lower chip structure (100) is mounted, and may include a lower insulating layer (311), lower redistribution layers (312), and lower redistribution vias (313).
[0044] The lower insulating layer (311) may include an insulating resin. The insulating resin may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which inorganic fillers are impregnated into these resins, for example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide-Triazine). For example, the lower insulating layer (311) may include a photosensitive resin such as PID (Photo-Imageable Dielectric). The lower insulating layer (311) may include a plurality of insulating layers (not shown) stacked in the vertical direction (D3). Depending on the process, the boundaries between the plurality of insulating layers (not shown) may be indistinct.
[0045] The lower redistribution layer (312) is disposed on and within the lower insulating layer (311) and can redistribute the first connection terminal (100P) of the lower chip structure (100). The lower redistribution layer (312) may include a metal including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The lower redistribution layer (312) may perform various functions according to the design. For example, the lower redistribution layer (312) may include a ground pattern, a power pattern, and a signal pattern. Here, the signal pattern may be defined as a transmission path for various signals, such as data signals, excluding the ground pattern, power pattern, etc. The lower redistribution layer (312) may include more or fewer redistribution layers than shown in the drawing. The lower redistribution layer (312) may include pads in contact with the connection bumps (BP) and the plurality of posts (330).
[0046] The lower redistribution via (313) may extend within the lower insulating layer (311) and be electrically connected to the lower redistribution layer (312). For example, the lower redistribution via (313) may interconnect lower redistribution layers (312) of different levels. The lower redistribution via (313) may include signal vias, ground vias, and power vias. The lower redistribution via (313) may include a metallic material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The lower redistribution via (313) may be a filled via in which the metallic material is filled inside the via hole, or a conformal via in which the metallic material extends along the inner wall of the via hole.
[0048] External connection bumps (360) may be disposed below the lower redistribution structure (310). The external connection bumps (360) may be electrically connected to the lower redistribution layer (312). The semiconductor package (300) may be connected to an external device, such as a module substrate or a system board, through the external connection bumps (360). According to an embodiment, the external connection bumps (360) may have a combined form of a pillar (or underbump metal) and a ball. The pillar may include copper (Cu) or an alloy of copper (Cu), and the ball may include a low-melting-point metal, for example, tin (Sn) or an alloy containing tin (e.g., Sn-Ag-Cu). According to an embodiment, the external connection bumps (360) may include only a pillar or only a ball. According to an embodiment, a resist layer may be formed on the lower surface of the lower redistribution structure (310) to protect external connection bumps (360) from physical and chemical damage.
[0050] A plurality of posts (330) are disposed on at least one side of the lower chip structure (100) and can electrically connect the lower redistribution layer (312) and the upper redistribution layer (352) by penetrating the sealing material (320). The plurality of posts (330) may include copper (Cu), nickel (Ni), titanium (Ti), lead (Pb), aluminum (Al), silver (Ag), gold (Au), platinum (Pt), or an alloy thereof. The plurality of posts (330) may extend in a vertical direction (D3) within the sealing material (320). The plurality of posts (330) may have a cylindrical shape, but are not limited thereto.
[0051] Each of the plurality of posts (330) may include a lower metal layer (331) adjacent to a lower redistribution structure (310) and an upper metal layer (332) adjacent to an upper redistribution structure (350). In one embodiment, the lower metal layer (331) may be referred to as a first part, and the upper metal layer (332) may be referred to as a second part.
[0052] The lower metal layer (331) is disposed on the lower redistribution layer (312) of the lower redistribution structure (310) and may extend in a vertical direction (D3) from the upper surface of the lower redistribution layer (312). The width of the lower metal layer (331) in the horizontal direction (D1 and / or D2) according to the height (H_L) in the vertical direction (D3) may be substantially the same. With respect to the upper surface of the lower redistribution structure (310), the upper surface of the lower metal layer (331) may be at a higher level than the upper surface of the lower chip structure (100).
[0053] The upper metal layer (332) may be positioned between the lower metal layer (331) and the upper rewiring structure (350). The upper metal layer (332) may be positioned, for example, between the lower metal layer (331) and the lowest upper rewiring via (353L) of the upper rewiring vias (353). The width of the upper metal layer (332) in the horizontal direction (D1 and / or D2) may vary depending on the height (H_U) in the vertical direction (D3). The width (D1) of the lower region of the upper metal layer (332) may be smaller than the width (D2) of the upper region of the upper metal layer (332). The width of the upper metal layer (332) may increase, for example, from the lower region of the upper metal layer (332) to the upper region of the upper metal layer (332). The minimum value of the width (D1) of the lower region of the upper metal layer (332) is defined on the lower surface of the upper metal layer (332), and the maximum value of the width (D2) of the upper region of the upper metal layer (332) can be defined on the upper surface of the upper metal layer (332).
[0054] The ratio of the width of the upper surface of the upper metal layer (332) to the width of the lower surface of the upper metal layer (332) may be about 1.5 or more. In one embodiment, the ratio may be in the range of about 1.5 or more to about 3.0 or less. In one embodiment, the ratio may be in the range of about 1.5 or more to about 2.0 or less.
[0055] The angle (θ) formed by the upper surface of the upper metal layer (332) and the side of the upper metal layer (332) may be in the range of about 20° to about 80°. In one embodiment, the angle (θ) may be in the range of about 30° to about 70°. In one embodiment, the angle (θ) may be in the range of about 30° to about 60°.
[0057] The surface roughness of the side of the upper metal layer (332) may be greater than the surface roughness of the side of the lower metal layer (331). In another aspect, a plurality of grooves (GR) may be formed on the side of the upper metal layer (332). Here, the plurality of grooves (GR) may refer to the recessed portions among the irregularities formed on the side of the upper metal layer (332).
[0058] The first height (H_L) in the vertical direction (D3) of the lower metal layer (331) may be greater than the second height (H_U) in the vertical direction (D3) of the upper metal layer (332). For example, the ratio of the first height (H_L) to the second height (H_U) may be about 1.5 or greater. In one embodiment, the ratio may be in the range of about 1.5 to about 10.0. In one embodiment, the ratio may be in the range of about 2.0 to about 8.0. In one embodiment, the ratio may be in the range of about 2.0 to about 5.0.
[0059] The width of the lower surface of the upper metal layer (332) may be smaller than the width of the upper surface of the lower metal layer (331). In another aspect, the edge of the upper surface of the lower metal layer (331) may be covered by a sealant (320).
[0060] The width of the lower surface of the lower upper rewiring via (353L) may be smaller than the width of the upper surface of the upper metal layer (332). In another aspect, the edge of the upper surface of the upper metal layer (332) may be covered by the upper insulating layer (351) of the upper rewiring structure (350).
[0062] The sealant (320) can cover the sides of the lower chip structure (100) and each of the plurality of posts (330). The sealant (320) may include, for example, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or prepreg, ABF, FR-4, BT, EMC (Epoxy Molding Compound), etc.
[0063] The suture material (320) may be defined to include a plurality of first to third parts (320_1, 320_2, 320_3). The boundaries between the plurality of first to third parts (320_1, 320_2, 320_3) may not be distinguishable.
[0064] The first part (320_1) may be a part that covers the upper (or upper surface) of the lower chip structure (100) of the suture material (320).
[0065] The second part (320_2) extends horizontally (D1 and / or D2) from the first part (320_1) and may surround the top of the lower metal layer (331) and the side of the upper metal layer (332). The second part (320_2) may, for example, cover the edge of the upper surface of the lower metal layer (331) and surround the side surface of the top of the lower metal layer (331). The second part (320_2) may, for example, surround the side surface of the upper metal layer (332). The second part (320_2) may, for example, fill a plurality of grooves (GR) among the irregularities formed on the side surface of the upper metal layer (332).
[0066] The third part (320_3) extends downward from the second part (320_2) and covers the side and bottom surface of the lower chip structure (100), and can surround the rest of the lower metal layer (331) except for the top.
[0068] The upper redistribution structure (350) is placed on the sealant (320) and may include an upper insulating layer (351), upper redistribution layers (352), and upper redistribution vias (353).
[0069] The upper insulating layer (351) may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which an inorganic filler is impregnated into these resins, such as prepreg, ABF, FR-4, BT. For example, the upper insulating layer (351) may include a photosensitive resin such as PID. The upper insulating layer (351) may include a plurality of insulating layers stacked in the vertical direction (D3). Depending on the process, the boundary between the plurality of insulating layers may be indistinct. The upper insulating layer (351) may cover the edge of the upper surface of the upper metal layer (332).
[0070] The upper redistribution layer (352) may be disposed on and within the upper insulating layer (351). The upper redistribution layer (352) may redistribute a chip structure mounted on the upper redistribution structure (350), for example, the upper chip structure (200) of FIG. 7. The upper redistribution layer (352) may include a metal comprising, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The upper redistribution layer (352) may include a ground pattern, a power pattern, and a signal pattern according to the design. The upper redistribution layer (352) may include more or fewer redistribution layers than shown in the drawing.
[0071] The upper redistribution via (353) may extend within the upper insulating layer (351) and be electrically connected to the upper redistribution layer (352). For example, the upper redistribution via (353) may interconnect upper redistribution layers (352) at different levels. The upper redistribution via (353) may include a metallic material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The upper redistribution via (353) may be a filled via in which the metallic material is filled inside the via hole, or a conformal via in which the metallic material extends along the inner wall of the via hole.
[0072] The via located at the lowest of the upper rewiring vias (353) can be defined as the lowest upper rewiring via (353L). The bottom of the lowest upper rewiring via (353L) may come into contact with the top of the upper metal layer (332). The width of the bottom surface of the lowest upper rewiring via (353L) may be smaller than the width of the top surface of the upper metal layer (332).
[0074] According to the present disclosure, the post (330) has a lower metal layer (331) and an upper metal layer (332) disposed on the lower metal layer (331) and having a width different from that of the lower metal layer (331), thereby minimizing or preventing delamination that may occur at the interface between the post (330) and the suture material (320). Additionally, the surface roughness of the side of the upper metal layer (332) is greater than the surface roughness of the side of the lower metal layer (331), thereby minimizing or preventing the delamination phenomenon.
[0075] For example, the width of the lower surface of the upper metal layer (332) is smaller than the width of the upper surface of the lower metal layer (331), and the width of the upper metal layer (332) increases as it extends toward the upper region of the upper metal layer (332), and accordingly, the adhesive strength at the interface between the top of the post (330) and the sealant (320) can be improved. The adhesive strength can be improved by the surface roughness of the side of the upper metal layer (332) being greater than the surface roughness of the side of the lower metal layer (331).
[0077] FIG. 2 is a drawing for explaining a variation of an exemplary embodiment.
[0078] Referring to FIG. 2, the semiconductor package (300A) may be the same or similar as described with reference to FIG. 1a through 1c, except that it may further include a seed layer (e.g., 331', 332') disposed below a metal layer (e.g., 331, 332).
[0079] A lower seed layer (331') may be disposed on the lower part of the lower metal layer (331). The lower seed layer (331') may include titanium (Ti), copper (Cu), etc.
[0080] An upper seed layer (332') may be disposed below the upper metal layer (332). The upper seed layer (332') may include titanium (Ti), copper (Cu), etc.
[0082] FIG. 3a is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present disclosure, FIG. 3b is a plan view along line II' of FIG. 3a, and FIG. 3c is a partial enlarged view of area 'B' of FIG. 3a.
[0083] Referring to FIGS. 3a to 3c, the semiconductor package (300B) may be the same or similar as described with reference to FIGS. 1a to 2, except that it further includes a cover layer (150) and a plurality of via structures (335) on the upper surface of the lower chip structure (100).
[0084] A cover layer (150) may be disposed on a lower chip structure (100). The cover layer (150) may be formed by a deposition process such as PVD or CVD or a spin coating process. The cover layer (150) may include silicon oxide (SiO), silicon nitride (SiN), silicon carbonitride (SiCN), and combinations thereof.
[0085] The side of the cover layer (150) and the side of the lower chip structure (100) can be aligned. The cover layer (150) may include a first surface in contact with the upper surface of the lower chip structure (100) and a second surface opposite to the first surface.
[0087] A plurality of via structures (335) may penetrate the seal (320) between the cover layer (150) and the upper rewiring structure (350). A plurality of via structures (335) may be spaced apart in a first horizontal direction (D1) and a second horizontal direction (D2). A plurality of via structures (335) may be dummy via structures that do not form an electrical connection. In another aspect, separate rewiring vias may not be placed on the plurality of via structures (335). A plurality of via structures (335) may comprise the same material as the upper metal layer (331). For example, a plurality of via structures (335) may comprise copper (Cu), nickel (Ni), titanium (Ti), lead (Pb), aluminum (Al), silver (Ag), gold (Au), platinum (Pt), or an alloy thereof.
[0088] The width of each of the multiple via structures (335) in the horizontal direction (D1 and / or D2) may vary depending on the height in the vertical direction (D3). The width (D1') of the lower region of the via structure (335) may be smaller than the width (D2') of the upper region of the via structure (335). The width of the via structure (335) may increase, for example, from the lower region of the via structure (335) to the upper region of the via structure (335). The minimum value of the width (D1') of the lower region of the via structure (335) may be defined at the lower surface of the via structure (335), and the maximum value of the width (D2') of the upper region of the via structure (335) may be defined at the upper surface of the via structure (335).
[0089] The ratio of the width of the upper surface of the via structure (335) to the width of the lower surface of the via structure (335) may be about 1.5 or more. In one embodiment, the ratio may be in the range of about 1.5 or more to about 3.0 or less. In one embodiment, the ratio may be in the range of about 1.5 or more to about 2.0 or less. The ratio of the width of the upper surface of the via structure (335) to the width of the lower surface of the via structure (335) may be smaller than the ratio of the width of the upper surface of the upper metal layer (332) to the width of the lower surface of the upper metal layer (332).
[0090] In the horizontal direction (D1 and / or D2), the width of the via structure (335) may be smaller than the width of the upper metal layer (332). The width of the lower surface of the via structure (335) may be smaller than the width of the lower surface of the upper metal layer (332). The width of the upper surface of the via structure (335) may be smaller than the width of the upper surface of the upper metal layer (332).
[0092] The vertical height (D3) of the via structure (335) may be substantially the same as the vertical height (H_U) of the upper metal layer (332).
[0094] The angle (θ') formed by the upper surface of the via structure (335) and the side of the via structure (335) may be in the range of about 20° to about 80°. In one embodiment, the angle (θ') may be in the range of about 30° to about 70°. In one embodiment, the angle (θ') may be in the range of about 30° to about 60°. The angle (θ') formed by the upper surface of the via structure (335) and the side of the via structure (335) may be greater than the angle (θ) formed by the upper surface of the upper metal layer (332) and the side of the upper metal layer (332).
[0096] The side of the via structure (335) may have surface roughness. In another view, a plurality of grooves (GR') may be formed on the side of the via structure (335). Here, the plurality of grooves (GR') may refer to the recessed portions among the irregularities formed on the side of the via structure (335).
[0098] FIG. 4 is a drawing for illustrating a variation of an exemplary embodiment.
[0099] Referring to FIG. 4, the semiconductor package (300C) may be the same or similar as described with reference to FIG. 1a through FIG. 3c, except that it may further include a seed layer (e.g., 331', 332') disposed below a metal layer (e.g., 331, 332) and a seed layer (335') disposed below a via structure (335).
[0100] A lower seed layer (331') may be disposed on the lower part of the lower metal layer (331). The lower seed layer (331') may include titanium (Ti), copper (Cu), etc.
[0101] An upper seed layer (332') may be disposed below the upper metal layer (332). The upper seed layer (332') may include titanium (Ti), copper (Cu), etc.
[0102] A seed layer (335') may be disposed at the bottom of the via structure (335). The seed layer (335') may include titanium (Ti), copper (Cu), etc.
[0104] FIG. 5 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.
[0105] Referring to FIG. 5, the semiconductor package (300D) may be the same or similar as described with reference to FIG. 1a through FIG. 4, except that it includes a plurality of via structures (335) spaced apart in a first direction (e.g., D1) and each extending in the second direction (e.g., D2).
[0106] A plurality of via structures (335) may be spaced apart in a first horizontal direction (D1). Each of the plurality of via structures (335) may extend in a second horizontal direction (D2). In another aspect, the plurality of via structures (335) may be spaced apart in a second horizontal direction (D2), and each of the plurality of via structures (335) may extend in a first horizontal direction (D1).
[0108] FIG. 6 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.
[0109] Referring to FIG. 6, the semiconductor package (300E) may have the same or similar features as described with reference to FIG. 1a through FIG. 5, except that it includes a lower chip structure (or 'chip structure') (100A) in which a plurality of semiconductor chips (100a, 100b) are embedded.
[0110] At least some of the plurality of semiconductor chips (100a, 100b) (e.g., '100a') may include through-vias (130) that electrically connect the plurality of semiconductor chips (100a, 100b) to each other. The plurality of semiconductor chips (100a, 100b) may be chiplets that constitute a Multi-Chip Module (MCM). The plurality of semiconductor chips (100a, 100b) may include a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application-specific integrated circuit (ASIC), volatile memory, non-volatile memory, input / output (I / O) circuits, analog circuits, serial-to-parallel conversion circuits, etc.
[0111] A chip structure (100A) may include a base chip (100a) and at least one stacked chip (100b). For example, the base chip (100a) may include a processor circuit, and the at least one stacked chip (100b) may include at least one of an input / output circuit, an analog circuit, a memory circuit, and a serial-to-parallel conversion circuit for the processor circuit. The base chip (100a) and the at least one stacked chip (100b) may be provided in a greater number than shown in the drawing. For example, the at least one stacked chip (100b) may include two or more semiconductor chips arranged horizontally and / or vertically on the base chip (100a).
[0113] A base chip (100a) and at least one stacked chip (100b) may include a substrate (101), an upper protective layer (103), an upper pad (105), a circuit layer (110), a lower pad (104), and / or through-vias (130). The substrate (101) may include a semiconductor element such as silicon or germanium (Ge), for example, or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The substrate (101) may have a Silicon On Insulator (SOI) structure. The substrate (101) may have a conductive region, for example, an impurity-doped well, or an impurity-doped active surface and an inactive surface opposite. The substrate (101) may include various device isolation structures such as a Shallow Trench Isolation (STI) structure.
[0114] An upper protective layer (103) is formed on an inactive surface of a substrate (101) and can protect the substrate (101). The upper protective layer (103) may be formed as an insulating layer such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, etc., but the material of the upper protective layer (103) is not limited to the above materials. For example, the upper protective layer (103) may be formed as a polymer such as PI (Polyimide). Although not shown in the drawing, a lower protective layer may be further formed on the lower surface of the circuit layer (110).
[0115] The upper pad (105) may be placed on the upper protective layer (103). The upper pad (105) may include, for example, at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). The lower pad (104) may be placed on the lower part of the circuit layer (110) and may include a material similar to that of the upper pad (105). However, the materials of the upper pad (105) and the lower pad (104) are not limited to the above materials. The lower pad (104) may be understood as corresponding to the first connection terminals (100P) described above.
[0116] The circuit layer (110) is disposed on the active surface of the substrate (101) and may include various types of devices. For example, the circuit layer (110) may include various active and / or passive devices such as FETs like planar FETs (Field Effect Transistors) or FinFETs, memory devices such as flash memory, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), and RRAM (Resistive Random Access Memory), logic devices such as AND, OR, and NOT, and system LSI (Large Scale Integration), CIS (CMOS Imaging Sensor), and MEMS (Micro-Electro-Mechanical System). The circuit layer (110) may include a wiring structure electrically connected to the above-described elements and an interlayer insulating layer surrounding the wiring structure. The interlayer insulating layer may include silicon oxide or silicon nitride. The wiring structure may include multilayer wiring and / or vertical contacts. The wiring structure may connect the elements of the circuit layer (110) to one another, connect the elements to a conductive region of the substrate (101), or connect the elements to a through-via (130).
[0117] A through-via (130) penetrates the substrate (101) in a vertical direction (D3 direction) and can provide an electrical path connecting the upper pad (105) and the lower pads (104). The through-via (130) may include a conductive plug and a barrier film surrounding it. The conductive plug may include a metal, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu). The conductive plug may be formed by a plating process, a PVD process, or a CVD process. The barrier film may include an insulating barrier film or / and a conductive barrier film. The insulating barrier film may be made of an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof. The conductive barrier film may be placed between the insulating barrier film and the conductive plug. The conductive barrier film may include a metal compound, for example, tungsten nitride (WN), titanium nitride (TiN), or tantalum nitride (TaN). The barrier film can be formed by a PVD process or a CVD process.
[0119] Bumps (141) and an adhesive layer (142) may be disposed between a base chip (100a) and at least one stacked chip (100b). The bumps (141) may electrically connect the base chip (100a) and at least one stacked chip (100b). The bumps (141) include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or alloys thereof, and, depending on the embodiment, may have a combined form of a metal pillar and a solder ball. The adhesive layer (142) surrounds each of the bumps (141) and may bond the base chip (100a) and at least one stacked chip (100b). The adhesive layer (142) may be formed using a non-conductive film (NCF), but is not limited thereto, and may be formed by any type of insulating film capable of a heat-pressing process, for example. According to an embodiment, the adhesive layer (142) may cover at least a portion of the side of at least one laminated chip (100b).
[0121] A mold (143) surrounding at least one laminated chip (100b) and an adhesive layer (142) may be disposed on a base chip (100a). The mold (143) may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or prepreg, ABF, FR-4, BT, EMC, etc.
[0123] FIG. 7 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.
[0124] Referring to FIG. 7, the semiconductor package (300F) may have the same or similar features as described with reference to FIG. 1a through FIG. 6, except that it includes a lower chip structure (or 'chip structure') (100B) in which a base chip (100a) and stacked chips (100b) are directly bonded and combined.
[0125] The chip structure (100B) may include a base chip (100a), at least one stacked chip (100b), and a mold (143). The base chip (100a) and at least one stacked chip (100b) may be directly bonded and joined without a separate connecting member (e.g., solder bump, copper pillar, etc.). The chip structure (100B) may include a bonding surface (BS) formed by bonding the upper surface of the base chip (100a) and the lower surface of at least one stacked chip (100b). The bonding surface (BS) may be formed by metal bonding and dielectric bonding. The upper pad (105) of the base chip (100a) and the lower pad (104) of the stacked chip (100b) may include copper (Cu). The upper protective layer (103) surrounding the upper pad (105) of the base chip (100a) and the dielectric layer surrounding the lower pad (104) of the stacked chip (100b) may include at least one of a material that can be bonded together, for example, silicon oxide (SiO), silicon nitride (SiN), and silicon carbonitride (SiCN).
[0127] FIG. 8 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.
[0128] Referring to FIG. 8, the semiconductor package (300G) may have the same or similar features as described with reference to FIG. 1a through FIG. 7, except that it further includes an upper chip structure (200) and / or a heat dissipation member (340).
[0129] The upper chip structure (200) may be a bare chip or a packaged chip having a logic circuit or a memory circuit formed thereon. According to an embodiment, the upper chip structure (200) may be a package structure in which a plurality of semiconductor chips are mounted on a substrate. The upper chip structure (200) may include a semiconductor chip of a different type from the lower chip structure (100). For example, the lower chip structure (100) may include a logic chip, and the upper chip structure (200) may include a memory chip.
[0130] The upper chip structure (200) may be placed on the upper redistribution structure (350). The upper chip structure (200) may be electrically connected to the lower redistribution layer (312) through a plurality of posts (330). According to an embodiment, the plurality of posts (330) may be arranged in a position that overlaps the upper chip structure (200) in a vertical direction (D3). The upper chip structure (200) may include second connection terminals (200P) that are electrically connected to the plurality of posts (330). The second connection terminals (200P) may be connected to the plurality of posts (330) through upper connection bumps (250) placed between the upper chip structure (200) and the plurality of posts (330). The upper chip structure (200) may be electrically connected to the lower chip structure (100) through the lower redistribution layer (312) and the plurality of posts (330). According to an embodiment, an insulating material layer surrounding the upper connecting bumps (250) may be formed below the upper chip structure (200).
[0131] The heat dissipation member (340) may be disposed on at least one side of the upper chip structure (200). The heat dissipation member (340) may overlap vertically (in the D3 direction) with at least a part of the lower chip structure (100). According to an embodiment, the heat dissipation member (340) may have a shape that surrounds four sides of the upper chip structure (200). The heat dissipation member (340) can control warpage of the semiconductor package (300D) and dissipate heat generated from the lower chip structure (100) to the outside.
[0132] The heat dissipation member (340) may include a thermal interface material (TIM) layer (341) and a heat slug (342). The thermal interface material layer (341) may be in contact with the upper surface (100T) of the lower chip structure (100). The thermal interface material layer (341) may include, for example, a thermally conductive adhesive tape, a thermally conductive grease, a thermally conductive adhesive, etc. The heat slug (342) may be placed on the thermal interface material layer (341). The heat slug (342) may include a material with excellent thermal conductivity, for example, aluminum (Al), gold (Au), silver (Ag), copper (Cu), iron (Fe), graphite, graphene, etc.
[0134] FIG. 9 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.
[0135] Referring to FIG. 9, the semiconductor package (300H) may have the same or similar features as described with reference to FIG. 1a through FIG. 8, except that it does not include a separate upper rewiring structure (e.g., 350 in FIG. 1a) and the upper chip structure (200) is placed on the sealing material (320).
[0136] The upper chip structure (200) may be a bare chip or a packaged chip having a logic circuit or a memory circuit formed thereon. According to an embodiment, the upper chip structure (200) may be a package structure in which a plurality of semiconductor chips are mounted on a substrate. The upper chip structure (200) may include a semiconductor chip of a different type from the lower chip structure (100). For example, the lower chip structure (100) may include a logic chip, and the upper chip structure (200) may include a memory chip.
[0137] The upper chip structure (200) may be placed on the sealant (320). The upper chip structure (200) may include a lower surface on which a connection terminal (200P) is placed. At least a portion of the lower surface of the connection terminal (200P) and at least a portion of the upper surface of the second portion (332) of the post (300) may face each other. In another aspect, the connection terminal (200P) and the second portion (332) may be aligned in a vertical direction (e.g., D3 direction).
[0138] The semiconductor package (300H) may further include a connection bump (250) between the upper chip structure (200) and the sealing material (320). The connection bump (250) may be positioned between the connection terminal (200P) and the second part (332). The connection bump (250) may electrically connect the connection terminal (200P) and the second part (332). The upper chip structure (200) may be electrically connected to the lower redistribution layer (312) through the connection bump (250) and the post (330). According to an embodiment, an insulating material layer surrounding the connection bumps (250) may be formed below the upper chip structure (200).
[0140] FIGS. 10a to 10g are cross-sectional views illustrating the manufacturing process of a semiconductor package (300) according to one embodiment of the present invention.
[0141] Referring to FIG. 10a, a chip structure (100) may be mounted on a lower redistribution structure (310). The lower redistribution structure (310) may be formed on a carrier substrate (CR). A first photoresist layer (PR1) may be formed on the lower redistribution structure (310) and the chip structure (100).
[0142] The lower redistribution structure (310) may be formed at the wafer level or panel level. The lower redistribution structure (310) may include a lower insulating layer (311), a lower redistribution layer (312), and a lower redistribution via (313). The lower insulating layer (311) may be formed by sequentially applying and curing a photosensitive material, for example, PID. The lower redistribution layer (312) and the lower redistribution via (313) may be formed by performing an exposure process and a development process to form via holes penetrating the lower insulating layer (311), and by patterning a metal material on the lower insulating layer (311) using a plating process.
[0143] A chip structure (100) can be formed on a lower redistribution structure (310). The first connection terminals (100P) and the lower redistribution layer (312) can be physically and electrically connected through connection bumps (BP) disposed between the chip structure (100) and the lower redistribution structure (310).
[0144] A first photoresist layer (PR1) can be formed to cover the chip structure (100) on the lower redistribution structure (310). The first photoresist layer (PR1) can be formed through a spin coating process or other suitable application method. The first photoresist layer (PR1) can serve as a mask to form a part of the post (330 in FIG. 1a). In one embodiment, the first photoresist layer (PR1) may include a positive or negative photoresist. In one embodiment, the first photoresist layer (PR1) may include a negative photoresist.
[0146] Referring to FIG. 10b, a plurality of preliminary lower metal layers (331p) can be formed.
[0147] A plurality of first openings (OP1) can be formed that penetrate the first photoresist layer (PR1) and expose the upper surface of the lower redistribution layer (312). The plurality of first openings (OP1) can be formed by a first exposure process and a first development process.
[0148] A conductive material can be filled into the plurality of first openings (OP1) to form a lower portion (331L) filling the plurality of first openings (OP1) and an upper portion (331U) on the first photoresist layer (PR1).
[0149] The preliminary lower metal layer (331p) can be formed by an electroplating process using a seed layer (see 331' in FIG. 2) within the plurality of first openings (OP1). The seed layer may include titanium (Ti), copper (Cu), etc.
[0151] Referring to FIG. 10c, a plurality of lower metal layers (331) can be formed.
[0152] Referring to FIG. 10b and FIG. 10c together, a planarization process may be applied to remove the upper portion (331U) and to make the upper surface of the first photoresist layer (PR1) substantially co-plane. The planarization process may include, but is not limited to, a grinding process, a CMP (Chemical Mechanical Polishing) process, etc.
[0153] Flattening the upper surface of the first photoresist layer (PR1) can be understood as generating a standing wave in a second exposure process for forming a second opening ('OP2' in FIG. 10d) penetrating the second photoresist layer ('PR2' in FIG. 10d). For example, flattening the upper surface of the first photoresist layer (PR1) can be interpreted as being advantageous for generating the standing wave.
[0155] Referring to FIG. 10d, a second photoresist layer (PR2) may be formed on a first photoresist layer (PR1) and a plurality of lower metal layers (331).
[0156] A plurality of second openings (OP2) can be formed that penetrate the second photoresist layer (PR2) to expose the upper surface of the lower metal layer (331). The plurality of second openings (OP2) can be formed by a second exposure process and a second development process.
[0157] The width of the lower surface of each of the plurality of second openings (OP2) may be smaller than the width of the upper surface of the lower metal layer (331). Each of the plurality of second openings (OP2) may have a width that increases from the lower region to the upper region. For example, the plurality of second openings (OP2) may have an inverted trapezoidal shape in terms of cross-sectional area.
[0158] A plurality of grooves may be formed on the inner wall of each of the plurality of second openings (OP2). The plurality of grooves may be understood as being formed by the standing wave described with reference to FIG. 10c. The plurality of grooves may refer to the recessed portions among the irregularities formed on the inner wall.
[0159] In one embodiment, the second photoresist layer (PR2) may include a positive or negative photoresist. In one embodiment, the second photoresist layer (PR2) may include a material different from the first photoresist layer (PR1). The second photoresist layer (PR2) may include, for example, a positive photoresist.
[0161] Referring to FIG. 10e, a plurality of upper metal layers (332) can be formed.
[0162] An upper metal layer (332) can be formed by filling the plurality of second openings (OP2) with a conductive material. The upper metal layer (332) can be formed by an electroplating process using a seed layer (see 332' in FIG. 2) within the plurality of second openings (OP2). The seed layer may include titanium (Ti), copper (Cu), etc.
[0163] The conductive material may fill the plurality of grooves. In another aspect, a plurality of grooves (GR) corresponding to the plurality of grooves may be formed on the surface of each of the plurality of upper metal layers (332). Accordingly, a post (330) having a plurality of components having different surface roughness may be formed. For example, the surface roughness of the side of the upper metal layer (332) may be greater than the surface roughness of the side of the lower metal layer (331).
[0165] Referring to FIG. 10f, a suture material (320) can be formed.
[0166] The first and second photoresist layers (PR1, PR2) are removed, and a sealant (320) can be formed on the lower rewiring structure (310). The sealant (320) can cover the chip structure (100) and the posts (330). The sealant (320) may include, for example, EMC and may be formed by a Molded UnderFill (MUF) process.
[0168] Referring to FIG. 10g, an upper redistribution structure (350) may be formed on a sealing material (320). The upper redistribution structure (350) may include an upper insulating layer (351), an upper redistribution layer (352), and an upper redistribution via (353). Subsequently, the lower redistribution structure (310), the sealing material (320), and the upper redistribution structure (350) may be cut along a scribe lane (SC) to separate the unit packages (300').
[0170] FIGS. 11a to 11g are cross-sectional views illustrating the manufacturing process of a semiconductor package (300B) according to one embodiment of the present invention.
[0171] Referring to FIG. 11a, a chip structure (100) may be mounted on a lower redistribution structure (310). A cover layer (150) may be disposed on one side of the chip structure (100). The lower redistribution structure (310) may be formed on a carrier substrate (CR). A first photoresist layer (PR1) may be formed on the lower redistribution structure (310), the chip structure (100), and the cover layer (150).
[0172] A chip structure (100) can be formed on a lower redistribution structure (310). A cover layer (150) can be formed on the upper surface of the chip structure (100).
[0173] A first photoresist layer (PR1) can be formed to surround the side of the chip structure (100) on the lower redistribution structure (310). With respect to the upper surface of the lower redistribution structure (310), the upper surface of the first photoresist layer (PR1) may be substantially the same as the upper surface of the cover layer (150).
[0174] The first photoresist layer (PR1) can be formed through a spin coating process or other suitable application method. The first photoresist layer (PR1) can serve as a mask to form a part of the post (330 in FIG. 3a). In one embodiment, the first photoresist layer (PR1) may include a positive or negative photoresist. In one embodiment, the first photoresist layer (PR1) may include a negative photoresist.
[0176] Referring to FIG. 11b, a plurality of preliminary lower metal layers (331p) can be formed.
[0177] A plurality of first openings (OP1) can be formed that penetrate the first photoresist layer (PR1) and expose the upper surface of the lower redistribution layer (312). The plurality of first openings (OP1) can be formed by a first exposure process and a first development process.
[0178] A conductive material may be filled into the plurality of first openings (OP1) to form a lower portion (331L) filling the plurality of first openings (OP1) and an upper portion (331U) on the first photoresist layer (PR1). In this embodiment, the upper surface of the lower portion (331L) may be at substantially the same level as the upper surface of the cover layer (150).
[0179] The preliminary lower metal layer (331p) can be formed by an electroplating process using a seed layer (see 331' in FIG. 4) within the plurality of first openings (OP1). The seed layer may include titanium (Ti), copper (Cu), etc.
[0181] Referring to FIG. 11c, a plurality of lower metal layers (331) can be formed.
[0182] Referring to FIG. 11b and FIG. 11c together, a planarization process may be applied to remove the upper portion (331U) and to make the upper surface of the first photoresist layer (PR1) substantially co-plane. The planarization process may include, but is not limited to, a grinding process, a CMP (Chemical Mechanical Polishing) process, etc.
[0183] Flattening the upper surface of the first photoresist layer (PR1) can be understood as generating a standing wave in a second exposure process for forming a second opening ('OP2' in FIG. 11d) penetrating the second photoresist layer ('PR2' in FIG. 11d). For example, flattening the upper surface of the first photoresist layer (PR1) can be interpreted as being advantageous for generating the standing wave.
[0185] Referring to FIG. 11d, a second photoresist layer (PR2) may be formed on a first photoresist layer (PR1) and a plurality of lower metal layers (331).
[0186] A plurality of second openings (OP2) can be formed that penetrate the second photoresist layer (PR2) to expose the upper surface of the lower metal layer (331). A plurality of third openings (OP3) can be formed that penetrate the second photoresist layer (PR2) to expose the upper surface of the cover layer (150). The plurality of second and third openings (OP2, OP3) can be formed by a second exposure process and a second development process.
[0187] Each of the plurality of third openings (OP3) may be formed spaced apart in the first and second directions (D1, D2). In one embodiment, each of the plurality of third openings (OP3) may be formed extending in the second direction (e.g., D2) and spaced apart in the first direction (e.g., D1) (see FIG. 5).
[0188] The width of the lower surface of each of the plurality of second openings (OP2) may be smaller than the width of the upper surface of the lower metal layer (331). Each of the plurality of second openings (OP2) may have a width that increases from the lower region to the upper region. For example, the plurality of second openings (OP2) may have an inverted trapezoidal shape in terms of cross-sectional area.
[0189] Each of the plurality of third openings (OP3) may have a width that increases from the lower region to the upper region. For example, the plurality of third openings (OP3) may have an inverted trapezoidal shape in terms of cross-sectional area.
[0190] A plurality of grooves may be formed on the inner wall of each of the plurality of second and third openings (OP2, OP3). The plurality of grooves may be understood as being formed by the standing wave described with reference to FIG. 11c. The plurality of grooves may refer to the recessed portions among the irregularities formed on the inner wall.
[0191] In one embodiment, the second photoresist layer (PR2) may include a positive or negative photoresist. In one embodiment, the second photoresist layer (PR2) may include a material different from the first photoresist layer (PR1). The second photoresist layer (PR2) may include, for example, a positive photoresist.
[0193] Referring to FIG. 11e, a plurality of upper metal layers (332) and a plurality of dummy via structures (335) may be formed.
[0194] A conductive material can be filled into the plurality of second and third openings (OP2, OP3) to form an upper metal layer (332) and a dummy via structure (335). The upper metal layer (332) can be formed by an electroplating process using a seed layer (see 332' in FIG. 4) within the plurality of second openings (OP2). The dummy via structure (335) can be formed by an electroplating process using a seed layer (see 335' in FIG. 4) within the plurality of third openings (OP3). The seed layers may include titanium (Ti), copper (Cu), etc.
[0195] The conductive material may fill the plurality of grooves. In another aspect, a plurality of grooves (GR) corresponding to the plurality of grooves may be formed on the surface of each of the plurality of upper metal layers (332). A plurality of grooves (GR') corresponding to the plurality of grooves may be formed on the surface of each of the plurality of dummy via structures (335).
[0197] Referring to FIG. 11f, a suture material (320) can be formed.
[0198] The first and second photoresist layers (PR1, PR2) are removed, and a sealant (320) can be formed on the lower rewiring structure (310). The sealant (320) can cover the chip structure (100), the cover layer (150), the posts (330), and the dummy structures (335). The sealant (320) may include, for example, EMC and may be formed by a Molded UnderFill (MUF) process.
[0200] Referring to Fig. 11g, an upper rewiring structure (350) can be formed on the suture material (320).
[0201] The upper redistribution structure (350) may include an upper insulating layer (351), an upper redistribution layer (352), and an upper redistribution via (353). Subsequently, the lower redistribution structure (310), the sealant (320), and the upper redistribution structure (350) can be cut along the scribe lane (SC) to separate the unit packages (300'').
[0203] The present disclosure is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art without departing from the technical spirit of the present disclosure as described in the claims, and such are also to be considered to fall within the scope of the present disclosure. Explanation of the symbols
[0204] 100: Lower chip structure 100P: Connection terminals 150: Cover layer 310: Lower redistribution structure 320: Suture 320_1: Part 1 320_2: Part 2 320_3: Part 3 330: Post 331: Lower metal layer 332: Upper metal layer 335: Via structure 350: Upper redistribution structure 351: Upper insulation layer 352: Upper redistribution layers 353: Upper rewiring via 353L: Bottommost upper rewiring via 360: External connection bumps BP: Connection bumps SL: Solder part PL: Pillar part
Claims
Claim 1 A semiconductor package comprising: a lower redistribution structure including a lower redistribution layer; a lower chip structure on the lower redistribution structure; a sealing material covering the lower chip structure; a post penetrating the sealing material and connected to the lower redistribution layer; and external connection bumps disposed below the lower redistribution structure and electrically connected to the lower redistribution layer, wherein the post comprises: a first portion disposed on the lower redistribution layer of the lower redistribution structure and extending vertically from the lower redistribution layer; and a second portion on the first portion, wherein the width of the lower region of the second portion is smaller than the width of the upper region of the first portion, and the surface roughness of the side of the second portion is greater than the surface roughness of the side of the first portion. Claim 2 A semiconductor package according to claim 1, wherein the second portion has a shape with a width that increases from the lower region of the second portion to the upper region of the second portion. Claim 3 A semiconductor package according to claim 1, further comprising: an upper chip structure disposed on the sealant and having a lower surface on which a connection terminal is disposed; and a connection bump disposed between the connection terminal of the upper chip structure and the second portion of the post, electrically connecting the connection terminal and the second portion. Claim 4 A semiconductor package according to claim 1, wherein the lower chip structure comprises: a base chip including connection pads electrically connected to the lower redistribution layer, upper pads facing the connection pads, and through vias electrically connecting the connection pads and the upper pads; and at least one stacked chip disposed on the base chip, electrically connected to the base chip, and having a lower surface on which the lower pads are disposed. Claim 5 A semiconductor package according to claim 1, further comprising an upper redistribution structure disposed on the sealant and including a plurality of upper redistribution layers and upper redistribution vias electrically connecting the plurality of upper redistribution layers, wherein the second portion of the post electrically connects the first portion and the first upper redistribution via located at the lowest of the upper redistribution vias. Claim 6 A semiconductor package comprising: a lower redistribution structure including a lower redistribution layer; a chip structure on the lower redistribution structure; a sealing material covering the chip structure; an upper redistribution structure disposed on the sealing material and including an upper insulating layer, and an upper redistribution layer and an upper redistribution via within the upper insulating layer; a plurality of posts penetrating the sealing material and electrically connecting the lower redistribution layer and the upper redistribution layer; and external connection bumps disposed below the lower redistribution structure and electrically connected to the lower redistribution layer, wherein each of the plurality of posts comprises: a lower metal layer on the lower redistribution layer of the lower redistribution structure; and an upper metal layer disposed between the lower metal layer and the upper redistribution via and electrically connecting the lower metal layer and the upper redistribution via, wherein the width of the upper metal layer increases in the vertical direction, and the surface of the upper metal layer has a plurality of grooves, the width of the lower region of the upper metal layer is smaller than the width of the upper region of the lower metal layer, and at least a portion of the sealing material fills the plurality of grooves of the upper metal layer. Claim 7 In claim 6, the upper insulating layer of the upper redistribution structure covers the edge of the upper metal layer of the post and the sealant, in a semiconductor package. Claim 8 A semiconductor package according to claim 6, further comprising: a cover layer including a first surface in contact with the chip structure and a second surface opposite to the first surface; and a plurality of via structures between the lower surface of the upper insulating layer of the upper redistribution structure and the second surface of the cover layer. Claim 9 A lower redistribution structure comprising a lower redistribution layer; a chip structure on the lower redistribution structure; an upper redistribution structure disposed on the chip structure and comprising an upper redistribution layer; at least one post electrically connecting the lower redistribution layer and the upper redistribution layer on at least one side of the chip structure; and a sealant covering the chip structure and a plurality of posts between the lower redistribution structure and the upper redistribution structure, wherein the at least one post comprises a lower metal layer on the lower redistribution layer of the lower redistribution structure; and an upper metal layer disposed between the lower metal layer and the upper redistribution layer and electrically connecting the lower metal layer and the upper redistribution layer, wherein the surface of the upper metal layer has a plurality of grooves, and the sealant comprises a first portion covering the rear surface of the chip structure. A semiconductor package comprising a second portion extending horizontally from at least a portion of the first portion, filling the plurality of grooves of the upper metal layer of the post, covering the edge of the upper surface of the lower metal layer of the post, and surrounding at least a portion of the side of the lower metal layer of the post. Claim 10 A semiconductor package according to claim 9, wherein the sealant further comprises a third portion extending from the second portion toward the upper surface of the lower redistribution structure and surrounding a portion of the side of the chip structure and the side of the lower metal layer of the post.