NANO electromechanical capacitive memory device and method for manufacturing the same

Abstract

According to an embodiment of the present application, a nanoelectromechanical capacitive memory device and a method for manufacturing the same are provided. The memory device comprises: a first lower electrode and a second lower electrode spaced apart from each other; a plurality of via structures formed on the upper side of the first lower electrode and the second lower electrode; a first upper electrode and a second upper electrode respectively disposed on the upper side of the first lower electrode and the second lower electrode so as to contact the upper side of the via structures; a movable beam disposed between the first upper electrode and the second upper electrode; and a support member connected to one side of the movable beam to support the movable beam, wherein the via structures can form a first capacitance between the first upper electrode and the first lower electrode and form a second capacitance between the second upper electrode and the second lower electrode.

Description

Technology Field

[0001] The present application relates to a nanoelectromechanical capacitive memory device and a method for manufacturing the same. Background Technology

[0002] Resistance-based nanoelectromechanical memory devices have garnered attention as a next-generation memory technology that offers high compatibility with CMOS processes, low power consumption, and non-volatility. These devices feature a structure that stores information by utilizing the flow of current when a movable beam contacts a specific electrode. Compared to conventional DRAM, SRAM, and Flash memory, they offer the advantages of operating at lower operating voltages and facilitating 3D integration. Additionally, switching methods utilizing metal-to-metal contact can provide fast response speeds, and active research has been conducted in various memory application fields based on their high compatibility with existing semiconductor processes.

[0003] However, resistance-based nanoelectromechanical memory has several limitations. For instance, when implementing a memory array structure, a 2T1N (2-Transistor-1-NEM Memory) structure, which requires two transistors to perform selective read and write operations, must be used. Since this structure requires additional transistors, it increases the area of ​​the unit cell and limits its application to high-density memory. Furthermore, due to the nature of resistance-based switching methods, current flows continuously during switching operations, leading to issues with leakage current and static power consumption. In particular, repeated current flow between the moving beam and the electrode induces Joule heating, and increases the likelihood of stiction failure, where the metal-to-metal contact surface welds during long-term operation. When this phenomenon occurs, the movable beam becomes stuck to the electrode and can no longer perform normal switching operations, and as a result, the lifespan of the device is shortened and reliability is reduced.

[0004] These reliability issues are acting as a major factor hindering the commercialization of resistance-based nanoelectromechanical memory devices. In particular, there are difficulties in meeting the high durability and power efficiency requirements of artificial intelligence (AI) computation and in-memory computing technologies that necessitate large-scale parallel processing.

[0005] Therefore, there is a need to develop a new memory device that can overcome the limitations of existing resistance-based nanoelectromechanical memory devices and simultaneously improve reliability and power efficiency. The problem to be solved

[0006] The present application aims to provide a nanoelectromechanical capacitive memory device and a method for manufacturing the same. means of solving the problem

[0007] According to an embodiment of the present application, a nanoelectromechanical capacitive memory device is provided. The memory device comprises: a first lower electrode and a second lower electrode spaced apart from each other; a plurality of via structures formed on the upper side of the first lower electrode and the second lower electrode; a first upper electrode and a second upper electrode respectively disposed on the upper side of the first lower electrode and the second lower electrode so as to contact the upper side of the via structures; a movable beam disposed between the first upper electrode and the second upper electrode; and a support member connected to one side of the movable beam to support the movable beam, wherein the via structures can form a first capacitance between the first upper electrode and the first lower electrode and form a second capacitance between the second upper electrode and the second lower electrode.

[0008] In addition, the memory element can store at least two data states depending on whether it is in contact with the first upper electrode and the second upper electrode of the movable beam.

[0009] In addition, the via structure can form a metal-insulator-metal (MIM) capacitor between the first upper electrode and the first lower electrode and between the second upper electrode and the second lower electrode.

[0010] Additionally, the via structure may include a metal structure in contact with the first upper electrode and the second upper electrode; and an insulator deposited on the upper portion of the first lower electrode and the second lower electrode to surround the metal structure from the outside.

[0011] In addition, a third capacitance smaller in size than the first capacitance and the second capacitance may be formed by an air gap between at least one electrode among the first upper electrode and the second upper electrode that is not in contact with the movable beam and the movable beam.

[0012] Additionally, the memory element may form a high capacitance state (HCS) by the first capacitance or the second capacitance on the side of the electrode in contact with the movable beam among the first upper electrode and the second upper electrode, and form a low capacitance state (LCS) by the third capacitance on the side of the electrode not in contact with the movable beam among the first upper electrode and the second upper electrode.

[0013] In addition, the ratio of the capacitance in the high capacitance state to the capacitance in the low capacitance state may be 20 to 50:1.

[0014] In addition, the first capacitance and the second capacitance may be formed differently depending on at least one of the size and number of via structures formed between the first upper electrode and the first lower electrode and between the second upper electrode and the second lower electrode, respectively.

[0015] Additionally, a greater number of via structures are formed between the first upper electrode and the first lower electrode than between the second upper electrode and the second lower electrode, and the memory element can form a high capacitance state (HCS) by the first capacitance on the first upper electrode side when the movable beam contacts the first upper electrode, an intermediate capacitance state (MCS) by the second capacitance on the second upper electrode side when the movable beam contacts the second upper electrode, and a low capacitance state (LCS) by the second capacitance on the electrode side that does not contact the movable beam among the first upper electrode and the second upper electrode.

[0016] According to an embodiment of the present application, a memory device using a nanoelectromechanical capacitive memory element is provided. The memory device may include a memory cell array in which a plurality of unit memory cells, each composed of a nanoelectromechanical capacitive memory element, are arranged; at least one word line connected to a support portion of the memory element constituting the unit memory cell; and at least one bit line and bit line bar connected to a first lower electrode and a second lower electrode, respectively, of the memory element constituting the unit memory cell.

[0017] According to an embodiment of the present application, a method for manufacturing a nanoelectromechanical capacitive memory device is provided. The manufacturing method comprises the steps of: depositing a first insulating layer on a substrate and selectively etching the first insulating layer to form a region in which a lower wiring layer and a lower electrode are to be disposed; depositing a metal to form the lower electrode connected to the lower wiring layer; additionally depositing the first insulating layer and selectively etching the additionally deposited first insulating layer to form a plurality of via holes above the lower electrode; depositing a second insulating layer comprising a high dielectric constant material in an upper region including the inner side of the via holes; depositing a metal on the upper side of the second insulating layer to form a via structure in which a metal structure is wrapped by the second insulating layer in the inner side of the via holes; additionally depositing the first insulating layer in an upper region including the upper side of the via structure and selectively etching the additionally deposited first insulating layer to form a plurality of concave portions. The method may include the step of depositing a metal in an upper region including the inner side of the concave portion to form a movable beam disposed between an upper electrode disposed on the upper side of the via structure and the upper electrode; and the step of removing a portion of the first insulating layer so that the movable beam can move.

[0018] In addition, the via structure can form a metal-dielectric-metal (MIM) capacitor between the upper electrode and the lower electrode.

[0019] According to an embodiment of the present application, a method for manufacturing a nanoelectromechanical capacitive memory device is provided. The manufacturing method comprises the steps of: depositing a first insulating layer on a substrate and selectively etching the first insulating layer to form a region in which a lower wiring layer and a lower electrode are to be disposed; depositing a metal to form the lower electrode connected to the lower wiring layer; additionally depositing the first insulating layer and selectively etching the additionally deposited first insulating layer to form a first concave portion in which a plurality of via holes are formed in the lower portion and a second concave portion disposed between the first concave portion; depositing a second insulating layer comprising a high dielectric constant material in an upper region including the inner side of the first concave portion; and depositing a metal in an upper region including the inner side of the first concave portion and the inner side of the second concave portion to form a via structure in which a metal structure is wrapped by the second insulating layer and an upper electrode in the inner side of the first concave portion, and forming a movable beam in the inner side of the second concave portion. and may include the step of removing a portion of the first insulating layer so that the movable beam can move.

[0020] In addition, the via structure can form a metal-dielectric-metal (MIM) capacitor between the upper electrode and the lower electrode. Effects of the invention

[0021] According to the embodiments of the present application, a memory device having ultra-low power operation characteristics can be provided. By applying a data storage method utilizing capacitance change, static current is not generated during the read / write process, and consequently, energy consumption can be significantly reduced compared to conventional resistance-based memory.

[0022] In addition, according to the embodiments of the present application, the sneak path problem is eliminated due to the open circuit characteristics of the capacitor, so additional transistors are unnecessary, and the area occupied in the CMOS FEOL stage is significantly reduced, thereby increasing the integration density of the memory array.

[0023] In addition, according to the embodiments of the present application, since static current does not flow during the read / write process, the problem of reduced reliability due to the contact welding phenomenon can be prevented, and thereby, the long-term operational stability of the memory device can be corrected.

[0024] Furthermore, according to the embodiments of the present application, the manufacturing process can be simplified while maintaining high compatibility with existing CMOS processes. Since only an additional insulating layer deposition process is required in the area where the nanoelectromechanical capacitive memory is to be formed in the copper wiring process, it can be easily integrated with existing semiconductor manufacturing processes, making mass production and commercialization highly feasible.

[0025] The effects obtainable from the embodiments of the present application are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art to which the present application belongs from the description below. Brief explanation of the drawing

[0026] A brief description of each drawing is provided to help to better understand the drawings cited in this application. FIGS. 1 and 2 are drawings for explaining the structure of a nanoelectromechanical capacitive memory device according to an embodiment of the present application. FIGS. 3a to 3c are drawings for explaining the operation of a nanoelectromechanical capacitive memory device according to an embodiment of the present application. FIGS. 4a and 4b are drawings for illustrating a memory device implemented through a nanoelectromechanical capacitive memory element according to an embodiment of the present application. FIGS. 5 and 6 are drawings for explaining the programming process of a memory device implemented as a nanoelectromechanical capacitive memory element according to an embodiment of the present application. FIG. 7 is a diagram illustrating a reading process for a memory device implemented as a nanoelectromechanical capacitive memory element according to an embodiment of the present application. FIG. 8a is a diagram illustrating a method for controlling capacitance in a nanoelectromechanical capacitive memory device according to an embodiment of the present application. FIG. 8b is a diagram illustrating a method for implementing three capacitance states through a nanoelectromechanical capacitive memory device according to an embodiment of the present application. FIGS. 9a and 9b are drawings for explaining a method for manufacturing a nanoelectromechanical capacitive memory device according to an embodiment of the present application. FIGS. 10a and FIGS. 10b are drawings for explaining a method for manufacturing a nanoelectromechanical capacitive memory device according to an embodiment of the present application. Specific details for implementing the invention

[0027] Hereinafter, embodiments of the present application will be described in detail with reference to the contents described in the attached drawings. Identical reference numbers or symbols presented in each drawing indicate parts or components that perform substantially the same function. For convenience of reference, the directions of up, down, left, and right described below are based on the drawings, and the scope of the rights of the present application is not limited to such directions.

[0028] In describing the technical concept of the present application, detailed descriptions of related prior art are omitted if it is determined that such descriptions would unnecessarily obscure the essence of the present application. Furthermore, numbers used in the description of the present application (e.g., First, Second, etc.) are merely identification symbols to distinguish one component from another.

[0029] The terms used herein are for the purpose of describing embodiments and are not intended to limit or / or restrict the present application. Singular expressions include plural expressions unless the context clearly indicates otherwise. When a part is described as being connected to another part in this specification, this includes not only cases where they are directly connected but also cases where they are indirectly connected with other components in between. Furthermore, when a part is described as including a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0030] Furthermore, in this application, the term "or" is intended to mean an implicit "or" rather than an exclusive "or." That is, unless otherwise specified or evident from the context, "X uses A or B" is intended to mean one of the natural implicit substitutions. In other words, if X uses A; if X uses B; or if X uses both A and B, "X uses A or B" may apply to any of these cases. Additionally, the term "and / or" as used herein should be understood to refer to and include all possible combinations of one or more of the enumerated related configurations.

[0031] Furthermore, when it is stated in this application that a member is located "on," "on the upper side," "on the upper side," "under," "on the lower side," or "on the lower side" of another member, this includes not only cases where a member is in contact with another member, but also cases where another member exists between the two members.

[0032] Furthermore, in this application, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0033] Furthermore, terms such as "approximately" and "substantially" as used in this application are used to mean at or near the stated value when inherent manufacturing and material tolerances are presented in the said sense, and are used to prevent unscrupulous infringers from unfairly exploiting the disclosure in which precise or absolute values ​​are mentioned to aid in understanding this application. Additionally, in this application, "steps to" or "steps of" do not mean "steps for."

[0034] Furthermore, it is intended to clarify that the classification of the components in this application is merely based on the primary function each component is responsible for. That is, two or more components described below may be combined into a single component, or a single component may be divided into two or more components based on more subdivided functions. Additionally, each component described below may additionally perform some or all of the functions performed by other components in addition to its own primary function, and it is obvious that some of the primary functions performed by each component may be exclusively performed by other components.

[0036] Hereinafter, embodiments of the present application will be described in detail in turn.

[0038] FIGS. 1 and 2 are drawings for explaining the structure of a nanoelectromechanical capacitive memory device according to an embodiment of the present application.

[0039] Specifically, FIG. 1 shows a perspective view of a memory device, FIG. 2 (a) shows a plan view of a memory device, and FIG. 2 (b) shows a vertical cross-sectional view of a memory device. Meanwhile, in FIG. 2 (b), one via structure is shown in each electrode area, but this is for convenience of explanation, and it is obvious that more via structures can be formed in the vertical cross-section.

[0040] The memory element (100) refers to a device that stores or retrieves data by mechanically controlling an electrical signal at a nanoscale, and in the present application, the memory element (100) can store a plurality of data states according to the switching operation of the movable beam (130).

[0041] Referring to FIGS. 1 and 2, the memory element (100) may include a lower electrode (110-1, 120-1), an upper electrode (110-2, 120-2), a movable beam (130), a support member (140), and a via structure (150).

[0042] The lower electrode (110-1, 120-1) includes a first lower electrode (110-1) and a second lower electrode (120-1), and the first lower electrode (110-1) and the second lower electrode (120-1) may be formed spaced apart from each other in a metal wiring layer at the bottom of the memory element (100). The first lower electrode (110-1) and the second lower electrode (120-1) are each connected to a bit line bar ( / Bit Line, / BL) and a bit line (Bit Line, BL), respectively, so that a write voltage or a read voltage can be applied therefrom.

[0043] The upper electrode (110-2, 120-2) includes a first upper electrode (110-2) and a second upper electrode (120-2), the first upper electrode (110-2) is spaced apart from the upper side of the first lower electrode (110-1), and the second upper electrode (120-2) can be spaced apart from the upper side of the second lower electrode (120-1).

[0044] The lower electrode (110-1, 120-1) and the upper electrode (110-2, 120-2) can be interconnected by a via structure (150) formed between them.

[0045] The lower electrode (110-1, 120-1) and the upper electrode (110-2, 120-2) can be implemented with a metal material such as copper, for example.

[0046] The movable beam (130) is a metal beam coupled to the support member (140) and is positioned between the first upper electrode (110-2) and the second upper electrode (120-2), and can come into contact with a specific upper electrode (110-2, 120-2) upon the application of an electrical signal to the lower electrode (110-1, 120-1) through a bit line. Specifically, when a write voltage is applied to the lower electrode (110-1, 120-1), the movable beam (130) moves toward the first upper electrode (110-2) or the second upper electrode (120-2) by an electrostatic force and can come into contact with the specific upper electrode (110-2, 120-2). Meanwhile, after contact, the state can be stably maintained by a Van der Waals force to provide non-volatile memory characteristics.

[0047] The memory element (100) can store at least two data states depending on whether it is in contact with the first upper electrode (110-2) and the second upper electrode (120-2) of the movable beam (130).

[0048] An anchor (140) is a structure that physically supports one end of a movable beam (130) by fixing it, and helps maintain a movable state of the movable beam (130) between the first upper electrode (110-2) and the second upper electrode (120-2). The anchor (140) can be connected to a word line (WL).

[0049] In the embodiment, the movable beam (130) and the support member (140) may be formed integrally and may be made of the same copper material as the upper electrode (110-2, 120-2) and the lower electrode (110-1, 120-1).

[0050] At least some of the lower electrode (110-1, 120-1), upper electrode (110-2, 120-2), movable beam (130), and support member (140) may have a barrier metal layer (B) formed thereon. The barrier metal layer (B) can prevent the metal constituting the electrode, movable beam, and support member from diffusing into an insulating layer or silicon, etc. during the manufacturing process of the memory device (100).

[0051] A via structure (150) is positioned between a lower electrode (110-1, 120-1) and an upper electrode (110-2, 120-2) to connect the two electrodes. Specifically, a plurality of via structures (150) may be formed on the upper surface of the first lower electrode (110-1) and the second lower electrode (120-1), respectively, and the first upper electrode (110-2) and the second upper electrode (120-2) may be connected to the upper side of the via structures (150), respectively.

[0052] The via structure (150) may include a metal structure (151) in contact with an upper electrode (110-2, 120-2) and an insulator (152) deposited on the upper part of a lower electrode (110-1, 120-1) to surround the metal structure (151) from the outside.

[0053] Through this structure, the via structure (150) can form a metal-insulator-metal (MIM) capacitor between the lower electrode (110-1, 120-1) and the upper electrode (110-2, 120-2). That is, the metal structure (151) inside the via structure (150), the insulator (152) surrounding it, and the lower electrode (110-1, 120-1) can form a metal-insulator-metal (MIM) capacitor.

[0054] The via structure (150) functions as a capacitor to form a first capacitance between the first upper electrode (110-2) and the first lower electrode (110-1), and can form a second capacitance between the second upper electrode (120-2) and the second lower electrode (120-1).

[0055] The first capacitance and the second capacitance may be formed differently depending on at least one of the size and number of via structures (150) formed between the first upper electrode (110-2) and the first lower electrode (110-1) and between the second upper electrode (120-2) and the second lower electrode (120-1), the deposition thickness of the insulator (152) formed in each via structure (150), the type of insulator (152), etc.

[0056] The insulator (152) may be composed of a high dielectric constant material such as aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), silicon nitride (Si₃N₄), tantalum pentoxide (Ta₂O₅), titanium dioxide (TiO₂), and hafnium silicon tetroxide (HfSiO₄), and preferably may be composed of aluminum oxide (Al₂O₃) or hafnium oxide (HfO₂).

[0057] Meanwhile, in the memory element (100), a third capacitance smaller than the first capacitance and the second capacitance may be formed by an air gap between the movable beam (130) and at least one upper electrode (110-2, 120-2) that is not in contact with the movable beam (130) among the first upper electrode (110-2) or the second upper electrode (120-2). By these first to third capacitances, the memory element (100) may form a high capacitance state (HCS) and a low capacitance state (LCS).

[0058] In an embodiment, a plurality of memory elements (100) may be formed to be connected in a constant manner to form a memory cell array. At this time, each memory element (100) may operate as a unit memory cell. This will be described in detail below with reference to FIGS. 4a to 7.

[0059] Meanwhile, the configuration of the memory element (100) described above with reference to FIGS. 1 and 2 may be varied according to the embodiment to which the present application is applied as an exemplary.

[0061] FIGS. 3a to 3c are drawings for explaining the operation of a nanoelectromechanical capacitive memory device according to an embodiment of the present application.

[0062] Specifically, FIG. 3a illustrates a memory element in an initial state (Pristine) where the movable beam (130) does not come into contact with either upper electrode (110-2, 120-2), FIG. 3b illustrates a first state where the movable beam (130) comes into contact with the first upper electrode (110-2), and FIG. 3c illustrates a second state where the movable beam (130) comes into contact with the second upper electrode (120-2). Meanwhile, the following description is to be made on the premise that via structures (150) are formed in equal numbers on both electrodes, so that the first capacitance and the second capacitance are equal.

[0063] As described above, the movable beam can change from an initial state to a first state or a second state depending on the application of voltage (write voltage) to the bit line (BL) and bit line bar ( / BL) connected to the lower electrode.

[0064] First, in the initial state, when a write voltage is applied to the bit line bar ( / BL) while the bit line (BL) is grounded, the movable beam (130) moves toward the first upper electrode (110-2) by electrostatic attraction and comes into contact, thereby changing to the first state. At this time, the movable beam (130) and the first upper electrode (110-2) continuously maintain contact without additional voltage by van der Waals attraction and store the state as a non-volatile memory.

[0065] Conversely, in the initial state, when a write voltage is applied to the bit line (BL) while the bit line bar ( / BL) is grounded, the movable beam (130) moves toward the second upper electrode (120-2) and comes into contact by the same principle, thereby changing to the second state.

[0066] Referring to (c) of FIG. 3a, in the initial state, a third capacitance (C) is generated by the air cap between the movable beam (130) and the upper electrodes (110-2, 120-2) spaced apart. cap The first capacitance (C1) or the second capacitance (C2) formed by the ) and the via structure (150) may also be connected in series. At this time, the third capacitance (C) formed by the air cap cap Since ) is sufficiently smaller than the first capacitance (C1) or the second capacitance (C2), the memory element (100) forms a low capacitance state (LSC).

[0067] Next, referring to (c) of FIG. 3b, in the case of the first state, the resistance (R) generated by the contact surface between the movable beam (130) and the first upper electrode (110-2) on the side of the first upper electrode (110-2) coThe first capacitance (C1) formed by the via structure (150) and the ) is also connected in series, thereby forming a high capacitance state (HSC). Meanwhile, on the side of the second upper electrode (110-2), the third capacitance (C cap ) and the second capacitance (C2) are connected in series to form a low capacitance state (LSC).

[0068] Next, referring to (c) of FIG. 3c, in the case of the second state, unlike the first state, a high capacitance state (HSC) can be formed on the second upper electrode (110-2) side by the same principle.

[0069] In summary, the memory element (100) forms a high capacitance state (HCS) by a first capacitance (C1) or a second capacitance (C2) on the side of the upper electrodes (110-2, 120-2) that are in contact with the movable beam (130), and a third capacitance (C) on the side of the electrode not in contact with the movable beam (130). cap A low capacitance state (LCS) can be formed by ).

[0070] In the embodiment, for the operational reliability of the memory element (100), the ratio of the capacitance of the high capacitance state (HCS) to the capacitance of the low capacitance state (LCS) may be 10 to 50:1.

[0072] FIGS. 4a and 4b are drawings for illustrating a memory device implemented through a nanoelectromechanical capacitive memory element according to an embodiment of the present application.

[0073] Specifically, FIG. 4a is a perspective view illustrating the configuration of a memory device in an exemplary manner, and FIG. 4b is a circuit diagram illustrating the memory element of FIG. 4a.

[0074] A memory device may include a memory cell array and a plurality of word lines (WL), bit lines (BL), and bit line bars ( / BL) for applying electrical signals to the memory cell array.

[0075] A memory cell array may have a plurality of unit memory cells arranged in a predetermined manner. At this time, the unit memory cells may be implemented through the nanoelectromechanical capacitive memory device described above with reference to FIGS. 1 to 3c.

[0076] A transistor for selective application of a signal may be connected to a plurality of word lines (WL), bit lines (BL), and bit line bars ( / BL).

[0077] By applying voltage to the word line (WL), bit line (BL), and / or bit line bar ( / BL), a write (program) operation to store a data state in the unit memory cell and a read operation to read the stored data state can be performed. For example, as shown in FIGS. 4a and 4b, unique data can be stored in each unit memory cell by selectively contacting a different electrode with a movable beam of a memory element included in the unit memory cell.

[0078] Meanwhile, FIGS. 4a and 4b show that unit memory cells are arranged in a 3x3 array to form a memory cell array, but this is exemplary, and memory cell arrays of various arrangements can be implemented according to embodiments of the present application.

[0080] FIGS. 5 and 6 are diagrams illustrating a programming process for a memory device implemented as a nanoelectromechanical capacitive memory element according to an embodiment of the present application. In FIGS. 5 and 6, for convenience of explanation, a write operation is described using a memory device implemented as a 2x2 array.

[0081] As shown in graph (a) of Fig. 6, by applying control voltages to BL, / BL and WL, Cell 11 and Cell 22 can be selectively programmed in sequence.

[0082] First, to program Cell 11, apply voltage (Vpi) to BL1 while simultaneously applying voltage (V) to BL1_cont and WL1_cont DD ) is applied to activate BL1 and connect WL1 to ground. Accordingly, the movable beam (130) is pulled in to the second upper electrode (120-2) and comes into contact with the second upper electrode (120-2). Meanwhile, WL2_cont is not activated and WL2 is kept in a floating state. Accordingly, the voltage of WL2 is coupled by BL1 and rises, but the voltage between the movable beam (130) and the upper electrode (110-2, 120-2) in Cell 12 is maintained below Vpi, so no program operation is performed. This means that the selective program operation is performed normally, which can be confirmed through the movable beam displacement of each cell in FIG. 6 (b).

[0083] Next, to use Cell 22, Vpi is applied to / BL2, WL2 is connected to ground, and WL1 is left in a floating state. According to the same principle, only the movable beam of Cell 22 is pulled in to the first upper electrode (110-2) and comes into contact with the first upper electrode (110-2), while the movable beam of Cell 21 is not pulled in because a sufficient voltage difference is not formed.

[0084] Finally, to switch Cell 11, which has already been pulled into the second upper electrode (120-2) and is storing its state without external voltage, to the first upper electrode (110-2), a switching voltage is applied to / BL1, WL1 is connected to ground, and WL2 is kept in a floating state. Through this, it can be confirmed that only Cell 11 is selectively switched without changing the storage state of the remaining cells.

[0085] Meanwhile, after the program operation, input voltage is applied to BL and / BL and WL is connected to ground, thereby allowing a read operation to be performed based on the amount of charge stored due to the capacitance difference.

[0087] FIG. 7 is a diagram illustrating a reading process for a memory device implemented as a nanoelectromechanical capacitive memory element according to an embodiment of the present application.

[0088] The memory device of FIG. 7 is in a state where a program is executed for each unit memory cell, just like the memory device shown in FIG. 4a and FIG. 4b, and accordingly, it can be seen that a large capacitance is formed on the electrode side where the movable beam (130) is in contact.

[0089] In a plurality of word lines (WL1 to WL3), there is an amplifier for detecting the output and a reference capacitor (C ref ) can be connected.

[0090] First, apply 0V (ground voltage) to BL and simultaneously activate (turn on) the input and output ground switches of the amplifier. Subsequently, apply the read voltage (V) to BL read Apply ) and apply 0V to / BL to charge the capacitor activated according to the program state of each unit memory cell.

[0091] After charging is complete, if the ground switches of the amplifier's input and output are disabled (Off) and BL is set back to 0V, the charges stored in the capacitors of each unit memory cell [are transferred] to the reference capacitor (C ref It is transferred as ). Subsequently, depending on the transferred charge amount, the output voltage (V out ) is formed, and by measuring it, a memory read operation can be performed.

[0093] FIG. 8a is a diagram illustrating a method for controlling capacitance in a nanoelectromechanical capacitive memory device according to an embodiment of the present application, and FIG. 8b is a diagram illustrating a method for implementing three capacitance states through the memory device of FIG. 8a.

[0094] First, referring to FIG. 8a, the number of via structures (150) formed on the spaced-apart electrodes (110-2, 120-2) can be implemented differently. For example, more via structures (150) can be formed on the side of the second upper electrode (120-2) than on the side of the first upper electrode (110-2). Accordingly, the third capacitance formed between the second upper electrode (120-2) and the second lower electrode (120-1) can be implemented to be larger than the second capacitance formed between the first upper electrode (110-2) and the first lower electrode (110-1).

[0095] Depending on the difference in capacitance between the electrodes, the memory device can have three capacitance states, as shown in FIG. 8b.

[0096] First, in the initial state where the movable beam (130) does not come into contact with either upper electrode (110-2, 120-2), a low capacitance state can be formed as described above. Meanwhile, when the movable beam (130) comes into contact with the first upper electrode (110-2), an intermediate capacitance state (MCS) is formed by the second capacitance, and when the movable beam (130) comes into contact with the second upper electrode (120-2), a high capacitance state (HCS) is formed by the third capacitance.

[0098] FIGS. 9a and 9b are drawings for explaining a method for manufacturing a nanoelectromechanical capacitive memory device according to an embodiment of the present application.

[0099] In the first step, a first insulating layer (910) is deposited on a substrate, and lithography and etching processes are performed to form a region where a lower wiring layer and a lower electrode (110-1, 120-1) are to be placed ((a) of FIG. 9a).

[0100] During this process, lithographic patterning and etching of the first insulating layer (910) are performed, and a barrier metal layer (B) may be additionally deposited. The first insulating layer (910) may be composed of, for example, SiO₂ (silicon dioxide), and the barrier metal layer (B) may be composed of Ta / TaN (tantalum / tantalum nitride).

[0101] In the second step, a metal (920) can be deposited on the upper side to form a lower electrode (110-1, 120-1) connected to the lower wiring layer ((b) and (c) of FIG. 9a).

[0102] That is, after the first step, copper (Cu) deposition is performed, and a process of planarizing the surface is carried out through CMP (chemical mechanical polishing) and etch stop layer (C) deposition. Through this, the lower electrode (110-1, 120-1) and the wiring layer can be formed. The etch stop layer (C) may also be referred to as a capping layer and may be composed of, for example, SiN (silicon nitride).

[0103] In the third step, a first insulating layer (910) may be additionally deposited on the upper side, and the additionally deposited first insulating layer (910) may be selectively etched to form a plurality of via holes (930) on the upper side of the lower electrode (110-1, 120-1) ((d) of FIG. 9a).

[0104] In the same way as in the first step, a via pattern (i.e., via hole (930)) is formed through lithography and etching. Through the via hole (930), a connection between the upper and lower wiring layers is made possible.

[0105] In the fourth step, a second insulating layer (940) can be deposited in an upper region including the inner side of the via hole (930) (e of FIG. 9a).

[0106] This step is for forming an MIM capacitor, wherein a second insulating layer (940) is deposited, and additionally, a barrier metal layer (B) may be deposited.

[0107] The second insulating layer (940) may be composed of a high dielectric constant material such as aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), silicon nitride (Si₃N₄), tantalum pentoxide (Ta₂O₅), titanium dioxide (TiO₂), and hafnium silicon tetroxide (HfSiO₄), and preferably may be composed of aluminum oxide (Al₂O₃) or hafnium oxide (HfO₂).

[0108] In the fifth step, a metal (920) can be deposited on the upper side of the second insulating layer (940) to form a via structure (150) in which a metal structure is wrapped by the second insulating layer (940) inside the via hole (930) ((f) in FIG. 9a and (g) in FIG. 9b).

[0109] In this step, the interior of the via hole (930) is filled and planarized through copper deposition and CMP processes. The formed via structure (150) is positioned above the lower electrode (110-1, 120-1), thereby forming an MIM capacitor structure in which the lower electrode (110-1, 120-1), the second insulating layer (940), the barrier metal layer (B), and the metal structure are stacked in order.

[0110] In the sixth step, a first insulating layer (910) may be additionally deposited in an upper region including the upper portion of the via structure (150), and the additionally deposited first insulating layer (910) may be selectively etched to form a plurality of concave portions (950) ((h) of FIG. 9b).

[0111] Here, a plurality of concave portions (950) are configured with shapes corresponding to upper electrodes (110-2, 120-2), movable beams (130), etc., and in particular, the concave portions (950) corresponding to upper electrodes (110-2, 120-2) can be etched (or patterned) to be connected to via holes (930).

[0112] In the seventh step, a metal (920) is deposited in an upper region including the inner side of the concave portion (950) to form a movable beam (130) positioned between the upper electrode (110-2, 120-2) and the upper electrode (110-2, 120-2) positioned on the upper side of the via structure (150).

[0113] That is, through the processes of copper deposition, CMP (chemical mechanical polishing), and etching stop layer (C) deposition, an upper electrode (110-2, 120-2) connected to the metal of the via structure (150) and a movable beam (130) are formed. Meanwhile, at this stage, a support member (140) supporting the movable beam (130) can be formed integrally with the movable beam (130). To this end, in the sixth step, a concave portion (950) corresponding to the shape of the support member (140) can be further created.

[0114] In the eighth step, a portion of the first insulating layer (910) can be removed to allow the movable beam (130) to move. That is, in this step, a process is performed to release the movable beam (130) by etching SiN and SiO₂. This allows the movable beam (130) to move freely and enables the operation of the nanoelectromechanical capacitive memory device.

[0116] FIGS. 10a and FIGS. 10b are drawings for explaining a method for manufacturing a nanoelectromechanical capacitive memory device according to an embodiment of the present application.

[0117] First, in the first and second steps, a first insulating layer (910) is deposited on a substrate, and the first insulating layer (910) is optionally etched to form a region where a lower wiring layer and a lower electrode (110-1, 120-1) are to be placed (Fig. 10a (a)), and then a metal (920) is deposited to form a lower electrode (110-1, 120-1) connected to the lower wiring layer (Fig. 10a (b) and (c)). These steps can be performed in the same manner as the first and second steps described above with reference to Figs. 9a and 9b.

[0118] In the embodiment, the lower part of the support member (140) may be formed together in the first and second steps.

[0119] Next, in the third step, a first insulating layer (910) is additionally deposited, and the additionally deposited first insulating layer (910) is selectively etched to form a first concave portion (1010) in which a plurality of via holes (930) are formed at the bottom, and a second concave portion (1020) disposed between the first concave portion (1010) ((d) of FIG. 10a).

[0120] In this step, a first insulating layer (910) and an etching stop layer (C) are deposited, and then an additional first insulating layer (910) is deposited on the upper side, and then a pattern corresponding to the first concave portion (1010) and the second concave portion (1020) can be formed through lithography and etching.

[0121] Here, the first concave portion (1010) has a shape corresponding to the via structure (150) and the upper electrode (110-2, 120-2) integrally connected thereto, and the second concave portion (1020) may have a formation corresponding to the upper part of the movable beam (130) and the support portion (140).

[0122] In the fourth step, a second insulating layer (940) containing a high dielectric constant material can be deposited in an upper region including the inner side of the first concave portion (1010) ((e) of FIG. 10a).

[0123] At this stage, the second insulating layer (940) is deposited only in the inner and surrounding portions of the first concave portion (1010), excluding the second concave portion (1020), and after the deposition of the second insulating layer (940), the barrier metal layer (B) can be deposited over the entire area spanning the first concave portion (1010) and the second concave portion (1020).

[0124] In the fifth step, a metal (920) is deposited in an upper region including the inner side of the first concave portion (1010) and the second concave portion (1020) to integrally form a via structure (150) in which a metal structure is wrapped by a second insulating layer (940) and an upper electrode (110-2, 120-2) inside the first concave portion (1010), and a movable beam (130) and a support portion (140) can be formed inside the second concave portion (1020) ((f) in FIG. 10a and (g) in FIG. 10b).

[0125] That is, through the processes of copper deposition, CMP (chemical mechanical polishing), and etching stop layer (C) deposition, a via structure (150) and an upper electrode (110-2, 120-2) are integrally formed in the first concave portion (1010), and a movable beam (130) and a support portion (140) are formed inside the second concave portion (1020).

[0126] At this time, a second insulating layer (940) and a metal structure can be laminated on the upper side of the lower electrode (110-1, 120-1) to form an MIM capacitor structure.

[0127] In the sixth step, a portion of the first insulating layer (910) can be removed so that the movable beam (130) can move ((h) of FIG. 10b). That is, in this step, a process is carried out to release the movable beam (130) by performing SiN and SiO₂ etching.

[0129] Although the embodiments have been described in detail above, the scope of the present application is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present application as defined in the following claims also fall within the scope of the present application.

Claims

Claim 1 A nanoelectromechanical capacitive memory device comprising: a first lower electrode and a second lower electrode spaced apart from each other; a plurality of via structures formed on the upper side of the first lower electrode and the second lower electrode; a first upper electrode and a second upper electrode respectively disposed on the upper side of the first lower electrode and the second lower electrode so as to contact the upper side of the via structures; a movable beam disposed between the first upper electrode and the second upper electrode; and a support member connected to one side of the movable beam to support the movable beam, wherein the via structures form a first capacitance between the first upper electrode and the first lower electrode and form a second capacitance between the second upper electrode and the second lower electrode. Claim 2 In claim 1, the memory element stores at least two data states depending on whether the movable beam is in contact with the first upper electrode and the second upper electrode. Claim 3 A memory device according to claim 1, wherein the via structure forms a metal-insulator-metal (MIM) capacitor between the first upper electrode and the first lower electrode and between the second upper electrode and the second lower electrode. Claim 4 A memory device according to claim 1, wherein the via structure comprises: a metal structure in contact with the first upper electrode and the second upper electrode; and an insulator deposited on the upper portion of the first lower electrode and the second lower electrode to surround the metal structure from the outside. Claim 5 A memory device according to claim 1, wherein a third capacitance smaller than the first capacitance and the second capacitance is formed by an air gap between at least one electrode among the first upper electrode and the second upper electrode that is not in contact with the movable beam and the movable beam. Claim 6 In claim 5, the memory element forms a high capacitance state (HCS) by the first capacitance or the second capacitance on the side of the electrode in contact with the movable beam among the first upper electrode and the second upper electrode, and forms a low capacitance state (LCS) by the third capacitance on the side of the electrode not in contact with the movable beam among the first upper electrode and the second upper electrode. Claim 7 A memory element according to claim 6, wherein the ratio of the capacitance in the high capacitance state to the capacitance in the low capacitance state is 10 to 50:

1. Claim 8 A memory device according to claim 6, wherein the first capacitance and the second capacitance are formed differently depending on at least one of the size and number of via structures formed between the first upper electrode and the first lower electrode and between the second upper electrode and the second lower electrode, respectively. Claim 9 In claim 7, a greater number of via structures are formed between the first upper electrode and the first lower electrode than between the second upper electrode and the second lower electrode, and the memory element forms a high capacitance state (HCS) by the first capacitance on the first upper electrode side when the movable beam contacts the first upper electrode, forms an intermediate capacitance state (MCS) by the second capacitance on the second upper electrode side when the movable beam contacts the second upper electrode, and forms a low capacitance state (LCS) by the second capacitance on the electrode side among the first upper electrode and the second upper electrode that does not contact the movable beam. Claim 10 A memory cell array comprising a plurality of unit memory cells, each composed of a nanoelectromechanical capacitive memory element according to any one of claims 1 to 9; at least one word line connected to a support portion of the memory element constituting the unit memory cell; and at least one bit line and bit line bar connected to a first lower electrode and a second lower electrode of the memory element constituting the unit memory cell, respectively. Claim 11 A method for manufacturing a nanoelectromechanical capacitive memory device comprises the steps of: depositing a first insulating layer on a substrate and selectively etching the first insulating layer to form a region in which a lower wiring layer and a lower electrode are to be disposed; depositing a metal to form the lower electrode connected to the lower wiring layer; additionally depositing the first insulating layer and selectively etching the additionally deposited first insulating layer to form a plurality of via holes above the lower electrode; depositing a second insulating layer comprising a high dielectric constant material in an upper region including the inner side of the via holes; depositing a metal above the second insulating layer to form a via structure in which a metal structure is wrapped by the second insulating layer in the inner side of the via holes; additionally depositing the first insulating layer in an upper region including the upper side of the via structure and selectively etching the additionally deposited first insulating layer to form a plurality of concave portions; and depositing a metal in an upper region including the inner side of the concave portions to form a movable beam disposed between an upper electrode disposed on the upper side of the via structure and the upper electrode. A manufacturing method comprising the step of removing a portion of the first insulating layer so that the movable beam can move. Claim 12 A method of manufacturing wherein, in claim 11, the via structure forms a metal-dielectric-metal (MIM) capacitor between the upper electrode and the lower electrode. Claim 13 A method for manufacturing a nanoelectromechanical capacitive memory device, comprising: a step of depositing a first insulating layer on a substrate and selectively etching the first insulating layer to form a region in which a lower wiring layer and a lower electrode are to be disposed; a step of depositing a metal to form the lower electrode connected to the lower wiring layer; a step of additionally depositing the first insulating layer and selectively etching the additionally deposited first insulating layer to form a first concave portion in which a plurality of via holes are formed in the lower portion and a second concave portion disposed between the first concave portion; a step of depositing a second insulating layer comprising a high dielectric constant material in an upper region including the inner side of the first concave portion; a step of depositing a metal in an upper region including the inner side of the first concave portion and the inner side of the second concave portion to form a via structure in which a metal structure is wrapped by the second insulating layer and an upper electrode in the inner side of the first concave portion, and forming a movable beam in the inner side of the second concave portion; and a step of removing a portion of the first insulating layer so that the movable beam can move. Claim 14 A method of manufacturing wherein, in claim 13, the via structure forms a metal-dielectric-metal (MIM) capacitor between the upper electrode and the lower electrode.

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