Error-correcting code ram initialization apparatus and method

Abstract

The present invention relates to a RAM initialization device and method, and more specifically, to an ECC RAM initialization device and method that initializes an Error Correction Code (ECC) RAM by utilizing RAM used by any IP within the system to initialize the ECC RAM.

Description

Technology Field

[0001] The present invention relates to a RAM initialization device and method, and more specifically, to an ECC RAM initialization device and method that initializes an Error Correction Code (ECC) RAM by utilizing RAM used by any IP within the system to initialize the ECC RAM. Background Technology

[0002] As miniaturization process technology advances, it has become possible to implement memory cells with high integration density. However, at the same time, due to process limitations, the number of defective memory cells may increase, and data in memory cells may be written incorrectly or read incorrectly at times due to unknown causes. To solve these problems and correct data integrity, there is an increasing demand for memory that requires error checking and correction functions (Error Correction Code: ECC, or "Error Correction Code").

[0003] In the case of ECC RAM with the ECC function applied, an ECC error may occur due to the initial value of the read address of the ECC RAM when reading an area that has never been written.

[0004] In particular, since such errors can frequently occur during the prefetch process, where control units such as the CPU retrieve memory data in advance, RAM initialization is essential.

[0005] For this reason, an initialization task is required to write specific values ​​to the entire area of ​​RAM during the boot process, and this process causes the overall boot time to increase.

[0006] In particular, in systems such as PCIe, system initialization and configuration must be completed within 200ms, making the initialization time of RAM containing ECC RAM an even more critical factor. Since delays in initialization speed can affect the overall system performance, it is important to optimize the system so that ECC RAM initialization is performed quickly.

[0007] Typically, ECC RAM has a problem of long boot times because it enhances security by reading all cells of RAM using the ECC scrubbing method and correcting errors when detected, or by filling the initial memory with zeros or setting it to random values ​​using the zeroing method.

[0008] Therefore, there is a need to develop a device that can improve system performance while maintaining the reliability and stability of ECC RAM with ECC functionality by initializing ECC RAM in an optimized manner during the boot process to reduce the time required for initialization, prevent ECC errors, and simultaneously improve memory initialization speed. Prior art literature

[0009] Republic of Korea Registered Patent No. 10-0693559 (Published on March 14, 2007) The problem to be solved

[0010] Therefore, the objective of the present invention is to provide an ECC RAM initialization device and method that initializes the ECC RAM by utilizing the RAM used by any IP within the system. means of solving the problem

[0011] The ECC RAM initialization device of the present invention for achieving the above-mentioned purpose comprises: a first memory in which an initialization utilization area is allocated; a second memory which is an ECC RAM having a certain address depth and a data area for each address of the address depth, and processes writing, deleting, and reading data in the data area in address units; and a RAM initialization module which, when a RAM initialization event is detected by the input of an address generation start (START_FLAG) signal after a system reset, sets an initialization utilization area having a size corresponding to the address depth of the second memory in the first memory and initializes a tag bit corresponding to the size of the initialization utilization area as an initialization bit, and then initializes the data area of ​​the second memory with the initialization data in sequential address units for the address depth, and updates the tag bit of the initialization utilization area corresponding to the initialized address as an update bit.

[0012] The above device comprises: a function module and a bus connection terminal to which a bus transmitting and receiving a RAM bus control command and data therefrom is connected to the RAM initialization module, and a MUX connected to the first memory by a bus, wherein the MUX receives a selection signal from the RAM initialization module and connects either the bus of the function module or the bus of the RAM initialization module to the bus connected to the first memory, wherein the RAM initialization module outputs a module selection signal as a selection signal to the MUX to connect the first memory to the RAM initialization module when the initialization event occurs, and when the data area of ​​the last address according to the address depth of the second memory is initialized and the last tag bit of the initialization utilization area is updated, it outputs an IP selection signal as a selection signal to the MUX to connect the first memory to the function module.

[0013] The above RAM initialization module is characterized by allocating an initialization utilization area having a size corresponding to the address depth of the second memory and an address depth obtained by dividing the address depth of the second memory by the data width of the first memory.

[0014] The above RAM initialization module is configured to receive system control (SYS_CTRL) and an address (SYS_ADDR) by the control unit and output a RAM control command (RAM_CTRL), a RAM address command (RAM_ADDR), and RAM write data (RAM_WDATA) to the first memory, and when the RAM initialization event occurs, the first memory control unit outputs the first memory RAM control command (RAM_CTRL), a RAM address command (RAM_ADDR), and RAM write data (RAM_WDATA) to the first memory to allocate an initialization utilization area to the first memory and initialize the tag bit of the initialization utilization area with an initialization bit, or update the tag bit of the initialization utilization area corresponding to either the input address (SYS_ADDR) or the address (GEN_ADDR) with an update bit; A second memory control unit configured to receive system control (SYS_CTRL) and an address (SYS_ADDR) by the above control unit and output an ECC RAM control command (ECC_RAM_CTRL), an ECC RAM address command (ECC_RAM_ADDR), and ECC RAM write data (ECC_RAM_WDATA) to the second memory, receiving an input address (SYS_ADDR or GEN_ADDR) of an ECC RAM and outputting an ECC RAM control command (ECC_RAM_CTRL), an ECC RAM address command (ECC_RAM_ADDR), and ECC RAM write data (ECC_RAM_WDATA) to the second memory to initialize the data area of ​​the ECC RAM corresponding to the address (ECC_RAM_ADDR) with an initialization bit; The method is characterized by including an address generation unit that, once the initialization utilization area setting and initialization of the first memory are completed, sequentially generates an address (GEN_ADDR) according to the address depth of the ECC RAM and outputs it to the first memory and second memory control unit.

[0015] The RAM initialization module is characterized by stopping the initialization of the second memory when a write access to a specific address (SYS_ADDR) of the second memory occurs during the initialization of the second memory, writing the corresponding data to the data area of ​​the second memory address (ECC_RAM_ADDR) corresponding to the said address, updating the tag bit of the initialization utilization area of ​​the first memory corresponding to the specific address where the data was written to the update bit, and when the update of the tag bit is completed, proceeding with the initialization of the second memory again, but skipping the initialization for the specific address of the data area that was updated.

[0016] The above-mentioned write access is characterized by being generated by a control unit.

[0017] The above device is characterized by further including a reset control unit that controls a system reset in response to a software and hardware reset request and a software and hardware reboot request of the system, and outputs an address generation start (START_FLAG) signal, which is a RAM initialization event signal, to a RAM initialization module.

[0018] The ECC RAM initialization method of the present invention for achieving the above-mentioned purpose comprises: a first memory initialization utilization area setting process in which a RAM initialization module sets an initialization utilization area of ​​a size corresponding to the address depth of a second memory, which is an ECC RAM, in a first memory when a RAM initialization event is detected; a second memory initialization process in which the RAM initialization module initializes the data area of ​​the second memory with initialization data in sequential address units for the address depth; and a tag bit update process in which the RAM initialization module updates the tag bit of the initialization utilization area, which corresponds to the address of the initialized second memory and is initialized with an initial bit, with an update bit.

[0019] The above process for setting the first memory initialization utilization area is characterized by including: an initialization utilization area setting step in which the RAM initialization module sets an initialization utilization area of ​​a size corresponding to the address depth of the second memory in the first memory when the RAM initialization event is detected; and a tag bit initialization step in which the RAM initialization module initializes the tag bit of the initialization utilization area of ​​the first memory as an initialization bit.

[0020] The above process for setting the initialization utilization area is characterized by comprising: a first memory usage setting step in which, when the RAM initialization module detects the RAM initialization event, the RAM initialization module outputs a module selection signal to a MUX that is connected to the first memory via a bus, wherein the MUX receives a selection signal from the RAM initialization module and connects either the bus of the function module or the bus of the RAM initialization module to the bus connected to the first memory, thereby performing a usage setting of the first memory; an initialization utilization area setting step in which the RAM initialization module sets an initialization utilization area corresponding to the address depth of the second memory in the first memory; and a tag bit initialization step in which the RAM initialization module initializes a tag bit, which is a data bit of the initialization utilization area of ​​the first memory, as an initialization bit.

[0021] The above initialization utilization area setting step is characterized by including: an initialization utilization area information loading step in which the RAM initialization module loads initialization utilization area information including a size corresponding to the address depth of the second memory and an address depth calculated by dividing the address depth of the second memory by the data width of the first memory; and an area setting step in which the RAM initialization module sets the initialization utilization area having the size and address depth of the loaded initialization utilization area information.

[0022] The above initialization bit is 1 or 0, and when the initialization bit is 0, the tag bit corresponding to the address of the initialized data area of ​​the second memory is updated to update bit 1.

[0023] The above method is characterized by further including a first memory return process in which, when the data area for the last address according to the address depth of the second memory is initialized through the second memory initialization process of the RAM initialization module, the first memory is initialized and an IP selection signal is output to the MUX.

[0024] The second memory initialization process includes an address generation step in which a RAM initialization module sequentially generates and outputs an address (GEN_ADDR) according to the address depth through an address generation unit; and an ECC RAM initialization step in which the RAM initialization module initializes the data area of ​​the second memory address (ECC_RAM_ADDR) corresponding to the address (GEN_ADDR) input from the address generation unit through a second memory control unit, and the tag bit update process is characterized in that when an address (GEN_ADDR) is input from the address generation unit through a first memory control unit, the RAM initialization module outputs a tag bit address (RAM_ADDR), an initialization bit (RAM_WDATA), and an update command (RAM_CTRL) corresponding to the address (GEN_ADDR) to the first memory, thereby updating the tag bit of the tag bit address (RAM_ADDR) corresponding to the address (GEN_ADDR) of the initialization utilization area of ​​the first memory to an update bit.

[0025] The above memory initialization process further comprises: an external write monitoring step in which the RAM initialization module monitors whether a write access to a specific address of the second memory by an arbitrary IP occurs during the initialization of the second memory through the second memory control unit; an external data write processing step in which, if an external write access occurs in the external write monitoring step, the RAM initialization module stops the initialization of the second memory through the second memory control unit and performs data writing according to an external write request by writing the corresponding data to the data area of ​​the specific address according to the external write request; and an external data initialization processing step in which the RAM initialization module updates the tag bit of the initialization utilization area of ​​the first memory corresponding to the specific address where the data was written through the first memory control unit, wherein the RAM initialization module proceeds with the initialization of the second memory again after the external data initialization processing step, but skips the initialization for the specific address of the data area that was updated. Effects of the invention

[0026] The present invention initializes the ECC RAM by utilizing the RAM used by any IP of the system, so it is not necessary to provide a dedicated RAM for initialization, which has the effect of optimizing the configuration of the system.

[0027] In addition, the present invention has the effect of stably performing CPU write and initialization processing simultaneously without errors, as it records data corresponding to the write access in the ECC RAM and simultaneously processes the address where the data corresponding to the write access is recorded, even when a write access occurs by a control unit which is an IP during the initialization of the ECC RAM. Brief explanation of the drawing

[0029] FIG. 1 is a diagram showing the configuration of an error correction code RAM initialization device according to the present invention. FIG. 2 is a diagram showing the configuration of a RAM initialization module of an error correction code RAM initialization device according to the present invention. FIG. 3 is a flowchart illustrating an error correction code RAM initialization method according to the present invention. Specific details for implementing the invention

[0030] The configuration and operation of an error correction code RAM initialization device according to the present invention will be described in detail below with reference to the attached drawings, and a method for initializing ECC RAM in said device will be described.

[0031] FIG. 1 is a diagram showing the configuration of an error correction code RAM initialization device according to the present invention.

[0032] Referring to FIG. 1, the Error Correction Code (ECC) RAM initialization device according to the present invention includes a control unit (100), a system bus (200), a first memory (400), a second memory (500) which is an ECC RAM, a RAM initialization module (600), and a reset control unit (700), and according to an embodiment, may further include an Intellectual Property (IP) (300) and a selector (MUX) (800).

[0033] The reset control unit (700) controls the system reset according to the software and hardware reset request of the system and the software and hardware reboot request, and outputs the address generation start (START_FLAG) signal, which is a RAM initialization event signal according to the present invention, to the RAM initialization module (600).

[0034] The control unit (100) is one of the IPs such as a Central Processor Unit (CPU) or a Microcontroller Unit (MCU), and performs software and hardware resets and software and hardware reboots of the system. The command transmitted to write, delete, read, etc., data to the first memory (400) and the second memory (500) is referred to as a ram bus control command, and the ram bus control command may include a system address (SYS_ADDR), a system control (command) (SYS_CTRL), system write data (SYS_WDATA), etc.

[0035] Additionally, when a write access occurs to the second memory (500), the control unit (100) outputs a system control command (SYS_CTRL) containing a write command, a system address (SYS_ADDR) containing the address of the memory to be accessed, and system_write_data (SYS_WDATA) to be written to the address to the RAM initialization module (600) via the system bus (200), and when a read occurs to the second memory (ECC RAM) (500) or the first memory (400), it outputs a system control command (SYS_CTRL), a system address (SYS_ADDR), etc. to the RAM initialization module (600) via the system bus (200), and receives ECC RAM read data (ECC_RAM_RDATA) or RAM read data (RAM_RDATA) from the RAM initialization module (600).

[0036] The system bus (200) includes an address bus, a control bus, a data bus, etc., for transmitting and receiving control data, data, etc., between devices within the system.

[0037] The functional module (300) is an Intellectual Property (IP) which is a reusable hardware block and is a modularized design element that performs a specific function, and may be a CPU, MPU, GPU (Graphic Processor Unit), DSP (Digital Signal Processor), interface controller, memory controller, etc.

[0038] The function module (300) may have RAM for its own use or may use shared RAM.

[0039] The first memory (400) may be a general shared RAM according to the embodiment, or it may be a RAM exclusively used by the function module part (IP) (300), but it is preferable that it be a RAM exclusively used by the function module part (300).

[0040] The first memory (400) is allocated an area of ​​arbitrary size directly or via the system bus (200) by the RAM initialization module (600) to set an initialization utilization area. The initialization utilization area is set to a size corresponding to the address depth of the second memory (500) and consists of tag bits indicating whether the data area of ​​the corresponding address has been initialized or not, in address units according to the address depth of the second memory (500). Before initialization, the tag bit is set to an initialization bit ('0' or '1') indicating that it has not been initialized, and when initialized, it will be updated to an update bit ('1' or '0') indicating that it has been initialized. Therefore, the first memory (400) must be larger than the size corresponding to the address depth of the second memory (500). For example, if the size of the second memory (500) is 4096 (address depth) * 32 (data width), the size of the initialization utilization area will be 4096 bits. Therefore, the size of the first memory (400) must be 4096 bits or more (e.g., 1024*64, 64*256, 124*124, etc.).

[0041] The second memory (500) is an ECC RAM and has a data area of ​​a certain size for each address according to the address depth. For example, the second memory (500) may have 4096 (address depth) * 32 bits (data area size).

[0042] Each bit of the data area of ​​the second memory (500) will have an arbitrary value written to it before initialization.

[0043] When a RAM initialization event signal (START_FLAG) is input from the reset control unit (700), the RAM initialization module (600) sets an initialization utilization area in the first memory (400) via the system bus (200) or directly according to the embodiment, and initializes the tag bit of the initialization utilization area to an initialization bit ('0' or '1').

[0044] The size of the initialization utilization area is determined to be a size corresponding to the address depth of the second memory (500). For example, if the second memory (500) has a memory size of 4096 (address depth) * 32 bits (data width (width of the data area)), the initialization utilization area is determined to be a size of 4096 corresponding to the address depth, 4096, of the second memory (500).

[0045] When an initialization event occurs, the RAM initialization module (600) allocates and initializes an initialization utilization area of ​​the first memory (400) of a predetermined size, then sequentially generates an address (GEN_ADDR) according to the address depth of the second memory (500), and initializes the bits of the data area corresponding to the address of the second memory (500) corresponding to the generated address (GEN_ADDR) with a predetermined initialization data. For example, if the size of the data area is 8 bits, the initialization data may be '00000000' or '11111111'.

[0046] The RAM initialization module (600) initializes the data area of ​​the address (GEN_ADDR) of the second memory (500) and updates the tag bit of the initialization utilization area of ​​the first memory (400) corresponding to the address (GEN_ADDR) to an update bit (if the initialization bit is '0' (or '1'), it becomes '1' (or '0')).

[0047] The selector (MUX) (800) is connected to the function module (300) which is an IP and to the bus connection terminal to which a bus is connected to transmit and receive RAM bus control commands and corresponding data from the RAM initialization module (600), and is connected to the first memory (400) by a bus, and receives a selection signal (DONE) from the RAM initialization module (600) and connects either the bus of the IP or the bus of the RAM initialization module (600) to the bus connected to the first memory (400).

[0048] The MUX (800) is configured when the first memory (400) is used as a dedicated memory for the function module (IP) (300), and is controlled by the RAM initialization module (600) to allow the first memory (400) to be used jointly by the function module (300) and the RAM initialization module (600). The MUX (800) is basically configured so that the function module (300) can use the first memory (400).

[0049] The MUX (800) receives a selection signal (DONE) from the RAM initialization module (600), and if the selection signal is a module selection signal, it enables the RAM initialization module (600) to use the first memory (400), and if the selection signal is an IP selection signal, it enables the function module (300) to use the first memory (400).

[0050] That is, when a RAM initialization event is detected, the RAM initialization module (600) outputs a module selection signal (DONE) to the MUX (800) to set itself to use the first memory (400), and when the data area of ​​all addresses according to the address depth of the second memory (500) is initialized, it outputs an IP selection signal to the MUX (800) to return the usage setting so that the function module (300) can use it.

[0051] FIG. 2 is a diagram showing the configuration of a RAM initialization module of an error correction code RAM initialization device according to the present invention.

[0052] Referring to FIG. 2, the RAM initialization module (600) includes an address generation unit (610), a first memory control unit (620), and a second memory control unit (630).

[0053] The address generation unit (610) receives a system address (SYS_ADDR) and a system control signal (SYS_CTRL) from the control unit (100) via the system bus (200) when a RAM initialization event occurs, which is an address generation start (START_FLAG) signal from the reset control unit (700), and operates by sequentially generating an address (GEN_ADDR) according to the address depth and outputting it to the first memory control unit (620) and the second memory control unit (630).

[0054] The address generation unit (610) outputs an IP selection signal (DONE) to the MUX (800) after the output of the last address (GEN_ADDR) to return the use of the first memory (400) to the function module unit (300).

[0055] The first memory control unit (620) sets (allocates) an initialization utilization area in the first memory (400) having a size corresponding to the address depth of the second memory (500) that is pre-set when a RAM initialization event occurs, and initializes the initialization utilization area with an initialization bit. The initialization utilization area is calculated by dividing the address depth of the second memory (500) by the data width of the first memory (400). The calculation may be pre-calculated and set in the first memory control unit (620). The first memory control unit (620) may store information on the initialization utilization area including the size corresponding to the address depth of the second memory (500) and the address depth calculated by dividing the address depth of the second memory (500) by the data width of the first memory (400), or may receive and obtain this information from the outside via a system bus. The first memory control unit (620) may receive an address generation start signal in the same way as the address generation unit (610) to detect the occurrence of a RAM initialization event, or it may be configured to determine that the RAM initialization event has occurred upon the input of the first address (GEN_ADDR) generated by the address generation unit (610).

[0056] When the first memory control unit (620) receives an address (GEN_ADDR) from the address generation unit (610) after setting the initialization utilization area, it outputs the RAM address (RAM_ADDR), RAM control (RAM_CTRL), and RAM write data (RAM_WDATA) to the first memory (400) and updates the tag bit recorded as the initialization bit of the initialization utilization area corresponding to the input address (GEN_ADDR) to the update bit.

[0057] When the last tag bit of the initialization utilization area is updated, the first memory control unit (620) disables the usage setting of the initialization utilization area and initializes the entire first memory (400) or initializes the initialization utilization area.

[0058] The first memory control unit (620) checks the tag bit corresponding to the address (GEN_ADDR) when the address (GEN_ADDR) is input from the address generation unit (610) to determine whether the tag bit is an initialization bit or an update bit, and if it is an update bit, does not perform an update of the tag bit.

[0059] When a write access occurs from the control unit (100) during the initialization of the second memory (500), the first memory control unit (620) recognizes this through system control (SYS_CTRL), stops the initialization, performs the corresponding write to the address of the second memory (500) where the write occurred, and updates the tag bit of the initialization utilization area corresponding to the address. The address resulting from the write access by the control unit may be an address corresponding to an initialized address (GEN_ADDR) or an address corresponding to an address that has not yet been initialized (GEN_ADDR). In the former case, the tag bit corresponding to the address is maintained, and in the latter case, the tag bit corresponding to the address is updated from an initialization bit to an update bit.

[0060] The second memory control unit (630) initializes the second memory (500) by address unit by writing initialization data to the data area of ​​the second memory (500) corresponding to the address (GEN_ADDR) input from the address generation unit (610) when a RAM initialization event occurs.

[0061] The second memory control unit (630) checks whether the tag bit of the initialization utilization area of ​​the first memory (400) corresponding to the address is an initialization bit or an update bit when initializing by address, and if it is an update bit, does not perform initialization for the address of the second memory (500).

[0062] Additionally, when the second memory control unit (630) initializes by address, if a read access occurs at an arbitrary address of the second memory (500), it checks the tag bit of the address and, if it determines that the data area of ​​the address has not been initialized, it masks the ECC error information.

[0063] FIG. 3 is a flowchart illustrating an error correction code RAM initialization method according to the present invention.

[0064] Referring to FIG. 3, the RAM initialization module (600) monitors whether a RAM initialization event occurs due to an address generation start (START_FLAG) signal from the reset control unit (700) (S111).

[0065] When a RAM initialization event occurs, the RAM initialization module (600) sets an initialization utilization area in the first memory (400) that indicates whether to initialize per address, having a size corresponding to the address depth of the second memory (500) through the first memory control unit (620), and initializes the initialization utilization area with an initialization bit (S113).

[0066] After setting and initializing the initialization utilization area of ​​the first memory (400), the RAM initialization module (600) sequentially generates the address (ADDR) of the second memory (500) according to the address depth of the second memory (500) through the address generation unit (610) and starts outputting it to the first memory control unit (620) and the second memory control unit (630) (S115).

[0067] When the address (GEN_ADDR) of the second memory (500) is generated, the RAM initialization module (600) monitors whether access by the control unit (100) occurs (S117).

[0068] When access by the control unit (100) occurs while the address (GEN_ADDR) is being generated, the RAM initialization module (600) executes the corresponding control unit (e.g., CPU) command (S131), and maintains the tag bit or updates it to an update bit according to the execution of the control unit command (S133). If the control unit command is a read command, the tag bit is maintained as an initialization bit, and if it is a write command, the tag bit corresponding to the address where data was written according to the control unit command is updated to an update bit.

[0069] On the other hand, if there is no access by the control unit (100), the tag bit of the initialization utilization area of ​​the first memory corresponding to the second memory address (GEN_ADDR) is read (S119), and it is determined whether the read tag bit is an initialization bit, and whether the data area of ​​the address (GEN_ADDR) is initialized or data is written to the address (GEN_ADDR) by a write access by an external control unit (100), or whether it is not initialized or data is not written by a write access by the control unit (100) (S123).

[0070] If there is no write access by the control unit (100) and data has not been written to the data area of ​​the address to be initialized (GEN_ADDR) by the write access of the control unit (100) previously, the RAM initialization module (600) initializes the data area of ​​the address (GEN_ADDR) of the second memory (500) through the second memory control unit (630), updates the tag bit of the initialization utilization area corresponding to the address (GEN_ADDR) of the first memory (400) with an update bit through the first memory control unit (620) (S125), and proceeds to S127.

[0071] On the other hand, if the tag bit is an update bit, the RAM initialization module (600) skips the initialization for the above address (GEN_ADDR) without performing it (S126) and proceeds to S127.

[0072] In S127, the RAM initialization module (600) determines whether the generated address (GEN_ADDR) is the last address according to the address depth (S127), and if the generated address (GEN_ADDR) is not the last address according to the address depth, it increments the address (GEN_ADDR) (S129) and repeats the process after S117 described above, and if it is the last address, it initializes the first memory (400) through the first memory control unit (620), releases its use, and outputs an IP selection signal to the MUX (800) through the address generation unit (610) to return the use of the first memory (400) (S134).

[0073] Meanwhile, it will be readily understood by those skilled in the art that the present invention is not limited to the typical preferred embodiments described above, but can be implemented with various improvements, modifications, substitutions, or additions within the scope of the essence of the invention. If such implementation through improvements, modifications, substitutions, or additions falls within the scope of the appended claims below, the technical concept thereof should also be considered to belong to the present invention. Explanation of the symbols

[0074] 100: Control unit 200: System bus 300: Function Module (IP) 400: 1st memory 500: Second Memory 600: RAM Initialization Module 610: Address generation section 620: 1st Memory Control Unit 630: Second Memory Control Unit 700: Reset control unit 800: MUX

Claims

Claim 1 An error correction code RAM initialization device characterized by comprising: a first memory to which an initialization utilization area is allocated; an ECC RAM, which has a certain address depth and is provided with an address-specific data area for said address depth to process writing, deleting, and reading data in said data area on an address-by-address basis; and a RAM initialization module that, when a RAM initialization event is detected by inputting an address generation start (START_FLAG) signal after a system reset, sets an initialization utilization area having a size corresponding to the address depth of said second memory in said first memory and initializes a tag bit corresponding to the size of said initialization utilization area as an initialization bit, and then initializes the data area of ​​said second memory with said initialization data on a sequential address-by-address basis for said address depth, and updates the tag bit of the initialization utilization area corresponding to the initialized address as an update bit. Claim 2 An error correction code RAM initialization device according to claim 1, comprising a function module and a bus connection terminal to which a bus transmitting and receiving RAM bus control commands and corresponding data is connected from the RAM initialization module, and further comprising a MUX connected to the first memory by a bus, wherein the MUX receives a selection signal from the RAM initialization module and connects either the bus of the function module or the bus of the RAM initialization module to the bus connected to the first memory, wherein the RAM initialization module outputs a module selection signal as a selection signal to the MUX to connect the first memory to the RAM initialization module upon the occurrence of the initialization event, and when the data area of ​​the last address according to the address depth of the second memory is initialized and the last tag bit of the initialization utilization area is updated, outputs an IP selection signal as a selection signal to the MUX to connect the first memory to the function module. Claim 3 An error correction code RAM initialization device according to claim 1, wherein the RAM initialization module allocates an initialization utilization area having a size corresponding to the address depth of the second memory and an address depth obtained by dividing the address depth of the second memory by the data width of the first memory. Claim 4 In claim 1, the RAM initialization module is configured to receive system control (SYS_CTRL) and an address (SYS_ADDR) by the control unit and output a RAM control command (RAM_CTRL), a RAM address command (RAM_ADDR), and RAM write data (RAM_WDATA) to the first memory, and when the RAM initialization event occurs, allocate an initialization utilization area to the first memory and initialize the tag bit of the initialization utilization area with an initialization bit, or update the tag bit of the initialization utilization area corresponding to either the input address (SYS_ADDR) or the address (GEN_ADDR) with an update bit; a first memory control unit that receives system control (SYS_CTRL) and an address (SYS_ADDR) by the control unit and outputs an ECC RAM control command (ECC_RAM_CTRL), an ECC An error correction code RAM initialization device characterized by comprising: a second memory control unit configured to output a RAM address command (ECC_RAM_ADDR) and ECC RAM write data (ECC_RAM_WDATA), receiving an input address (SYS_ADDR or GEN_ADDR) of an ECC RAM, and outputting an ECC RAM control command (ECC_RAM_CTRL), an ECC RAM address command (ECC_RAM_ADDR), and ECC RAM write data (ECC_RAM_WDATA) to a second memory to initialize the data area of ​​the ECC RAM corresponding to the address (ECC_RAM_ADDR) with an initialization bit; and an address generation unit that, when the initialization utilization area setting and initialization of the first memory are completed, sequentially generates an address (GEN_ADDR) according to the address depth of the ECC RAM and outputs it to the first memory and the second memory control unit. Claim 5 In paragraph 2, the RAM initialization module is configured to receive system control (SYS_CTRL) and an address (SYS_ADDR) by the control unit and output a RAM control command (RAM_CTRL), a RAM address command (RAM_ADDR), and RAM write data (RAM_WDATA) to the first memory, and when the RAM initialization event occurs, allocate an initialization utilization area to the first memory and initialize the tag bit of the initialization utilization area with an initialization bit, or update the tag bit of the initialization utilization area corresponding to either the input address (SYS_ADDR) or the address (GEN_ADDR) with an update bit, and output a first memory RAM control command (RAM_CTRL), a RAM address command (RAM_ADDR), and RAM write data (RAM_WDATA) to the first memory; and receives system control (SYS_CTRL) and an address (SYS_ADDR) by the control unit and outputs an ECC RAM control command (ECC_RAM_CTRL), ECC to the second memory. An error correction code RAM initialization device characterized by comprising: a second memory control unit configured to output a RAM address command (ECC_RAM_ADDR) and ECC RAM write data (ECC_RAM_WDATA), receiving an input address (SYS_ADDR or GEN_ADDR) of an ECC RAM, and outputting an ECC RAM control command (ECC_RAM_CTRL), an ECC RAM address command (ECC_RAM_ADDR), and ECC RAM write data (ECC_RAM_WDATA) to a second memory to initialize the data area of ​​the ECC RAM corresponding to the address (ECC_RAM_ADDR) with an initialization bit; and an address generation unit that, when the initialization utilization area setting and initialization of the first memory are completed, sequentially generates an address (GEN_ADDR) according to the address depth of the ECC RAM and outputs it to the first memory and the second memory control unit. Claim 6 An error correction code RAM initialization device according to claim 4 or 5, wherein the RAM initialization module stops the initialization of the second memory when a write access to a specific address (SYS_ADDR) of the second memory occurs during the initialization of the second memory, writes the corresponding data to the data area of ​​the second memory address (ECC_RAM_ADDR) corresponding to the said address, updates the tag bit of the initialization utilization area of ​​the first memory corresponding to the specific address where the data was written to an update bit, and when the update of the tag bit is completed, resumes the initialization of the second memory, but skips the initialization for the specific address of the data area that was updated. Claim 7 An error correction code RAM initialization device according to claim 6, characterized in that the write access is generated by a control unit. Claim 8 An error correction code RAM initialization device according to claim 1, further comprising a reset control unit that controls a system reset in response to a software and hardware reset request and a software and hardware reboot request of the system, and outputs an address generation start (START_FLAG) signal, which is the RAM initialization event signal, to a RAM initialization module. Claim 9 An error correction code RAM initialization method characterized by comprising: a first memory initialization utilization area setting process in which a RAM initialization module sets an initialization utilization area of ​​a size corresponding to the address depth of a second memory, which is an ECC RAM, in a first memory when a RAM initialization event is detected; a second memory initialization process in which the RAM initialization module initializes a data area of ​​the second memory with initialization data in sequential address units for the address depth; and a tag bit update process in which the RAM initialization module updates a tag bit of an initialization utilization area corresponding to the address of the initialized second memory, which is initialized with an initial bit, with an update bit. Claim 10 In claim 9, the error correction code RAM initialization method is characterized in that the process of setting the first memory initialization utilization area includes: an initialization utilization area setting step in which the RAM initialization module sets an initialization utilization area of ​​a size corresponding to the address depth of the second memory in the first memory when the RAM initialization event is detected; and a tag bit initialization step in which the RAM initialization module initializes the tag bit of the initialization utilization area of ​​the first memory with an initialization bit. Claim 11 In claim 9, the process of setting the initialization utilization area comprises: a first memory usage setting step in which, when the RAM initialization module detects the RAM initialization event, the RAM initialization module outputs a module selection signal to a MUX that receives a selection signal from the RAM initialization module and connects either the bus of the function module or the bus of the RAM initialization module to the bus connected to the first memory, thereby performing a usage setting of the first memory; an initialization utilization area setting step in which the RAM initialization module sets an initialization utilization area corresponding to the address depth of the second memory in the first memory; and a tag bit initialization step in which the RAM initialization module initializes a tag bit, which is a data bit of the initialization utilization area of ​​the first memory, into an initialization bit. Claim 12 An error correction code RAM initialization method according to claim 10 or 11, wherein the initialization utilization area setting step comprises: an initialization utilization area information loading step in which the RAM initialization module loads initialization utilization area information including a size corresponding to the address depth of the second memory and an address depth calculated by dividing the address depth of the second memory by the data width of the first memory; and an area setting step in which the RAM initialization module sets the initialization utilization area having the size and address depth of the loaded initialization utilization area information. Claim 13 An error correction code RAM initialization method according to claim 12, wherein the initialization bit is 1 or 0, and when the initialization bit is 0, the tag bit corresponding to the address of the initialized data area of ​​the second memory is updated to update bit 1. Claim 14 An error correction code RAM initialization method according to claim 11, further comprising a first memory return process in which, when the data area for the last address according to the address depth of the second memory is initialized through the second memory initialization process, the RAM initialization module initializes the first memory and outputs an IP selection signal to a MUX. Claim 15 In claim 9, the second memory initialization process comprises: an address generation step in which a RAM initialization module sequentially generates and outputs an address (GEN_ADDR) according to the address depth through an address generation unit; and an ECC RAM initialization step in which the RAM initialization module initializes the data area of ​​the second memory address (ECC_RAM_ADDR) corresponding to the address (GEN_ADDR) input from the address generation unit through a second memory control unit; and the tag bit update process is characterized in that when an address (GEN_ADDR) is input from the address generation unit through a first memory control unit, the RAM initialization module outputs a tag bit address (RAM_ADDR), an initialization bit (RAM_WDATA), and an update command (RAM_CTRL) corresponding to the address (GEN_ADDR) to the first memory, thereby updating the tag bit of the tag bit address (RAM_ADDR) corresponding to the address (GEN_ADDR) of the initialization utilization area of ​​the first memory to an update bit. Claim 16 In claim 15, the memory initialization process further comprises: an external write monitoring step in which the RAM initialization module monitors whether a write access to a specific address of the second memory by an arbitrary IP occurs during the initialization of the second memory through the second memory control unit; an external data write processing step in which, if an external write access occurs in the external write monitoring step, the RAM initialization module stops the initialization of the second memory through the second memory control unit and performs data writing according to an external write request by writing the corresponding data to the data area of ​​the specific address according to the external write request; and an external data initialization processing step in which the RAM initialization module updates the tag bit of the initialization utilization area of ​​the first memory corresponding to the specific address where the data was written through the first memory control unit, wherein the RAM initialization module proceeds with the initialization of the second memory again after the external data initialization processing step, but skips the initialization for the specific address of the updated data area.

Images