Memory device for detecting connection fault in signal paths

Abstract

A memory device includes a base chip and a core chip stacked via a signal path, wherein the base chip and the core chip drive the signal path during a scan operation and detect a connection failure of the signal path according to the logic level at which an internal node connected to the signal path is driven, and the base chip controls the timing for latching the logic level of the internal node.

Description

Technology Field

[0001] The present invention relates to a memory device for detecting a connection failure between signal paths for stacking a plurality of chips. Background Technology

[0003] As the technology for manufacturing memory devices advances, packaging technology for multiple core chips used to implement memory devices is also becoming increasingly integrated and high-performance. Packaging technologies for implementing memory devices are moving away from a two-dimensional structure in which multiple core chips are arranged planarly on a printed circuit board (PCB), and are developing various technologies related to a three-dimensional structure in which multiple core chips are stacked vertically. Memory devices with a three-dimensional structure can be implemented by stacking multiple core chips through TSVs (Through silicon vias, hereinafter referred to as "through-vias"), such as in High Bandwidth Memory (HBM), or by stacking multiple core chips through wire bonding.

[0004] Meanwhile, as integration and performance increase, methods for detecting connection failures of through-silicon vias (TSVs) for stacking multiple core chips are required. A typical method for detecting connection failures of through-silicon vias (TSVs) can be performed through a scan operation (Through Silicon Via Open Short test) in which a PMOS transistor connected to a through-silicon via (TSV) of a core chip placed on the top layer is turned on, an NMOS transistor connected to a through-silicon via (TSV) of a base chip placed at the bottom is turned on, and then a through-silicon via (TSV) is detected to be driven to a set logic level.

[0005] This type of scan operation (Through Silicon Via Open Short test) can detect open failures where through-vias (TSVs) are disconnected, but it has the problem of being difficult to detect short failures where through-vias (TSVs) are connected. The problem to be solved

[0007] The present invention provides a memory device for detecting a connection failure between signal paths for stacking a plurality of chips. means of solving the problem

[0009] To this end, the present invention provides a memory device comprising a base chip and a core chip stacked through a signal path, wherein the base chip and the core chip drive the signal path during a scan operation and detect a connection failure of the signal path according to the logic level at which an internal node connected to the signal path is driven, and wherein the base chip controls the timing for latching the logic level of the internal node.

[0010] In addition, the present invention provides a memory device comprising a base chip and a core chip stacked through a signal path and a voltage path, wherein the base chip and the core chip drive the signal path during a scan operation and detect a connection failure of the signal path and a connection failure of the signal path and the voltage path according to the logic level at which an internal node connected to the signal path is driven, and wherein the base chip controls the timing for latching the logic level of the internal node. Effects of the invention

[0012] According to the present invention, by adjusting the timing for latching the logic level of an internal node connected to a plurality of signal paths, it is possible to detect various connection failures of a plurality of signal paths.

[0013] In addition, according to the present invention, by adjusting the timing for latching the logic level of an internal node connected to a plurality of signal paths, it is possible to detect various connection failures of a plurality of signal paths and voltage paths. Brief explanation of the drawing

[0015] FIG. 1 is a block diagram illustrating the configuration of a memory system according to an example of the present invention. FIG. 2 is a block diagram illustrating the configuration of a memory device according to an example of the present invention. FIG. 3 is a block diagram illustrating the configuration of a base chip according to an example of the present invention. FIG. 4 is a block diagram illustrating the configuration of a test control circuit according to an example of the present invention. FIG. 5 is a diagram illustrating the configuration of a periodic signal generation circuit according to an example of the present invention. FIG. 6 is a block diagram illustrating the configuration of a scan pulse generation circuit according to an example of the present invention. FIG. 7 is a timing diagram for explaining the operation of a counter according to an example of the present invention. FIG. 8 is a block diagram illustrating the configuration of a shifting circuit according to an example of the present invention. FIG. 9 is a diagram illustrating the configuration of a latch signal generation circuit according to an example of the present invention. FIG. 10 is a block diagram illustrating the configuration of a base test circuit according to an example of the present invention. FIG. 11 is a diagram illustrating the configuration of a first defective signal generation circuit according to an example of the present invention. FIG. 12 is a block diagram illustrating the configuration of a fourth core chip according to an example of the present invention. FIG. 13 is a block diagram illustrating the configuration of a core test circuit according to an example of the present invention. FIG. 14 is a circuit diagram illustrating the configuration of a first path driving circuit according to an example of the present invention. FIGS. 15 to 18 are drawings for explaining the scanning operation of a memory device according to an example of the present invention. Specific details for implementing the invention

[0016] In the description of the following embodiments, the term "pre-set" means that the numerical value of a parameter is predetermined when the parameter is used in a process or algorithm. Depending on the embodiment, the numerical value of the parameter may be set when the process or algorithm starts or during the period in which the process or algorithm is executed.

[0017] Terms such as "first" and "second," used to distinguish various components, are not limited by the components. For example, the first component may be named the second component, and conversely, the second component may be named the first component.

[0018] When it is stated that one component is "connected" or "connected" to another component, it should be understood that they are connected directly or through an intermediate component. On the other hand, the descriptions "directly connected" and "directly connected" should be understood as meaning that one component is directly connected to another component without any intermediary component.

[0019] "Logic high level" and "logic low level" are used to describe the logic levels of signals. A signal having a "logic high level" is distinguished from a signal having a "logic low level." For example, when a signal having a first voltage corresponds to a "logic high level," a signal having a second voltage may correspond to a "logic low level." According to one embodiment, the "logic high level" may be set to a voltage greater than the "logic low level." Meanwhile, the logic levels of the signals may be set to different logic levels or opposite logic levels according to an embodiment. For example, a signal having a logic high level may be set to have a logic low level according to an embodiment, and a signal having a logic low level may be set to have a logic high level according to an embodiment.

[0020] The present invention will be described in more detail below through examples. These examples are merely for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

[0021] FIG. 1 is a block diagram illustrating the configuration of a memory system (1) according to an example of the present invention. As shown in FIG. 1, the memory system (1) may include a printed circuit board (11), a substrate (13), an interposer (15), a memory device (17), and a processor (19).

[0022] A printed circuit board (11) connects various electronic components to form an electronic circuit (not shown). A copper layer, a solder mask, and a silk screen may be formed on the printed circuit board (11). A circuit path for transmitting signals or power may be formed in the copper layer. The solder mask prevents damage to the circuit and protects specific areas where components can be soldered. Additionally, the silk screen indicates the location or information of electronic components using characters or symbols printed on the surface of the printed circuit board (11).

[0023] A substrate (13) is formed on a printed circuit board (11) through bump pads (e.g., 111) to mechanically support an interposer (15), a memory device (17), and a processor (19). The substrate (13) can be used as a material that serves as the physical base of the printed circuit board (11) and is typically an insulator. Materials for the substrate (13) include FR4, an insulator made of glass fiber and epoxy resin; ceramic, which can withstand high temperatures and has excellent thermal conductivity and is mainly used in high-frequency circuits or high-temperature environments; and polyimide, which is used as a base material for flexible PCBs due to its flexible characteristics.

[0024] The interposer (15) is formed on the substrate (13) via bump pads and may include wiring connecting electronic components (e.g., memory device (17) and processor (19)) that do not match in form factor or pin arrangement. The interposer (15) can convert signals at different interfaces.

[0025] A memory device (17) may be formed on an interposer (15) via microbump pads (e.g., 113). Under the control of a processor (19), the memory device (17) may store data applied from the processor (19) or output stored data to the processor (19). The memory device (17) may include a base chip (120) and a plurality of core chips (130-1 to 130-L). The plurality of core chips (130-1 to 130-L) may be stacked on the base chip (120) via microbump pads. The base chip (120) and the plurality of core chips (130-1 to 130-L) may be connected vertically to each other via through-vias. The base chip (120) may drive a signal path during a scan operation. The base chip (120) can detect a connection failure in the signal path according to the logic level at which the internal node (ND221 in FIG. 11) connected to the signal path is driven during a scan operation. The base chip (120) can adjust the timing for latching the logic level of the internal node (ND221 in FIG. 11) connected to the signal path during a scan operation. The signal path can be set as a path where a through-via and a microbump pad are connected.

[0026] Among the multiple core chips (130-1 to 130-L), the core chip (130-L) placed on the top layer can drive a signal path during a scan operation. Each of the multiple core chips (130-1 to 130-L) can input and output data through the signal paths. Each of the multiple core chips (130-1 to 130-L) can store data and output the stored data. Each of the multiple core chips (130-1 to 130-L) may include multiple channel regions that operate independently. Each of the multiple channel regions may be assigned a channel that operates independently to receive or transmit data. The number (L) of the core chips (130-1 to 130-L) can be implemented as 4, 8, 12, 16, etc. For example, when each of the core chips (130-1 to 130-12) has 8 channels, each of the core chips (130-1 to 130-4), core chips (130-5 to 130-8), and core chips (130-9 to 130-12) can transmit and receive data with the processor (19) in rank units consisting of 32 channels, including 32 channel regions.

[0027] The processor (19) can detect a faulty signal transmission path among the signal transmission paths of the base chip (120) through wiring formed inside the interposer (15).

[0028] FIG. 2 is a block diagram illustrating the configuration of a memory device (17) according to an example of the present invention. As shown in FIG. 2, the memory device (17) may include a base chip (120), a first core chip (130-1), a second core chip (130-2), a third core chip (130-3), and a fourth core chip (130-4).

[0029] The base chip (120) can be electrically connected to the first to fourth signal paths and voltage paths. The first signal path can be implemented by electrically connecting through-vias (T11, T12, T13, T14, T15) and microbump pads (B11, B12, B13, B14). The second signal path can be implemented by electrically connecting through-vias (T21, T22, T23, T24, T25) and microbump pads (B21, B22, B23, B24). The third signal path can be implemented by electrically connecting through-vias (T31, T32, T33, T34, T35) and microbump pads (B31, B32, B33, B34). The fourth signal path can be implemented by electrically connecting through-vias (T41, T42, T43, T44, T45) and microbump pads (B41, B42, B43, B44). The first to fourth signal paths can be implemented as paths through which signals for controlling the operation of the first core chip (130-1), the second core chip (130-2), the third core chip (130-3), and the fourth core chip (130-4) are input and output. The voltage path can be implemented by electrically connecting through-vias (T51, T52, T53, T54, T55) and microbump pads (B51, B52, B53, B54). The voltage path can be set as a path to which the power supply voltage (VDD) and ground voltage (VSS) supplied to the first core chip (130-1), the second core chip (130-2), the third core chip (130-3), and the fourth core chip (130-4) are applied. Although the voltage path is shown as a single voltage path, the path to which the power supply voltage (VDD) is applied and the path to which the ground voltage (VSS) is applied can be implemented separately.

[0030] Through-vias (T11, T12, T13, T14, T15, T21, T22, T23, T24, T25, T31, T32, T33, T34, T35, T41, T42, T43, T44, T45, T51, T52, T53, T54, T55) can be implemented in the form of cylinders made of a conductive material to vertically stack through the base chip (12), the first core chip (130-1), the second core chip (30), the third core chip (40), and the fourth core chip (50). Microbump pads (B11, B12, B13, B14, B21, B22, B23, B24, B31, B32, B33, B34, B41, B42, B43, B44, B51, B52, B53, B54) can be implemented in the form of balls made of a conductive material for direct connection to a circuit board. The first to fourth signal paths and voltage paths are implemented to include five through-vias, but depending on the embodiment, they may be implemented to include an varying number of through-vias.

[0031] The base chip (120) may include through-vias (T11, T21, T31, T41, T51), a base test circuit (22), and a defect detection circuit (23).

[0032] The through-via (T11) can be electrically connected to the microbump pad (B11). The through-via (T21) can be electrically connected to the microbump pad (B21). The through-via (T31) can be electrically connected to the microbump pad (B31). The through-via (T41) can be electrically connected to the microbump pad (B41). The through-via (T51) can be electrically connected to the microbump pad (B51).

[0033] The base test circuit (22) can drive through-vias (T11, T21, T31, T41) through either a PMOS transistor or an NMOS transistor during a scan operation. The base test circuit (22) can drive through-vias (T11, T21, T31, T41) to a power supply voltage (VDD) through a PMOS transistor during an up-scan operation of the scan operation. The base test circuit (22) can drive through-vias (T11, T21, T31, T41) to a ground voltage (VSS) through an NMOS transistor during a down-scan operation of the scan operation. The base test circuit (22) can control the timing for latching the logic level of an internal node (ND221 in FIG. 11) during a scan operation. The base test circuit (22) can detect the logic level of an internal node (ND221 in FIG. 11) connected to through-vias (T11, T21, T31, T41) during a scan operation and generate a defect detection signal (FD<1:4> in FIG. 3).

[0034] The defect detection circuit (23) can detect a defect in the connection of the first to fourth signal paths based on the defect detection signal (FD<1:4> in FIG. 3) during the scan operation.

[0035] The first core chip (130-1) can be electrically connected to microbumps (B11, B21, B31, B41, B51) and stacked on top of the base chip (120).

[0036] The first core chip (130-1) may include through-vias (T12, T22, T32, T42, T52).

[0037] A through-via (T12) can be electrically connected between a microbump pad (B11) and a microbump pad (B12). A through-via (T22) can be electrically connected between a microbump pad (B21) and a microbump pad (B22). A through-via (T32) can be electrically connected between a microbump pad (B31) and a microbump pad (B32). A through-via (T42) can be electrically connected between a microbump pad (B41) and a microbump pad (B42). A through-via (T52) can be electrically connected between a microbump pad (B51) and a microbump pad (B52).

[0038] The second core chip (130-2) can be electrically connected to microbump pads (B12, B22, B32, B42, B52) and stacked on top of the first core chip (130-1).

[0039] The second core chip (130-2) may include through-vias (T13, T23, T33, T43, T53).

[0040] A through-via (T13) can be electrically connected between a microbump pad (B12) and a microbump pad (B13). A through-via (T23) can be electrically connected between a microbump pad (B22) and a microbump pad (B23). A through-via (T33) can be electrically connected between a microbump pad (B32) and a microbump pad (B33). A through-via (T43) can be electrically connected between a microbump pad (B42) and a microbump pad (B43). A through-via (T53) can be electrically connected between a microbump pad (B52) and a microbump pad (B53).

[0041] The third core chip (130-3) can be electrically connected to microbump pads (B13, B23, B33, B43, B53) and stacked on top of the second core chip (130-2).

[0042] The third core chip (130-3) may include through-vias (T14, T24, T34, T44, T54).

[0043] A through-via (T14) can be electrically connected between microbump pad (B13) and microbump pad (B14). A through-via (T24) can be electrically connected between microbump pad (B23) and microbump pad (B24). A through-via (T34) can be electrically connected between microbump pad (B33) and microbump pad (B34). A through-via (T44) can be electrically connected between microbump pad (B43) and microbump pad (B44). A through-via (T54) can be electrically connected between microbump pad (B53) and microbump pad (B54).

[0044] The fourth core chip (130-4) can be electrically connected to microbump pads (B14, B24, B34, B44, B54) and stacked on top of the third core chip (130-3).

[0045] The fourth core chip (130-4) may include through-vias (T15, T25, T35, T45, T55) and a core test circuit (51).

[0046] The core test circuit (51) can drive through-vias (T15, T25, T35, T45) through either a PMOS transistor or an NMOS transistor during a scan operation. The core test circuit (51) can drive through-vias (T15, T25, T35, T45) to a power supply voltage (VDD) through a PMOS transistor during a downscan operation of the scan operation. The core test circuit (51) can drive through-vias (T15, T25, T35, T45) to a ground voltage (VSS) through an NMOS transistor during an upscan operation of the scan operation.

[0047] In FIG. 2, the first core chip (130-1), the second core chip (130-2), the third core chip (130-3), and the fourth core chip (130-4) are vertically stacked on top of the base chip (120), but depending on the embodiment, the number of core chips can be stacked in various numbers, such as 8 or 16.

[0048] The memory device (17) illustrated in FIG. 2 is implemented such that a base chip (120), a first core chip (130-1), a second core chip (130-2), a third core chip (130-3), and a fourth core chip (130-4) are vertically stacked through through silicon vias (TSV), as in High Bandwidth Memory (HBM), but according to the embodiment, a plurality of core chips can be stacked through wire bonding. According to the embodiment, wire bonding can be set as a signal path for signals input and output from the base chip (120), the first core chip (130-1), the second core chip (130-2), the third core chip (130-3), and the fourth core chip (130-4).

[0049] FIG. 3 is a block diagram illustrating the configuration of a base chip (120) according to an example of the present invention. The base chip (120) may include a test control circuit (21), a base test circuit (22), and a defect detection circuit (13).

[0050] The test control circuit (21) can generate a downscan signal (DNS) and an upscan signal (UPS) based on a downscan enable signal (DEN) and an upscan enable signal (UEN). The downscan enable signal (DEN) can be set as a signal that is enabled during the downscan operation of the scan operation. The upscan enable signal (UEN) can be set as a signal that is enabled during the upscan operation of the scan operation.

[0051] The test control circuit (21) provides the first and second test delay signals (TD<1:2>), the fourth to fourth test selection signals (TS<1:4>), and the first test control signal (TC) when either the down-down scan enable signal (DEN) or the up-scan enable signal (UEN) is enabled. <1> Based on ), a down latch signal (DLAT) and an up latch signal (ULAT) can be generated. The first and second test delay signals (TD<1:2>) can be set as signals to adjust the pulse width of the period signal (OSC in FIG. 4). The fourth to fourth test selection signals (TS<1:4>) can be set as signals to adjust the time for which the logic level of the internal node (ND221 in FIG. 11) is latched. The first test control signal (TC <1> ) can be set as a signal for generating a down latch signal (DLAT) and an up latch signal (ULAT) from a scan pulse (SP in Fig. 4) generated during a scan operation.

[0052] The test control circuit (21) can generate a normal latch signal (NLAT), a pad latch signal (PLAT), and second and third test control signals (TC<2:3>) as a down latch signal (DLAT) and an up latch signal (ULAT). The normal latch signal (NLAT) can be set as a signal that is enabled at a set time (time X in FIGS. 15 to 18) during a scan operation to latch the logic level of an internal node (ND221 in FIG. 11). The pad latch signal (PLAT) can be set as a signal input to latch the logic level of an internal node (ND221 in FIG. 11) through a pad connected to an external device. The second test control signal (TC <2> ) can be set as a signal for generating a down latch signal (DLAT) and an up latch signal (ULAT) from a normal latch signal (NLAT). The third test control signal (TC <3> ) can be set as a signal for generating a down latch signal (DLAT) and an up latch signal (ULAT) from a pad latch signal (PLAT).

[0053] The base test circuit (22) can be electrically connected to through-vias (T11, T21, T31, T41). The base test circuit (22) can drive the through-vias (T11, T21, T31, T41) through either a PMOS transistor or an NMOS transistor during a scan operation. The base test circuit (22) can drive the through-vias (T11, T21, T31, T41) through either a PMOS transistor or an NMOS transistor based on a down-scan signal (DNS) and an up-scan signal (UPS) during a scan operation. The base test circuit (22) can control the timing at which a down-latch signal (DLAT) and an up-latch signal (ULAT) are generated to latch the logic level of an internal node (ND221 in FIG. 11) connected to the signal path during a scan operation. The base test circuit (22) can latch the logic level of an internal node (ND221 in FIG. 11) connected to through-vias (T11, T21, T31, T41) based on a down latch signal (DLAT) and an up latch signal (ULAT) during a scan operation. The base test circuit (22) can detect the logic level of the internal node (ND221 in FIG. 11) connected to the latched through-vias (T11, T21, T31, T41) during a scan operation and generate first to fourth defect detection signals (FD<1:4>).

[0054] The defect detection circuit (23) can detect a connection failure of the through-vias (T11, T21, T31, T41) based on the first to fourth defect detection signals (FD<1:4>) during a scan operation. The defect detection circuit (23) can detect a first open failure in which the through-vias (T11, T21, T31, T41) are disconnected by detecting the logic level of the first to fourth defect detection signals (FD<1:4>) during a scan operation. The defect detection circuit (23) can detect a second open failure in which the connection between the through-via included in the first to fourth signal paths and the microbump pad is defective by detecting the logic level of the first to fourth defect detection signals (FD<1:4>) during a scan operation.

[0055] The defect detection circuit (23) can detect the logic level of the first to fourth defect detection signals (FD<1:4>) during a scan operation and detect a first short circuit defect in which the ground voltage (VSS) applied to the first to fourth signal paths and voltage paths is weakly connected. The defect detection circuit (23) can detect the logic level of the first to fourth defect detection signals (FD<1:4>) during a scan operation and detect a second short circuit defect in which the ground voltage (VSS) applied to the first to fourth signal paths and voltage paths is strongly connected. The defect detection circuit (23) can detect the logic level of the first to fourth defect detection signals (FD<1:4>) during a scan operation and detect a third short circuit defect in which the power supply voltage (VDD) applied to the first to fourth signal paths and voltage paths is strongly connected.

[0056] FIG. 4 is a block diagram illustrating the configuration of a test control circuit (21) according to an example of the present invention. The test control circuit (21) may include a buffer circuit (211), a periodic signal generation circuit (212), a scan pulse generation circuit (213), and a latch signal generation circuit (214).

[0057] The buffer circuit (211) can generate a downscan signal (DNS) and an upscan signal (UPS) based on the down-enable signal (DEN) and the up-enable signal (UEN). The buffer circuit (211) can generate a downscan signal (DNS) by buffering the down-enable signal (DEN). The buffer circuit (211) can generate an upscan signal (UPS) by buffering the up-enable signal (UEN).

[0058] The periodic signal generation circuit (212) can generate a periodic signal (OSC) based on a downscan signal (DNS), an upscan signal (UPS), and first and second test delay signals (TD<1:2>). The periodic signal generation circuit (212) can generate a periodic signal (OSC) including pulses that occur periodically by detecting the timing of when the downscan signal (DNS) and the upscan signal (UPS) occur. The periodic signal generation circuit (212) can generate a periodic signal (OSC) with a pulse width that is adjusted based on the first and second test delay signals (TD<1:2>). The periodic signal generation circuit (212) can generate a periodic signal (OSC) that is disabled when the reset signal (RST) is enabled.

[0059] The scan pulse generation circuit (213) can generate a scan pulse (SP) based on a periodic signal (OSC) and first to fourth test selection signals (TS<1:4>). The scan pulse generation circuit (213) can generate a scan pulse (SP) from any one of a plurality of counting signals (CNT<1:8> in FIG. 6) generated by counting the periodic signal (OSC) based on the first to fourth test selection signals (TS<1:4>). The scan pulse generation circuit (213) can control the timing at which a scan pulse (SP) is generated to latch the logic level of an internal node (ND221 in FIG. 11) connected to the signal path during a scan operation. The scan pulse generation circuit (213) can generate a reset signal (RST) that is enabled when all bits of a plurality of counting signals (CNT<1:8> in FIG. 6) generated by counting a periodic signal (OSC) are counted.

[0060] The latch signal generation circuit (214) can generate a down latch signal (DLAT) and an up latch signal (ULAT) based on the first to third test control signals (TC<1:3>), down scan signal (DNS), up scan signal (UPS), scan pulse (SP), normal latch signal (NLAT), and pad latch signal (PLAT). The latch signal generation circuit (214) can generate the first test control signal (TC <1> When ) is enabled and the downscan signal (DNS) is enabled, a down latch signal (DLAT) can be generated based on the scan pulse (SP). The latch signal generation circuit (214) generates the first test control signal (TC <1> When ) is enabled and the upscan signal (UPS) is enabled, an up-latch signal (ULAT) can be generated based on the scan pulse (SP). The latch signal generation circuit (214) generates the second test control signal (TC <2> When ) is enabled and the downscan signal (DNS) is enabled, a down latch signal (DLAT) can be generated based on the normal latch signal (NLAT). The latch signal generation circuit (214) generates the second test control signal (TC <2> When ) is enabled and the upscan signal (UPS) is enabled, an uplatch signal (ULAT) can be generated based on the normal latch signal (NLAT). The latch signal generation circuit (214) generates the third test control signal (TC <3> When ) is enabled and the downscan signal (DNS) is enabled, a down latch signal (DLAT) can be generated based on the pad latch signal (PLAT). The latch signal generation circuit (214) generates the third test control signal (TC <3> When ) is enabled and the upscan signal (UPS) is enabled, an uplatch signal (ULAT) can be generated based on the padlatch signal (PLAT).

[0061] FIG. 5 is a diagram illustrating the configuration of a periodic signal generation circuit (212) according to an example of the present invention. The periodic signal generation circuit (212) may include a detection signal generation circuit (212-1), an enable signal generation circuit (212-2), and an oscillator (212-3).

[0062] The detection signal generation circuit (212-1) can be implemented as an OR gate (212-11). The detection signal generation circuit (212-1) can generate a detection signal (DET) that is enabled when either a downscan (DNS) or an upscan signal (UPS) occurs. The detection signal generation circuit (212-1) can generate a detection signal (DET) that is enabled at a logic high level when the downscan (DNS) occurs at a logic high level. The detection signal generation circuit (212-1) can generate a detection signal (DET) that is enabled at a logic high level when the upscan signal (UPS) occurs at a logic high level.

[0063] The enable signal generation circuit (212-2) can be implemented with inverters (212-21, 212-22) and NAND gates (212-23, 212-24). The enable signal generation circuit (212-2) can generate an enable signal (EN) based on a detection signal (DET) and a reset signal (RST). The enable signal generation circuit (212-2) can generate an enable signal (EN) that is enabled at a logic high level when the detection signal (DET) is enabled at a logic high level. The enable signal generation circuit (212-2) can generate an enable signal (EN) that is disabled at a logic low level when the reset signal (RST) is enabled at a logic high level. The enable signal generation circuit (212-2) can generate an enable signal (EN) that is enabled at a logic high level from the point in time when the detection signal (DET) is enabled at a logic high level until the point in time when the reset signal (RST) is enabled at a logic high level.

[0064] The oscillator (212-3) can generate a periodic signal (OSC) with a pulse width adjusted based on the enable signal (EN) and the first and second test delay signals (TD<1:2>). The oscillator (212-3) is enabled when the enable signal (EN) is enabled to a logic high level, and the first test delay signal (TD <1> ) can generate a periodic signal (OSC) with a short pulse width when enabled to a logic high level. The oscillator (212-3) is enabled when the enable signal (EN) is enabled to a logic high level, and the second test delay signal (TD <2> When ) is enabled to a logic high level, a periodic signal (OSC) with a long pulse width can be generated. The first and second test delay signals (TD<1:2>) are implemented to include 2 bits for controlling the pulse width of the periodic signal (OSC), but can be implemented to include various bits to control the pulse width of the periodic signal (OSC) in various ways.

[0065] FIG. 6 is a block diagram illustrating the configuration of a scan pulse generation circuit (213) according to an example of the present invention. The scan pulse generation circuit (213) may include a counter (213-1), a shifting circuit (213-2), and a reset signal generation circuit (213-3).

[0066] The counter (213-1) can generate first to eighth counting signals (CNT<1:8>) that are sequentially counted by pulses included in the periodic signal (OSC). The counter (213-1) can generate first to eighth counting signals (CNT<1:8>) that are sequentially counted whenever a pulse included in the periodic signal (OSC) occurs at a logic high level.

[0067] The shifting circuit (213-2) includes the first to fourth test selection signals (TS<1:4>) and the third counting signal (CNT <3> A scan pulse (SP) can be generated based on ). The shifting circuit (213-2) can generate a third counting signal (CNT <3> The initialization signal (INIT in FIG. 8) is shifted in synchronization with the ) and a scan pulse (SP) can be generated based on the initialization signal (INIT in FIG. 8) shifted by the first to fourth test selection signals (TS<1:4>). The shifting circuit (213-2) is a third counting signal (CNT <3> Although it is implemented to generate a scan pulse (SP) based on ), it may be implemented to generate a scan pulse (SP) based on any one of the first to eighth counting signals (CNT<1:8>) according to the embodiment. The shifting circuit (213-2) can control the timing at which the scan pulse (SP) is generated by generating a scan pulse (SP) based on any one of the first to eighth counting signals (CNT<1:8>) during a scan operation.

[0068] The reset signal generation circuit (213-3) is the 8th counting signal (CNT <8> A reset signal (RST) can be generated based on ). The reset signal generation circuit (213-3) can generate the 8th counting signal (CNT <8> A reset signal (RST) that is enabled to a logic high level can be generated when ) occurs at a logic high level.

[0069] FIG. 7 is a timing diagram for explaining the operation of a counter (213) according to an example of the present invention.

[0070] The counter (213) is a first counting signal (CNT) that toggles whenever a pulse to be included in the periodic signal (OSC) occurs at a logic high level. <1> Can generate ).

[0071] The counter (213) is the first counting signal (CNT <1> A second counting signal (CNT) that toggles whenever a pulse to be included in ) occurs at a logic high level. <2> Can generate ).

[0072] The counter (213) is a second counting signal (CNT <2> A third counting signal (CNT) that toggles whenever a pulse to be included in ) occurs at a logic high level. <3> Can generate ).

[0073] The counter (213) is the third counting signal (CNT <3> A fourth counting signal (CNT) that toggles whenever a pulse to be included in ) occurs at a logic high level. <4> Can generate ).

[0074] The counter (213) is the fourth counting signal (CNT <4> A fifth counting signal (CNT) that toggles whenever a pulse to be included in ) occurs at a logic high level. <5> Can generate ).

[0075] The counter (213) is the fifth counting signal (CNT <5> A sixth counting signal (CNT) that toggles whenever a pulse to be included in ) occurs at a logic high level. <6> Can generate ).

[0076] The counter (213) is the 6th counting signal (CNT <6> A seventh counting signal (CNT) that toggles whenever a pulse to be included in ) occurs at a logic high level. <7> Can generate ).

[0077] The counter (213) is the 7th counting signal (CNT <7> The 8th counting signal (CNT) that toggles whenever a pulse to be included in ) occurs at a logic high level. <8> Can generate ).

[0078] FIG. 8 is a block diagram illustrating the configuration of a shifting circuit (213-2) according to an example of the present invention. The shifting circuit (213-2) may include a register circuit (213-21) and a pulse selection circuit (213-22).

[0079] The register circuit (213-21) can be implemented with flip-flops (213-211, 213-212, 213-213, 213-214). The flip-flop (213-211) is a third counting signal (CNT). <3> The initialization signal (INIT) can be latched when the pulse included in ) occurs at a logic high level. The flip-flop (213-211) is the third counting signal (CNT <3> When a pulse included in ) occurs at a logic high level, a latched initialization signal (INIT) can be output as a first shifting signal (SF1). The flip-flop (213-211) can generate a first shifting signal (SF1) that is disabled at a logic low level when a reset signal (RST) occurs at a logic high level. The initialization signal (INIT) can be set as a signal that is enabled at a logic high level when the power-up operation ends. The power-up operation can be set as a time interval in which the voltage level of the internal voltage (not shown) generated when the memory device (17) starts operation rises along with the voltage level of the externally supplied power voltage (VDD) to rise to a preset voltage level.

[0080] The flip-flop (213-212) is the third counting signal (CNT <3> The first shifting signal (SF1) can be latched when the pulse included in ) occurs at a logic high level. The flip-flop (213-212) is the third counting signal (CNT <3> When a pulse included in ) occurs at a logic high level, the latched first shifting signal (SF1) can be output as a second shifting signal (SF2).

[0081] The flip-flop (213-213) is the third counting signal (CNT <3> The second shifting signal (SF2) can be latched when the pulse included in ) occurs at a logic high level. The flip-flop (213-213) is the third counting signal (CNT <3> When a pulse included in ) occurs at a logic high level, the latched second shifting signal (SF2) can be output as a third shifting signal (SF3).

[0082] The flip-flops (213-214) are the third counting signal (CNT <3> The third shifting signal (SF3) can be latched when the pulse included in ) occurs at a logic high level. The flip-flop (213-214) can latch the third counting signal (CNT <3> When a pulse included in ) occurs at a logic high level, the latched third shifting signal (SF3) can be output as a fourth shifting signal (SF4).

[0083] The register circuit (213-21) is the third counting signal (CNT <3> When a pulse included in ) occurs at a logic high level, the initialization signal (INIT) can be shifted to generate first to fourth shifting signals (SF1, SF2, SF3, SF4) that are sequentially enabled. The register circuit (213-21) can generate first to fourth shifting signals (SF1, SF2, SF3, SF4) that are disabled at a logic low level when a reset signal (RST) occurs at a logic high level.

[0084] The pulse selection circuit (213-22) can generate a scan pulse (SP) from any one of the first to fourth shifting signals (SF1, SF2, SF3, SF4) based on the first to fourth test selection signals (TS<1:4>). The pulse selection circuit (213-22) can generate a scan pulse (SP) from the first test selection signal (TS<1:4>). <1> When ) is enabled to a logic high level, the first shifting signal (SF1) can be output as a scan pulse (SP). The pulse selection circuit (213-22) outputs the second test selection signal (TS <2> When ) is enabled to a logic high level, the second shifting signal (SF2) can be output as a scan pulse (SP). The pulse selection circuit (213-22) outputs the third test selection signal (TS <3> When ) is enabled to a logic high level, the third shifting signal (SF3) can be output as a scan pulse (SP). The pulse selection circuit (213-22) outputs the fourth test selection signal (TS <4> When ) is enabled to a logic high level, the fourth shifting signal (SF4) can be output as a scan pulse (SP). The first to fourth test selection signals (TS<1:4>) are implemented to include 4 bits to generate a scan pulse (SP) from any one of the first to fourth shifting signals (SF1, SF2, SF3, SF4), but can be implemented to include various bits to generate a scan pulse (SP) from multiple shifting signals.

[0085] FIG. 9 is a block diagram illustrating the configuration of a latch signal generation circuit (214) according to an example of the present invention. The latch signal generation circuit (214) may include a latch selection pulse generation circuit (214-1) and a logic circuit (214-2).

[0086] The latch selection pulse generation circuit (214-1) can generate a latch selection pulse (LSP) based on the first to third test control signals (TC<1:3>), scan pulse (SP), normal latch signal (NLAT), and pad latch signal (PLAT). The latch selection pulse generation circuit (214-1) can generate the first test control signal (TC <1> When ) is enabled, the scan pulse (SP) can be output as a latch select pulse (LSP). The latch select pulse generation circuit (214-1) outputs the second test control signal (TC <2> When ) is enabled, the normal latch signal (NLAT) can be output as a latch select pulse (LSP). The latch select pulse generation circuit (214-1) outputs the third test control signal (TC <3> When ) is enabled, the pad latch signal (PLAT) can be output as a latch select pulse (LSP).

[0087] The logic circuit (214-2) can be implemented with AND gates (214-21, 214-22). The logic circuit (214-2) can generate a down latch signal (DLAT) and an up latch signal (ULAT) based on a down scan signal (DNS), an up scan signal (UPS), and a latch select pulse (LSP). The logic circuit (214-2) can generate a down latch signal (DLAT) that is enabled to a logic high level when the down scan signal (DNS) is enabled to a logic high level and the latch select pulse (LSP) is enabled to a logic high level. The logic circuit (214-2) can generate an up latch signal (ULAT) that is enabled to a logic high level when the up scan signal (UPS) is enabled to a logic high level and the latch select pulse (LSP) is enabled to a logic high level.

[0088] FIG. 10 is a block diagram illustrating the configuration of a base test circuit (22) according to an example of the present invention. The base test circuit (22) may include a first defect signal generation circuit (221), a second defect signal generation circuit (222), a third defect signal generation circuit (223), a fourth defect signal generation circuit (224), and a defect detection signal generation circuit (225).

[0089] The first fault signal generation circuit (221) can be electrically connected to the through-via (T11), which is the first signal path. The first fault signal generation circuit (221) generates a first fault signal (FAIL) based on the downscan signal (DNS), upscan signal (UPS), down latch signal (DLAT), and up latch signal (ULAT). <1> It can generate ). The first fault signal generation circuit (221) can drive the through-via (T11) through the NMOS transistor (221-13 in FIG. 11) when the downscan signal (DNS) is enabled. The first fault signal generation circuit (221) can latch the logic level of the internal node (ND221 in FIG. 11) connected to the through-via (T11) driven through the NMOS transistor (221-23 in FIG. 11) when the down-latch signal (DLAT) is enabled. The first fault signal generation circuit (221) can drive the through-via (T11) through the PMOS transistor (221-12 in FIG. 11) when the upscan signal (UPS) is enabled. The first failure signal generation circuit (221) can latch the logic level of an internal node (ND221 in FIG. 11) connected to a through-via (T11) driven through a PMOS transistor (221-12 in FIG. 11) when an up-latch signal (ULAT) is enabled. The first failure signal generation circuit (221) generates a first failure signal (FAIL) based on the logic level of the internal node (ND221 in FIG. 11) connected to the through-via (T11). <1> Can generate ).

[0090] The second fault signal generation circuit (222) can be electrically connected to the through-via (T21), which is the second signal path. The second fault signal generation circuit (222) generates a second fault signal (FAIL) based on the downscan signal (DNS), upscan signal (UPS), down latch signal (DLAT), and up latch signal (ULAT). <2> It can generate ). The second fault signal generation circuit (222) can drive the through-via (T21) through an NMOS transistor (not shown) when the downscan signal (DNS) is enabled. The second fault signal generation circuit (222) can latch the logic level of an internal node (not shown) connected to the through-via (T21) driven through an NMOS transistor (not shown) when the down latch signal (DLAT) is enabled. The second fault signal generation circuit (222) can drive the through-via (T21) through a PMOS transistor (not shown) when the upscan signal (UPS) is enabled. The second fault signal generation circuit (222) can latch the logic level of an internal node (not shown) connected to the through-via (T21) driven through a PMOS transistor (not shown) when the up latch signal (ULAT) is enabled. The second fault signal generation circuit (222) generates a second fault signal (FAIL) based on the logic level of an internal node (not shown) connected to the through-via (T21). <2> Can generate ).

[0091] The third fault signal generation circuit (223) can be electrically connected to the through-via (T31), which is the third signal path. The third fault signal generation circuit (223) generates a third fault signal (FAIL) based on the downscan signal (DNS), upscan signal (UPS), down latch signal (DLAT), and up latch signal (ULAT). <3> It can generate ). The third fault signal generation circuit (223) can drive the through-via (T31) through an NMOS transistor (not shown) when the downscan signal (DNS) is enabled. The third fault signal generation circuit (223) can latch the logic level of an internal node (not shown) connected to the through-via (T31) driven through an NMOS transistor (not shown) when the down latch signal (DLAT) is enabled. The third fault signal generation circuit (223) can drive the through-via (T31) through a PMOS transistor (not shown) when the upscan signal (UPS) is enabled. The third fault signal generation circuit (223) can latch the logic level of an internal node (not shown) connected to the through-via (T31) driven through a PMOS transistor (not shown) when the up latch signal (ULAT) is enabled. The third failure signal generation circuit (223) generates a third failure signal (FAIL) based on the logic level of an internal node (not shown) connected to the through-via (T31). <3> Can generate ).

[0092] The fourth fault signal generation circuit (224) can be electrically connected to the through-via (T41), which is the fourth signal path. The fourth fault signal generation circuit (224) generates a fourth fault signal (FAIL) based on the downscan signal (DNS), upscan signal (UPS), down latch signal (DLAT), and up latch signal (ULAT). <4> It can generate ). The fourth fault signal generation circuit (224) can drive the through-via (T41) through an NMOS transistor (not shown) when the downscan signal (DNS) is enabled. The fourth fault signal generation circuit (224) can latch the logic level of an internal node (not shown) connected to the through-via (T41) driven through an NMOS transistor (not shown) when the down latch signal (DLAT) is enabled. The fourth fault signal generation circuit (224) can drive the through-via (T41) through a PMOS transistor (not shown) when the upscan signal (UPS) is enabled. The fourth fault signal generation circuit (224) can latch the logic level of an internal node (not shown) connected to the through-via (T41) driven through a PMOS transistor (not shown) when the up latch signal (ULAT) is enabled. The fourth failure signal generation circuit (224) generates a fourth failure signal (FAIL) based on the logic level of an internal node (not shown) connected to the through-via (T41). <4> Can generate ).

[0093] The defect detection signal generation circuit (225) can generate first to fourth defect detection signals (FD<1:4>) based on first to fourth defect signals (FAIL<1:4>). The defect detection signal generation circuit (225) can latch the first to fourth defect signals (FAIL<1:4>). The defect detection signal generation circuit (225) can output the latched first to fourth defect signals (FAIL<1:4>) as first to fourth defect detection signals (FD<1:4>).

[0094] FIG. 11 is a diagram illustrating the configuration of a first fault signal generation circuit (221) according to an example of the present invention. The first fault signal generation circuit (221) may include a first base driving circuit (221-1) and a first storage circuit (221-2).

[0095] The first base driving circuit (221-1) may include an inverter (221-11), a PMOS transistor (221-12), and an NMOS transistor (221-13). The inverter (221-11) may invert and output an upscan signal (UPS). The PMOS transistor (221-12) is connected between the power supply voltage (VDD) and the node (ND221), and when the output signal of the inverter (221-11) is at a logic low level, it may drive the node (ND221) to the voltage level of the power supply voltage (VDD) to generate a first base data (BD1) at a logic high level. The NMOS transistor (221-13) is connected between the node (ND221) and the ground voltage (VSS), and when the downscan signal (DNS) is at a logic high level, it may drive the node (ND221) to the voltage level of the ground voltage (VSS) to generate a first base data (BD1) at a logic low level. The PMOS transistor (221-12) of the first base driving circuit (221-1) can be set to have a driving force greater than the driving force of the NMOS transistor (511-3 in FIG. 14) of the first path driving circuit (511). Accordingly, the first base driving circuit (221-1) can drive the through-vias (T11, T12, T13, T14) to the voltage level of the power supply voltage (VDD) when no defects occur in the through-vias (T11, T12, T13, T14) which are the first signal path.

[0096] The first storage circuit (221-2) may include a first latch (221-21), a second latch (221-22), and an AND gate (221-23).

[0097] The first latch (221-21) can generate a first latch data (LD1) at a logic high level when the power-up operation ends. The first latch (221-21) can latch the first base data (BD1) when the down latch signal (DLAT) is enabled at a logic high level. The first latch (221-21) can output the latched first base data (BD1) as the first latch data (LD1).

[0098] The second latch (221-22) can generate a second latch data (LD2) at a logic high level when the power-up operation ends. The second latch (221-22) can latch the first base data (BD1) when the up latch signal (ULAT) is enabled at a logic high level. The second latch (221-22) can output the latched first base data (BD1) as the second latch data (LD2).

[0099] The AND gate (221-23) transmits a first failure signal (FAIL) according to the logic levels of the first latch data (LD1) and the second latch data (LD2). <1> It can generate ). The AND gate (221-23) generates a first failure signal (FAIL) of logic high level when the first latch data (LD1) is at a logic high level and the second latch data (LD2) is at a logic high level. <1> ) can be generated. The AND gate (221-23) generates a first failure signal (FAIL) of a logic low level when at least one of the first latch data (LD1) and the second latch data (LD2) is at a logic low level. <1> Can generate ).

[0100] Meanwhile, the second to fourth fault signal generating circuits (222, 223, 224) shown in FIG. 10 are electrically connected to through-vias (T21, T31, T41) to generate second to fourth fault signals (FAIL<2:4>), and since they are implemented as the same circuit as the first fault signal generating circuit (221) shown in FIG. 11 and perform the same operation, a detailed description is omitted.

[0101] FIG. 12 is a block diagram illustrating the configuration of a fourth core chip (130-4) according to an example of the present invention. The fourth core chip (130-4) may include through-vias (T15, T25, T35, T45, T55) and a core test circuit (51).

[0102] The core test circuit (51) can receive downscan signals (DNS) and upscan signals (UPS) from the base chip (120). The downscan signals (DNS) and upscan signals (UPS) can be input from the base chip (120) to the core test circuit (51) through separate through-vias, excluding through-vias (T11, T12, T13, T14, T21, T22, T23, T24, T31, T32, T33, T34, T41, T42, T43, T44, T51, T52, T53, T54).

[0103] The core test circuit (51) can be electrically connected to the through-vias (T15, T25, T35, T45). The core test circuit (51) can drive the through-vias (T15, T25, T35, T45) through either a PMOS transistor or an NMOS transistor during a scan operation. The core test circuit (51) can drive the through-vias (T14, T24, T34, T44) through either a PMOS transistor or an NMOS transistor based on the downscan signal (DNS) and upscan signal (UPS) during a scan operation. The core test circuit (51) can drive the through-vias (T15, T25, T35, T45) to the power supply voltage (VDD in FIG. 14) through the PMOS transistor when the downscan signal (DNS) is enabled during the downscan operation of the scan operation. The core test circuit (51) can drive the through-vias (T15, T25, T35, T45) to ground voltage (VSS in FIG. 14) through an NMOS transistor when the up-scan signal (UPS) is enabled during the up-scan operation of the scan operation.

[0104] FIG. 13 is a block diagram illustrating the configuration of a core test circuit (51) according to an example of the present invention. The core test circuit (51) may include a first path driving circuit (511), a second path driving circuit (512), a third path driving circuit (513), and a fourth path driving circuit (514).

[0105] The first path driving circuit (511) can be electrically connected to the through-via (T15), which is the first signal path. The first path driving circuit (511) can drive the through-via (T15) based on the downscan signal (DNS) and the upscan signal (UPS). The first path driving circuit (511) can drive the through-via (T15) through the PMOS transistor (511-2 in FIG. 14) when the downscan signal (DNS) is enabled. The first path driving circuit (511) can drive the through-via (T15) through the NMOS transistor (511-3 in FIG. 14) when the upscan signal (UPS) is enabled.

[0106] The second path driving circuit (512) can be electrically connected to the through-via (T25), which is the second signal path. The second path driving circuit (512) can drive the through-via (T25) based on the downscan signal (DNS) and the upscan signal (UPS). The second path driving circuit (512) can drive the through-via (T25) through a PMOS transistor (not shown) when the downscan signal (DNS) is enabled. The second path driving circuit (512) can drive the through-via (T25) through an NMOS transistor (not shown) when the upscan signal (UPS) is enabled.

[0107] The third path driving circuit (513) can be electrically connected to the through-via (T35), which is the third signal path. The third path driving circuit (513) can drive the through-via (T35) based on the downscan signal (DNS) and the upscan signal (UPS). The third path driving circuit (513) can drive the through-via (T35) through a PMOS transistor (not shown) when the downscan signal (DNS) is enabled. The third path driving circuit (513) can drive the through-via (T35) through an NMOS transistor (not shown) when the upscan signal (UPS) is enabled.

[0108] The fourth path driving circuit (514) can be electrically connected to the through-via (T45), which is the fourth signal path. The fourth path driving circuit (514) can drive the through-via (T45) based on the downscan signal (DNS) and the upscan signal (UPS). The fourth path driving circuit (514) can drive the through-via (T45) through a PMOS transistor (not shown) when the downscan signal (DNS) is enabled. The fourth path driving circuit (514) can drive the through-via (T45) through an NMOS transistor (not shown) when the upscan signal (UPS) is enabled.

[0109] FIG. 14 is a circuit diagram illustrating the configuration of a first path driving circuit (511) according to an example of the present invention.

[0110] The first path driving circuit (511) may include an inverter (511-1), a PMOS transistor (511-2), and an NMOS transistor (511-3). The inverter (511-1) may invert and output a downscan signal (DNS). The PMOS transistor (511-2) is connected between the power supply voltage (VDD) and the node (ND511), and when the output signal of the inverter (511-1) is at a logic low level, it may drive the node (ND511) to the voltage level of the power supply voltage (VDD) to generate a first memory data (MD1) at a logic high level. The NMOS transistor (511-3) is connected between the node (ND511) and the ground voltage (VSS), and when the upscan signal (UPS) is at a logic high level, it may drive the node (ND511) to the voltage level of the ground voltage (VSS) to generate a first memory data (MD1) at a logic low level. The PMOS transistor (511-2) of the first path driving circuit (511) can be set to have a driving force greater than the driving force of the NMOS transistor (221-13 in FIG. 11) of the first fault signal generation circuit (221). Accordingly, the first path driving circuit (511) can drive the through-vias (T11, T12, T13, T14) to the voltage level of the power supply voltage (VDD) when no fault occurs in the through-vias (T11, T12, T13, T14) which are the first signal path.

[0111] Meanwhile, the second to fourth path driving circuits (512, 513, 514) shown in FIG. 13 are electrically connected to the through-vias (T25, T35, T45) to drive the through-vias (T25, T35, T45), and are implemented as the same circuit as the first path driving circuit (511) shown in FIG. 14 and perform the same operation, so a detailed description is omitted.

[0112] Referring to FIG. 15, the operation of detecting a connection failure of signal paths of a memory device (17) according to one embodiment of the present invention is described, and the operation of detecting a first open failure in which a first signal path is disconnected during a downscan operation of a scan operation is described as follows.

[0113] The test control circuit (21) generates a downscan signal (DNS) that is enabled at a logic high level when the downscan enable signal (DEN) is enabled.

[0114] The first path driving circuit (511) drives the through-via (T15) of the first signal path to the voltage level of the power supply voltage (VDD) through the PMOS transistor (511-2) when the downscan signal (DNS) is enabled to a logic high level.

[0115] The first base driving circuit (221-1) drives the through-via (T11) of the first signal path to the ground voltage (VSS) voltage level through the NMOS transistor (221-13) when the downscan signal (DNS) is enabled to the logic high level. At this time, when the through-via (T15) of the first signal path and the through-via (T11) of the first signal path are disconnected (OPEN), the node (ND221) connected to the through-via (T11) is driven to the ground voltage (VSS) voltage level, and the first base data (BD1) is generated at the logic low level.

[0116] Here, as shown in the graph, the case where node (ND221) is driven at the voltage level of the power supply voltage (VDD) at time X signifies the case where no failure occurs in the first signal path (NORMAL). The case where node (ND221) is driven at the voltage level of the ground voltage (VSS) at time X signifies the case where the first open failure (OPEN1) occurs.

[0117] The first storage circuit (221-2) latches the first base data (BD1) at time X when the down latch signal (DLAT) is enabled to a logic high level, thereby providing a first failure signal (FAIL) at a logic low level. <1> Generates ). X time point refers to the time set during the scan operation, and can be set as the time point when the normal latch signal (NLAT) is enabled during the scan operation in the prior art.

[0118] The base test circuit (22) has a first failure signal (FAIL) at a logic low level. <1> From ) the first fault monitoring signal (FD) of the logic low level <1> Creates ).

[0119] The defect detection circuit (23) receives the first defect monitoring signal (FD) during the scan operation. <1> When ) is generated at a logic low level, a first open failure (OPEN1) is detected in which the first signal path is disconnected.

[0120] Referring to FIG. 16, an operation for detecting a connection failure of signal paths of a memory device (17) according to one embodiment of the present invention is described, and an operation for detecting a second open failure in which the connection between a through-via and a microbump included in the first signal path is weakly connected during a down-scan operation of a scan operation is described as follows.

[0121] The test control circuit (21) generates a downscan signal (DNS) that is enabled at a logic high level when the downscan enable signal (DEN) is enabled.

[0122] The first path driving circuit (511) drives the through-via (T15) of the first signal path to the voltage level of the power supply voltage (VDD) through the PMOS transistor (511-2) when the downscan signal (DNS) is enabled to a logic high level.

[0123] The first base driving circuit (221-1) drives the through-via (T11) of the first signal path to the voltage level of the ground voltage (VSS) through the NMOS transistor (221-13) when the downscan signal (DNS) is enabled to the logic high level. At this time, when the connection between the through-via (T15) of the first signal path and the through-via and microbump included in the first signal path is weakly connected, the node (ND221) connected to the through-via (T11) is driven slowly to the voltage level of the power supply voltage (VDD), and the first base data (BD1) is generated at the logic low level.

[0124] Here, as shown in the graph, the case where the node (ND221) is driven at the voltage level of the power supply voltage (VDD) at time X signifies the case where no failure occurs in the first signal path (NORMAL). The case where the node (ND221) is driven slowly at the voltage level of the power supply voltage (VDD) at time X signifies the case where a second open failure (OPEN2) occurs.

[0125] The first storage circuit (221-2) latches the first base data (BD1) at time X when the down latch signal (DLAT) is enabled to a logic high level, thereby providing a first failure signal (FAIL) at a logic low level. <1> Generates ). X time point refers to the time set during the scan operation, and can be set as the time point when the normal latch signal (NLAT) is enabled during the scan operation in the prior art.

[0126] The base test circuit (22) has a first failure signal (FAIL) at a logic low level. <1> From ) the first fault monitoring signal (FD) of the logic low level <1> Creates ).

[0127] The defect detection circuit (23) receives the first defect monitoring signal (FD) during the scan operation. <1> When ) is generated at a logic low level, a second open failure (OPEN2) is detected in which the connection between the through-via and the microbump included in the first signal path is weakly connected.

[0128] Referring to FIG. 17, an operation for detecting a connection failure of signal paths of a memory device (17) according to one embodiment of the present invention is described, and an operation for detecting a first short circuit failure in which the ground voltage (VSS) applied to the first signal path and the voltage path is weakly connected by continuously performing a downscan operation and an upscan operation of a scan operation is described as follows.

[0129] The test control circuit (21) generates a downscan signal (DNS) that is enabled at a logic high level when the downscan enable signal (DEN) is enabled.

[0130] The first path driving circuit (511) drives the through-via (T15) of the first signal path to the voltage level of the power supply voltage (VDD) through the PMOS transistor (511-2) when the downscan signal (DNS) is enabled to a logic high level.

[0131] The first base driving circuit (221-1) drives the through-via (T11) of the first signal path to the voltage level of the ground voltage (VSS) through the NMOS transistor (221-13) when the downscan signal (DNS) is enabled to the logic high level. At this time, when the ground voltage (VSS) applied to the first signal path and the voltage path is weakly connected, the node (ND221) connected to the through-via (T11) is driven slowly to the voltage level of the power supply voltage (VDD), and the first base data (BD1) is generated at the logic low level.

[0132] The test control circuit (21) generates an upscan signal (UPS) that is enabled to a logic high level when the upscan enable signal (UEN) is enabled.

[0133] The first path driving circuit (511) drives the through-via (T15) of the first signal path to the voltage level of the ground voltage (VSS) through the NMOS transistor (511-3) when the upscan signal (UPS) is enabled to a logic high level.

[0134] The first base driving circuit (221-1) drives the through-via (T11) of the first signal path to the voltage level of the power supply voltage (VDD) through the PMOS transistor (221-12) when the upscan signal (UPS) is enabled to the logic high level. At this time, when the ground voltage (VSS) applied to the first signal path and the voltage path is weakly connected, the node (ND221) connected to the through-via (T11) is driven slowly to the voltage level of the power supply voltage (VDD), and the first base data (BD1) is generated at the logic low level.

[0135] Here, as shown in the graph, the case where the node (ND221) is driven at the voltage level of the power supply voltage (VDD) at time X signifies the case where no defect occurs in the first signal path (NORMAL). The case where the node (ND221) is driven slowly at the voltage level of the power supply voltage (VDD) at time X signifies the case where the first short circuit defect (SHORT1) occurs.

[0136] The first storage circuit (221-2) latches the first base data (BD1) at time X, when the down latch signal (DLAT) is enabled to a logic high level during a downscan operation, and the first latch signal (LD) at a logic low level <1> Generates ), and at time X when the up-latch signal (ULAT) is enabled to a logic high level during an up-scan operation, latches the first base data (BD1) to generate a second latch signal (LD) at a logic low level. <2> ) generates. The first storage circuit (221-2) generates a first latch signal (LD) at a logic low level. <1> ) and the second latch signal of the logic low level (LD <2> According to ), the first failure signal (FAIL) of the logic low level <1> Generates ). X time point refers to the time set during the scan operation, and can be set as the time point when the normal latch signal (NLAT) is enabled during the scan operation in the prior art.

[0137] The base test circuit (22) has a first failure signal (FAIL) at a logic low level. <1> From ) the first fault monitoring signal (FD) of the logic low level <1> Creates ).

[0138] The defect detection circuit (23) detects the first defect monitoring signal (FD) when the downscan and upscan operations of the scan operation are performed continuously. <1> When ) is generated at a logic low level, a first short circuit fault (SHORT1) is detected in which the ground voltage (VSS) applied to the first signal path and the voltage path is weakly connected.

[0139] Referring to FIG. 17, an operation for detecting a connection failure of signal paths of a memory device (17) according to one embodiment of the present invention is described, and an operation for detecting a second short circuit failure in which the ground voltage (VSS) applied to the first signal path and the voltage path is strongly connected by continuously performing a downscan operation and an upscan operation of a scan operation is described as follows.

[0140] The test control circuit (21) generates a downscan signal (DNS) that is enabled at a logic high level when the downscan enable signal (DEN) is enabled.

[0141] The first path driving circuit (511) drives the through-via (T15) of the first signal path to the voltage level of the power supply voltage (VDD) through the PMOS transistor (511-2) when the downscan signal (DNS) is enabled to a logic high level.

[0142] The first base driving circuit (221-1) drives the through-via (T11) of the first signal path to the voltage level of the ground voltage (VSS) through the NMOS transistor (221-13) when the downscan signal (DNS) is enabled to the logic high level. At this time, when the ground voltage (VSS) applied to the first signal path and the voltage path is strongly connected, the node (ND221) connected to the through-via (T11) is driven to the voltage level of the ground voltage (VSS), and the first base data (BD1) is generated at the logic low level.

[0143] The test control circuit (21) generates an upscan signal (UPS) that is enabled to a logic high level when the upscan enable signal (UEN) is enabled.

[0144] The first path driving circuit (511) drives the through-via (T15) of the first signal path to the voltage level of the ground voltage (VSS) through the NMOS transistor (511-3) when the upscan signal (UPS) is enabled to a logic high level.

[0145] The first base driving circuit (221-1) drives the through-via (T11) of the first signal path to the voltage level of the power supply voltage (VDD) through the PMOS transistor (221-12) when the upscan signal (UPS) is enabled to the logic high level. At this time, when the ground voltage (VSS) applied to the first signal path and the voltage path is strongly connected, the node (ND221) connected to the through-via (T11) is driven to the voltage level of the ground voltage (VSS), and the first base data (BD1) is generated at the logic low level.

[0146] Here, as shown in the graph, the case where node (ND221) is driven at the voltage level of the power supply voltage (VDD) at time X signifies the case where no failure occurs in the first signal path (NORMAL). The case where node (ND221) is driven at the voltage level of the ground voltage (VSS) at time X signifies the case where a second short-circuit failure (SHORT2) occurs.

[0147] The first storage circuit (221-2) latches the first base data (BD1) at time X, when the down latch signal (DLAT) is enabled to a logic high level during a downscan operation, and the first latch signal (LD) at a logic low level <1> Generates ), and at time X when the up-latch signal (ULAT) is enabled to a logic high level during an up-scan operation, latches the first base data (BD1) to generate a second latch signal (LD) at a logic low level. <2> ) generates. The first storage circuit (221-2) generates a first latch signal (LD) at a logic low level. <1> ) and the second latch signal of the logic low level (LD <2> According to ), the first failure signal (FAIL) of the logic low level <1> Generates ). X time point refers to the time set during the scan operation, and can be set as the time point when the normal latch signal (NLAT) is enabled during the scan operation in the prior art.

[0148] The base test circuit (22) has a first failure signal (FAIL) at a logic low level. <1> From ) the first fault monitoring signal (FD) of the logic low level <1> Creates ).

[0149] The defect detection circuit (23) detects the first defect monitoring signal (FD) when the downscan and upscan operations of the scan operation are performed continuously. <1> When ) is generated at a logic low level, a second short circuit fault (SHORT2) is detected in which the ground voltage (VSS) applied to the first signal path and the voltage path is strongly connected.

[0150] Referring to FIG. 18, an operation for detecting a connection failure of signal paths of a memory device (17) according to one embodiment of the present invention is described, and an operation for detecting a third short circuit failure in which the power supply voltage (VDD) applied to the first signal path and the voltage path is strongly connected is described as follows.

[0151] The test control circuit (21) generates a downscan signal (DNS) that is enabled at a logic high level when the downscan enable signal (DEN) is enabled.

[0152] The first path driving circuit (511) drives the through-via (T15) of the first signal path to the voltage level of the power supply voltage (VDD) through the PMOS transistor (511-2) when the downscan signal (DNS) is enabled to a logic high level.

[0153] The first base driving circuit (221-1) drives the through-via (T11) of the first signal path to the voltage level of the ground voltage (VSS) through the NMOS transistor (221-13) when the downscan signal (DNS) is enabled to the logic high level. At this time, when the power supply voltage (VDD) applied to the first signal path and the voltage path is strongly connected, the node (ND221) connected to the through-via (T11) is driven to the voltage level of the power supply voltage (VDD), and the first base data (BD1) is generated at the logic high level.

[0154] The test control circuit (21) generates an upscan signal (UPS) that is enabled to a logic high level when the upscan enable signal (UEN) is enabled.

[0155] The first path driving circuit (511) drives the through-via (T15) of the first signal path to the voltage level of the ground voltage (VSS) through the NMOS transistor (511-3) when the upscan signal (UPS) is enabled to a logic high level.

[0156] The first base driving circuit (221-1) drives the through-via (T11) of the first signal path to the voltage level of the power supply voltage (VDD) through the PMOS transistor (221-12) when the upscan signal (UPS) is enabled to the logic high level. At this time, when the power supply voltage (VDD) applied to the first signal path and the voltage path is strongly connected, the node (ND221) connected to the through-via (T11) is driven to the voltage level of the power supply voltage (VDD), and the first base data (BD1) is generated to the logic high level.

[0157] Here, as shown in the graph, the case where node (ND221) is driven at the voltage level of the power supply voltage (VDD) at time X signifies the case where no defect occurs in the first signal path (NORMAL). The case where node (ND221) is driven at the voltage level of the power supply voltage (VDD) at time X signifies the case where a third short-circuit defect (SHORT3) occurs.

[0158] The first storage circuit (221-2) latches the first base data (BD1) at time X, when the down latch signal (DLAT) is enabled to a logic high level during a downscan operation, and the first latch signal (LD) at a logic high level <1> Generates ), and at time X when the up-latch signal (ULAT) is enabled to a logic high level during an up-scan operation, latches the first base data (BD1) to generate a logic high level second latch signal (LD <2> ) generates. The first storage circuit (221-2) generates a first latch signal (LD) at a logic high level. <1> ) and the second latch signal of the logic high level (LD <2> According to ), the first failure signal (FAIL) of the logic high level <1> Generates ). X time point refers to the time set during the scan operation, and can be set to a time point earlier than the time point when the normal latch signal (NLAT) is enabled during the scan operation in the prior art.

[0159] The base test circuit (22) has a first failure signal (FAIL) at a logic high level. <1> From ) the first fault monitoring signal (FD) of logic high level <1> Creates ).

[0160] The defect detection circuit (23) detects the first defect monitoring signal (FD) when the downscan and upscan operations of the scan operation are performed continuously. <1> When ) is generated at a logic high level, a third short circuit fault (SHORT3) is detected in which the power supply voltage (VDD) applied to the first signal path and the voltage path is strongly connected.

[0161] A memory device (17) according to one example of the present invention can detect various connection failures of a plurality of signal paths by adjusting the timing for latching the logic level of an internal node connected to a plurality of signal paths. The memory device (17) can detect various connection failures of a plurality of signal paths and voltage paths by adjusting the timing for latching the logic level of an internal node connected to a plurality of signal paths.

[0162] The present invention has been described above with reference to embodiments. Those skilled in the art will understand that the present invention may be embodied in modified forms without departing from the essential characteristics of the invention. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the invention is defined by the claims, not by the foregoing description, and all variations within the scope of equivalents should be interpreted as being included in the invention. Explanation of the symbols

[0164] 1. Memory System 11. Printed circuit board 13. Substrate 15. Interposer 17. Memory Device 19. Processor 120. Base chip 130-1. First Core Chip 130-2. Second Core Chip 130-3. The Third Core Chip 130-4. The 4th Core Chip 21. Test control circuit 22. Base test circuit 23. Defect detection circuit 51. Core test circuit 211. Buffer Circuit 211-1. Detect signal generation circuit 212-2. Enable Signal Generation Circuit 212-3. Oscillator 212. Periodic Signal Generation Circuit 213. Scan pulse generation circuit 213-1. Counter 213-2. Shifting Circuit 213-21. Register Circuits 213-22. Pulse Selector Circuit 213-3. Reset Signal Generation Circuit 214. Latch signal generation circuit 214-1. Latch Selection Pulse Generation Circuit 214-2. Logic Circuits 221. First fault signal generation circuit 222. Second fault signal generation circuit 223. Third fault signal generation circuit 224. 4th fault signal generation circuit 225. Defect detection signal generation circuit 221-1. Base Driving Circuit 221-2. Storage Circuit 511. First path driving circuit 512. Second path driving circuit 513. Third path driving circuit 514. Fourth path driving circuit

Claims

Claim 1 A memory device comprising a base chip and a core chip stacked through a signal path, wherein the base chip and the core chip drive the signal path during a scan operation and detect a connection failure of the signal path according to the logic level at which an internal node connected to the signal path is driven, and wherein the base chip controls the timing for latching the logic level of the internal node. Claim 2 A memory device according to claim 1, wherein the signal path includes a first through-via included in the core chip, a microbump pad, and a second through-via included in the base chip, wherein the first through-via and the second through-via are electrically connected through the microbump pad, and the first through-via is driven by a power supply voltage through a PMOS transistor during the scan operation, and the second through-via is driven by a ground voltage through an NMOS transistor during the scan operation. Claim 3 In claim 1, the base chip is a memory device that detects a first open failure in which the signal path is disconnected when the logic level of the internal node is at the level of the ground voltage during a downscan operation in the scan operation. Claim 4 In claim 1, the base chip is a memory device that detects a second open defect in which the connection between a through-via and a microbump pad included in the signal path is poor when the logic level of the internal node does not reach the level of the power supply voltage during a down-scan operation in the scan operation. Claim 5 In claim 1, the base chip comprises: a test control circuit that generates a down-scan signal and an up-scan signal from a down-enable signal and an up-enable signal for performing the scan operation, and generates a down-latch signal and an up-latch signal for latching the logic level of the internal node based on a test delay signal and a test selection signal; a base test circuit that drives the signal path based on the down-scan signal and the up-scan signal, and generates a defect detection signal according to the voltage level of the internal node when the down-latch signal and the up-latch signal occur; and a defect detection circuit that detects a connection failure of the signal path based on the defect detection signal. Claim 6 In claim 5, the test control circuit comprises: a buffer circuit that buffers the down-enable signal and the up-enable signal to generate the down-scan signal and the up-scan signal; a periodic signal generation circuit that detects the timing of the down-scan operation and the up-scan signal occurrence to generate a periodic signal including a pulse that occurs periodically, and adjusts the pulse width of the periodic signal based on the test delay signal; a scan pulse generation circuit that generates a scan pulse from one of a plurality of counting signals generated by counting the periodic signal based on the test selection signal; and a latch signal generation circuit that generates the down-latch signal based on the scan pulse when the down-scan signal is enabled, and generates the up-latch signal based on the scan pulse when the up-scan signal is enabled. Claim 7 In claim 6, the periodic signal generating circuit comprises: a detection signal generating circuit that generates a detection signal that is enabled when either the downscan operation or the upscan signal occurs; an enable signal generating circuit that generates an enable signal that is enabled from the point in time when the detection signal is enabled until the point in time when the reset signal is enabled; and an oscillator that generates the periodic signal in which the pulse width is adjusted based on the test delay signal when the enable signal is enabled. Claim 8 In claim 6, the memory device comprises: a counter that generates a plurality of counting signals that are counted by pulses included in the periodic signal; a shifting circuit that generates the scan pulse from any one of the plurality of counting signals based on the test selection signal; and a reset signal generating circuit that generates a reset signal that is enabled when all of the plurality of counting signals are counted. Claim 9 In claim 6, the latch signal generation circuit comprises: a latch selection pulse generation circuit that outputs the scan pulse as a latch selection pulse based on a test control signal; and a logic circuit that generates the down latch signal based on the latch selection pulse when the down scan signal is enabled, and generates the up latch signal based on the latch selection pulse when the up scan signal is enabled. Claim 10 A memory device comprising a base chip and a core chip stacked through a signal path and a voltage path, wherein the base chip and the core chip drive the signal path during a scan operation, and detect a connection failure of the signal path and a connection failure of the signal path and the voltage path according to the logic level at which an internal node connected to the signal path is driven, wherein the base chip controls the timing for latching the logic level of the internal node. Claim 11 In claim 10, the memory device wherein the signal path is a path through which a signal for controlling the operation of the core chip is input and output, and the voltage path is a path through which a power supply voltage and a ground voltage supplied to the core chip are applied. Claim 12 In claim 10, the signal path comprises a first through-via included in the core chip, a microbump pad, and a second through-via included in the base chip, and the first through-via and the second through-via are electrically connected through the microbump pad. Claim 13 A memory device according to claim 12, wherein the first through-via is driven to a power supply voltage through a first PMOS transistor during a downscan operation of the scan operation, the second through-via is driven to a ground voltage through a first NMOS transistor during a downscan operation of the scan operation, the first through-via is driven to the ground voltage through a second NMOS transistor during an upscan operation of the scan operation, and the second through-via is driven to a power supply voltage through a second PMOS transistor during an upscan operation of the scan operation. Claim 14 In claim 10, the base chip is a memory device that detects a first open failure in which the signal path is disconnected when the logic level of the internal node is at the level of the ground voltage during a downscan operation in the scan operation. Claim 15 In claim 10, the base chip is a memory device that detects a second open failure in which the connection between a through-via and a microbump included in the signal path is weakly connected when the logic level of the internal node does not reach the level of the power supply voltage during a down-scan operation in the scan operation. Claim 16 In claim 10, the base chip is a memory device that detects a first short circuit defect in which the ground voltage applied to the signal path and the voltage path is weakly connected when the logic level of the internal node does not reach the level of the power supply voltage during the down-scan and up-scan operations in the scan operation. Claim 17 In claim 10, the base chip is a memory device that detects a second short circuit defect in which the ground voltage applied to the signal path and the voltage path is strongly connected when the logic level of the internal node is at the level of the ground voltage during the down-scan and up-scan operations in the scan operation. Claim 18 In claim 10, the base chip is a memory device that detects a third short circuit defect in which the signal path and the power supply voltage are connected when the logic level of the internal node is at the level of the power supply voltage during the down-scan and up-scan operations in the scan operation. Claim 19 In claim 10, the base chip comprises: a test control circuit that generates a down-scan signal and an up-scan signal from a down-enable signal and an up-enable signal for performing the scan operation, and generates a down-latch signal and an up-latch signal for latching the logic level of the internal node based on a test delay signal and a test selection signal; a base test circuit that drives the signal path based on the down-scan signal and the up-scan signal, and generates a defect detection signal according to the voltage level of the internal node when the down-latch signal and the up-latch signal occur; and a defect detection circuit that detects a connection failure of the signal path based on the defect detection signal. Claim 20 In claim 19, the test control circuit comprises: a buffer circuit that buffers the down-enable signal and the up-enable signal to generate the down-scan signal and the up-scan signal; a periodic signal generation circuit that detects the time at which the down-scan operation and the up-scan signal occur to generate a periodic signal that occurs periodically, and adjusts the pulse width of the periodic signal based on the test delay signal; a scan pulse generation circuit that generates a scan pulse from one of a plurality of counting signals generated by counting the periodic signal based on the test selection signal; and a latch signal generation circuit that generates the down-latch signal based on the scan pulse when the down-scan signal is enabled, and generates the up-latch signal based on the scan pulse when the up-scan signal is enabled. Claim 21 In claim 20, the periodic signal generating circuit comprises: a detection signal generating circuit that generates a detection signal that is enabled when either the downscan operation or the upscan signal occurs; an enable signal generating circuit that generates an enable signal that is enabled from the point in time when the detection signal is enabled until the point in time when the reset signal is enabled; and an oscillator that generates the periodic signal in which the pulse width is adjusted based on the test delay signal when the enable signal is enabled. Claim 22 In claim 20, the memory device comprises: a counter that generates a plurality of counting signals that are counted by pulses included in the periodic signal; a shifting circuit that generates the scan pulse from any one of the plurality of counting signals based on the test selection signal; and a reset signal generating circuit that generates a reset signal that is enabled when all of the plurality of counting signals are counted. Claim 23 In claim 20, the latch signal generating circuit comprises: a latch selection pulse generating circuit that outputs the scan pulse as a latch selection pulse based on a test control signal; and a logic circuit that generates the down latch signal based on the latch selection pulse when the down scan signal is enabled, and generates the up latch signal based on the latch selection pulse when the up scan signal is enabled.

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