Gate dielectrics of nanostructure transistors and the methods of forming the same
Patent Information
- Application Number
- KR1020260026287
- Authority / Receiving Office
- KR · KR
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-06-17
- Filing Date
- 2026-02-10
- Publication Date
- 2026-09-02
Smart Images
Figure PAT00001_ABST
Abstract
Description
Technology Field
[0001] This application claims the benefit of the following provisional U.S. patent application: Application No. 63 / 763,694, filed February 26, 2025, titled “Gate Oxide Thickness Modulation,” which is incorporated herein by reference. Background Technology
[0002] Technological advancements in Integrated Circuit (IC) materials and design have created generations of ICs, each featuring smaller and more complex circuits than the previous generation. Throughout the evolution of ICs, functional density (e.g., the number of interconnected devices per chip area) has generally increased, while geometric size has decreased. This scaling down process generally offers advantages by increasing production efficiency and lowering associated costs.
[0003] Such scaling down has also increased the complexity of IC processing and manufacturing, and similar developments in IC processing and manufacturing are required to realize these advancements. For example, Gate-All-Around (GAA) transistors have been introduced to replace planar transistors. Structures of GAA transistors and methods for manufacturing them are being developed. Brief explanation of the drawing
[0004] The aspects of this disclosure are best understood from the following detailed description when read together with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be increased or decreased at will for the sake of clarity of discussion. FIGS. 1 to 4, FIGS. 5a, FIGS. 5b, FIGS. 6a, FIGS. 6b, FIGS. 7a, FIGS. 7b, FIGS. 8a, FIGS. 8b, FIGS. 9a, FIGS. 9b, FIGS. 10a, FIGS. 10b, FIGS. 11a, FIGS. 11b, FIGS. 12 to 28, FIGS. 29a, FIGS. 29b, FIGS. 29c, FIGS. 30a and FIGS. 30b illustrate drawings of intermediate stages in the formation of a nanostructured transistor according to some embodiments. FIGS. 31 to 33 illustrate the effect of modulated gate oxide thickness on the performance of a nanostructured transistor according to some embodiments. FIG. 34 illustrates a process flow for forming a nanostructured transistor according to some embodiments. Specific details for implementing the invention
[0005] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.
[0006] Additionally, spatially relative terms such as “below,” “below,” “lower,” “above,” and “upper” may be used herein for convenience of description to explain the relationship of one element or feature to other element(s) or feature(s) as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations illustrated in the drawings. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may likewise be interpreted accordingly.
[0007] A nanostructured transistor (also referred to as a nanosheet transistor or a GAA (Gate All-Around) transistor) and a method for forming the same are provided. According to some embodiments, a gate dielectric is formed on a semiconductor nanostructure, and the semiconductor nanostructure acts as a channel region of the transistor. The gate dielectric comprises an interface layer and a high-k dielectric layer above the interface layer. The thickness of the high-k dielectric layer, which is above, below, at the corners of, and on the sidewalls of the nanosheet, is modulated by adopting different process conditions. By modulating the thickness of the gate oxide, the reliability and performance of the nanostructured transistor can be tuned and balanced based on requirements.
[0008] The embodiments discussed herein are intended to provide examples that enable the subject matter of this disclosure to be made or used, and those skilled in the art will understand that modifications may be made while remaining within the scope of the different embodiments considered. Across various aspects and exemplary embodiments, similar reference numbers are used to designate similar elements. Method embodiments may be discussed as being performed in a specific order, but other method embodiments may be performed in any logical order.
[0009] FIGS. 1 to 4, FIGS. 5a, FIGS. 5b, FIGS. 6a, FIGS. 6b, FIGS. 7a, FIGS. 7b, FIGS. 8a, FIGS. 8b, FIGS. 9a, FIGS. 9b, FIGS. 10a, FIGS. 10b, FIGS. 11a, FIGS. 11b, FIGS. 12 to 28, FIGS. 29a, FIGS. 29b, FIGS. 29c, FIGS. 30a and FIGS. 30b illustrate cross-sectional views of intermediate stages in the formation of a nanostructured transistor according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in the process flow as illustrated in FIG. 34.
[0010] Referring to FIG. 1, a perspective view of a wafer (10) is shown. The wafer (10) comprises a multilayer structure including a multilayer stack (22) on a substrate (20). According to some embodiments, the substrate (20) is a semiconductor substrate that may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., whereas other substrates and / or structures such as a semiconductor-on-insulator (SOI), modified SOI, silicon germanium on an insulator, etc. may be used. The substrate (20) may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor substrate.
[0011] According to some embodiments, a multilayer stack (22) is formed through a series of deposition processes for depositing alternating materials. Each process is exemplified by a process (202) of a process flow (200) as illustrated in FIG. 34. According to some embodiments, the multilayer stack (22) comprises a first layer (22A) formed of a first semiconductor material and a second layer (22B) formed of a second semiconductor material different from the first semiconductor material.
[0012] According to some embodiments, the first semiconductor material of the first layer (22A) is formed of or includes SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer (22A) (e.g., SiGe) is carried out through epitaxial growth, and the corresponding deposition method may include vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), or reduced pressure CVD (RPCVD). According to some embodiments, the first layer (22A) is formed with a first thickness within the range of about 30 Å and about 300 Å. However, any suitable thickness may be used while remaining within the range of the embodiments.
[0013] When the first layer (22A) is deposited on the substrate (20), the second layer (22B) is deposited on the first layer (22A). According to some embodiments, the second layer (22B) is formed or comprises a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or a combination thereof, and the second semiconductor material is different from the first semiconductor material of the first layer (22A). For example, according to some embodiments where the first layer (22A) is silicon germanium, the second layer (22B) may be formed of silicon, and vice versa. It should be understood that any suitable combination of materials may be used for the first layer (22A) and the second layer (22B).
[0014] According to some embodiments, the second layer (22B) is epitaxially grown on the first layer (22A) using a deposition technique similar to that used to form the first layer (22A). According to some embodiments, the second layer (22B) is formed with a thickness similar to that of the first layer (22A). The second layer (22B) may also be formed with a thickness different from that of the first layer (22A). According to some embodiments, the second layer (22A) has a thickness in the range of about 4 nm to 7 nm, while the second layer (22B) has a thickness in the range of, for example, about 8 nm to 12 nm.
[0015] When the second layer (22B) is formed on the first layer (22A), the deposition process is repeated to form the remaining layers in the multilayer stack (22) until the desired top layer of the multilayer stack (22) is formed. According to some embodiments, the first layer (22A) has the same or similar thickness, and the second layer (22B) has the same or similar thickness. The first layer (22A) may also have the same thickness as or a different thickness from the second layer (22B). According to some embodiments, the first layer (22A) is removed in a subsequent process and is alternatively referred to as the sacrificial layer (22A) throughout the description. According to an alternative embodiment, the second layer (22B) is sacrificial and is removed in a subsequent process.
[0016] According to some embodiments, there are some pad oxide layer(s) and hard mask layer(s) (not shown) formed on the multilayer stack (22). These layers are patterned and used for subsequent patterning of the multilayer stack (22).
[0017] Referring to FIG. 2, a portion of the multilayer stack (22) and the substrate (20) underneath is patterned in an etching process(s) to form a trench (23). Each process is exemplified by a process (204) of the process flow (200) as illustrated in FIG. 34. The trench (23) extends into the substrate (20). The remaining portion of the multilayer stack is hereinafter referred to as the multilayer stack (22'). Below the multilayer stack (22'), a portion of the substrate (20) is left and is hereinafter referred to as the substrate strip (20'). The multilayer stack (22') includes semiconductor layers (22A and 22B). Subsequently, the semiconductor layer (22A) is alternatively referred to as a sacrificial layer, and the semiconductor layer (22B) is alternatively referred to as a nanostructure. The portion of the multilayer stack (22') and the substrate strip (20') underneath is collectively referred to as the semiconductor strip (24).
[0018] In the embodiments described above, the GAA transistor structure can be patterned by any suitable method. For example, the structure may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes to produce a pattern having a smaller pitch than that can be obtained, for example, using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.
[0019] FIG. 3 illustrates the formation of an isolation region (26), also referred to as a shallow trench isolation (STI) region throughout this description. Each process is illustrated as a process (206) of a process flow (200) as illustrated in FIG. 34. The STI region (26) may include a liner oxide (not shown), which may be a thermal oxide formed through the thermal oxidation of a surface layer of the substrate (20). The liner oxide may also be a deposited silicon oxide layer formed, for example, using ALD, High-Density Plasma Chemical Vapor Deposition (HDPCVD), CVD, etc. The STI region (26) may also include a dielectric material over the liner oxide, which may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on coating, HDPCVD, etc. After that, a flattening process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process may be performed to flatten the top surface of the dielectric material, and the remaining part of the dielectric material is an STI region (26).
[0020] Subsequently, the STI region (26) is recessed, so that the uppermost portion of the semiconductor strip (24) protrudes higher than the uppermost surface (26T) of the remaining portion of the STI region (26) to form a protruding pin (28). The protruding pin (28) includes the uppermost portion of the substrate strip (20') and the multilayer stack (22'). Recessing of the STI region (26) can be performed via a dry etching process, for example, NF3 and NH3 are used as etching gases. During the etching process, plasma may be generated. Argon may also be included. According to an alternative embodiment of the present disclosure, recessing of the STI region (26) is performed via a wet etching process. The etching chemical may include, for example, HF.
[0021] Referring to FIG. 4, a dummy gate stack (30) and a gate spacer (38) are formed on the top surface and sidewall of the (protruding) pin (28). Each process is exemplified by process (208) of the process flow (200) as illustrated in FIG. 34. The dummy gate stack (30) may include a dummy gate dielectric (32) and a dummy gate electrode (34) on the dummy gate dielectric (32). The dummy gate dielectric (32) may be formed by oxidizing a surface portion of the protruding pin (28) to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. The dummy gate electrode (34) may be formed using, for example, polysilicon or amorphous silicon, and other materials such as amorphous carbon may also be used.
[0022] Each dummy gate stack (30) may also include one (or multiple) hard mask layers (36) on the dummy gate electrode (34). The hard mask layers (36) may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or a multilayer thereof. The dummy gate stack (30) may cross over a single protruding pin (28) or multiple protruding pins (28) and an STI region (26) between the protruding pins (28). The dummy gate stack (30) also has a longitudinal direction perpendicular to the longitudinal direction of the protruding pin (28). Formation of the dummy gate stack (30) includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer on the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layer through patterning process(s).
[0023] Next, a gate spacer (38) is formed on the sidewall of the dummy gate stack (30). According to some embodiments of the present disclosure, the gate spacer (38) is formed from a dielectric material such as silicon nitride (SiN), silicon carbide (SiC), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), or silicon oxycarbonitride (SiOCN), and may have a multilayer structure or a single layer structure comprising a plurality of dielectric layers. The process of forming the gate spacer (38) may include depositing one dielectric layer or a plurality of dielectric layers, and then performing anisotropic etching process(s) on the dielectric layer(s). The remaining portion of the dielectric layer(s) is the gate spacer (38).
[0024] FIGS. 5A and 5B illustrate cross-sectional views of the structure illustrated in FIGS. 4. FIGS. 5A illustrates reference cross-section A1-A1 in FIGS. 4, which cuts through the portion of the protruding pin (28) that is not covered by the dummy gate stack (30) and the gate spacer (38), and is perpendicular to the gate length direction. FIGS. 5B illustrates reference cross-section BB in FIGS. 4, which is parallel to the length direction of the protruding pin (28).
[0025] Referring to FIGS. 6a and 6b, a portion of the protruding pin (28) (Fig. 4) that is not located directly beneath the dummy gate stack (30) and the gate spacer (38) is recessed through an etching process to form a recess (42). Each process is exemplified by a process (210) of the process flow (200) as illustrated in FIG. 34. For example, the dry etching process may be performed using a mixture of HBr, Cl2 and O2, a mixture of HBr, Cl2, O2 and CH2F2, C2F6, CF4, SO2, etc. to etch the multilayer semiconductor stack (22') and the substrate strip (20') underneath. The bottom of the recess (42) may be at least flat with the bottom of the multilayer semiconductor stack (22'), or lower than the bottom of the multilayer semiconductor stack (22') (as illustrated in FIG. 6b). As shown in FIG. 6b, the etching can be anisotropic so that the sidewall of the multilayer semiconductor stack (22') facing the recess (42) is vertical and straight.
[0026] Referring to FIGS. 7a and 7b, the sacrificial semiconductor layer (22A) is laterally recessed to form a laterally recess (41) that is recessed from the edges of the nanostructures (22B) above and below, respectively. Each process is exemplified by process (212) of the process flow (200) as illustrated in FIG. 34.
[0027] Lateral retaking of the sacrificial semiconductor layer (22A) can be achieved through a wet etching process using an etchant that is more selective for the material of the sacrificial semiconductor layer (22A) (e.g., silicon germanium (SiGe)) than for the material of the nanostructure (22B) and the substrate (20) (e.g., silicon (Si)). For example, in an embodiment where the sacrificial semiconductor layer (22A) is formed of silicon germanium and the nanostructure (22B) is formed of silicon, the wet etching process can be performed using an etchant such as hydrochloric acid (HCl). The wet etching process can be performed using a dip process, a spray process, a spin-on process, etc.
[0028] According to an alternative embodiment, transverse resetting of the sacrificial semiconductor layer (22A) is performed through an isotropic dry etching process or a combination of a dry etching process and a wet etching process.
[0029] Referring to FIGS. 8a and 8b, an internal spacer (44) is formed. Each process is exemplified by process (214) of the process flow (200) as illustrated in FIG. 34. According to some embodiments, the formation of the internal spacer (44) involves depositing a conformal dielectric layer extending into a transverse recess (41) (Fig. 7b). Next, an etching process (also referred to as a spacer trimming process) is performed to trim a portion of the spacer layer outside the transverse recess (41) and leave a portion of the spacer layer within the transverse recess (41). The remaining portion of the spacer layer is referred to as the internal spacer (44). The internal spacer (44) may be a single-layer spacer or may comprise a plurality of sublayers (e.g., two to three sublayers).
[0030] Referring to FIGS. 9a and 9b, an epitaxial source / drain region (48) is formed in the recess (42). Each process is exemplified by process (216) of the process flow (200) as illustrated in FIG. 34. According to some embodiments, the source / drain region (48) may apply stress to a nanostructure (22B) used as a channel for the corresponding GAA transistor, thereby improving performance. Depending on whether the resulting transistor is a p-type transistor or an n-type transistor, p-type or n-type impurities may be in-situ doped as the epitaxial process progresses. For example, when the resulting transistor is a p-type transistor, silicon germanium boron (SiGeB), silicon boron (SiB), etc. may be grown. Conversely, when the resulting transistor is an n-type transistor, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. may be grown. After the recess (42) is filled with the epitaxy region (48), further epitaxial growth of the epitaxy region (48) may cause the epitaxy region (48) to expand horizontally and form facets. Further growth of the epitaxy region (48) may also cause adjacent epitaxy regions (48) to merge with each other. Alternatively, when the formation of the epitaxy region (48) is complete, the epitaxy regions (48) grown from different parts of the substrate strip (20') are separated from each other.
[0031] Referring to FIGS. 10a and 10b, a Contact Etch Stop Layer (CESL) (50) and an Inter-Layer Dielectric (ILD) (52) are formed. Each process is exemplified by a process (218) of the process flow (200) as illustrated in FIG. 34. The CESL (50) may be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and may be formed using CVD, ALD, etc. The ILD (52) may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or any other suitable deposition method. The ILD (52) may be formed from an oxygen-containing dielectric material, such as silicon oxide, PSG (Phospho-Silicate Glass), BSG (Boro-Silicate Glass), BPSG (Boron-Doped Phospho-Silicate Glass), USG (Undoped Silicate Glass), etc.
[0032] CESL (50) and ILD (52) are flattened through a flattening process such as a CMP process or a mechanical grinding process. According to some embodiments, the flattening process may remove the hard mask (36) to expose the dummy gate electrode (34), as shown in FIG. 10a. According to an alternative embodiment, the flattening process may expose the hard mask (36) and stop on the hard mask (36). According to some embodiments, after the flattening process, the top surface of the dummy gate electrode (34) (or hard mask (36)), the gate spacer (38), and the ILD (52) is flat within process variation.
[0033] Next, as illustrated in FIGS. 11a and 11b, the dummy gate electrode (34) and dummy gate dielectric (32) (and hard mask (36) if remaining) are removed in one or more etching processes so that a recess (58) is formed. Each process is exemplified by the process (220) of the process flow (200) as illustrated in FIG. 34.
[0034] Afterward, the sacrificial layer (22A) is removed, and the recess (58) between the nanostructures (22B) is extended. Each process is also illustrated as process (220) of the process flow (200) as illustrated in FIG. 34. The sacrificial layer (22A) can be removed by performing an isotropic etching process, such as a wet etching process using a selective etchant for the material of the sacrificial layer (22A), while the nanostructure (22B), substrate (20), and STI region (26) remain unetched compared to the sacrificial layer (22A).
[0035] FIGS. 12 through 26 illustrate a diagram in the formation of a gate dielectric (68) comprising an interface layer (64) surrounding a nanostructure (22B) and a high-k dielectric layer (66) on the interface layer (64), according to some embodiments. FIG. 12 illustrates a portion of a wafer (10) in a different device region. The illustrated structure in the different device region is essentially the same as that obtained from the region (59) in FIG. 11a.
[0036] The preceding process can be used to form a number of nanostructured transistors capable of meeting different reliability and different performance requirements. In subsequent discussion, four device regions for forming transistors therein are illustrated. For example, FIG. 12 illustrates device regions (60A, 60B, 60C, and 60D), and the structures illustrated herein are formed using the process as discussed in the preceding drawings. Each of the device regions (60A, 60B, 60C, and 60D) may be a p-type transistor region (where a p-type transistor is formed) or an n-type transistor region (where an n-type transistor is formed) in any combination.
[0037] Throughout the description, the portion of the gate dielectric (and the corresponding high-k dielectric layer) that is on the nanostructure and on the top surface of the nanostructure is referred to as the top (or upper) portion of the gate dielectric (and the high-k dielectric layer). The portion of the gate dielectric (and the corresponding high-k dielectric layer) that is below the nanostructure and in contact with the bottom surface of the nanostructure is referred to as the bottom (or lower) portion of the gate dielectric (and the high-k dielectric layer). The top (or upper) portion of the gate dielectric on the top nanostructure (22B) is referred to as the top portion of the gate dielectric. Similarly, corner portions and sidewall portions of the gate dielectric and the high-k dielectric layer can be realized.
[0038] The device region (60A) is a device region where the high-k dielectric portion on the top nanostructure (22B) is formed to be thicker than other portions. The device region (60B) is a device region where the high-k dielectric portion on the top nanostructure (22B) is formed to be thinner than other portions. The device region (60C) is a device region where the thickness of the corner portions and sidewall portions is increased, and the sidewall portions will be formed to be thicker than their respective top and bottom portions. The device region (60D) is a device region where the inner portion (top and bottom portions facing the nanostructure (22B) above or below) is formed to be thinner than the top portion and may also be thinner than the sidewall portions.
[0039] As illustrated in FIG. 12, an interface layer (IL) (64) is formed, and the interface layer (IL) (64) may comprise silicon oxide. Each process is exemplified by a process (222) of the process flow (200) as illustrated in FIG. 34. The formation process may include an oxidation process. The oxidation process may be performed using oxygen, for example, by generating a plasma from an oxygen-containing gas. The oxidation process may also include a chemical oxidation process. According to some embodiments, the top portion, bottom portion, and sidewall portion of the IL (64) may have the same or similar thicknesses, for example, with a difference of about 20% or less than 10%.
[0040] FIGS. 13 through 26 illustrate the formation of high-k dielectric layers (66A, 66B, 66C, and 66D) in device regions (60A, 60B, 60C, and 60D), respectively. The high-k dielectric layers (66A, 66B, 66C, and 66D) are individually and collectively referred to as the high-k dielectric layer (66). According to some embodiments, the high-k dielectric layer (66) may comprise hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, combinations thereof and / or multilayers thereof metal oxides or silicates.
[0041] The high-k dielectric layer (66) is deposited through a deposition process such as ALD or CVD. This deposition process is generally considered a conformal deposition process. However, according to some embodiments of the present disclosure, the process condition is tuned to change the thickness of some parts (top part (top / upper horizontal part), bottom part (bottom / lower horizontal part), sidewall part (vertical part), and corner part to be greater or smaller than the thickness of other parts.
[0042] Although the high-k dielectric layers (66A, 66B, 66C, and 66D) may be formed by different processes, the materials of the high-k dielectric layers (66A, 66B, 66C, and 66D) may be the same or different from one another in any combination. In the following discussion, the formation of HfO2 is discussed as an example of the material of the high-k dielectric layer (66), while the high-k dielectric layer (66) may also be formed of or include other types of high-k dielectric materials. Corresponding available precursors may also be realized.
[0043] FIGS. 13 through 16, FIGS. 17 through 19, FIGS. 20 through 22, and FIGS. 23 through 26 illustrate the formation of a high-k dielectric layer (66) having different thickness profiles according to various embodiments. The illustrated process flow illustrates that four different thickness profiles are formed on the same wafer and the same device die, but the nanostructured transistor formed on one wafer and device die may select a single thickness profile, two thickness profiles, three thickness profiles (instead of all the thickness profiles illustrated), or four thickness profiles in any combination. Additionally, when more than one thickness profile is adopted, the sequence forming the different profiles may be any available sequence different from the illustrated sequence.
[0044] FIGS. 13 to 16 illustrate a process for forming a high-k dielectric layer (66A) in a device region (60A) according to some embodiments, wherein the uppermost portion of the high-k dielectric layer (66A) above the uppermost nanostructure (22B) has a thickness greater than the remaining portion, including the lower portion below the high-k dielectric layer (66A), the uppermost portion (below the uppermost nanostructure (22B)), and the sidewall portion.
[0045] According to some embodiments, the formation of a high-k dielectric layer (66A) containing HfO2 adopts tetrakis(ethylmethylamino)hafnium (TEMAH) as a hafnium precursor. H2O, O2, and / or O3 may be used as oxidizing agents.
[0046] Referring to FIG. 13, a hard mask (70A) is formed. Each process is exemplified by a process (224) of the process flow (200) as illustrated in FIG. 34. The hard mask (70A) may include metal oxides, metal nitrides, metal oxynitrides, metal nitrides, metal oxynitrides, etc. The metal in the hard mask (70A) may include Al, Zr, Ti, La, etc., or a combination thereof, but other metals may also be used. A non-metal-containing material may also be used to form the hard mask (70A).
[0047] According to some embodiments, the hard mask (70A) may be deposited via a conformal deposition process such as ALD, CVD, etc., so as to fill the gaps between the nanostructures (22B). The hard mask (70A) is deposited in the device regions (60A, 60B, 60C, and 60D).
[0048] Subsequently, an etching mask (74A) is formed over the hard mask (70A) in the device regions (60A, 60B, 60C, and 60D). Each process is exemplified by process (226) of the process flow (200) as illustrated in FIG. 34. The etching mask (74A) may include photoresist. The etching mask (74A) is patterned and removed from the device region (60A), including the portion remaining in the device regions (60B, 60C, and 60D).
[0049] Afterward, an etching process (72A) is performed to remove a portion of the hard mask (70A) in the device area (60A) so that the corresponding portion of the IL (64) is exposed. Each process is exemplified by process (228) of the process flow (200) as illustrated in FIG. 34. After the etching process (72A), the etching mask (74A) is removed. The resulting structure is illustrated in FIG. 14.
[0050] Referring to FIG. 15, a high-k dielectric layer (66A) is deposited. Each process is exemplified by process (230) of process flow (200) as illustrated in FIG. 34. According to some embodiments, process conditions are adjusted so that the thickness (T1A) of the top portion of the high-k dielectric layer (66A) above the top nanostructure (22B) is greater than the thickness (T1'A and T2'A) of the bottom portion of the high-k dielectric layer (66A) and the thickness (T3A) of the sidewall portion. The thickness (T1A) is also greater than the thickness (T2A) of the top portion of the high-k dielectric layer (66A) below the top nanostructure (22B). For example, the thickness difference (T1A - T1'A) may be in the range between about 0.5 Å and about 2 Å. The ratio (T1A / T1A') is greater than 1.0 and may be in the range between approximately 1.1 and approximately 2.0. In other words, the thickness (T1A) is greater than the thicknesses (T1'A, T2A, T2'A, and T3A). The thicknesses (T1'A, T2A, T2'A, and T3A) may be the same or different from each other.
[0051] According to some embodiments, the high-k dielectric layer (66A) is deposited via an ALD process. To increase the thickness (T1A) of the top portion of the high-k dielectric layer (66A), the wafer temperature in the deposition process may be relatively high, for example, in the range between about 300°C and about 400°C. The chamber pressure of the deposition chamber where the ALD process is performed may also be relatively high, for example, in the range between about 3 Torr and about 4 Torr. The pulsing time for the hafnium precursor (assuming the high-k dielectric layer (66A) contains hafnium oxide) (and possibly an oxidizing agent) may be relatively long, for example, in the range between about 1 second and about 10 seconds. The purging time for the hafnium precursor (and possibly an oxidizing agent) may also be relatively long, for example, in the range between about 1 second and about 5 seconds. Longer pulse times can result in a larger thickness of the high-k dielectric layer, and longer fuzzy times can result in a smaller thickness of the high-k dielectric layer, and vice versa.
[0052] Throughout the description, when a first process condition is described as relatively high / long and a second process condition is described as relatively low / short, this may also mean that the first process condition is higher (or longer) than the second process condition. For example, when the first wafer temperature for forming the high-k dielectric layer (66A) is relatively high and the second wafer temperature for forming the high-k dielectric layer (66B) (Fig. 18) is relatively low, this may also mean that the first wafer temperature is higher than the second wafer temperature. Similarly, when the first pulse time (or fuzzy time) for forming the high-k dielectric layer (66A) is relatively long and the second pulse time (or fuzzy time) for forming the high-k dielectric layer (66B) (Fig. 18) is relatively short, this may also mean that the first pulse time (or fuzzy time) is longer than the second pulse time (or fuzzy time).
[0053] Afterward, the hard mask (70A) is removed through an etching process, and the resulting structure is illustrated in FIG. 16. Each process is exemplified by process (232) of the process flow (200) as illustrated in FIG. 34. Removal of the hard mask (70A) may include forming a patterned etching mask (not shown) to cover the device area (60A) while leaving the device areas (60B, 60C and 60D) open, etching a portion of the high-k dielectric layer (66A) over the portion of the hard mask (70A), etching the hard mask (70A), and removing the patterned etching mask.
[0054] In some situations, it is advantageous to make the upper portion of the high-k dielectric layer (66A) thicker. For example, increasing the upper portion of the high-k dielectric layer (66A) can improve yield and reliability. Such an embodiment may be adopted when a subsequent dipole integration process that may include an etching / cleaning process that may cause yield and reliability issues is adopted.
[0055] FIGS. 17 through 19 illustrate the formation of a high-k dielectric layer (66B) in a device region (60B). Each process is illustrated as process (234) of the process flow (200) as illustrated in FIG. 34. Additionally, FIGS. 20 through 22 illustrate the formation of a high-k dielectric layer (66C) in a device region (60C), and FIGS. 23 through 26 illustrate the formation of a high-k dielectric layer (66D) in a device region (60D). Unless otherwise specified, the material, structure, and formation process of the component in these processes are essentially the same as the similar component indicated by similar reference numerals in the processes discussed with reference to FIGS. 12 through 16. Throughout the description, details regarding the material, structure, and formation process provided for one device region may be applied to other device regions whenever applicable.
[0056] Referring to FIG. 17, a hard mask (70B) is deposited and patterned, and an etching mask (74B) is formed. A portion of the etching mask (74B) in the device area (60B) is removed, and a portion in the device areas (60A, 60C, and 60D) remains. Next, an etching process (72B) is performed to remove the hard mask (70B) from the device area (60B). Afterward, the etching mask (74B) is removed, and the resulting structure is shown in FIG. 18.
[0057] FIG. 18 also illustrates the deposition of a high-k dielectric layer (66B) according to some embodiments. Process conditions are adjusted so that the thickness (T1B) of the top portion of the high-k dielectric layer (66B) above the top nanostructure (22B) is smaller than the thickness (T1'B and T2'B) of the bottom portion of the high-k dielectric layer (66B) and the thickness (T3B) of the sidewall portion. The thickness (T1B) is also smaller than the thickness (T2B) of the top portion of the high-k dielectric layer (66B) below the top nanostructure (22B). For example, the thickness difference (T1'B - T1B) may be in the range between about 0 Å and about 0.5 Å. The ratio (T1'B / T1B) may be in the range between about 1.1 and about 2. In other words, the thickness (T1B) is reduced to be smaller than the thicknesses (T1', T1'B, T2B, T2'B, and T3B). The thicknesses (T1'B, T2B, T2'B, and T3B) may be the same or different from each other.
[0058] According to some embodiments, relationships (T1B < T1A (Fig. 15) and T1'B => T1'A) may also exist.
[0059] According to some embodiments, to reduce the thickness (T1B), the wafer temperature may be relatively low, for example, in the range between about 200°C and about 300°C. The chamber pressure of the deposition chamber where the ALD process is performed may also be relatively low, for example, in the range between about 1 Torr and about 3 Torr. The pulse time for the hafnium precursor (assuming the high-k dielectric layer (66B) contains hafnium oxide) and possibly the oxidizer may be relatively short, for example, in the range between about 0.1 seconds and about 3 seconds. The purge time for the precursor and possibly the oxidizer may be relatively short, for example, in the range between about 0.1 seconds and about 2 seconds.
[0060] Afterward, the hard mask (70B) is removed through an etching process, and the resulting structure is shown in FIG. 19. The removal of the hard mask (70B) may include forming a patterned etching mask (not shown) to cover the device area (60B) while leaving the device area (60A, 60C and 60D) open, etching a portion of the high-k dielectric layer (66B) over the portion of the hard mask (70B), etching the hard mask (70B), and removing the etching mask.
[0061] In some situations, it is advantageous to make the uppermost portion of the high-k dielectric layer (66B) thinner. This embodiment can be adopted when the dipole integration process is not adopted, and there is no concern regarding yield and reliability issues.
[0062] FIGS. 20 through 22 illustrate the formation of a high-k dielectric layer (66C) according to some embodiments. Each process is illustrated by process (236) of the process flow (200) as shown in FIG. 34. Referring to FIG. 20, a hard mask (70C) is deposited and patterned, and an etching mask (74C) is formed. A portion of the etching mask (74C) in the device area (60C) is removed, and a portion in the device areas (60A, 60B, and 60D) remains. Next, an etching process (72C) is performed to remove the hard mask (70C) from the device area (60C). Afterward, the etching mask (74C) is removed, and the resulting structure is shown in FIG. 21.
[0063] FIG. 21 also illustrates the deposition of a high-k dielectric layer (66C) according to some embodiments. Process conditions are adjusted so that the thickness (T3C) of the sidewall portion of the high-k dielectric layer (66C) is greater than the thickness (T1C, T1'C, T2C, and T2'C). For example, the thickness difference (T3C - T1C), (T3C - T1'C), (T3C - T2C), and (T3C - T2C) may be greater than about 0.5 Å and may be in the range between about 0.5 Å and about 2 Å. The thickness ratio (T3C / T1C, T3C / T1'C, T3C / T2C, and T3C / T2'C) may be greater than about 1.1 and may be in the range between about 1.1 and about 2.0.
[0064] According to some embodiments, relationships (T3C > T3A (Fig. 15), T3C > T3B (Fig. 18), T1C < T1A (Fig. 15), and T1C > T1B (Fig. 18)) may also exist.
[0065] According to some embodiments, to reduce the sidewall thickness (T3C) and corner thickness (T4C), the wafer temperature may be relatively high, for example, in the range between about 300°C and about 400°C. The chamber pressure of the deposition chamber where the ALD process is performed may also be relatively high, for example, in the range between about 3 Torr and about 4 Torr. The pulse time for the hafnium precursor (assuming the high-k dielectric layer (66C) contains hafnium oxide) and possibly the oxidizer may be relatively long, for example, in the range between about 1 second and about 10 seconds. The purge time for the hafnium precursor and possibly the oxidizer may be relatively long, for example, in the range between about 1 second and about 5 seconds.
[0066] After that, the hard mask (70C) is removed through an etching process, and the resulting structure is shown in FIG. 22.
[0067] In some situations, it is advantageous to make the sidewall and corner portions of the high-k dielectric layer (66C) thicker. For example, increasing the sidewall and corner portions of the high-k dielectric layer can improve yield and reliability. This embodiment may be adopted when a dipole integration process is performed, and the corresponding etching / cleaning process may cause yield and reliability issues.
[0068] FIGS. 23 through 26 illustrate the formation of a high-k dielectric layer (66D) according to some embodiments. Each process is illustrated by a process (238) of the process flow (200) as shown in FIG. 34. Referring to FIG. 23, a hard mask (70D) is deposited and patterned, and an etching mask (74D) is formed. A portion of the etching mask (74D) in the device area (60D) is removed, and a portion in the device areas (60A, 60B, and 60C) remains. Next, an etching process (72D) is performed to remove the hard mask (70D) from the device area (60D). Afterward, the etching mask (74D) is removed, and the resulting structure is shown in FIG. 24.
[0069] FIG. 25 illustrates the deposition of a high-k dielectric layer (66D) according to some embodiments. Process conditions are adjusted so that the internal thickness (T1'D, T2D, and T2'D) of the internal portion of the high-k dielectric layer (66C) is reduced to be smaller than the thickness (T1D and T3D). Throughout the description, the portion of the high-k dielectric layer facing the nanostructure (22B) above or below is referred to as the internal portion, and their thickness (T1'D, T2D, and T2'D) is referred to as the internal thickness. The thickness (T1D and T3D) may be greater than the internal thickness (T1'D, T2D, and T2'D) by a thickness difference greater than about 0.5 Å and may be in the range between about 0.5 Å and about 1 Å. The thickness ratio (T1D or T3D) / (T1'D or T2D or T2'D) can be greater than approximately 1.1 and may be in the range between approximately 1.1 and approximately 2.0. The internal thicknesses (T1'D, T2D, and T2'D) are It can be smaller than about 1.5 Å.
[0070] According to some embodiments, relationships (T1'D < T1'A (Fig. 15), T1D < T1A (Fig. 15) and T3D = T3A (Fig. 15), T1'D < T1'B (Fig. 18), T1D > T1B (Fig. 18), T3D = T3A (Fig. 18), and T1'D < T1'C (Fig. 21), and T1D = T1C (Fig. 21)) may also exist.
[0071] According to some embodiments, to reduce the internal thickness (T1'D, T2D, and T2'D), the wafer temperature may be relatively high, for example, in the range between about 300 °C and about 400 °C. The chamber pressure of the deposition chamber where the ALD process is performed may also be relatively high, for example, in the range between about 3 Torr and about 4 Torr. The pulse time for the precursor (assuming the high-k dielectric layer (66B) contains hafnium oxide) and possibly the oxidizer may be relatively short, for example, in the range between about 0.1 seconds and about 3 seconds. The purge time for the precursor may be relatively short, for example, in the range between about 0.1 seconds and about 0.2 seconds.
[0072] In some situations, it is advantageous to make the inner portion of the high-k dielectric layer (66D) thinner. For example, reducing the inner thickness of the high-k dielectric layer can improve device performance (e.g., current). Additionally, reducing the inner thickness of the high-k dielectric layer makes it easier to fill the dipole film (not shown) in a subsequent process, so that the dipole film can fill all the spaces between the nanostructures (22B).
[0073] After that, the hard mask (70D) is removed through an etching process, and the resulting structure is shown in FIG. 26. In FIG. 26, the IL (64) and the high-k dielectric layers (66A, 66B, 66C, 66D) above each collectively form the gate dielectric (68A, 68B, 68C, and 68D), respectively.
[0074] FIG. 27 illustrates an embodiment in which a dipole film (75) is formed to dope a dipole dopant into the high-k dielectric layers (66A and 66C), thereby tuning the threshold voltage of each nanostructure transistor within the device regions (66A and 66C). In another embodiment, the dipole doping process is skipped. The dipole film (75) may contain an n-type dipole dopant, which can lower the threshold voltage of the n-type nanostructure transistor and increase the threshold voltage of the p-type nanostructure transistor. Alternatively, the dipole film (75) may contain a p-type dipole dopant, which can increase the threshold voltage of the n-type nanostructure transistor and decrease the threshold voltage of the p-type nanostructure transistor.
[0075] FIG. 27 further illustrates an annealing process (73) for driving / integrating dipole dopants within the dipole film (75) into the high-k dielectric layers (66A and 66C). Each process is illustrated as process (240) of the process flow (200) as illustrated in FIG. 34. According to an alternative embodiment, the dipole doping process is skipped. After the annealing process, the dipole film (75) is removed. FIG. 28 illustrates the resulting structure. If the top portion or the sidewall / corner portion is thicker, the high-k dielectric layers (66A and 66C) are less likely to be damaged during the etching of the dipole film (75).
[0076] FIGS. 29a and 29b illustrate a cross-section of a wafer (10) after the formation of an IL (64) and a high-k dielectric layer (66) as discussed in the preceding embodiment. The illustrated gate dielectric (68) represents a gate dielectric (68A, 68B, 68C, and 68D) as illustrated in FIG. 28.
[0077] FIG. 29c illustrates a perspective view of a portion of the nanostructure (22B) and the corresponding high-k dielectric (66). It is understood that some features are not illustrated. From FIG. 29c, it can be seen that a thicker gate dielectric (68) (due to the thicker high-k dielectric layer (66)) is desirable for improving yield and reliability but undesirable for improving device performance. Conversely, a thinner gate dielectric (68) is desirable for improving device performance but undesirable for improving yield and reliability. Thus, embodiments of the present disclosure may be used to suit different requirements.
[0078] Subsequently, as illustrated in FIGS. 30a and FIGS. 30b, a gate electrode (70) is formed. Each process is exemplified by process (242) of process flow (200) as illustrated in FIG. 34. The gate dielectric (68) and the gate electrode (70) collectively form an alternate gate stack (72). In the process of forming the gate electrode (70), first, a conductive layer is formed on the high-k dielectric layer (66) so that the remaining portion of the recess (58) is filled, and a planarization process, such as a CMP process or a mechanical grinding process, follows to remove excess material. The gate electrode (70) may comprise a metal-containing material such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, a combination thereof, or a multilayer thereof. Accordingly, a nanostructure transistor (74) is formed, and a nanostructure transistor (74A, 74B, 74C, and 74D) having a gate dielectric (68A, 68B, 68C, and 68D) as shown in FIG. 28 can be represented.
[0079] FIGS. 31 through 33 schematically illustrate the effect of adjusting the thickness of different parts of a high-k dielectric layer to adjust device performance, yield, and reliability (referred to as yield / reliability). The X-axis represents thickness, and the Y-axis represents device performance or yield / reliability. Line (82) represents device performance and illustrates that device performance decreases as the thickness of the high-k dielectric layer increases. Line (84) represents yield / reliability and illustrates that yield / reliability improves as the thickness of the high-k dielectric layer increases.
[0080] The X-axis in FIG. 31 illustrates the thickness of the top portion of the high-k dielectric layer (66A) (Fig. 15). The yield / reliability and device performance of the nanostructured transistor having a conformal high-k dielectric layer will be at a position with the same thickness as TCon, and the yield / reliability and device performance of the nanostructured transistor (74A) (Fig. 30a and Fig. 30b), in which the top portion of the high-k dielectric layer (66A) is thicker, will be at a position with the same thickness as T1A (Fig. 15). It is understood that the nanostructured transistor (74A) has reduced device performance and improved yield / reliability.
[0081] The X-axis in FIG. 32 illustrates the thickness of the corner / sidewall portion of the high-k dielectric layer (66C) (Fig. 21). The yield / reliability and device performance of a nanostructured transistor having a conformal high-k dielectric layer will be at a position with the same thickness as TCon, and the yield / reliability and device performance of a nanostructured transistor (74C) (Fig. 30a and Fig. 30b) with a thicker corner / sidewall portion of the high-k dielectric layer (66C) will be at a position with the same thickness as T3C / T4C (Fig. 21). It is understood that the nanostructured transistor (74D) has reduced device performance and improved yield / reliability.
[0082] The X-axis in FIG. 33 illustrates the thickness of the inner portion of the high-k dielectric layer (66D) (Fig. 25). The yield / reliability and device performance of the nanostructured transistor having a conformal high-k dielectric layer will be at a position with the same thickness as TCon, and the yield / reliability and device performance of the nanostructured transistor (74D) (Fig. 30a and Fig. 30b), in which the inner portion of the high-k dielectric layer (66D) is thinner, will be at a position with the same inner thickness as T1'D (Fig. 25). It is understood that the nanostructured transistor (74C) has improved device performance and reduced yield / reliability.
[0083] Embodiments of the present disclosure have some advantageous features. By adopting different process conditions to modulate the profile of the high-k dielectric layer, the nanostructured transistor can be modulated for different requirements, such as improved yield and reliability, or improved device performance.
[0084] According to some embodiments of the present disclosure, the method comprises the steps of: forming a plurality of first semiconductor nanostructures—the plurality of first semiconductor nanostructures comprising a first lower semiconductor nanostructure; and a first upper semiconductor nanostructure on the first lower semiconductor nanostructure—; forming interface layers in contact with the plurality of first semiconductor nanostructures; and depositing first high-k dielectric layers surrounding the interface layers, wherein among the first high-k dielectric layers, the first upper high-k dielectric layer surrounding the first upper semiconductor nanostructure comprises: a first upper horizontal portion overlapping with the first upper semiconductor nanostructure; a first lower horizontal portion overlapping by the first upper semiconductor nanostructure; and a first sidewall portion on the sidewall of the first upper semiconductor nanostructure, wherein a first portion selected from the first upper horizontal portion, the first lower horizontal portion, and the first sidewall portion has a first thickness, and a second portion selected from the first upper horizontal portion, the first lower horizontal portion, and the first sidewall portion has a second thickness different from the first thickness.
[0085] In an example, the second thickness is smaller than the first thickness. In an example, the step of depositing the first high-k dielectric layers includes an atomic layer deposition process. In an example, the thinner first portion is the first upper horizontal portion, and the thicker second portion is the first lower horizontal portion. In an example, the first sidewall portion has the same thickness as the first lower horizontal portion.
[0086] In an embodiment, the method further comprises the steps of forming a plurality of second semiconductor nanostructures—the plurality of second semiconductor nanostructures comprising a second lower semiconductor nanostructure; and a second upper semiconductor nanostructure on top of the second lower semiconductor nanostructure—and depositing a second high-k dielectric layer surrounding the plurality of second semiconductor nanostructures, wherein among the second high-k dielectric layers, the second upper high-k dielectric layer surrounding the second upper semiconductor nanostructure comprises: a second upper horizontal portion overlapping with the second upper semiconductor nanostructure; and a second lower horizontal portion overlapping with the second upper semiconductor nanostructure, and the second upper horizontal portion is thicker than the first upper horizontal portion.
[0087] In an embodiment, the second lower horizontal portion is thinner than the second upper horizontal portion. In an embodiment, the first portion is the first sidewall portion, and the second portion is the first lower horizontal portion. In an embodiment, the method further comprises the steps of: forming a source / drain region adjacent to and in contact with a plurality of first semiconductor nanostructures; and forming a gate electrode on the first high-k dielectric layers. In an embodiment, the first high-k dielectric layers comprise hafnium oxide. In an embodiment, the interface layers comprise silicon oxide.
[0088] According to some embodiments of the present disclosure, the method comprises: forming a plurality of first semiconductor nanostructures including a first top-level semiconductor nanostructure; forming a plurality of second semiconductor nanostructures including a second top-level semiconductor nanostructure; depositing a first high-k dielectric layer surrounding the first top-level semiconductor nanostructure, wherein the first high-k dielectric layer is deposited using first process conditions; and depositing a second high-k dielectric layer surrounding the second top-level semiconductor nanostructure, wherein the second high-k dielectric layer is deposited using second process conditions different from the first process conditions, and the first high-k dielectric layer comprises the same high-k dielectric material as the second high-k dielectric layer; forming a first gate electrode surrounding the first high-k dielectric layer; and forming a second gate electrode surrounding the second high-k dielectric layer, wherein the first gate electrode and the second gate electrode are formed by sharing common processes.
[0089] In an embodiment, the method further comprises the steps of: forming a first interface layer on a first top-level semiconductor nanostructure before a first high-k dielectric layer is formed; and forming a second interface layer on a second top-level semiconductor nanostructure before a second high-k dielectric layer is formed, wherein the first interface layer is formed in the same formation process as the second interface layer.
[0090] In an embodiment, the first process conditions include a first wafer temperature and a first chamber pressure, and the second process conditions include a second wafer temperature higher than the first wafer temperature; and a second chamber pressure higher than the first chamber pressure. In an embodiment, the first high-k dielectric layer includes a first upper horizontal portion overlapping with a first upper semiconductor nanostructure; and a first lower horizontal portion overlapping with the first upper semiconductor nanostructure, wherein the first upper horizontal portion is thinner than the first lower horizontal portion.
[0091] In an embodiment, the second high-k dielectric layer comprises a second upper horizontal portion that overlaps with the second upper semiconductor nanostructure; and a second lower horizontal portion that overlaps with the second upper semiconductor nanostructure, wherein the second upper horizontal portion is thicker than the second lower horizontal portion. In an embodiment, both the first high-k dielectric layer and the second high-k dielectric layer are deposited through atomic layer deposition processes.
[0092] According to some embodiments of the present disclosure, the structure comprises a plurality of first semiconductor nanostructures—the plurality of first semiconductor nanostructures include: a first lower semiconductor nanostructure; and a first upper semiconductor nanostructure above the first lower semiconductor nanostructure—; an interface layer surrounding the first upper semiconductor nanostructure; and a first high-k dielectric layer surrounding the interface layer, wherein the first high-k dielectric layer comprises: a first upper horizontal portion overlapping the first upper semiconductor nanostructure and having a first thickness; a first lower horizontal portion overlapping the first upper semiconductor nanostructure and having a second thickness different from the first thickness; and a first sidewall portion on the sidewall of the first upper semiconductor nanostructure.
[0093] In an embodiment, the first thickness is smaller than the second thickness. In an embodiment, the structure further comprises a second plurality of semiconductor nanostructures—the second plurality of semiconductor nanostructures being a second lower semiconductor nanostructure; and a second upper semiconductor nanostructure above the second lower semiconductor nanostructure—; and a second high-k dielectric layer surrounding the second upper semiconductor nanostructure, wherein the second high-k dielectric layer overlaps the second upper semiconductor nanostructure and comprises a second upper horizontal portion having a third thickness; and a second lower horizontal portion overlapped by the second upper semiconductor nanostructure and having a fourth thickness smaller than the third thickness. In an embodiment, the first upper horizontal portion is thinner than the first sidewall portion.
[0094] The foregoing describes the features of various embodiments to enable those skilled in the art to better understand the aspects of the present disclosure. Those skilled in the art should recognize that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure.
[0095] Examples
[0096] Example 1. In the method,
[0097] Step of forming a plurality of first semiconductor nanostructures - the plurality of first semiconductor nanostructures are:
[0098] First sub-semiconductor nanostructure; and
[0099] Includes a first uppermost semiconductor nanostructure on the first lower semiconductor nanostructure above;
[0100] The step of forming interface layers on the plurality of first semiconductor nanostructures; and
[0101] The method comprises the step of depositing first high-k dielectric layers surrounding the interface layers, wherein among the first high-k dielectric layers, the first uppermost high-k dielectric layer surrounding the first uppermost semiconductor nanostructure comprises:
[0102] A first uppermost horizontal portion overlapping with the first uppermost semiconductor nanostructure;
[0103] A first lower horizontal portion superimposed by the first uppermost semiconductor nanostructure; and
[0104] A method comprising a first sidewall portion on the sidewall of the first uppermost semiconductor nanostructure, wherein the first uppermost horizontal portion, the first lower horizontal portion, and the first portion selected from the first sidewall portion have a first thickness, and the second portion selected from the first uppermost horizontal portion, the first lower horizontal portion, and the first sidewall portion have a second thickness different from the first thickness.
[0105] Example 2. In Example 1,
[0106] A method in which the second thickness is smaller than the first thickness.
[0107] Example 3. In Example 1,
[0108] A method in which the thinner first part is the first uppermost horizontal part and the thicker second part is the first lower horizontal part.
[0109] Example 4. In Example 3,
[0110] A method in which the first side wall portion has the same thickness as the first lower horizontal portion.
[0111] Example 5. In Example 3,
[0112] Step of forming a plurality of second semiconductor nanostructures - the plurality of second semiconductor nanostructures are:
[0113] Second sub-semiconductor nanostructure; and
[0114] Includes a second uppermost semiconductor nanostructure on the second lower semiconductor nanostructure; and
[0115] The method further includes the step of depositing second high-k dielectric layers surrounding the plurality of second semiconductor nanostructures, wherein among the second high-k dielectric layers, the second uppermost high-k dielectric layer surrounding the second uppermost semiconductor nanostructure comprises:
[0116] A second uppermost horizontal portion overlapping with the second uppermost semiconductor nanostructure; and
[0117] A method comprising a second lower horizontal portion that overlaps with the second uppermost semiconductor nanostructure, wherein the second uppermost horizontal portion is thicker than the first uppermost horizontal portion.
[0118] Example 6. In Example 5,
[0119] A method in which the second lower horizontal portion is thinner than the second upper horizontal portion.
[0120] Example 7. In Example 1,
[0121] A method in which the first part is the first side wall part and the second part is the first lower horizontal part.
[0122] Example 8. In Example 1,
[0123] A step of forming a source / drain region adjacent to the plurality of first semiconductor nanostructures and in contact with the plurality of first semiconductor nanostructures; and
[0124] A method further comprising the step of forming a gate electrode on the first high-k dielectric layers.
[0125] Example 9. In Example 1,
[0126] A method in which the first high-k dielectric layers include hafnium oxide.
[0127] Example 10. In Example 1,
[0128] A method in which the above interface layers comprise silicon oxide.
[0129] Example 11. In the method,
[0130] A step of forming a plurality of first semiconductor nanostructures including a first top-level semiconductor nanostructure;
[0131] A step of forming a plurality of second semiconductor nanostructures including a second top-level semiconductor nanostructure;
[0132] A step of depositing a first high-k dielectric layer surrounding the first uppermost semiconductor nanostructure - the first high-k dielectric layer is deposited using first process conditions -;
[0133] A step of depositing a second high-k dielectric layer surrounding the second uppermost semiconductor nanostructure—the second high-k dielectric layer is deposited using second process conditions different from the first process conditions, and the first high-k dielectric layer comprises the same high-k dielectric material as the second high-k dielectric layer—;
[0134] A step of forming a first gate electrode surrounding the first high-k dielectric layer; and
[0135] A method comprising the step of forming a second gate electrode surrounding the second high-k dielectric layer, wherein the first gate electrode and the second gate electrode are formed by sharing common processes.
[0136] Example 12. In Example 11,
[0137] A step of forming a first interface layer on the first top-most semiconductor nanostructure before the first high-k dielectric layer is formed; and
[0138] A method further comprising the step of forming a second interface layer on the second uppermost semiconductor nanostructure before the second high-k dielectric layer is formed, wherein the first interface layer is formed in the same formation process as the second interface layer.
[0139] Example 13. In Example 11,
[0140] The first process conditions above include a first wafer temperature and a first chamber pressure, and the second process conditions are:
[0141] A second wafer temperature higher than the first wafer temperature; and
[0142] A method comprising a second chamber pressure higher than the first chamber pressure.
[0143] Example 14. In Example 13,
[0144] The above-mentioned first high-k dielectric layer is:
[0145] A first uppermost horizontal portion overlapping with the first uppermost semiconductor nanostructure; and
[0146] A method comprising a first lower horizontal portion that overlaps with the first uppermost semiconductor nanostructure, wherein the first uppermost horizontal portion is thinner than the first lower horizontal portion.
[0147] Example 15. In Example 14,
[0148] The above-mentioned second high-k dielectric layer is:
[0149] A second uppermost horizontal portion overlapping with the second uppermost semiconductor nanostructure; and
[0150] A method comprising a second lower horizontal portion that overlaps with the second uppermost semiconductor nanostructure, wherein the second uppermost horizontal portion is thicker than the second lower horizontal portion.
[0151] Example 16. In Example 11,
[0152] A method in which both the first high-k dielectric layer and the second high-k dielectric layer are deposited through atomic layer deposition processes.
[0153] Example 17. In a structure,
[0154] Multiple first semiconductor nanostructures - the multiple first semiconductor nanostructures are:
[0155] First sub-semiconductor nanostructure; and
[0156] Includes a first uppermost semiconductor nanostructure on the first lower semiconductor nanostructure above;
[0157] An interface layer surrounding the first uppermost semiconductor nanostructure; and
[0158] It includes a first high-k dielectric layer surrounding the interface layer, wherein the first high-k dielectric layer is:
[0159] A first upper horizontal portion having a first thickness that overlaps with the first uppermost semiconductor nanostructure;
[0160] A first lower horizontal portion superimposed by the first uppermost semiconductor nanostructure and having a second thickness different from the first thickness; and
[0161] A structure comprising a first sidewall portion on the sidewall of the first uppermost semiconductor nanostructure.
[0162] Example 18. In Example 17,
[0163] A structure in which the first thickness is smaller than the second thickness.
[0164] Example 19. In Example 18,
[0165] Multiple second semiconductor nanostructures - the multiple second semiconductor nanostructures are:
[0166] Second sub-semiconductor nanostructure; and
[0167] Includes a second uppermost semiconductor nanostructure on the second lower semiconductor nanostructure; and
[0168] It includes a second high-k dielectric layer surrounding the second uppermost semiconductor nanostructure, wherein the second high-k dielectric layer comprises:
[0169] A second upper horizontal portion having a third thickness that overlaps with the second uppermost semiconductor nanostructure; and
[0170] A structure comprising a second lower horizontal portion having a fourth thickness different from the third thickness, which is superimposed by the second uppermost semiconductor nanostructure.
[0171] Example 20. In Example 18,
[0172] A structure in which the first upper horizontal portion is thinner than the first side wall portion.
Claims
Claim 1 In the method, the step of forming a plurality of first semiconductor nanostructures - said plurality of first semiconductor nanostructures are: First sub-semiconductor nanostructure; and The method comprises: a first uppermost semiconductor nanostructure on the first lower semiconductor nanostructure; a step of forming interface layers on the plurality of first semiconductor nanostructures; and a step of depositing first high-k dielectric layers surrounding the interface layers, wherein among the first high-k dielectric layers, the first uppermost high-k dielectric layer surrounding the first uppermost semiconductor nanostructure comprises: A first uppermost horizontal portion overlapping with the first uppermost semiconductor nanostructure; A first lower horizontal portion superimposed by the first uppermost semiconductor nanostructure; and A method comprising a first sidewall portion on the sidewall of the first uppermost semiconductor nanostructure, wherein the first uppermost horizontal portion, the first lower horizontal portion, and the first portion selected from the first sidewall portion have a first thickness, and the second portion selected from the first uppermost horizontal portion, the first lower horizontal portion, and the first sidewall portion have a second thickness different from the first thickness. Claim 2 A method according to claim 1, wherein the second thickness is smaller than the first thickness. Claim 3 A method according to claim 1, wherein the thinner first portion is the first uppermost horizontal portion and the thicker second portion is the first lowermost horizontal portion. Claim 4 A method according to claim 1, wherein the first part is the first side wall part and the second part is the first lower horizontal part. Claim 5 A method according to claim 1, further comprising: forming a source / drain region adjacent to and in contact with the plurality of first semiconductor nanostructures; and forming a gate electrode on the first high-k dielectric layers. Claim 6 A method according to claim 1, wherein the first high-k dielectric layers comprise hafnium oxide. Claim 7 The method of claim 1, wherein the interface layers comprise silicon oxide. Claim 8 A method comprising: forming a plurality of first semiconductor nanostructures including a first top-level semiconductor nanostructure; forming a plurality of second semiconductor nanostructures including a second top-level semiconductor nanostructure; depositing a first high-k dielectric layer surrounding the first top-level semiconductor nanostructure, wherein the first high-k dielectric layer is deposited using first process conditions; depositing a second high-k dielectric layer surrounding the second top-level semiconductor nanostructure, wherein the second high-k dielectric layer is deposited using second process conditions different from the first process conditions, and the first high-k dielectric layer comprises the same high-k dielectric material as the second high-k dielectric layer; forming a first gate electrode surrounding the first high-k dielectric layer; and forming a second gate electrode surrounding the second high-k dielectric layer, wherein the first gate electrode and the second gate electrode are formed by sharing common processes. Claim 9 In the structure, a plurality of first semiconductor nanostructures - said plurality of first semiconductor nanostructures are: First sub-semiconductor nanostructure; and Comprising a first uppermost semiconductor nanostructure on the first lower semiconductor nanostructure; an interface layer surrounding the first uppermost semiconductor nanostructure; and a first high-k dielectric layer surrounding the interface layer, wherein the first high-k dielectric layer comprises: A first upper horizontal portion having a first thickness that overlaps with the first uppermost semiconductor nanostructure; A first lower horizontal portion superimposed by the first uppermost semiconductor nanostructure and having a second thickness different from the first thickness; and A structure comprising a first sidewall portion on the sidewall of the first uppermost semiconductor nanostructure. Claim 10 A structure according to claim 9, wherein the first thickness is smaller than the second thickness.