Display device and electronic device including the same

Abstract

The display device comprises a first partition on a substrate, an inorganic layer on the first partition, a second partition on the inorganic layer, a first electrode on the second partition, a light-emitting layer on the first electrode, a second electrode on the light-emitting layer, and an encapsulation layer on the second electrode, wherein the encapsulation layer is in contact with the side of the inorganic layer.

Description

Technology Field

[0001] The present invention relates to a display device and an electronic device including the same. Background Technology

[0002] With the recent rise in interest in information displays, research and development on display devices is continuously being carried out. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a display device with improved reliability and an electronic device including the same.

[0004] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A display device according to an embodiment for solving the above problem comprises a first partition on a substrate, an inorganic layer on the first partition, a second partition on the inorganic layer, a first electrode on the second partition, a light-emitting layer on the first electrode, a second electrode on the light-emitting layer, and an encapsulation layer on the second electrode, wherein the encapsulation layer is in contact with the side of the inorganic layer.

[0006] The above-mentioned inorganic layer is disposed on the edge region of the first bulkhead and may include an opening that overlaps with the central region of the first bulkhead.

[0007] The above edge region can surround the above central region.

[0008] The above-mentioned bag layer can be in contact with the side of the above-mentioned second partition.

[0009] The above display device may further include a conductive layer between the first partition and the inorganic layer.

[0010] The width of the above conductive layer may be the same as the width of the above inorganic layer.

[0011] The conductive layer is disposed on the edge region of the first bulkhead and may include an opening that overlaps with the central region of the first bulkhead.

[0012] The above edge region can surround the above central region.

[0013] The above display device may further include a connection line between the substrate and the first partition.

[0014] The above connection line can be electrically connected to the first bulkhead.

[0015] The above display device may further include a connecting electrode between the second partition and the first electrode.

[0016] The above connecting electrode can be electrically connected to the above second partition.

[0017] The above display device may further include an insulating layer between the connecting electrode and the first electrode.

[0018] The insulating layer is in contact with the first surface of the connecting electrode, and the second electrode can be in contact with the second surface of the connecting electrode.

[0019] The above-mentioned packaging layer can come into contact with the second surface of the above-mentioned connecting electrode.

[0020] The width of the insulation layer may be greater than the width of the second partition.

[0021] The above connecting electrode can be electrically separated from the first electrode.

[0022] The width of the above connecting electrode may be greater than the width of the above second partition.

[0023] The second electrode can be electrically connected to the connecting electrode.

[0024] An electronic device according to an embodiment for solving the above problem comprises a processor and pixels, and includes a display device configured to display an image on the pixels according to the control of the processor, wherein the display device comprises a first barrier on a substrate, a second barrier on the first barrier, an inorganic layer between the first barrier and the second barrier, a first electrode on the second barrier, a light-emitting layer on the first electrode, a second electrode on the light-emitting layer, and an encapsulation layer on the second electrode, wherein the encapsulation layer is in contact with the inorganic layer.

[0025] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0026] According to the above-described embodiment, moisture permeability can be improved by enhancing the bonding strength of the bag layer through contact with the inorganic layer disposed on the first partition.

[0027] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0028] FIG. 1 is a block diagram showing an example of a display device. FIG. 2 is a block diagram showing an embodiment of any one of the subpixels of FIG. 1. Figure 3 is a plan view showing an example of the display panel of Figure 1. Figure 4 is a plan view showing an example of the pixel of Figure 3. FIGS. 5 to 7 are cross-sectional views showing an embodiment of any one of the subpixels of FIG. 4. FIGS. 8 to 17 are cross-sectional views of the process steps of a method for manufacturing a display device according to an embodiment. FIGS. 18 and 19 are cross-sectional views of the process steps of a method for manufacturing a display device according to an embodiment. FIG. 20 is a block diagram of an electronic device according to an embodiment. FIG. 21 is a schematic diagram of an electronic device according to various embodiments. Specific details for implementing the invention

[0029] Hereinafter, preferred embodiments according to the present invention may be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the parts necessary for understanding the operation according to the present invention are described, and the description of other parts may be omitted to avoid obscuring the gist of the present invention. The present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided merely to explain in detail sufficient for a person skilled in the art to easily implement the technical concept of the present invention.

[0030] Throughout the specification, when a part is described as being "connected" to another part, this may include not only cases where they are "directly connected," but also cases where they are "indirectly connected" with other elements interposed between them. The terms used herein are intended to describe specific embodiments and are not intended to limit the invention. Throughout the specification, when a part is described as being "comprised" of a certain component, this may mean that it may include additional components rather than excluding other components, unless specifically stated otherwise. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Here, "and / or" may include all combinations of one or more of such components.

[0031] Herein, terms such as first, second, etc. may be used to describe various components, but these components are not limited to these terms. These terms may be used to distinguish one component from another. Accordingly, the first component may refer to the second component to the extent that it does not depart from what is disclosed herein.

[0032] Spatially relative terms, such as "below" and "above," may be used for descriptive purposes to explain the relationship between one element or feature and other element(s) or feature(s) as depicted in the drawings. Spatially relative terms are intended to include different directions during use, operation, and / or manufacturing, in addition to the directions depicted in the drawings. For example, if the device depicted in the drawings is inverted, elements described as being located "below" other elements or features may be located in the direction "above" of other elements or features. Accordingly, in the embodiments, the term "below" may include both directions of up and down. Furthermore, the device may face other directions (e.g., rotated 90 degrees or in other directions), and accordingly, the spatially relative terms used herein may be interpreted accordingly.

[0033] Various embodiments may be described with reference to drawings illustrating ideal embodiments. Accordingly, it will be expected that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the specific shapes depicted, but should be interpreted to include, for example, variations in shapes resulting from manufacturing. As such, the shapes depicted in the drawings may not depict the actual shapes of the regions of the device, and the embodiments are not limited thereto.

[0034] FIG. 1 is a block diagram showing an example of a display device.

[0035] Referring to FIG. 1, the display device (100) may include a display panel (110), a gate driver (120), a data driver (130), a voltage generator (140), and a controller (150).

[0036] The display panel (110) may include subpixels (SP). The subpixels (SP) may be connected to a gate driver (120) through first to m gate lines (GL1 to GLm). The subpixels (SP) may be connected to a data driver (130) through first to n data lines (DL1 to DLn).

[0037] Each of the subpixels (SP) may include at least one light-emitting element configured to generate light. Accordingly, each of the subpixels (SP) may generate light of a specific color, such as red, green, blue, cyan, magenta, yellow, etc. Two or more of the subpixels (SP) may form a single pixel (PXL). For example, as shown in FIG. 1, three subpixels (SP) may form a single pixel (PXL).

[0038] The gate driver (120) can be connected to subpixels (SP) arranged in a row direction through the first to m gate lines (GL1 to GLm). The gate driver (120) can output gate signals to the first to m gate lines (GL1 to GLm) in response to a gate control signal (GCS). In an embodiment, the gate control signal (GCS) may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting gate signals in synchronization with the timing at which data signals are applied, etc.

[0039] In an embodiment, first to m light emission control lines (EL1 to ELm) connected to row-direction subpixels (SP) may be further provided. In this case, the gate driver (120) may include a light emission control driver configured to control the first to m light emission control lines (EL1 to ELm), and the light emission control driver may operate under the control of the controller (150).

[0040] The gate driver (120) may be positioned on one side of the display panel (110). However, embodiments are not limited thereto. For example, the gate driver (120) may be divided into two or more physically and / or logically separated drivers, and such drivers may be positioned on one side of the display panel (110) and on the other side of the display panel (110) opposite to that side. Thus, the gate driver (120) may be positioned around the display panel (110) in various forms according to the embodiments.

[0041] The data driver (130) can be connected to subpixels (SP) arranged in a column direction through the first to nth data lines (DL1 to DLn). The data driver (130) can receive image data (DATA) and a data control signal (DCS) from the controller (150). The data driver (130) can operate in response to the data control signal (DCS). In an embodiment, the data control signal (DCS) may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0042] The data driver (130) can apply data signals including grayscale voltages corresponding to image data (DATA) to the first to nth data lines (DL1 to DLn) using voltages from the voltage generator (140). When a gate signal is applied to each of the first to mth gate lines (GL1 to GLm), data signals corresponding to image data (DATA) can be applied to the data lines (DL1 to DLm). Accordingly, the corresponding subpixels (SP) can generate light corresponding to the data signals. Accordingly, an image can be displayed on the display panel (110).

[0043] In the embodiment, the gate driver (120) and the data driver (130) may include CMOS (complementary metal-oxide semiconductor) circuit elements.

[0044] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) can be configured to generate multiple voltages and provide the generated voltages to the components of the display device (100). For example, the voltage generator (140) can be configured to generate multiple voltages by receiving an input voltage from outside the display device (100), adjusting the received voltage, and regulating the adjusted voltage.

[0045] The voltage generator (140) can generate a first power supply voltage (VDD) and a second power supply voltage (VSS), and the generated first and second power supply voltages (VDD, VSS) can be provided to subpixels (SP). The first power supply voltage (VDD) has a relatively high voltage level, and the second power supply voltage (VSS) may have a lower voltage level than the first power supply voltage (VDD). In another embodiment, the first power supply voltage (VDD) or the second power supply voltage (VSS) may be provided by an external device of the display device (100).

[0046] In addition to this, the voltage generator (140) can generate various voltages. For example, the voltage generator (140) can generate an initialization voltage applied to subpixels (SP). For example, during a sensing operation to sense the electrical characteristics of the transistors and / or light-emitting elements of the subpixels (SP), a predetermined reference voltage may be applied to the first to nth data lines (DL1 to DLn), and the voltage generator (140) can generate such a reference voltage.

[0047] The controller (150) can control the various operations of the display device (100). The controller (150) can receive input image data (IMG) and a control signal (CTRL) for controlling the display thereof from an external source. In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS).

[0048] The controller (150) can convert the input image data (IMG) to be suitable for the display device (100) or display panel (110) and output image data (DATA). In an embodiment, the controller (150) can output image data (DATA) by aligning the input image data (IMG) to be suitable for row-unit subpixels (SP).

[0049] Two or more components of the data driver (130), voltage generator (140), and controller (150) may be mounted on a single integrated circuit. As illustrated in FIG. 1, the data driver (130), voltage generator (140), and controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), voltage generator (140), and controller (150) may be functionally separate components within a single driver integrated circuit (DIC). In another embodiment, at least one of the data driver (130), voltage generator (140), and controller (150) may be provided as a component separate from the driver integrated circuit (DIC).

[0050] FIG. 2 is a block diagram showing an embodiment of any one of the subpixels of FIG. 1. In FIG. 2, subpixels (SPij) arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) of the subpixels (SP) of FIG. 1 may be illustrated as an example.

[0051] Referring to FIG. 2, the subpixel (SPij) may include a subpixel circuit (SPC) and a light-emitting element (LD).

[0052] A light-emitting element (LD) can be connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) is a node that transmits the first power supply voltage (VDD) of FIG. 1, and the second power supply voltage node (VSSN) may be a node that transmits the second power supply voltage (VSS) of FIG. 1.

[0053] The anode electrode (AE) of the light-emitting element (LD) may be connected to a first power supply voltage node (VDDN) through a sub-pixel circuit (SPC), and the cathode electrode (CE) of the light-emitting element (LD) may be connected to a second power supply voltage node (VSSN). For example, the anode electrode (AE) of the light-emitting element (LD) may be connected to the first power supply voltage node (VDDN) through one or more transistors included in the sub-pixel circuit (SPC).

[0054] The subpixel circuit (SPC) can be connected to the i-th gate line (GLi) among the first to m-th gate lines (GL1 to GLm) of FIG. 1, the i-th light emission control line (ELi) among the first to m-th light emission control lines (EL1 to ELm) of FIG. 1, and the j-th data line (DLj) among the first to n-th data lines (DL1 to DLn) of FIG. 1. The subpixel circuit (SPC) can be configured to control the light-emitting element (LD) according to signals received through these signal lines.

[0055] The subpixel circuit (SPC) can operate in response to a gate signal received through the i-th gate line (GLi). The i-th gate line (GLi) may include one or more sub-gate lines. In an embodiment, as shown in FIG. 2, the i-th gate line (GLi) may include first and second sub-gate lines (SGL1, SGL2). The subpixel circuit (SPC) can operate in response to gate signals received through the first and second sub-gate lines (SGL1, SGL2). Thus, when the i-th gate line (GLi) includes two or more sub-gate lines, the subpixel circuit (SPC) can operate in response to gate signals received through the corresponding sub-gate lines.

[0056] The subpixel circuit (SPC) can operate in response to a light emission control signal received through the i-th light emission control line (ELi). In an embodiment, the i-th light emission control line (ELi) may include one or more sub-light emission control lines. If the i-th light emission control line (ELi) includes two or more sub-light emission control lines, the subpixel circuit (SPC) can operate in response to light emission control signals received through the said sub-light emission control lines.

[0057] The subpixel circuit (SPC) can receive a data signal through the j-th data line (DLj). The subpixel circuit (SPC) can store a voltage corresponding to the data signal in response to at least one of the gate signals received through the first and second sub-gate lines (SGL1, SGL2). The subpixel circuit (SPC) can regulate the current flowing from the first power supply voltage node (VDDN) to the second power supply voltage node (VSSN) through the light-emitting element (LD) according to the stored voltage in response to a light-emitting control signal received through the i-th light-emitting control line (ELi). Accordingly, the light-emitting element (LD) can generate light of a brightness corresponding to the data signal.

[0058] Figure 3 is a plan view showing an example of the display panel of Figure 1.

[0059] Referring to FIG. 3, an embodiment (DP) of the display panel (110) of FIG. 1 may include a display area (DA) and a non-display area (NDA). The display panel (DP) may display an image through the display area (DA). The non-display area (NDA) may be placed around the display area (DA).

[0060] A display panel (DP) may include a substrate (SUB), subpixels (SP), and pads (PD). Subpixels (SP) may be placed in a display area (DA) on the substrate (SUB). Subpixels (SP) may be arranged in a matrix form along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). However, embodiments are not limited thereto. For example, subpixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). For example, subpixels (SP) may be arranged in a pentile form. The first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction.

[0061] Two or more of the multiple subpixels (SP) can form a single pixel (PXL).

[0062] Components for controlling subpixels (SP) may be disposed in a non-display area (NDA) on a substrate (SUB). For example, wiring connected to subpixels (SP), such as the first to m gate lines (GL1 to GLm) and the first to n data lines (DL1 to DLn) of FIG. 1, may be disposed in the non-display area (NDA).

[0063] At least one of the gate driver (120), data driver (130), voltage generator (140), and controller (150) of FIG. 1 may be integrated in the non-display area (NDA) of the display panel (DP). In an embodiment, the gate driver (120) of FIG. 1 may be mounted on the display panel (DP) but placed in the non-display area (NDA). In another embodiment, the gate driver (120) may be implemented as an integrated circuit separated from the display panel (DP).

[0064] Pads (PDs) may be placed in a non-display area (NDA) on a substrate (SUB). The pads (PDs) may be electrically connected to subpixels (SPs) through wiring. For example, the pads (PDs) may be connected to the subpixels (SPs) through first to n data lines (DL1 to DLn).

[0065] Pads (PDs) can interface the display panel (DP) with other components of the display device (100, see FIG. 1). In an embodiment, voltages and signals required for the operation of components included in the display panel (DP) may be provided from the driver integrated circuit (DIC) of FIG. 1 through the pads (PDs). For example, the first to nth data lines (DL1 to DLn) may be connected to the driver integrated circuit (DIC) through the pads (PDs). For example, the first and second power supply voltages (VDD, VSS) may be received from the driver integrated circuit (DIC) through the pads (PDs). For example, if a gate driver (120) is mounted on the display panel (DP), a gate control signal (GCS) may be transmitted from the driver integrated circuit (DIC) to the gate driver (120) through the pads (PDs).

[0066] In an embodiment, a circuit board can be electrically connected to pads (PDs) using a conductive adhesive member such as an anisotropic conductive film. In this case, the circuit board may be a flexible circuit board (FPCB) or a flexible film comprising a flexible material. A driver integrated circuit (DIC) can be mounted on the circuit board and electrically connected to the pads (PDs).

[0067] In the embodiments, the display area (DA) may have various shapes. The display area (DA) may have the shape of a closed loop including straight and / or curved sides. For example, the display area (DA) may have shapes such as a polygon, a circle, a semicircle, an ellipse, etc.

[0068] In an embodiment, the display panel (DP) may have a flat display surface. In another embodiment, the display panel (DP) may have at least a partially rounded display surface. In an embodiment, the display panel (DP) may be bendable, foldable, or rollable. In these cases, the display panel (DP) and / or the substrate (SUB) may comprise materials having flexible properties.

[0069] Figure 4 is a plan view showing an example of the pixel of Figure 3.

[0070] Referring to FIG. 4, the pixel (PXL) may include first to third subpixels (SP1 to SP3) arranged in a first direction (DR1).

[0071] The first subpixel (SP1) may include a first light-emitting region (EMA1) and a non-light-emitting region (NEA) around the first light-emitting region (EMA1). The second subpixel (SP2) may include a second light-emitting region (EMA2) and a non-light-emitting region (NEA) around the second light-emitting region (EMA2). The third subpixel (SP3) may include a third light-emitting region (EMA3) and a non-light-emitting region (NEA) around the third light-emitting region (EMA3).

[0072] The first light-emitting region (EMA1) may be a region where light is emitted from a light-emitting layer corresponding to the first subpixel (SP1). The second light-emitting region (EMA2) may be a region where light is emitted from a light-emitting layer corresponding to the second subpixel (SP2). The third light-emitting region (EMA3) may be a region where light is emitted from a light-emitting layer corresponding to the third subpixel (SP3). The first to third light-emitting regions (EMA1~EMA3) may each be understood as an opening of a pixel defining film (PDL) corresponding to each of the first to third subpixels (SP1~SP3).

[0073] FIGS. 5 to 7 are cross-sectional views showing an embodiment of any one of the subpixels of FIG. 4.

[0074] Referring to FIGS. 5 through 7, the substrate (SUB) may include a base layer and a circuit layer. The base layer may be formed of polyimide (PI), glass, or a silicon wafer, etc. The circuit layer includes conductive patterns and insulating layers, and the conductive patterns may function as sub-pixel circuits (see SPC in FIG. 2) and various wirings. The circuit layer may include circuit elements including transistors and at least one capacitor. Each transistor may include a semiconductor portion comprising a source region, a drain region, and a channel region, and a gate electrode superimposed on the semiconductor portion. Each capacitor may include electrodes spaced apart from each other in a third direction (DR3) with an insulating layer in between. The wirings of the circuit layer may include signal lines, for example, gate lines, light emission control lines, and data lines.

[0075] A connection line (CL) may be disposed on the substrate (SUB). The connection line (CL) may be formed entirely on the substrate (SUB), but is not necessarily limited thereto. In the embodiment, the connection line (CL) may be formed of titanium (Ti), but is not necessarily limited thereto.

[0076] A first bulkhead (SW1) may be disposed on the connection line (CL). The first bulkhead (SW1) may be disposed directly on the connection line (CL). The first bulkhead (SW1) may be electrically connected to the connection line (CL). The first bulkhead (SW1) may be formed of aluminum (Al), but is not necessarily limited thereto.

[0077] An inorganic layer (IL) may be disposed on the first bulkhead (SW1). The inorganic layer (IL) may serve to improve moisture permeability by contacting or combining with the sealing layer (TFE) to be described later. The inorganic layer (IL) may be disposed on the first region (A1) of the first bulkhead (SW1). The first region (A1) may refer to the edge region of the first bulkhead (SW1). The inorganic layer (IL) may include an opening that overlaps with the second region (A2) of the first bulkhead (SW1). The second region (A2) may refer to the central region of the first bulkhead (SW1). The second region (A2) may be surrounded by the first region (A1). The width of the first direction (DR1) of the first region (A1) may be smaller than the width of the first direction (DR1) of the second region (A2), but is not necessarily limited thereto. The area of ​​the first area (A1) may be smaller than the area of ​​the second area (A2), but is not necessarily limited thereto.

[0078] In the examples, the inorganic layer (IL) may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlxOy), titanium oxide (TiOx), tantalum oxide (TaxOy), hafnium oxide (HfOx), and zinc oxide (ZnOx), but is not necessarily limited thereto.

[0079] As illustrated in FIG. 5, the thickness of the inorganic layer (IL) in the third direction (DR3) may be thinner than the thickness of the second bulkhead (SW2) in the third direction (DR3). In this case, the second bulkhead (SW2) may be in contact with the side and top surfaces of the inorganic layer (IL).

[0080] According to an embodiment, as illustrated in FIG. 6, the thickness of the inorganic layer (IL) in the third direction (DR3) may be the same as the thickness of the second bulkhead (SW2) in the third direction (DR3). In this case, the inorganic layer (IL) may be in contact with the side (or edge) of the second bulkhead (SW2).

[0081] As illustrated in FIGS. 5 and 6, the inorganic layer (IL) can be placed directly on the first partition (SW1). According to an embodiment, as illustrated in FIG. 7, a conductive layer (ETL) may be further placed between the inorganic layer (IL) and the first partition (SW1). The conductive layer (ETL) may be placed directly on the first partition (SW1), and the inorganic layer (IL) may be placed directly on the conductive layer (ETL). When the conductive layer (ETL) is formed on the first partition (SW1) and the inorganic layer (IL) is formed on the conductive layer (ETL), arcing can be prevented during the process of forming the inorganic layer (IL).

[0082] A conductive layer (ETL) may be disposed on a first region (A1) of a first bulkhead (SW1). For example, the conductive layer (ETL) may be disposed on an edge region of the first bulkhead (SW1). The conductive layer (ETL) may include an opening that overlaps with a second region (A2) of the first bulkhead (SW1). For example, the conductive layer (ETL) may include an opening that overlaps with a central region of the first bulkhead (SW1). The first region (A1) of the first bulkhead (SW1) may surround the second region (A2) of the first bulkhead (SW1).

[0083] The width of the first direction (DR1) of the conductive layer (ETL) may be the same as the width of the first direction (DR1) of the inorganic layer (IL). The conductive layer (ETL) may completely overlap with the inorganic layer (IL). For example, the conductive layer (ETL) and the inorganic layer (IL) may be etched simultaneously in the same process, but are not necessarily limited thereto. The thickness of the third direction (DR3) of the conductive layer (ETL) may be thinner than the thickness of the third direction (DR3) of the inorganic layer (IL), but is not necessarily limited thereto.

[0084] The conductive layer (ETL) may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), but is not necessarily limited thereto.

[0085] A second bulkhead (SW2) may be disposed on the first bulkhead (SW1) and / or the inorganic layer (IL). The second bulkhead (SW2) may be disposed on the first bulkhead (SW1) exposed by an opening in the inorganic layer (IL). The second bulkhead (SW2) may be in contact with the first bulkhead (SW1) exposed by an opening in the inorganic layer (IL). The second bulkhead (SW2) may be electrically connected to the first bulkhead (SW1). The second bulkhead (SW2) may be disposed directly on the inorganic layer (IL). The second bulkhead (SW2) may be in contact with the upper surface and / or side surface of the inorganic layer (IL).

[0086] A connecting electrode (CNE) may be disposed on the second bulkhead (SW2). The connecting electrode (CNE) may be disposed directly on the second bulkhead (SW2). The lower surface (or second surface) of the connecting electrode (CNE) may be in contact with the second bulkhead (SW2). The connecting electrode (CNE) may be electrically connected to the second bulkhead (SW2).

[0087] The width of the first direction (DR1) of the connecting electrode (CNE) may be greater than the width of the first direction (DR1) of the second partition (SW2). For example, the edge of the connecting electrode (CNE) may protrude beyond the edge of the second partition (SW2). The width of the first direction (DR1) of the connecting electrode (CNE) may be greater than the width of the first direction (DR1) of the first partition (SW1). For example, the edge of the connecting electrode (CNE) may protrude beyond the edge of the first partition (SW1). Accordingly, the connecting electrode (CNE) may form a tip structure protruding from the first partition (SW1) and / or the second partition (SW2).

[0088] The connecting electrode (CNE) may contain the same material as the connecting line (CL). For example, the connecting electrode (CNE) and the connecting line (CL) may be formed of titanium (Ti), but are not necessarily limited thereto.

[0089] An insulating layer (INS) may be disposed on the connecting electrode (CNE). The insulating layer (INS) may be disposed directly on the connecting electrode (CNE). The insulating layer (INS) may be in contact with the upper surface (or first surface) of the connecting electrode (CNE).

[0090] In an embodiment, the width of the first direction (DR1) of the insulating layer (INS) may be greater than the width of the first direction (DR1) of the first partition (SW1). The edge of the insulating layer (INS) may protrude beyond the edge of the first partition (SW1). The width of the first direction (DR1) of the insulating layer (INS) may be greater than the width of the first direction (DR1) of the second partition (SW2). The edge of the insulating layer (INS) may protrude beyond the edge of the second partition (SW2). Accordingly, the insulating layer (INS) may form a tip structure protruding from the first partition (SW1) and / or the second partition (SW2) together with the connecting electrode (CNE).

[0091] The insulating layer (INS) may include an inorganic material. For example, the insulating layer (INS) may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlxOy), titanium oxide (TiOx), tantalum oxide (TaxOy), hafnium oxide (HfOx), and zinc oxide (ZnOx), but is not necessarily limited thereto.

[0092] An anode electrode (AE) (or a first electrode) may be disposed on the insulating layer (INS). The anode electrode (AE) may be disposed directly on the insulating layer (INS). The anode electrode (AE) may be electrically isolated from the connecting electrode (CNE) by the insulating layer (INS).

[0093] A pixel defining film (PDL) may be disposed on an insulating layer (INS) and / or an anode electrode (AE). The pixel defining film (PDL) may include an opening that at least partially exposes the anode electrode (AE). For example, the pixel defining film (PDL) may surround the edge of the anode electrode (AE).

[0094] In an embodiment, the edge of the pixel defining film (PDL) may protrude beyond the edge of the first partition (SW1). The edge of the pixel defining film (PDL) may protrude beyond the edge of the second partition (SW2). Accordingly, the pixel defining film (PDL) may form a tip structure protruding from the first partition (SW1) and / or the second partition (SW2) together with an insulating layer (INS) and / or a connecting electrode (CNE).

[0095] An emitting layer (EL) may be disposed on an insulating layer (INS), a pixel defining layer (PDL), and / or an anode electrode (AE). The emitting layers (EL) of each subpixel (SP1 to SP3) may be separated from one another. For example, the emitting layers (EL) of each subpixel (SP1 to SP3) may be separated from one another by the tip structure of the pixel defining layer (PDL), the insulating layer (INS), and / or the connecting electrode (CNE). Accordingly, the emitting layers (EL) of each subpixel (SP1 to SP3) may be spaced apart from one another. Each emitting layer (EL) of each subpixel (SP1 to SP3) may generate light of red, green, and blue colors, respectively.

[0096] A cathode electrode (CE) (or a second electrode) may be disposed on the light-emitting layer (EL). The cathode electrode (CE) may be disposed directly on the light-emitting layer (EL). The cathode electrode (CE) may cover the light-emitting layer (EL). The cathode electrodes (CE) of each subpixel (SP1 to SP3) may be separated from one another. The cathode electrodes (CE) of each subpixel (SP1 to SP3) may be spaced apart from one another.

[0097] The cathode electrode (CE) may come into contact with the lower surface (or second surface) of the connecting electrode (CNE). The cathode electrode (CE) may be electrically connected to the connecting electrode (CNE). The cathode electrode (CE) of each of the subpixels (SP1–SP3) may be electrically connected to the connecting line (CL) through the connecting electrode (CNE), the second barrier (SW2), and / or the first barrier (SW1). The cathode electrode (CE) of each of the subpixels (SP1–SP3) may be electrically connected to one another through the connecting line (CL).

[0098] The cathode electrode (CE) may include a transparent conductive material. As an example, the cathode electrode (CE) may include indium gallium zinc oxide (IGZO), but is not necessarily limited thereto.

[0099] The cathode electrode (CE) may include a first electrode layer (CE1) and a second electrode layer (CE2). The first electrode layer (CE1) may be disposed between the light-emitting layer (EL) and the second electrode layer (CE2).

[0100] An encapsulation layer (TFE) may be disposed on the cathode electrode (CE). The encapsulation layer (TFE) can prevent oxygen and / or moisture, etc., from penetrating into the light-emitting layer (EL), etc. The encapsulation layer (TFE) may include a structure in which one or more inorganic films and one or more organic films are alternately stacked.

[0101] The encapsulation layer (TFE) may come into contact with the lower surface (or second surface) of the connecting electrode (CNE). The encapsulation layer (TFE) may come into contact with the first barrier (SW1) and / or the second barrier (SW2). The encapsulation layer (TFE) may come into contact with the side of the inorganic layer (IL). In this way, when the encapsulation layer (TFE) comes into contact with the side of the inorganic layer (IL), the bonding strength of the encapsulation layer (TFE) can be improved, thereby improving moisture permeability. For example, interfacial moisture permeability between the encapsulation layer (TFE) and the first barrier (SW1) and / or the second barrier (SW2) may cause the cathode electrode (CE) to oxidize or the light-emitting layer (EL) to be damaged, which may lead to a decrease in the reliability of the display device. Accordingly, in accordance with the above-described embodiment, by contacting the inorganic layer (IL) disposed on the first partition (SW1) with the sealing layer (TFE), the bonding strength of the sealing layer (TFE) can be improved, thereby improving moisture permeability and improving the reliability of the display device.

[0102] Next, a method for manufacturing a display device according to the above-described embodiment will be described.

[0103] FIGS. 8 to 17 are cross-sectional views of process steps of a method for manufacturing a display device according to an embodiment. FIGS. 8 to 17 are cross-sectional views for explaining the method for manufacturing a display device of FIGS. 1 to 5, and for convenience of explanation, they are briefly illustrated and redundant content is omitted.

[0104] Referring to FIG. 8, a connection line (CL) and a first partition (SW1) are first sequentially formed on a substrate (SUB). The connection line (CL) may be formed entirely on the substrate (SUB). The first partition (SW1) may be formed partially on the connection line (CL). In an embodiment, the connection line (CL) may be formed of titanium (Ti) and the first partition (SW1) may be formed of aluminum (Al), but is not necessarily limited thereto.

[0105] Referring to FIG. 9, an inorganic layer (IL) is subsequently formed on the connecting line (CL) and / or the first partition (SW1). The inorganic layer (IL) may be formed entirely on the substrate (SUB). The inorganic layer (IL) may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlxOy), titanium oxide (TiOx), tantalum oxide (TaxOy), hafnium oxide (HfOx), and zinc oxide (ZnOx), but is not necessarily limited thereto.

[0106] Referring to FIG. 10, the inorganic layer (IL) is then etched. The inorganic layer (IL) may be etched and partially formed on the first bulkhead (SW1). For example, the inorganic layer (IL) may be formed on a first region (A1) (or edge region) of the first bulkhead (SW1). The inorganic layer (IL) may include an opening that overlaps with a second region (A2) (or central region) of the first bulkhead (SW1). The first region (A1) of the first bulkhead (SW1) may surround the second region (A2) of the first bulkhead (SW1).

[0107] Referring to FIG. 11, a second barrier (SW2) is subsequently formed on a connecting line (CL), a first barrier (SW1), and / or an inorganic layer (IL). The second barrier (SW2) may be formed entirely on a substrate (SUB). The second barrier (SW2) may be formed of aluminum (Al), but is not necessarily limited thereto.

[0108] Referring to FIG. 12, a connecting electrode (CNE), an insulating layer (INS), an anode electrode (AE), and / or a pixel defining film (PDL) are subsequently formed sequentially on the second partition (SW2). The connecting electrode (CNE), the insulating layer (INS), and / or the pixel defining film (PDL) may be formed entirely on the substrate (SUB).

[0109] Referring to FIG. 13, the pixel defining film (PDL), insulating layer (INS), connecting electrode (CNE), and / or second barrier (SW2) are subsequently etched. The pixel defining film (PDL), insulating layer (INS), connecting electrode (CNE), and / or second barrier (SW2) may be etched simultaneously in the same process, but are not necessarily limited thereto.

[0110] In an embodiment, the second partition (SW2) may be etched to have a width smaller in the first direction (DR1) than the connecting electrode (CNE). For example, the edge of the second partition (SW2) may be positioned inwardly than the edge of the connecting electrode (CNE). Accordingly, the connecting electrode (CNE) may form a tip structure protruding from the second partition (SW2).

[0111] Referring to FIG. 14, a light-emitting layer (EL) is subsequently formed. The light-emitting layer (EL) can be formed entirely on a substrate (SUB). The light-emitting layer (EL) can be formed on a pixel defining film (PDL), an anode electrode (AE), and / or a connecting line (CL). The light-emitting layer (EL) formed on the pixel defining film (PDL) and the anode electrode (AE) and the light-emitting layer (EL) formed on the connecting line (CL) can be separated from each other. For example, the light-emitting layer (EL) formed on the pixel defining film (PDL) and the anode electrode (AE) and the light-emitting layer (EL) formed on the connecting line (CL) can be separated and spaced apart from each other by the tip structure of the connecting electrode (CNE).

[0112] Referring to FIG. 15, a cathode electrode (CE) is subsequently formed. The cathode electrode (CE) can be formed entirely on a substrate (SUB). The cathode electrode (CE) can be formed on a light-emitting layer (EL). In an embodiment, a first electrode layer (CE1) and a second electrode layer (CE2) of the cathode electrode (CE) can be sequentially formed on the light-emitting layer (EL) and the connecting electrode (CNE).

[0113] Referring to FIG. 16, an encapsulation layer (TFE) is subsequently formed on the cathode electrode (CE). The encapsulation layer (TFE) may be formed entirely on the substrate (SUB). In an embodiment, the encapsulation layer (TFE) may be formed on the lower surface (or second surface) of the connecting electrode (CNE). The encapsulation layer (TFE) may be in contact with the lower surface (or second surface) of the connecting electrode (CNE). The encapsulation layer (TFE) may be formed on the first partition (SW1) and / or the second partition (SW2). The encapsulation layer (TFE) may be in contact with the first partition (SW1) and / or the second partition (SW2). The encapsulation layer (TFE) may be disposed on the side of the inorganic layer (IL). The encapsulation layer (TFE) may be in contact with the side of the inorganic layer (IL). As previously explained, when the encapsulation layer (TFE) comes into contact with the side of the inorganic layer (IL), the bonding strength of the encapsulation layer (TFE) can be enhanced, thereby improving moisture permeability.

[0114] Referring to FIG. 17, the encapsulation layer (TFE) and the cathode electrode (CE) are subsequently partially etched. The cathode electrode (CE) and the encapsulation layer (TFE) may be partially etched, excluding the area formed on the anode electrode (AE) and the light-emitting layer (EL). During the process of etching the encapsulation layer (TFE) and the cathode electrode (CE), the light-emitting layer (EL) formed between the encapsulation layer (TFE) and the connection line (CL) may be removed together. In this case, a space may be formed between the encapsulation layer (TFE) and the connection line (CL).

[0115] FIGS. 18 and 19 are cross-sectional views of the process steps of a method for manufacturing a display device according to an embodiment. FIGS. 18 and 19 are part of a set of cross-sectional views for explaining the method for manufacturing a display device of FIG. 7, and for convenience of explanation, they are briefly illustrated and redundant content is omitted.

[0116] Referring to FIG. 18, a conductive layer (ETL) is formed on a connecting line (CL) and / or a first barrier (SW1), and an inorganic layer (IL) is formed on the conductive layer (ETL). The conductive layer (ETL) can be formed entirely on a substrate (SUB). The inorganic layer (IL) can be formed entirely on a substrate (SUB).

[0117] The conductive layer (ETL) may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), but is not necessarily limited thereto.

[0118] The inorganic layer (IL) may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlxOy), titanium oxide (TiOx), tantalum oxide (TaxOy), hafnium oxide (HfOx), and zinc oxide (ZnOx), but is not necessarily limited thereto.

[0119] Referring to FIG. 19, the conductive layer (ETL) and / or the inorganic layer (IL) are then etched. The conductive layer (ETL) and / or the inorganic layer (IL) may be etched and partially formed on the first barrier (SW1). The conductive layer (ETL) and the inorganic layer (IL) may be etched simultaneously in the same process, but are not necessarily limited thereto.

[0120] A conductive layer (ETL) and / or an inorganic layer (IL) may be formed on a first region (A1) (or edge region) of the first bulkhead (SW1). The conductive layer (ETL) and / or the inorganic layer (IL) may include an opening that overlaps with a second region (A2) (or central region) of the first bulkhead (SW1). The first region (A1) of the first bulkhead (SW1) may surround the second region (A2) of the first bulkhead (SW1).

[0121] Since the subsequent manufacturing process may be substantially the same as the process described with reference to FIGS. 11 to 17, redundant descriptions are omitted.

[0122] The display device (100) according to the above-described embodiment can be applied to various electronic devices. The electronic device according to the embodiment includes the above-described display device (100) and may further include a module or device having other additional functions in addition to the display device (100).

[0123] FIG. 20 is a block diagram of an electronic device according to an embodiment.

[0124] Referring to FIG. 20, an electronic device (10) according to an embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0125] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0126] The memory (13) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (13), an image data signal and / or an input control signal is transmitted to the display module (11), and the display module (11) processes the received signal to output image information through a display screen, i.e., pixels.

[0127] The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power required for the operation of the electronic device (10).

[0128] At least one of each component of the electronic device (10) described above may be included in a display device according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, the display device may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device.

[0129] FIG. 21 is a schematic diagram of an electronic device according to various embodiments.

[0130] Referring to FIG. 21, various electronic devices to which a display device according to the embodiments is applied may include not only image display electronic devices such as a smartphone (10_1a), tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), head-mounted display (10_2b), and smart watch (10_2c), and automotive electronic devices (10_3) including display modules such as a CID (Center Information Display) and room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0131] Although specific embodiments have been described herein, other embodiments and variations may be derived from the foregoing description. Accordingly, the scope of the invention is not limited to these embodiments but extends to the claims set forth below, various obvious variations, and equivalents. Explanation of the symbols

[0132] SUB: Substrate SW1: 1st bulkhead SW2: Second bulkhead IL: Inorganic layer AE: Anode electrode EL: Emissive layer CE: Cathode electrode

Claims

Claim 1 A display device comprising: a first partition on a substrate; an inorganic layer on the first partition; a second partition on the inorganic layer; a first electrode on the second partition; a light-emitting layer on the first electrode; a second electrode on the light-emitting layer; and an encapsulation layer on the second electrode, wherein the encapsulation layer is in contact with the side of the inorganic layer. Claim 2 A display device according to claim 1, wherein the inorganic layer is disposed on the edge region of the first bulkhead and includes an opening that overlaps with the central region of the first bulkhead. Claim 3 In claim 2, the edge region is a display device surrounding the central region. Claim 4 In claim 1, the sealing layer is a display device in contact with the side of the second partition. Claim 5 A display device according to claim 1, further comprising a conductive layer between the first partition and the inorganic layer. Claim 6 In claim 5, a display device in which the width of the conductive layer is the same as the width of the inorganic layer. Claim 7 In claim 5, the conductive layer is disposed on the edge region of the first partition and includes an opening that overlaps with the central region of the first partition. Claim 8 In claim 7, the edge region is a display device surrounding the central region. Claim 9 A display device according to claim 1, further comprising a connection line between the substrate and the first partition. Claim 10 In claim 9, the connection line is a display device electrically connected to the first partition. Claim 11 A display device according to claim 1, further comprising a connecting electrode between the second partition and the first electrode. Claim 12 In claim 11, the connecting electrode is a display device electrically connected to the second partition. Claim 13 A display device according to claim 11, further comprising an insulating layer between the connecting electrode and the first electrode. Claim 14 A display device according to claim 13, wherein the insulating layer is in contact with the first surface of the connecting electrode and the second electrode is in contact with the second surface of the connecting electrode. Claim 15 In claim 14, the above-mentioned sealing layer is a display device in contact with the second surface of the above-mentioned connecting electrode. Claim 16 In claim 13, a display device in which the width of the insulating layer is greater than the width of the second partition. Claim 17 In claim 11, the connecting electrode is a display device that is electrically separated from the first electrode. Claim 18 In claim 11, a display device in which the width of the connecting electrode is greater than the width of the second partition. Claim 19 In claim 11, the second electrode is a display device electrically connected to the connecting electrode. Claim 20 An electronic device comprising a processor; and a display device including pixels, configured to display an image on the pixels according to the control of the processor, wherein the display device comprises a first partition on a substrate; a second partition on the first partition; an inorganic layer between the first partition and the second partition; a first electrode on the second partition; a light-emitting layer on the first electrode; a second electrode on the light-emitting layer; and an encapsulation layer on the second electrode, wherein the encapsulation layer is in contact with the inorganic layer.

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