Display device and electronic device including the same

Abstract

The display device of the present invention comprises a display panel including a first pad, an encapsulation substrate facing the display panel, and an anisotropic conductive adhesive layer having a closed line shape. The encapsulation substrate comprises a glass substrate, at least one insulating layer disposed on one side of the glass substrate, a signal line disposed on the one side of the glass substrate, and a second pad electrically connected to the signal line and corresponding to the first pad. The anisotropic conductive adhesive layer having a closed line shape is disposed between the display panel and the encapsulation substrate, combines the display panel and the encapsulation substrate, and electrically connects the first pad and the second pad. The display panel comprises a semiconductor substrate, a wiring layer disposed on the semiconductor substrate and including the first pad, and a light-emitting element disposed on the wiring layer.

Description

Technology Field

[0001] The present invention relates to a display device and an electronic device including the same, and more specifically, to a display device including a semiconductor substrate and an electronic device including the same. Background Technology

[0002] Electronic devices such as smartphones, laptop computers, navigation systems, and smart televisions that provide video to a user include a display device for displaying video. Additionally, the display device may include wearable devices such as virtual reality (VR) devices, augmented reality (AR) devices, and smartwatches. To provide high-resolution video, the wearable device may include an LEDoS (Light Emitting Diode on Silicon) or OLEDoS (Organic Light Emitting Diode on Silicon) comprising a silicon substrate and a light-emitting element disposed on the silicon substrate.

[0003] In the packaging process of a display device, the display panel and the encapsulation substrate can be bonded by an anisotropic conductive film (ACF) and sealed through a frit. Non-uniform curing may occur as the bonding and sealing processes proceed. Additionally, considering the width of the frit during the sealing process, it may be required to secure a sufficient border area of ​​the display panel. The problem to be solved

[0004] The present invention aims to provide a display device in which the curing performance between the display panel and the encapsulation substrate is improved and the border area is reduced.

[0005] The present invention aims to provide an electronic device comprising the above-described display device. means of solving the problem

[0006] A display device according to one embodiment of the present invention comprises a display panel including a first pad, an encapsulation substrate facing the display panel, and an anisotropic conductive adhesive layer having a closed line shape. The encapsulation substrate comprises a glass substrate, at least one insulating layer disposed on one surface of the glass substrate, a signal line disposed on the one surface of the glass substrate, and a second pad electrically connected to the signal line and corresponding to the first pad. The anisotropic conductive adhesive layer having a closed line shape is disposed between the display panel and the encapsulation substrate, combines the display panel and the encapsulation substrate, and electrically connects the first pad and the second pad. The display panel comprises a semiconductor substrate, a wiring layer disposed on the semiconductor substrate and including the first pad, and a light-emitting element disposed on the wiring layer.

[0007] The second pad may include a plurality of conductive patterns and a plurality of insulating patterns, the plurality of insulating patterns and the plurality of conductive patterns may be alternately stacked, and adjacent conductive patterns among the plurality of conductive patterns may come into contact with each other.

[0008] The second pad may include a first insulating pattern superimposed on the end portion of the signal line, a first conductive pattern electrically connected to the end portion of the signal line, a second insulating pattern superimposed on the first insulating pattern and disposed on the first conductive pattern, a second conductive pattern disposed on the first conductive pattern and electrically connected to the first conductive pattern, a third insulating pattern superimposed on the second insulating pattern and disposed on the second conductive pattern, and a third conductive pattern disposed on the second conductive pattern and electrically connected to the second conductive pattern.

[0009] The above at least one insulating layer comprises a first insulating layer, a second insulating layer, and a third insulating layer, and the second pad may include a first conductive pattern electrically connected to the end of the signal line through a first contact hole penetrating the first insulating layer, a second conductive pattern electrically connected to the first conductive pattern through a second contact hole penetrating the second insulating layer disposed on the first insulating layer, and a third conductive pattern electrically connected to the second conductive pattern through a third contact hole penetrating the third insulating layer disposed on the second insulating layer.

[0010] The maximum thickness of the second pad above may be 4㎛ or more and 7㎛ or less.

[0011] The above anisotropic conductive adhesive layer may include a photocurable resin and conductive balls mixed in the photocurable resin.

[0012] The above photocurable resin may have the characteristic of curing at 100°C or lower.

[0013] The area of ​​the above-mentioned encapsulation substrate may be larger than the area of ​​the above-mentioned semiconductor substrate.

[0014] The above display panel includes a display area where the light-emitting element is placed and a non-display area around the display area, and the width of the non-display area may be 400㎛ or more and less than 600㎛.

[0015] The above display device further includes a filling layer between the display panel and the encapsulation substrate, and the filling layer may be disposed on the inner side of the anisotropic conductive adhesive layer.

[0016] A recess is formed on the lower surface of the above-mentioned encapsulation substrate that corresponds to the above-mentioned display panel and faces the upper surface of the above-mentioned encapsulation substrate, and the filling layer may be disposed in the recess.

[0017] The above display device may not include a frit that combines the display panel and the encapsulation substrate on the inner or outer side of the anisotropic conductive adhesive layer.

[0018] An electronic device according to one embodiment of the present invention comprises a display panel including a first pad, an encapsulation substrate facing the display panel, a timing controller disposed on the encapsulation substrate, and an anisotropic conductive adhesive layer having a closed line shape. The encapsulation substrate comprises a glass substrate, at least one insulating layer disposed on one side of the glass substrate, a signal line disposed on one side of the glass substrate, and a second pad electrically connected to the signal line and corresponding to the first pad. The anisotropic conductive adhesive layer having a closed line shape is disposed between the display panel and the encapsulation substrate, combines the display panel and the encapsulation substrate, and electrically connects the first pad and the second pad. The display panel comprises a semiconductor substrate, a wiring layer disposed on the semiconductor substrate and including the first pad, and a light-emitting element disposed on the wiring layer.

[0019] The electronic device further includes a flexible circuit board electrically connected to the timing controller, and the timing controller and the flexible circuit board may be electrically connected through the wiring of the encapsulation board.

[0020] The electronic device further includes a source driving chip disposed on one side of the glass substrate, and the display panel may further include a third pad and a scan line electrically connected to the third pad. The encapsulation substrate may further include a sub-signal line disposed on one side of the glass substrate and electrically connected to the source driving chip, and a fourth pad electrically connected to the sub-signal line, and the third pad and the fourth pad may be electrically connected through the anisotropic conductive adhesive layer.

[0021] The second pad above includes a plurality of conductive patterns and a plurality of insulating patterns, the plurality of insulating patterns and the plurality of conductive patterns are alternately stacked, and adjacent conductive patterns among the plurality of conductive patterns can come into contact with each other.

[0022] The second pad above includes a first insulating pattern superimposed on the end portion of the signal line, and a first conductive pattern electrically connected to the end portion of the signal line. It may include a second insulating pattern that overlaps with the first insulating pattern and is disposed on the first conductive pattern, a second conductive pattern disposed on the first conductive pattern and electrically connected to the first conductive pattern, a third insulating pattern that overlaps with the second insulating pattern and is disposed on the second conductive pattern, and a third conductive pattern disposed on the second conductive pattern and electrically connected to the second conductive pattern.

[0023] The maximum thickness of the second pad above may be 4㎛ or more and 7㎛ or less.

[0024] The above display panel includes a display area where the light-emitting element is placed and a non-display area around the display area, and the width of the non-display area may be 400㎛ or more and less than 600㎛.

[0025] The above anisotropic conductive adhesive layer may include a photocurable resin and conductive balls mixed in the photocurable resin. Effects of the invention

[0026] According to the present invention, a display panel and an encapsulation substrate can be electrically connected through a closed-line shaped anisotropic conductive adhesive layer. As bonding is performed by the closed-line shaped anisotropic conductive adhesive layer in the pad area, the border area of ​​the display device can be reduced. In addition, the resin of the anisotropic conductive adhesive layer can be cured at a low temperature, thereby preventing uneven curing and improving curing performance.

[0027] In addition, as conductive patterns and insulating patterns are alternately stacked on the pads of the encapsulation substrate, the thickness of the pads can be increased, thereby improving electrical reliability between the display panel and the encapsulation substrate. Accordingly, the bonding reliability of the display device and the electronic device including the display device can be improved. Brief explanation of the drawing

[0028] FIG. 1 is a block diagram of an electronic device according to one embodiment. FIG. 2 is a schematic diagram of an electronic device according to various embodiments. FIG. 3 is an exploded perspective view of an electronic device according to one embodiment. FIG. 4 is a perspective view of a display panel according to one embodiment. FIG. 5 is a schematic cross-sectional view of a display panel according to one embodiment. FIG. 6 is a cross-sectional view of a display panel according to one embodiment. FIG. 7 is a schematic plan view of an electronic device according to one embodiment. FIG. 8 is a schematic cross-sectional view of an electronic device according to one embodiment. FIG. 9a is a planar enlarged view of a pad area according to one embodiment. FIG. 9b is a cross-sectional view of a packaging substrate according to one embodiment. FIG. 9c is a cross-sectional view showing the combined shape of a sealing substrate and a display panel according to one embodiment. Figure 10 is a cross-sectional view of the encapsulation substrate corresponding to III-III' of Figure 7. FIG. 11 is a cross-sectional view of an electronic device corresponding to IV-IV' of FIG. 7. FIG. 12a is a planar enlarged view of a pad area according to another embodiment. FIG. 12b is a cross-sectional view of a packaging substrate according to another embodiment. Specific details for implementing the invention

[0029] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them.

[0030] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. "And / or" includes all one or more combinations that the associated components may define.

[0031] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component, part, region, layer, or part from another component, part, region, layer, or part. For example, without departing from the scope of the present invention, a first component, a first part, a first region, a first layer, or a first part may be named a second component, a second part, a second region, a second layer, or a second part, and similarly, a second component, a second part, a second region, a second layer, or a second part may be named a first component, a first part, a first region, a first layer, or a first part. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0032] Additionally, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0033] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0034] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0035] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0037] The display device according to the embodiment can be applied to various electronic devices. An electronic device according to one embodiment includes the display device described above and may further include a module or device having other additional functions in addition to the display device.

[0038] FIG. 1 is a block diagram of an electronic device (ED) according to one embodiment. Referring to FIG. 1, the electronic device (ED) according to one embodiment may include a display module (DM), a processor (PR), a memory (MR), and a power module (PM).

[0039] The processor (PR) may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0040] The memory (MR) may store data information necessary for the operation of the processor (PR) or the display module (DM). When the processor (PR) executes an application stored in the memory (MR), video data signals and / or input control signals are transmitted to the display module (DM), and the display module (DM) can process the received signals to output video information through a display screen.

[0041] The power module (PM) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power required for the operation of an electronic device (ED).

[0042] At least one of each component of the electronic device (ED) described above may be included within the display device according to the embodiments described above. Additionally, some of the individual modules functionally included within a single module may be included within the display device, while others may be provided separately from the display device. For example, the display device may include a display module (DM), and the processor (PR), memory (MR), and power module (PM) may be provided in the form of other devices within the electronic device (ED) that are not part of the display device.

[0044] FIG. 2 is a schematic diagram of an electronic device according to various embodiments. FIG. 2 illustrates examples of various electronic devices to which a display device according to the embodiments is applied.

[0045] FIG. 2 illustrates examples of electronic devices, including a smartphone (10_1a), a tablet PC (10_1b), a laptop (10_1c), a TV (10_1d), and a desktop monitor (10_1e).

[0046] The smartphone (10_1a) may include an input module, such as a touch sensor, and a communication module in addition to the display module (DM). The smartphone (10_1a) can process information received through the communication module or other input modules and display the information through the display module of the display device.

[0047] In the case of a tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), it also includes a display module and an input module similar to a smartphone (10_1a), and may additionally include a communication module depending on the case.

[0048] FIG. 2 illustrates a case where an electronic device including a display module is applied to a wearable electronic device. The wearable electronic device may be smart glasses (10_2a), a head-mounted display (10_2b), a smart watch (10_2c), etc.

[0049] Smart glasses (10_2a) and a head-mounted display (10_2b) may include a display module that emits a display image and a reflector that reflects the emitted display screen to provide it to the user's eyes, thereby providing a virtual reality or augmented reality screen to the user.

[0050] The smart watch (10_2c) includes a bio-sensor as an input device and can provide bio-information recognized through the bio-sensor to the user through a display module.

[0051] FIG. 2 illustrates a case where an electronic device including a display module is applied to a vehicle. For example, the electronic device (10_3) may be applied to the instrument panel, center fascia, etc. of a vehicle, or may be applied to a Center Information Display (CID) placed on the dashboard of a vehicle or a room mirror display that replaces a side mirror.

[0052] Although not illustrated, electronic devices to which the display device according to the embodiments is applied may include not only devices primarily focused on screen display, such as billboards, electronic display boards, and game consoles, but also various home appliances that display information through display modules, such as refrigerators, washing machines, dryers, air conditioners, and robot vacuum cleaners. Additionally, if the display module has a function of transmitting light, it may be applied to electronic devices such as smart windows or transparent display devices that display both a background and a display image. The types of electronic devices according to the embodiments are not limited to those exemplified above, and various other electronic devices not exemplified may also be applied.

[0054] FIG. 3 is an exploded perspective view of an electronic device (ED) according to one embodiment.

[0055] Referring to FIG. 3, an electronic device (ED) according to one embodiment may include a display panel (DP), an encapsulation board (ES), a timing controller (T-IC), and a flexible circuit board (FPC).

[0056] The display panel (DP) may have a planar shape similar to a rectangle, having one side in the first direction (DR1) and the other side in the second direction (DR2) that intersects the first direction (DR1). The lengths of the one side in the first direction (DR1) and the other side in the second direction (DR2) of the display panel (DP) may differ from each other. The planar shape of the display panel (DP) is not limited to a rectangle and may be formed similarly to other polygons, circles, or ellipses. The display panel (DP) may be spaced apart from the timing controller (T-IC) and the flexible circuit board (FPC).

[0057] The lengths of one side in the first direction (DR1) and the other side in the second direction (DR2) of the encapsulation substrate (ES) may differ from each other. The planar shape of the encapsulation substrate (ES) is not limited to a rectangle and may be formed similarly to other polygons, circles, or ellipses. The encapsulation substrate (ES) may have a planar shape similar to a rectangle having one side in the first direction (DR1) and the other side in the second direction (DR2) that intersects the first direction (DR1). In one embodiment, the length of the other side in the second direction (DR2) of the encapsulation substrate (ES) may be longer than the length of the other side in the second direction (DR2) of the display panel (DP).

[0058] The encapsulation substrate (ES) can electrically connect the display panel (DP), the timing controller (T-IC), and the flexible circuit board (FPC), respectively. The encapsulation substrate (ES) is a substrate placed on the display panel (DP) and can be positioned to face the display panel (DP). The encapsulation substrate (ES) can be electrically connected to a plurality of pads in the pad area of ​​the display panel (DP) through an adhesive member, such as an anisotropic conductive adhesive layer described later. Additionally, the encapsulation substrate (ES) can also be electrically connected to the timing controller (T-IC) and the flexible circuit board (FPC), respectively, through the anisotropic conductive adhesive layer.

[0059] The timing controller (T-IC) can convert signals transmitted from the flexible circuit board (FPC) into driving signals according to timing signals. The timing controller (T-IC) can control the display panel (DP) by transmitting signals to the driving chip of the display panel (DP).

[0060] The flexible printed circuit board (FPC) may be a flexible printed circuit board having a flexible material, and a portion of it may overlap with the encapsulation board (ES). However, the flexible printed circuit board (FPC) is not limited to being spaced apart from the display panel (DP) and may be adhered to the pad area of ​​the display panel (DP).

[0062] FIG. 4 is a perspective view of a display panel (DP) according to one embodiment. FIG. 5 is a schematic cross-sectional view of a display panel (DP) according to one embodiment. FIG. 6 is a cross-sectional view of a display panel (DP) according to one embodiment.

[0063] Referring to FIG. 4, a display panel (DP) according to an embodiment of the present invention includes a display surface (DS) substantially parallel to a plane defined by a first direction (DR1) and a second direction (DR2). An image is displayed through the display surface. The normal direction of the display surface is defined as a third direction (DR3). In this specification, the meaning of "when viewed in a plane" is defined as a state viewed from the third direction (DR3).

[0064] The display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) displays an image, and the non-display area (NDA) does not display an image. The non-display area (NDA) may surround the display area (DA), but is not limited thereto, and the non-display area (NDA) may be placed on one side of the display area (DA).

[0065] A plurality of pixels (PX) may be arranged in a display area (DA). The pixels (PX) may be arranged in a matrix form. Each of the pixels (PX) may include a pixel circuit and a light-emitting element. All pixels (PX) may generate light of the same color. In one embodiment of the present invention, the pixels (PX) may include a plurality of groups that generate light of different colors.

[0066] Referring to FIG. 5, the display panel (DP) may include a circuit board (100), a light-emitting element layer (200), a thin film encapsulation layer (300), and an optical layer (400). As shown in FIG. 7, the display panel (DP) includes a display area (DA) and a non-display area (NDA) around the display area (DA), and the light-emitting element layer (200) may be disposed within the display area (DA).

[0067] The circuit board (100) may include a pixel circuit. The pixel circuit can control the operation of the light-emitting element of the light-emitting element layer (200). The pixel circuit may include at least one transistor. The circuit board (10) may include a CMOS wafer. The CMOS wafer may include a complementarily connected nMOSFET (NMOS) and pMOSFET (PMOS). A plurality of pixel regions are regularly arranged on the CMOS wafer, and a pixel circuit is disposed in each pixel region.

[0068] The light-emitting element layer (200) may include a light-emitting element electrically connected to a pixel circuit. In this embodiment, the light-emitting element may include an organic light-emitting element, but is not necessarily limited thereto. The light-emitting element may generate a first color light, a second color light, and a third color light. The first color light, the second color light, and the third color light may be mixed to form white light. However, it is not limited thereto, and the light-emitting element may generate only the first color light.

[0069] The thin film encapsulation layer (300) can protect the light-emitting element layer (200) from foreign substances such as moisture, oxygen, and dust particles. The thin film encapsulation layer (300) may include an inorganic layer, an organic layer, and a stacked structure of the inorganic layer, but is not necessarily limited thereto. As the thin film encapsulation layer (300) seals the light-emitting element layer (200), the durability and lifespan of the light-emitting element layer (200) can be improved.

[0070] The optical layer (400) may include a color filter. The color filter allows only a specific wavelength range of light generated by the light-emitting element to pass through, and absorbs other wavelength ranges. The optical layer (400) may include a plurality of color filters. The optical layer (400) may include a first color filter that selectively transmits a first color light, a second color filter that selectively transmits a second color light, and a third color filter that selectively transmits a third color light.

[0071] FIG. 6 illustrates a cross-sectional view of the display panel (DP) of FIG. 5 in detail. FIG. 6 may include a light-emitting region (PXA) and a non-light-emitting region (NPXA). Each pixel (PX, see FIG. 4) includes a light-emitting element (LD) and a pixel circuit connected to the light-emitting element (LD).

[0072] The circuit board (100) may be a CMOS (complementary metal oxide semiconductor) circuit board. The circuit board (100) includes a semiconductor substrate (110). The semiconductor substrate (110) may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. A plurality of transistors may be formed on the semiconductor substrate (110) by a semiconductor process.

[0073] Each of the source / drain regions (120) may be a region doped with a dopant. A pair of source / drain regions (120) together with the gate (140) described later may define a transistor. The source / drain regions (120) may become the source of the transistor or the drain of the transistor depending on the signal flow. That is, when one of the source / drain regions (120) is the source region (120), the other may be the drain region (120).

[0074] A wiring layer (110-1) is disposed on a semiconductor substrate (110). The wiring layer (110-1) may include at least one insulating layer (130, 150) and at least one conductive pattern (140, 160). In this embodiment, a wiring layer (110-1) including a plurality of insulating layers (130, 150) and a plurality of conductive patterns (140, 160) is illustrated as an example. The plurality of insulating layers (130, 150) may include inorganic films of the silicon carbon nitride (SiCN) series or the silicon oxide (SiO) series. The plurality of conductive patterns (140, 160) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of these.

[0075] A gate insulating layer (130) and gates (140) are disposed on a semiconductor substrate (110). The gates (140) may include metal. Each of the gates (140) is disposed corresponding to a pair of source / drain regions (120). The gate insulating layer (130) may include insulating patterns disposed corresponding to the gates (140).

[0076] A plurality of intermediate insulating layers (150) are disposed on a semiconductor substrate (110). Contact holes (CH) are defined in the intermediate insulating layers (150). A conductive pattern (160) is disposed in each of the contact holes (CH) of the intermediate insulating layers (150). The conductive pattern (160) disposed on the upper side can be connected to the conductive pattern disposed on the lower side, and the conductive pattern (160) disposed on the lowest side can be directly connected to the source / drain regions (120).

[0077] A reflective conductive pattern (170) is disposed on the semiconductor substrate (110) and penetrates an intermediate insulating layer (150) placed at the top. The reflective conductive pattern (170) can be electrically connected to a first electrode (AE) described later through a contact hole (CH). Thus, the source / drain regions (120) of the transistor can be electrically connected to the first electrode (AE) of the light-emitting element layer (200) through at least one conductive pattern (160) and a reflective conductive pattern (170). The reflective conductive pattern (170) can serve as a reflective layer of the light-emitting element layer (200). The reflective conductive pattern (170) can prevent light generated in the light-emitting element layer (200) from being absorbed by the opaque semiconductor substrate (110). In addition, the reflective conductive pattern (170) can reflect light generated in the light-emitting element layer (200) in a third direction (DR3), thereby improving the light emission efficiency.

[0078] The reflective conductive pattern (170) is not particularly limited as long as it is made of a material that is highly conductive and highly reflective. The reflective conductive pattern (170) may include copper (Cu), tungsten (W), or silver (Ag). The reflective conductive pattern (170) may also include an alloy containing copper (Cu), tungsten (W), or silver (Ag).

[0079] The upper surface of the reflective conductive pattern (170) can define the same plane as the upper surface of the best intermediate insulating layer (150). The reflective conductive pattern (170) can be formed by a chemical / physical polishing process, such as a damascene process.

[0080] The light-emitting element layer (200) may be disposed on the upper surface of the best intermediate insulating layer (150). The light-emitting element (LD) and the pixel defining film (PDL) may be disposed on the upper surface of the best intermediate insulating layer (150). The light-emitting element (LD) may include a first electrode (AE), a light-emitting layer (EL) disposed on the first electrode (AE), and a second electrode (CE). In this embodiment, the first electrode (AE) may be an anode, and the second electrode (CE) may be a cathode.

[0081] The first electrode (AE) may be placed directly on the best intermediate insulating layer (150) and directly on the reflective conductive pattern (170). The first electrode (AE) may be in contact with the upper surface of the best intermediate insulating layer (150) and the upper surface of the reflective conductive pattern (170). The first electrode (AE) may be electrically connected through direct contact with the reflective conductive pattern (170).

[0082] The first electrode (AE) may include a transparent conductive oxide pattern. The transparent conductive oxide pattern may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnOx), indium oxide (In2O3), or aluminum-doped zinc oxide (AZO), which facilitates hole injection. The first electrode (AE) may have a single-layer or multi-layer structure.

[0083] The pixel defining layer (PDL) may be disposed on the best intermediate insulating layer (150). The pixel defining layer (PDL) may be an organic layer. In this embodiment, a single-layer pixel defining layer (PDL) is illustrated as an example but is not limited thereto. An opening (OP) is defined in the pixel defining layer (PDL) that partially exposes the first electrode (AE). In this embodiment, the light-emitting region (PXA) may be defined to correspond to a portion of the first electrode (AE) exposed by the opening (OP).

[0084] A light-emitting layer (EL) is disposed on the first electrode (AE) and the pixel definition film (PDL). A second electrode (CE) is disposed on the light-emitting layer (EL). The light-emitting layer (EL) of the light-emitting elements (LD) may have a single shape, and the second electrode (CE) of the light-emitting elements (LD) may have a single shape. The light-emitting layer (EL) and the second electrode (CE) may overlap in common in the light-emitting region (PXA) and the non-light-emitting region (NPXA).

[0085] A thin film encapsulation layer (300) may be disposed on the light-emitting layer (EL). The thin film encapsulation layer (300) may include a plurality of thin films, although not illustrated, and may include, for example, a sequential stacked structure of an encapsulation inorganic layer, an encapsulation organic layer, and an encapsulation inorganic layer.

[0086] An optical layer (400) may be disposed on a thin film encapsulation layer (300). The optical layer (400) may include a color filter (CF) and a planarization layer (PZL) disposed on the color filter (CF).

[0087] The optical layer (400) may include a plurality of color filters (CF) and may include a first color filter, a second color filter, and a third color filter corresponding to each of the light-emitting regions (PXA). For example, the first color filter transmits the first color light among the first color light, the second color light, and the third color light generated in the light-emitting layer (EL), the second color filter transmits the second color light among the first color light, the second color light, and the third color light generated in the light-emitting layer (EL), and the third color filter transmits the third color light among the first color light, the second color light, and the third color light generated in the light-emitting layer (EL).

[0088] The flattening layer (PZL) may be placed on the color filters (CF). The flattening layer (PZL) may contain an organic material. Although not illustrated, the optical layer (400) may further include a light-blocking pattern.

[0090] FIG. 7 is a schematic plan view of an electronic device (ED) according to one embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of an electronic device (ED) according to one embodiment of the present invention. FIG. 8 is a cross-sectional view of an electronic device (ED) corresponding to I-I' in FIG. 7. Detailed descriptions of configurations identical to those described with reference to FIG. 3 to 6 are omitted.

[0091] Referring to FIGS. 7 and 8, the display device (DD) includes a display panel (DP), an encapsulation substrate (ES) facing the display panel (DP), and an anisotropic conductive adhesive layer (ACL). The electronic device (ED) may further include the display device (DD), a source driver chip (S-IC), a timing controller (T-IC), and a flexible circuit board (FPC).

[0092] The encapsulation substrate (ES) can be electrically connected to the display panel (DP) through an anisotropic conductive adhesive layer (ACL). The encapsulation substrate (ES) can electrically connect the display panel (DP) to the source driver chip (S-IC), timing controller (T-IC), and flexible circuit board (FPC), respectively, through signal lines within the encapsulation substrate (ES). That is, the timing controller (T-IC) and the flexible circuit board (FPC) can be electrically connected through the wiring of the encapsulation substrate (ES). In other words, the display panel (DP) and electronic components can be electrically connected through signal lines placed on one side of the encapsulation substrate (ES). Therefore, signal lines that could not be placed due to the wiring limitations of the display panel (DP) can be additionally placed on the glass substrate (GS) included in the encapsulation substrate (ES), thereby enabling the implementation of high resolution.

[0093] An anisotropic conductive adhesive layer (ACL) may be placed within the non-display area (NDA) of a display panel (DP) to bond the encapsulation substrate (ES) and the display panel (DP). An anisotropic conductive adhesive layer (ACL) may be placed between the display panel (DP) and the encapsulation substrate (ES) to bond the display panel (DP) and the encapsulation substrate (ES). On a planar surface, the anisotropic conductive adhesive layer (ACL) may have a closed-line shape. The anisotropic conductive adhesive layer (ACL) may have a closed-line shape that encloses four sides of the display area (DA) of the display panel (DP).

[0094] In one embodiment, the display panel (DP) may include a pad area (PA1) disposed within a non-display area (NDA). A first pad (PD1) of the display panel (DP) and a second pad (PD2) corresponding to the first pad (PD1) of the encapsulation substrate (ES) may each be disposed within the pad area (PA1). Referring to FIG. 7, the first pad (PD1) refers to a pad included in the display panel (DP), and the second pad (PD2) refers to a pad included in the encapsulation substrate (ES) corresponding to the first pad (PD1). An anisotropic conductive adhesive layer (ACL) is disposed between the first pad (PD1) and the second pad (PD2) to electrically connect the first pad (PD1) and the second pad (PD2). Accordingly, the display panel (DP) and the encapsulation substrate (ES) can be electrically connected.

[0095] In one embodiment, the display panel (DP) may further include a third pad (PD3) that is disposed within a non-display area (NDA) and electrically connected to a source driver chip (S-IC). The third pad (PD3) may be electrically connected to a signal line within the display panel (DP). For example, the third pad (PD3) may be electrically connected to a scan line among a plurality of signal lines within the display panel (DP). The encapsulation substrate (ES) may include a fourth pad (PD4) corresponding to the third pad (PD3). The encapsulation substrate (ES) may further include a sub-signal line (S-SL) electrically connected to the source driver chip (S-IC), and the fourth pad (PD4) may be electrically connected to the sub-signal line (S-SL). The third pad (PD3) and the fourth pad (PD4) may be electrically connected through an anisotropic conductive adhesive layer (ACL), similar to the first pad (PD1) and the second pad (PD2).

[0096] Referring to FIG. 8, the encapsulation substrate (ES) can be electrically connected to the display panel (DP) through an anisotropic conductive adhesive layer (ACL). The timing controller (T-IC) and the flexible circuit board (FPC) can each be placed on the lower surface of the encapsulation substrate (ES).

[0097] In one embodiment, the area of ​​the encapsulation substrate (ES) may be larger than the area of ​​the display panel (DP). That is, the encapsulation substrate (ES) may overlap with the display panel (DP), the timing controller (T-IC), and the flexible circuit board (FPC). The area of ​​the encapsulation substrate (ES) may be larger than the area of ​​the circuit board (100) of the display panel (DP).

[0098] The encapsulation substrate (ES) may include a recess (ES-TP) that corresponds to a display panel (DP) on the lower surface of the encapsulation substrate (ES) and faces the upper surface of the encapsulation substrate (ES). The recess (ES-TP) may be formed by being recessed inwardly into the encapsulation substrate (ES).

[0099] The electronic device (ED) may further include a filling layer (FL) disposed between the display panel (DP) and the encapsulation substrate (ES). The filling layer (FL) may be disposed inside the anisotropic conductive adhesive layer (ACL) and may fill the empty space between the recess (ES-TP) of the encapsulation substrate (ES) and the display panel (DP). That is, the filling layer (FL) may be disposed in the recess (ES-TP). The filling layer (FL) may include silicone gel, epoxy resin, acrylic resin, etc., which have high light transmittance.

[0100] An anisotropic conductive adhesive layer (ACL) can be placed in the pad area of ​​the display panel (DP) and the encapsulation substrate (ES). Accordingly, the anisotropic conductive adhesive layer (ACL) can prevent the fill layer (FL) from flowing out of the outer edge of the display panel (DP). The anisotropic conductive adhesive layer (ACL) can be placed between the encapsulation substrate (ES) and the timing controller (T-IC) to electrically connect the encapsulation substrate (ES) and the timing controller (T-IC). Similarly, the anisotropic conductive adhesive layer (ACL) can also be placed between the encapsulation substrate (ES) and the flexible circuit board (FPC) to electrically connect the encapsulation substrate (ES) and the flexible circuit board (FPC).

[0101] In one embodiment, the electronic device (ED) may not include frit on the inner or outer side of the anisotropic conductive adhesive layer (ACL). Frit may refer to a structure having glass characteristics formed by melt-curing glass in the form of a powder with added additives. As the display panel (DP) and the encapsulation substrate (ES) are bonded with the anisotropic conductive adhesive layer (ACL), the sealing process for curing the frit can be omitted. By omitting the sealing process, the problem of uneven curing caused by ultraviolet rays transmitted to the bonding area during the ultraviolet curing process of the frit can be resolved.

[0102] In one embodiment, the display panel (DP) may include a display area (DA) in which a light-emitting element (LD, see FIG. 6) is placed, and a non-display area (NDA) around the display area (DA). As illustrated in FIG. 8, the width of the non-display area (NDA) may be 400 μm or more and less than 600 μm. In this specification, the area within the non-display area where the circuit board (100) of the display panel (DP) and the encapsulation board (ES) are substantially combined may be referred to as the border area. As described above, since the frit is not included within the electronic device (ED), the border area that had to be considered for the width of the frit can be reduced. Accordingly, the ratio of the display area (DA) within the electronic device (ED) can be expanded, and thus the resolution can be increased.

[0104] FIG. 9a is a planar enlarged view of a pad region (PA1) according to an embodiment of the present invention. FIG. 9b is a cross-sectional view of an encapsulation substrate (ES) according to an embodiment of the present invention. FIG. 9c is a cross-sectional view showing the combined shape of an encapsulation substrate (ES) and a display panel (DP) according to an embodiment of the present invention. FIG. 9b is a cross-sectional view corresponding to II-II' of the encapsulation substrate (ES) of FIG. 9a, and FIG. 9c is a cross-sectional view showing the combined shape of the encapsulation substrate (ES) of FIG. 9b and the display panel (DP) through an anisotropic conductive adhesive layer (ACL, see FIG. 7).

[0105] The encapsulation substrate (ES) within the pad region (PA1) may include a second pad (PD2). The encapsulation substrate (ES) may include a glass substrate (GS), at least one insulating layer (IL) disposed on one side of the glass substrate (GS), signal lines (DL1, DL2, DL3) disposed on one side of the glass substrate (GS), and second pads (PD2) electrically connected to each of the signal lines (DL1, DL2, DL3). For convenience, the second pads described below may be described based on one second pad (PD2).

[0106] In one embodiment, the second pad (PD2) may include a plurality of conductive patterns (CL) and a plurality of insulating patterns (IL). The plurality of insulating patterns (IL) and the plurality of conductive patterns (CL) may be alternately stacked, and adjacent conductive patterns among the plurality of conductive patterns (CL) may come into contact with each other.

[0107] A buffer layer (BF) may be further included on one side of the glass substrate (GS). An end portion (DL-E) of a data line may be disposed on the buffer layer (BF). The second pad (PD2) may include a first insulating pattern (IL1) that overlaps the end portion (DL-E) of the signal line, and a first conductive pattern (CL1) that is electrically connected to the end portion (DL-E) of the signal line. The second pad (PD2) may include a second insulating pattern (IL2) placed on the first conductive pattern (CL1) and overlapping with the first insulating pattern (IL1), a second conductive pattern (CL2) placed on the first conductive pattern (CL1) and electrically connected to the first conductive pattern (CL1), a third insulating pattern (IL3) placed on the second conductive pattern (CL2) and overlapping with the second insulating pattern (IL2), and a third conductive pattern (CL3) placed on the second conductive pattern (CL2) and electrically connected to the second conductive pattern (CL2). As the second pad (PD2) includes a plurality of insulating patterns (IL) and a plurality of conductive patterns (CL), the thickness of the second pad (PD2) may be increased.

[0108] The end portion (DP-DL) of the signal line of the display panel included in the wiring layer (110-1) of the display panel can be connected to the first pad (PD1). The first pad (PD1) can correspond to the second pad (PD2) of the encapsulation substrate (ES), and the first pad (PD1) and the second pad (PD2) can be electrically connected through an anisotropic conductive adhesive layer (ACL). The first pad (PD1) in FIG. 9c may include the same material as the reflective electrode (170) of FIG. 6 and may be placed on the same layer.

[0109] In one embodiment, the anisotropic conductive adhesive layer (ACL) may comprise a photocurable resin (RS) and conductive balls (CB) mixed in the photocurable resin (RS). The photocurable resin (RS) may have the characteristic of not being fully cured after irradiation with ultraviolet light, but being fully cured by additional heat treatment conditions. For example, the photocurable resin (RS) may contain additives such as UV retardant curing agents, such as epoxy resins or acrylic resins, so that curing by ultraviolet light may be delayed. The photocurable resin with delayed curing by ultraviolet light is 60 More than 120 Curing may proceed under the following temperature conditions, and 80℃ or higher 100 Curing can proceed under the following temperature conditions. Compared to thermosetting resin, the photocurable resin (RS) can proceed with heat curing at a relatively low temperature, thereby preventing thermal damage to the circuit board (100).

[0110] In one embodiment, the maximum thickness (TH) of the second pad (PD2) may be 4 μm or more and 7 μm or less. As insulating patterns (IL1, IL2, IL3) are alternately stacked between conductive patterns (CL1, CL2, CL3), the thickness of the second pad (PD2) may be increased. Conductive balls (CB) are in contact between the second pad (PD2) and the first pad (PD1), so that the display panel (DP) and the glass substrate (GS) can be electrically connected. That is, as the thickness of the second pad (PD2) increases, the contact area with the conductive balls (CB) may be increased, and the non-contact of the conductive balls (CB) may be reduced, thereby improving electrical reliability.

[0112] FIG. 10 is a cross-sectional view of the encapsulation substrate (ES) corresponding to III-III' in FIG. 7. FIG. 11 is a cross-sectional view of the electronic device (ED) corresponding to IV-IV' in FIG. 7. FIG. 10 is a cross-sectional view of the encapsulation substrate (ES) that is not a pad area. FIG. 11 is a cross-sectional view of the pad area between the encapsulation substrate (ES) and the flexible circuit board (FPC).

[0113] Referring to FIG. 10, signal lines (DL1, DL2, DL3) may be disposed on a buffer layer (BF). At least one insulating layer (IL) may be disposed on the signal lines (DL1, DL2, DL3). The first insulating layer (IL1) may be an inorganic layer covering the signal lines (DL1, DL2, DL3). The second insulating layer (IL2) disposed on the first insulating layer (IL1) may be an inorganic layer and / or an organic layer and may have a single layer or a multilayer structure. The third insulating layer (IL3) disposed on the second insulating layer (IL2) may be a flattening layer and may be an organic layer.

[0114] FIG. 11 is identical to FIG. 9c except that the electronic component connected to the encapsulation substrate (ES) is a flexible circuit board (FPC). The flexible circuit board (FPC) may include a base layer (F-BS) and bump electrodes (BP) mounted on the base layer (F-BS). The bump electrodes (BP) of the flexible circuit board (FPC) may be electrically connected through a second pad (PD2) and conductive balls (CB) of an anisotropic conductive adhesive layer (ACL).

[0116] FIG. 12a is a planar enlarged view of a pad region (PA10) according to another embodiment, and FIG. 12b is a cross-sectional view of an encapsulation substrate (ES) according to another embodiment. A detailed description of configurations identical to those described with reference to FIG. 9a and 9b is omitted.

[0117] FIG. 12a is identical to FIG. 9 except that a contact hole (CNT) is formed within the insulating layer (IL) in a planar manner. Referring to FIG. 12b, the insulating layer (IL) may include a first insulating layer (IL10), a second insulating layer (IL20) disposed on the first insulating layer (IL10), and a third insulating layer (IL30) disposed on the second insulating layer (IL20). The conductive patterns (CL) of FIG. 12b may include a first conductive pattern (CL10) electrically connected to the end of a signal line through a first contact hole (CNT1) penetrating a first insulating layer (IL10), a second conductive pattern (CL20) electrically connected to the first conductive pattern (CL10) through a second contact hole (CNT2) penetrating a second insulating layer (IL20), and a third conductive pattern (CL30) electrically connected to the second conductive pattern (CL20) through a third contact hole (CNT3) penetrating a third insulating layer (IL30). The second pad (PD20) of FIG. 12b may include the first conductive pattern (CL10), the second conductive pattern (CL20), and the third conductive pattern (CL3). The thickness of the second pad (PD20) of FIG. 12b can be increased by a plurality of insulating patterns (IL) alternately arranged between a plurality of conductive patterns (CL), thereby improving electrical reliability with electronic components.

[0119] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the relevant technical field will understand that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0120] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0121] display panel DP Bag-making board ES glass substrate GS insulating layer IL 1st pad, 2nd pad PD1, PD2 Anisotropic conductive adhesive layer ACL semiconductor substrate 110 Wiring layer 110-1 light-emitting element LD Multiple insulation patterns IL1, IL2, IL3 Multiple challenge patterns CL1, CL2, CL3 Photocurable resin RS Challenge balls CB Timing controller T-IC Flexible circuit board FPC display device DD electronic devices ED

Claims

Claim 1 A display device comprising: a display panel including a first pad; a glass substrate, at least one insulating layer disposed on one side of the glass substrate, a signal line disposed on the one side of the glass substrate, a second pad electrically connected to the signal line and corresponding to the first pad, and facing the display panel; and an anisotropic conductive adhesive layer disposed between the display panel and the encapsulating substrate, coupling the display panel and the encapsulating substrate, electrically connecting the first pad and the second pad, and having a closed line shape (the display panel comprises: a semiconductor substrate; a wiring layer disposed on the semiconductor substrate and including the first pad; and a light-emitting element disposed on the wiring layer. Claim 2 A display device according to claim 1, wherein the second pad comprises a plurality of conductive patterns and a plurality of insulating patterns, the plurality of insulating patterns and the plurality of conductive patterns are alternately stacked, and adjacent conductive patterns among the plurality of conductive patterns are in contact with each other. Claim 3 In claim 1, the second pad A first insulation pattern superimposed on the end of the above signal line; A first conductive pattern electrically connected to the end of the above signal line; A second insulating pattern superimposed on the first insulating pattern and disposed on the first conductive pattern; A second conductive pattern disposed on the first conductive pattern and electrically connected to the first conductive pattern; A third insulating pattern that overlaps with the second insulating pattern and is disposed on the second conductive pattern; and A display device comprising a third conductive pattern disposed on the second conductive pattern and electrically connected to the second conductive pattern. Claim 4 In claim 1, the at least one insulating layer comprises a first insulating layer, a second insulating layer, and a third insulating layer, and the second pad is, A first conductive pattern electrically connected to the end of the signal line through a first contact hole penetrating the first insulating layer; A second conductive pattern electrically connected to the first conductive pattern through a second contact hole penetrating the second insulating layer disposed on the first insulating layer; A third conductive pattern electrically connected to the second conductive pattern through a third contact hole penetrating the third insulating layer disposed on the second insulating layer. second A display device including. Claim 5 A display device according to claim 1, wherein the maximum thickness of the second pad is 4㎛ or more and 7㎛ or less. Claim 6 In claim 1, the anisotropic conductive adhesive layer comprises a photocurable resin and conductive balls mixed in the photocurable resin, forming a display device. Claim 7 In claim 6, the photocurable resin is 120 A display device having the characteristic of hardening below. Claim 8 A display device according to claim 1, wherein the area of ​​the encapsulation substrate is larger than the area of ​​the semiconductor substrate. Claim 9 A display device according to claim 1, wherein the display panel includes a display area where the light-emitting element is disposed and a non-display area around the display area, and the width of the non-display area is 400㎛ or more and less than 600㎛. Claim 10 A display device according to claim 1, wherein a filling layer is further included between the display panel and the encapsulation substrate, and the filling layer is disposed inside the anisotropic conductive adhesive layer. Claim 11 A display device according to claim 10, wherein a recess is formed on the lower surface of the encapsulation substrate corresponding to the display panel and facing the upper surface of the encapsulation substrate, and the filling layer is disposed in the recess. Claim 12 A display device according to claim 1, comprising a frit that combines the display panel and the encapsulation substrate on the inner or outer side of the anisotropic conductive adhesive layer. Claim 13 An electronic device comprising: a display panel including a first pad; a glass substrate, at least one insulating layer disposed on one side of the glass substrate, a signal line disposed on one side of the glass substrate, a second pad electrically connected to the signal line and corresponding to the first pad, and facing the display panel; a timing controller disposed on the encapsulation substrate; and an anisotropic conductive adhesive layer in the shape of a closed line disposed between the display panel and the encapsulation substrate, coupling the display panel and the encapsulation substrate, and electrically connecting the first pad and the second pad, wherein the display panel comprises: a semiconductor substrate; a wiring layer disposed on the semiconductor substrate and including the first pad; and a light-emitting element disposed on the wiring layer. Claim 14 An electronic device according to claim 13, further comprising a flexible circuit board electrically connected to the timing controller, wherein the timing controller and the flexible circuit board are electrically connected through the wiring of the encapsulation board. Claim 15 An electronic device according to claim 13, further comprising a source driving chip disposed on one surface of the glass substrate, wherein the display panel further comprises a third pad and a scan line electrically connected to the third pad, and the encapsulation substrate further comprises a sub-signal line disposed on one surface of the glass substrate and electrically connected to the source driving chip and a fourth pad electrically connected to the sub-signal line, wherein the third pad and the fourth pad are electrically connected through the anisotropic conductive adhesive layer. Claim 16 An electronic device according to claim 13, wherein the second pad comprises a plurality of conductive patterns and a plurality of insulating patterns, the plurality of insulating patterns and the plurality of conductive patterns are alternately stacked, and adjacent conductive patterns among the plurality of conductive patterns are in contact with each other. Claim 17 In claim 13, the second pad is A first insulation pattern superimposed on the end of the above signal line; A first conductive pattern electrically connected to the end of the above signal line; A second insulating pattern superimposed on the first insulating pattern and disposed on the first conductive pattern; A second conductive pattern disposed on the first conductive pattern and electrically connected to the first conductive pattern; A third insulating pattern that overlaps with the second insulating pattern and is disposed on the second conductive pattern; and An electronic device comprising a third conductive pattern disposed on the second conductive pattern and electrically connected to the second conductive pattern. Claim 18 An electronic device according to claim 13, wherein the maximum thickness of the second pad is 4㎛ or more and 7㎛ or less. Claim 19 An electronic device according to claim 13, wherein the display panel comprises a display area where the light-emitting element is disposed and a non-display area surrounding the display area, and the width of the non-display area is 400㎛ or more and less than 600㎛. Claim 20 In claim 13, the anisotropic conductive adhesive layer comprises a photocurable resin and conductive balls mixed in the photocurable resin, in an electronic device.

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