Semiconductor memory device and electronic system including the same

Abstract

The present disclosure may provide a semiconductor memory device with improved electrical characteristics and reliability. The semiconductor memory device comprises a cell bottom insulating film including a cell array region and an extension region, a plurality of gate electrodes stacked spaced apart from each other on the cell bottom insulating film, a channel structure disposed on the cell array region and penetrating the plurality of gate electrodes, a word line contact disposed on the extension region and penetrating some of the gate electrodes of the plurality of gate electrodes, a gate separation trench penetrating the plurality of gate electrodes and extending in a first horizontal direction, an air gap disposed between the plurality of gate electrodes and within the gate separation trench, an opening connected to the gate separation trench, a source plate structure disposed on one end of the channel structure and extending in a second horizontal direction intersecting the first horizontal direction, and a cell top insulating film disposed on the source plate structure and covering the opening, wherein the air gap may be disposed on the cell array region and the extension region.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor memory device and an electronic system including the same. Background Technology

[0002] In electronic systems requiring data storage, there is a demand for semiconductor memory devices capable of storing high-capacity data. Accordingly, methods to increase the data storage capacity of semiconductor memory devices are being studied. For example, as one method to increase the data storage capacity of semiconductor memory devices, a semiconductor memory device comprising memory cells arranged in three dimensions instead of memory cells arranged in two dimensions is being proposed. The problem to be solved

[0003] The problem that the present disclosure aims to solve is to provide a semiconductor memory device with improved electrical characteristics and reliability.

[0004] The problem that the present disclosure aims to solve is to provide an electronic system with improved electrical characteristics and reliability.

[0005] The problem that the present disclosure aims to solve is to provide a method for manufacturing a semiconductor memory device with improved electrical characteristics and reliability. means of solving the problem

[0006] According to some embodiments of the present disclosure for solving the above technical problem, a semiconductor memory device comprises a cell bottom insulating film including a cell array region and an extension region, a plurality of gate electrodes stacked spaced apart from each other on the cell bottom insulating film, a channel structure disposed on the cell array region and penetrating the plurality of gate electrodes, a word line contact disposed on the extension region and penetrating some of the gate electrodes of the plurality of gate electrodes, a gate separation trench penetrating the plurality of gate electrodes and extending in a first horizontal direction, an air gap disposed between the plurality of gate electrodes and within the gate separation trench, an opening connected to the gate separation trench, a source plate structure disposed on one end of the channel structure and extending in a second horizontal direction intersecting the first horizontal direction, and a cell top insulating film disposed on the source plate structure and covering the opening, wherein the air gap may be disposed on the cell array region and the extension region.

[0007] According to some embodiments of the present disclosure for solving the above technical problem, a semiconductor memory device comprises a cell bottom insulating film including a cell array region and an extension region, a barrier film disposed on the cell bottom insulating film, a plurality of gate electrodes stacked spaced apart from each other on the barrier film, a channel structure disposed on the cell array region and penetrating the plurality of gate electrodes, a word line contact disposed on the extension region and connected to one of the gate electrodes, a gate separation trench penetrating the plurality of gate electrodes and extending in a first horizontal direction, an air gap disposed in at least a portion between the plurality of gate electrodes and within the gate separation trench, a source plate structure disposed on one end of the channel structure and extending in a second horizontal direction intersecting the first horizontal direction and including an opening connected to the gate separation trench, and a cell top insulating film disposed on the source plate structure and covering the opening, wherein the air gap may be disposed on the cell array region and the extension region.

[0008] According to some embodiments of the present disclosure for solving the above other technical problems, an electronic system comprises a semiconductor memory device including a main substrate, a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure on the main substrate, and a controller electrically connected to the semiconductor memory device on the main substrate, wherein the cell structure comprises a cell lower insulating film including a cell array region and an extension region, a barrier film disposed on the cell lower insulating film, a plurality of gate electrodes stacked spaced apart from each other on the barrier film, a channel structure disposed on the cell array region and penetrating the plurality of gate electrodes, a word line contact disposed on the extension region and connected to one of the plurality of gate electrodes, a gate separation trench penetrating the plurality of gate electrodes and extending in a first horizontal direction, an air gap disposed in at least a portion between the plurality of gate electrodes and within the gate separation trench, a source plate structure disposed on one end of the channel structure and extending in a second horizontal direction intersecting the first horizontal direction and including an opening connected to the gate separation trench, and a cell upper insulating film disposed on the source plate structure and covering the opening, wherein the air gap is disposed on the cell array region and the extension region It can be deployed.

[0009] According to some embodiments of the present disclosure for solving the above-mentioned additional technical problem, a method for manufacturing a semiconductor memory device may include the steps of: forming a mold structure, a channel structure, and a gate isolation structure, each comprising a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on a substrate; forming a barrier film extending along the lower surface of the mold structure, the lower surface of the channel structure, and the lower surface of the gate isolation structure; forming a cell lower insulating layer on the lower surface of the barrier film; coupling a peripheral circuit structure on the lower surface of the cell lower insulating layer; removing the substrate and forming a source plate structure; removing a portion of the source plate structure to form an opening, wherein the opening exposes the upper surface of the gate isolation structure; removing the gate isolation structure and forming a gate isolation trench; removing at least a portion of the plurality of mold insulating layers; and forming a cell upper insulating layer on the source plate structure.

[0010] According to some embodiments, the step of removing at least a portion of a plurality of mold insulating layers may include the step of removing at least a portion of a plurality of mold insulating layers by performing an etching process through a gate separation trench.

[0011] According to some embodiments, the etchant used in the etching process may have an etching selectivity ratio for a plurality of mold insulating layers and barrier films.

[0012] According to some embodiments, the step of forming a channel structure may include forming a channel hole penetrating a mold structure, forming a first high dielectric constant insulating film within the channel hole, and forming an information storage film and a semiconductor pattern within the first high dielectric constant insulating film.

[0013] According to some embodiments, prior to the step of forming a barrier film, the method further includes the step of removing a portion of the gate isolation structure, and the lower surface of the gate isolation structure may be positioned at a vertical level higher than the lower surface of the mold structure.

[0014] According to some embodiments, the step of forming a source plate structure may include removing a substrate to expose one end of a channel structure and one end of a gate isolation structure, removing one end of a channel structure to expose a semiconductor pattern of the channel structure, forming a semiconductor layer covering the exposed semiconductor pattern and the exposed end of a gate isolation structure, and forming a conductive layer on the semiconductor layer.

[0015] According to some embodiments, before forming a barrier film, the method further comprises the step of forming a support structure penetrating a mold structure, and the step of forming the support structure may include the step of forming a support structure hole penetrating the mold structure, the step of forming a second high dielectric constant insulating film within the support structure hole, and the step of forming a support structure within the second high dielectric constant insulating film.

[0016] According to some embodiments, the upper insulating layer of the cell can cover the opening of the source plate structure.

[0017] According to some embodiments, the upper surface of the channel structure may be positioned at the same vertical level as the upper surface of the gate separation structure.

[0018] According to some embodiments, the upper surface of the channel structure may be positioned at a vertical level higher than the upper surface of the gate separation structure. Effects of the invention

[0019] According to some embodiments of the present disclosure, by placing an air gap between a plurality of gate electrodes, the electrical characteristics and reliability of a semiconductor memory device can be improved.

[0020] According to some embodiments of the present disclosure, by placing an air gap over the cell array region and the extension region, the electrical characteristics and reliability of the semiconductor memory device can be improved. Brief explanation of the drawing

[0021] FIG. 1 is an exemplary plan view for illustrating a semiconductor memory device according to some embodiments of the present disclosure. Figure 2 is a cross-sectional view taken along line AA of Figure 1. Figure 3 is a cross-sectional view taken along the BB line and CC line of Figure 1. Figures 4 and 5 are enlarged views to illustrate the Q1 region of Figure 1. Figures 6 to 8 are enlarged views to explain the Q2 region of Figure 1. Figure 9 is an enlarged view to explain the Q3 region of Figure 2. FIGS. 10 and FIGS. 11 are drawings for illustrating a semiconductor memory device according to some embodiments of the present disclosure. FIGS. 12 and FIGS. 13 are drawings for illustrating a semiconductor memory device according to some embodiments of the present disclosure. FIG. 14 is a drawing for illustrating a semiconductor memory device according to some embodiments of the present disclosure. FIGS. 15 and 16 are drawings for illustrating a semiconductor memory device according to some embodiments of the present disclosure. FIG. 17 is a drawing for illustrating a semiconductor memory device according to some embodiments of the present disclosure. FIGS. 18 to 33 are drawings for explaining a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure. FIGS. 34 and FIGS. 35 are drawings for illustrating a method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure. FIGS. 36 and 37 are drawings for illustrating a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure. FIG. 38 is an exemplary block diagram for illustrating an electronic system according to some embodiments of the present disclosure. FIG. 39 is an exemplary perspective view for illustrating an electronic system according to some embodiments of the present disclosure. FIG. 40 is a schematic cross-sectional view cut along the VV line of FIG. 39. Specific details for implementing the invention

[0022] In this disclosure, the terms upper, lower, upper surface, and lower surface are for convenience of explanation and are not limited thereto. The upper, lower, upper surface, and lower surface are described based on what is shown in the drawings, and the terms referring to the vertical relationship may change when the drawings are rotated vertically.

[0023] A semiconductor device and a method for manufacturing the same according to some embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0024] FIG. 1 is an exemplary plan view for illustrating a semiconductor memory device according to some embodiments of the present disclosure. FIG. 2 is a cross-sectional view taken along line AA of FIG. 1. FIG. 3 is a cross-sectional view taken along lines BB and CC of FIG. 1. FIG. 4 and FIG. 5 are enlarged views for illustrating region Q1 of FIG. 1. FIG. 6 through 8 are enlarged views for illustrating region Q2 of FIG. 1. FIG. 9 is an enlarged view for illustrating region Q3 of FIG. 2.

[0025] Referring to FIGS. 1 through 9, a semiconductor memory device according to some embodiments may include a cell structure (CELL) and a peripheral circuit structure (PERI).

[0026] The cell structure (CELL) may include a plurality of gate electrodes (120), an air gap (AG), a gate separation trench (WCT), a source plate structure (105), an upper cell insulating film (180), a channel structure (CH), a bit line contact (136), a bit line (BL), a cell via (134), a barrier film (150), a support structure (160), a word line contact (170), a first bonding pad (195), and a lower cell insulating film (190).

[0027] The cell structure (CELL) may include a cell array region (CAR) and an extension region (EXT). For example, the cell bottom insulating film (190) may include a cell array region (CAR) and an extension region (EXT). The cell array region (CAR) is an area where the channel structure (CH) is placed, and the extension region (EXT) may be an area where the word line contact (170) is placed.

[0028] A plurality of gate electrodes (120) may be disposed on a cell array region (CAR) and an extension region (EXT). A plurality of gate electrodes (120) may be disposed spaced apart in a third direction (D3) on a cell bottom insulating film (190). Each of the plurality of gate electrodes (120) may be disposed spaced apart from each other in the third direction (D3). An air gap (AG) may be disposed between the plurality of gate electrodes (120). Each of the plurality of gate electrodes (120) may extend in a first direction (D1) and a second direction (D2). Each of the plurality of gate electrodes (120) may have a structure that extends in a direction parallel to the upper surface of a peripheral circuit board (200).

[0029] The first direction (D1) and the second direction (D2) may be directions parallel to the upper surface of the peripheral circuit board (200). The third direction (D3) may be a direction perpendicular to each of the first direction (D1) and the second direction (D2). The third direction (D3) may be a direction perpendicular to the upper surface of the peripheral circuit board (200). In some embodiments, the first direction (D1) and the second direction (D2) may be referred to as the first horizontal direction and the second horizontal direction, respectively, and the third direction (D3) may be referred to as the vertical direction.

[0030] In some embodiments, some of the plurality of gate electrodes (120) may be provided as a Ground Select Line (GSL) of a semiconductor memory device. Other of the plurality of gate electrodes (120) may be provided as a String Select Line (SSL) of a semiconductor memory device. For example, among the plurality of gate electrodes (120), a gate electrode (120) adjacent to a source plate structure (105) may be provided as a Ground Select Line (GSL). Among the plurality of gate electrodes (120), a gate electrode (120) adjacent to a bit line (BL) may be provided as a String Select Line (SSL). However, the present disclosure is not limited thereto. The arrangement and number of Ground Select Lines (GSL) and String Select Lines (SSL) may vary.

[0031] In some embodiments, some of the gate electrodes (120) among the plurality of gate electrodes (120) may be used as erase control lines (ECL) of a semiconductor memory device. The erase control lines (ECL) may be used as gate electrodes of erase transistors. The erase transistors may perform erase operations of the plurality of memory cell transistors by generating gate-induced drain leakage (GIDL).

[0032] In some embodiments, the gate electrode (120) may include an electrode barrier layer (122) and an electrode filling layer (124). The electrode barrier layer (122) may be disposed along the outer surface of the gate electrode (120). For example, the electrode barrier layer (122) may be disposed on an air gap (AG) and may be in contact with a channel structure (CH). The electrode filling layer (124) may fill the internal space of the electrode barrier layer (122).

[0033] The electrode barrier layer (122) may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and a two-dimensional (2D) material.

[0034] The electrode filling layer (124) may include, for example, at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn) and molybdenum (Mo).

[0035] A channel structure (CH) may be disposed on a cell bottom insulating film (190). The channel structure (CH) may penetrate a plurality of gate electrodes (120) and extend in a third direction (D3). The channel structure (CH) may intersect with a plurality of gate electrodes (120). The channel structure (CH) may be disposed within a channel hole extending in the third direction (D3). The channel structure (CH) may have a pillar shape (e.g., a cylinder shape) extending in the third direction (D3).

[0036] In some embodiments, due to the high aspect ratio of the stacked plurality of gate electrodes (120), the cross-section of the channel structure (CH) may have a slanted side such that the width becomes narrower as it approaches the source plate structure (105). However, the present disclosure is not limited thereto.

[0037] Referring to FIGS. 2 and FIGS. 4, the channel structure (CH) may include an information storage film (140), a semiconductor pattern (148), and a filling pattern (149).

[0038] The semiconductor pattern (148) may extend in a third direction (D3) and penetrate a plurality of gate electrodes (120). One end of the semiconductor pattern (148) may penetrate the lower surface of the source plate structure (105). One end of the semiconductor pattern (148) may be disposed within the source plate structure (105). The semiconductor pattern (148) may be connected to the semiconductor layer (102) of the source plate structure (105). Although the semiconductor pattern (148) is illustrated as having a cup shape, the present disclosure is not limited thereto. The semiconductor pattern (148) may have various shapes, such as a cylindrical shape, a rectangular shape, or a solid filler shape. The semiconductor pattern (148) may include semiconductor materials such as, for example, single-crystal silicon, polycrystalline silicon, organic semiconductors, and carbon nanostructures, but the present disclosure is not limited thereto.

[0039] The information storage film (140) may be interposed between the semiconductor pattern (148) and the gate electrode (120) and between the semiconductor pattern (148) and the air gap (AG). For example, the information storage film (140) may extend along the outer surface of the semiconductor pattern (148). The information storage film (140) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0040] In some embodiments, channel structures (CH) may be arranged in a zigzag shape from a planar perspective. For example, channel structures (CH) may be arranged staggered with respect to each other in a first direction (D1) and a second direction (D2). Channel structures (CH) arranged in a zigzag shape can further improve the integration density of the semiconductor memory device. In some embodiments, channel structures (CH) may be arranged in a honeycomb shape.

[0041] In some embodiments, the information storage film (140) may be formed as a multilayer film. The information storage film (140) may include a tunnel insulating film (142), a charge storage film (144), and a blocking insulating film (146) that are stacked sequentially on the outer surface of the semiconductor pattern (148).

[0042] The tunnel insulating film (142) may include, for example, silicon oxide or a high dielectric constant material having a dielectric constant higher than silicon oxide (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2)). The charge storage film (144) may include, for example, silicon nitride. The blocking insulating film (146) may include, for example, silicon oxide or a high dielectric constant material having a dielectric constant higher than silicon oxide (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2)).

[0043] In some embodiments, the channel structure (CH) may further include a filling pattern (149). The filling pattern (149) may be formed to fill the interior of a cup-shaped semiconductor pattern (148). The filling pattern (149) may include an insulating material, for example, silicon oxide, but the present disclosure is not limited thereto.

[0044] Referring to FIG. 5, in some embodiments, the channel structure (CH) may further include a first high dielectric constant insulating film (HK1). The first high dielectric constant insulating film (HK1) may be disposed on the outer surface of the information storage film (140). The first high dielectric constant insulating film (HK1) may define the outer surface of the channel structure (CH). For example, the first high dielectric constant insulating film (HK1) may surround the information storage film (140). The first high dielectric constant insulating film (HK1) may be disposed between the gate electrode (120) and the information storage film (140) and between the air gap (AG) and the information storage film (140).

[0045] Referring again to FIGS. 1 through 9, a gate separation trench (WCT) may be disposed on a cell bottom insulating film (190). For example, the gate separation trench (WCT) may be disposed on a second protrusion (190_PR) of the cell bottom insulating film (190). The gate separation trench (WCT) may extend in a third direction (D3) and penetrate a plurality of gate electrodes (120). For example, the gate separation trench (WCT) may extend in a first direction (D1) and a third direction (D3) to separate a plurality of gate electrodes (120). One end of the gate separation trench (WCT) may be disposed on a source plate structure (105).

[0046] As shown in FIG. 1, the gate isolation trench (WCT) can be extended in a first direction (D1) and placed on the cell array region (CAR) and the extension region (EXT). The gate isolation trench (WCT) can define a cell block (BLK). For example, a cell block (BLK) can be defined between adjacent gate isolation trenches (WCT) in a second direction (D2). The definition of the gate isolation trench (WCT) is described in detail in FIG. 30 and FIG. 31.

[0047] An air gap (AG) may be placed on the cell array region (CAR) and extension region (EXT) of the cell bottom insulating film (190). An air gap (AG) may be placed on the barrier film (150). An air gap (AG) may be placed between each of the plurality of gate electrodes (120), between the gate electrode (120) and the barrier film (150), and between the gate electrode (120) and the source plate structure (105). An air gap (AG) may be placed inside the gate separation trench (WCT). Each of the plurality of gate electrodes (120) may be spaced apart from each other in a third direction (D3) by the air gap (AG). The air gap (AG) may be referred to, for example, as an empty space, a cavity, etc.

[0048] In a semiconductor memory device according to some embodiments of the present disclosure, an air gap (AG) may be disposed between a plurality of gate electrodes (120). For example, the air gap (AG) may be disposed between a plurality of gate electrodes (120) on a cell array region (CAR) and an extension region (EXT). By disposing of an air gap (AG) with a dielectric constant lower than that of silicon oxide between the plurality of gate electrodes (120), the RC Delay and read time of the semiconductor memory device may be improved. Additionally, by disposing of an air gap (AG) in both the cell array region (CAR) and the extension region (EXT), the capacitance of the gate electrodes (120) may be improved. That is, the electrical characteristics of the semiconductor memory device may be improved.

[0049] The source plate structure (105) may be placed on the cell array region (CAR) and the extension region (EXT). The source plate structure (105) may be placed on one end of the channel structure (CH) on the cell array region (CAR). The source plate structure (105) may extend in a first direction (D1) and a second direction (D2). The source plate structure (105) may be connected to a gate isolation trench (WCT).

[0050] The source plate structure (105) may include a plurality of layers. For example, the source plate structure (105) may include a semiconductor layer (102) and a conductive layer (104). The semiconductor layer (102) may be in contact with one end of the channel structure (CH). For example, the semiconductor layer (102) may be connected to a semiconductor pattern (148) of the channel structure (CH). The semiconductor layer (102) may be in contact with one end of the dummy support structure (160). The conductive layer (104) may extend along the profile of the upper surface of the semiconductor layer (102). Although the source plate structure (105) has been described as including a plurality of layers, the present disclosure is not limited thereto. For example, the source plate structure (105) may be composed of a single layer.

[0051] The cell upper insulating film (180) may be placed on the source plate structure (105). The cell upper insulating film (180) may cover the source plate structure (105). For example, the cell upper insulating film (180) may cover the opening (OP) of the source plate structure (105) to be described later. By the cell upper insulating film (180) covering the opening (OP) of the source plate structure (105), the air gap (AG) placed between the plurality of gate electrodes (120) and within the gate isolation trench (WCT) may be isolated from the outside.

[0052] Referring to FIG. 6, the source plate structure (105) may include an opening (OP). The opening (OP) of the source plate structure (105) may be connected to a gate isolation trench (WCT). The opening (OP) of the source plate structure (105) may be defined by a first portion (P1). The source plate structure (105) may include a first side (105_SS1) and a second side (105_SS2). The first side (105_SS1) may face the second side (105_SS2) in a second direction (D2) (e.g., a second horizontal direction).

[0053] Each of the first side (105_SS1) and the second side (105_SS2) may include a first part (P1) and a second part (P2). For convenience of explanation, the first side (105_SS1) will be described in detail. The first part (P1) of the first side (105_SS1) may have a first slope, and the second part (P2) may have a second slope different from the first slope. The width of the opening (OP) in the second direction (D2) may decrease as it moves away from the cell upper insulating film (180). For example, the first part (P1) of the first side (105_SS1) may have a slope that causes the width of the opening (OP) in the second direction (D2) to decrease. On the other hand, the width of the gate separation trench (WCT) in the second direction (D2) may increase as it moves away from the cell upper insulating film (180). The second part (P2) of the first side (105_SS1) may have a slope in which the width increases in the first direction (D2) of the gate separation trench (WCT).

[0054] Although the first portion (P1) and the second portion (P2) of the first side (105_SS1) are depicted as being connected on the semiconductor layer (102), the present disclosure is not limited thereto. For example, the first portion (P1) and the second portion (P2) of the first side (105_SS1) may be connected on the conductive layer (104).

[0055] The cell upper insulating film (180) may include a first protrusion (180_PR). The first protrusion (180_PR) may be placed on an opening (OP) of the source plate structure (105). The first protrusion (180_PR) may fill at least a portion of the opening (OP). The first protrusion (180_PR) may overlap with the source plate structure (105) in a first direction (D1) and a second direction (D2).

[0056] The lower surface of the first protrusion (180_PR) may come into contact with the air gap (AG). The lower surface (180_BS) of the first protrusion (180_PR) may include a curved surface. In one embodiment, the lower surface (180_BS) of the first protrusion (180_PR) may include a concave curved surface as shown in FIG. 6. In another embodiment, the lower surface (180_BS) of the first protrusion (180_PR) may include a convex curved surface as shown in FIG. 7. In yet another embodiment, the lower surface (180_BS) of the first protrusion (180_PR) may include a flat plane as shown in FIG. 8.

[0057] Although the lower surface (180_BS) of the first protrusion (180_PR) is depicted as being positioned on the first portion (P1) of the first side (105_SS1), the present disclosure is not limited thereto. For example, the first protrusion (180_PR) may be protruded such that the lower surface (180_BS) of the first protrusion (180_PR) is positioned on the second portion (P2) of the first side (105_SS1).

[0058] The semiconductor layer (102) may include a semiconductor material. The semiconductor layer (102) may include, for example, polysilicon (Si). The conductive layer (104) may include a metal. The conductive layer (104) may include, for example, any one of tungsten (W), copper (Cu), aluminum (Al), and cobalt (Co). However, the present disclosure is not limited thereto.

[0059] Referring again to FIGS. 1 to 9, the cell bottom insulating film (190) may be disposed on the other end of the channel structure (CH). A barrier film (150) may be disposed on the cell bottom insulating film (190). For example, a barrier film (150) may be disposed between the cell bottom insulating film (190) and the air gap (AG).

[0060] The cell bottom insulating film (190) may include a plate portion (190_PL) and a second protrusion (190_PR). The plate portion (190_PL) may extend in a first direction (D1) and a second direction (D2). The second protrusion (190_PR) may protrude from the plate portion (190_PL) toward the cell top insulating film (180) in a third direction (D3). The distance from the lower surface of the cell bottom insulating film (190) to the upper surface of the second protrusion (190_PR) may be greater than the distance from the lower surface of the cell bottom insulating film (190) to the lower surface of the channel structure (CH). The second protrusion (190_PR) may overlap with the gate separation trench (WCT) in the third direction (D3).

[0061] A barrier film (150) may be placed on the cell bottom insulating film (190). The barrier film (150) may extend along the upper surface of the cell bottom insulating film (190). For example, the barrier film (150) may extend along the upper surface of the plate portion (190_PL) and the upper surface and side profile of the second protrusion (190_PR). Due to the barrier film (150), the cell bottom insulating film (190) may not come into contact with the air gap (AG).

[0062] The barrier film (150) may include a material having an etching selectivity with respect to silicon oxide. For example, the barrier film (150) may include an insulating film such as aluminum oxide. In some embodiments, the barrier film (150) may include the same material as the first high dielectric constant insulating film (HK1). However, the present disclosure is not limited thereto. For example, the barrier film (150) may include a material having an etching selectivity with respect to silicon oxide, such as silicon nitride.

[0063] Each of the cell lower insulating film (180) and the cell upper insulating film (190) may comprise, for example, at least one of silicon oxide, silicon oxynitride, and a low-dielectric (low-k) material having a dielectric constant lower than that of silicon oxide, but the present disclosure is not limited thereto.

[0064] The string separation structure (152) can penetrate some of the gate electrodes (120) among the plurality of gate electrodes (120). For example, the string separation structure (152) can penetrate two gate electrodes (120) positioned at the bottom among the plurality of gate electrodes (120). Although the string separation structure (152) is illustrated as penetrating two gate electrodes (120), the present disclosure is not limited thereto. For example, the string separation structure (152) can penetrate four gate electrodes (120) or more than four gate electrodes (120).

[0065] A channel pad (132) may be placed on a channel structure (CH). The channel pad (132) may be placed on the lower part of the channel structure (CH) and electrically connected to a semiconductor pattern (148). A bit line contact (136) may be placed on the channel pad (132). The bit line contact (136) may be placed within a cell lower insulating film (190). The cell lower insulating film (190) may surround the bit line contact (136). The bit line contact (136) may penetrate a barrier film (150) and be connected to the channel pad (132).

[0066] The channel pad (132) may comprise, for example, impurity-doped polysilicon, but the present disclosure is not limited thereto. The bit line contact (136) may comprise, for example, a conductive material such as tungsten (W), copper (Cu), aluminum (Al), or molybdenum (Mo).

[0067] A bit line (BL) can be placed within a cell bottom insulating film (190). The cell bottom insulating film (190) can surround the bit line (BL). The bit line (BL) can be extended in a second direction (D2). The bit line (BL) can be connected to a channel pad (132) through a bit line contact (136). A cell via (138) can be placed on the bit line (BL). The cell via (138) can connect the bit line (BL) to a first bonding pad (195). The first bonding pad (195) can be placed on the lower surface of the cell bottom insulating film (190).

[0068] Some of the gate electrodes (120) among the plurality of gate electrodes (120) may be arranged in a stepped shape. For example, among the plurality of gate electrodes (120), gate electrodes (120_1, 120_2) provided as a String Select Line (SSL) may be arranged in a stepped shape. In some embodiments, the gate electrodes (120_1, 120_2) may have a stepped shape that is symmetric in terms of cross-sectional area. For example, the shape of the gate electrodes (120_1, 120_2) may have a stepped structure that is symmetric with respect to an imaginary line extending in a third direction (D3). However, the present disclosure is not limited thereto. For example, the shape of the gate electrodes (120_1, 120_2) may include a single stepped shape.

[0069] A cell string contact (176) may be disposed on the gate electrodes (120_1, 120_2). The cell string contact (176) may be connected to the gate electrodes (120_1, 120_2) by penetrating the barrier film (150). A portion of the cell string contact (176) may be surrounded by an air gap (AG). The cell string contact (176) may be connected to a cell wiring structure (182). The cell wiring structure (182) may be disposed within the cell bottom insulating film (190).

[0070] A word line contact (170) may be placed on an extended region (EXT). The word line contact (170) may extend in a third direction (D3). The word line contact (170) may be connected to one of a plurality of gate electrodes (120). The word line contact (170) may penetrate the gate electrodes (120) placed between the connected gate electrode (120) and the cell bottom insulating film (190). A word line via (174) may be placed on the word line contact (170). The word line via (174) may be connected to a first bonding pad (195).

[0071] The contact spacer (172) may surround the word line contact (170). For example, the contact spacer (172) may be placed on the outer surface of the word line contact (170). The contact spacer (172) may not be placed on the upper surface of the word line contact (170). For example, the contact spacer (172) may be placed between the side of the word line contact (170) and the gate electrode (120) and between the side of the word line contact (170) and the air gap (AG), and may not be placed between the upper surface of the word line contact (170) and the gate electrode (120). The word line contact (170) and the gate electrode (120) may be separated in a first direction (D1) and a second direction (D2) by the contact spacer (172).

[0072] In some embodiments, the semiconductor memory device may further include a second high dielectric constant insulating film (HK2) surrounding the word line contact (170). The second high dielectric constant insulating film (HK2) may be placed on the outer surface of the contact spacer (172). The second high dielectric constant insulating film (HK2) may surround the contact spacer (172). A portion of the second high dielectric constant insulating film (HK2) may be placed on the air gap (AG), and another portion of the second high dielectric constant insulating film (HK2) may be in contact with the gate electrode (120).

[0073] A support structure (160) may be placed on an extension area (EXT). A support structure (160) may be placed around a word line contact (170). For example, four support structures (160) may be placed around one word line contact (170). However, the present disclosure is not limited thereto. For example, three support structures (160) may be placed around one word line contact (170). The support structure (160) supports a plurality of gate electrodes (120) and word line contacts (170) to prevent the word line contacts (170) from collapsing or falling over.

[0074] The support structure (160) may include a vertical portion (160_V) extending in a third direction (D3) and a horizontal portion (160_H) extending in a fourth direction (D4). Here, the fourth direction (D4) may be a direction parallel to the lower surface of the cell bottom insulating film (190). The vertical portion (160_V) of the support structure (160) may be formed in a shape similar to the channel structure (CH). The horizontal portion (160_H) of the support structure (160) may extend in a first direction (D1), a second direction (D2), and a fourth direction (D4). The horizontal portion (160_H) of the support structure (160) may be positioned at the same vertical level as the gate electrode (120). In the present disclosure, the same vertical level may mean being positioned at the same height in the third direction (D3) from the lower surface of the cell bottom insulating film (190). Here, "identical" may mean substantially identical, including manufacturing process errors.

[0075] The support structure (160) may include an insulating material. For example, the support structure (160) may include a silicon oxide-based insulating material. However, the present disclosure is not limited thereto.

[0076] In some embodiments, the support structure (160) may further include a third high dielectric constant insulating film (HK3). The third high dielectric constant insulating film (HK3) may define the outer surface of the support structure (160). For example, the third high dielectric constant insulating film (HK3) may surround the vertical portion (160_V) and the horizontal portion (160_H) of the support structure (160). The vertical portion (160_V) and the horizontal portion (160_H) of the support structure (160) may be placed within the third high dielectric constant insulating film (HK3). A portion of the third high dielectric constant insulating film (HK3) may be placed on the air gap (AG), and another portion of the third high dielectric constant insulating film (HK3) may be in contact with the gate electrode (120).

[0077] Each of the first high dielectric constant insulating film (HK1), the second high dielectric constant insulating film (HK2), and the third high dielectric constant insulating film (HK3) may include a high dielectric constant material. High dielectric constant materials may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0078] In some embodiments, the first high dielectric constant insulating film (HK1), the second high dielectric constant insulating film (HK2), and the third high dielectric constant insulating film (HK3) may comprise the same material. However, the present disclosure is not limited thereto. For example, some of the first high dielectric constant insulating film (HK1), the second high dielectric constant insulating film (HK2), and the third high dielectric constant insulating film (HK3) may comprise the same material, and each of the first high dielectric constant insulating film (HK1), the second high dielectric constant insulating film (HK2), and the third high dielectric constant insulating film (HK3) may comprise different materials.

[0079] The peripheral circuit structure (PERI) may include a peripheral circuit board (200), a peripheral circuit element (260), and a peripheral circuit wiring structure (280).

[0080] The peripheral circuit board (200) may include a semiconductor substrate such as, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the peripheral circuit board (200) may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0081] A peripheral circuit element (260) may be formed on a peripheral circuit board (200). The peripheral circuit element (260) may constitute a peripheral circuit that controls the operation of a semiconductor memory device. In the following description, the surface of the peripheral circuit board (200) on which the peripheral circuit element (260) is placed may be referred to as the front side of the peripheral circuit board (200). Conversely, the surface of the peripheral circuit board (200) opposite to the front side of the peripheral circuit board (200) may be referred to as the back side of the peripheral circuit board (200).

[0082] The peripheral circuit element (260) may include, for example, a transistor, but is not limited thereto. For example, the peripheral circuit element (260) may include various active elements such as a transistor, as well as various passive elements such as a capacitor, a resistor, and an inductor.

[0083] A peripheral circuit wiring structure (280) may be formed on a peripheral circuit element (260). For example, a peripheral circuit insulating film (290) may be formed on the front surface of a peripheral circuit board (200), and the peripheral circuit wiring structure (280) may be formed within the peripheral circuit insulating film (290). The peripheral circuit wiring structure (280) may be electrically connected to the peripheral circuit element (260). The number of layers and arrangement of the illustrated peripheral circuit wiring structure (280) are merely exemplary and are not limited thereto.

[0084] In some embodiments, the cell structure (CELL) may be laminated on the peripheral circuit structure (PERI). For example, the cell structure (CELL) may be laminated on the peripheral circuit insulating film (290).

[0085] A semiconductor memory device according to some embodiments may have a C2C (chip to chip) structure. A C2C structure means fabricating an upper chip including a cell structure (CELL) on a first wafer, fabricating a lower chip including a peripheral circuit structure (PERI) on a second wafer different from the first wafer (e.g., a peripheral circuit board (200)), and then connecting the upper chip and the lower chip to each other by a bonding method.

[0086] In some embodiments, the bonding method may refer to a method of electrically connecting a first bonding pad (195) formed on the uppermost metal layer of an upper chip and a second bonding pad (295) formed on the uppermost metal layer of a lower chip. For example, if the first bonding pad (195) and the second bonding pad (295) are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. However, this is merely exemplary, and the first bonding pad (195) and the second bonding pad (295) may, of course, be formed of various other metals such as aluminum (Al) or tungsten (W).

[0087] As the first bonding pad (195) and the second bonding pad (295) are bonded, the cell wiring structure (182) and the cell via (138) can be connected to the peripheral circuit wiring structure (280). Through this, the bit line (BL) and / or each gate electrode (120) can be electrically connected to the peripheral circuit element (260).

[0088] FIGS. 10 and 11 are drawings for illustrating a semiconductor memory device according to some embodiments of the present disclosure. For convenience of explanation, the description will focus on configurations different from those described in FIGS. 1 to 9.

[0089] Referring to FIGS. 10 and FIGS. 11, in a semiconductor memory device according to some embodiments, the source plate structure (105) may include a step (ST).

[0090] The step (ST) of the source plate structure (105) may be placed on the conductive layer (104). For example, the step (ST) of the source plate structure (105) may be formed on the conductive layer (104) placed above the opening (OP). The step (ST) of the source plate structure (105) may have a stepped shape.

[0091] In some embodiments, the air gap (AG) may be placed on the gate separation trench (WCT), the opening (OP), and the step (ST) of the source plate structure (105). For example, the air gap (AG) may be placed on the remainder of the portion of the step (ST) of the source plate structure (105) where the cell top insulating film (180) is placed.

[0092] FIGS. 12 and 13 are drawings for illustrating a semiconductor memory device according to some embodiments of the present disclosure. For convenience of explanation, the description will focus on configurations different from those described in FIGS. 1 through 9.

[0093] Referring to FIGS. 12 and 13, in a semiconductor memory device according to some embodiments, a cell structure (CH) may include a first width extension region (CH_ER).

[0094] The first width expansion region (CH_ER) may be placed at one end of the channel structure (CH). The first width expansion region (CH_ER) may be placed within the source plate structure (105). For example, the semiconductor layer (102) may surround the first width expansion region (CH_ER). The first width expansion region (CH_ER) is placed at one end of the cell structure (CH) and may be defined as a portion where the width changes abruptly in the first direction (D1) and the second direction (D2). For example, the first width expansion region (CH_ER) of the channel structure (CH) and the remaining area may be separated by a step.

[0095] The support structure (160) may include a second width expansion region (160_ER). The second width expansion region (160_ER) may be placed at one end of the support structure (160). The second width expansion region (160_ER) may be placed within the source plate structure (105). For example, the semiconductor layer (102) may surround the second width expansion region (160_ER). The second width expansion region (160_ER) is placed at one end of the support structure (160) and may be defined as a portion where the width changes abruptly in the first direction (D1) and the second direction (D2). For example, the second width expansion region (160_ER) and the remaining portion of the vertical portion of the dummy support structure (160) may be separated by a step.

[0096] FIG. 14 is a drawing for illustrating a semiconductor memory device according to some embodiments of the present disclosure. For convenience of explanation, the description focuses on configurations different from those described in FIG. 1 to 9.

[0097] Referring to FIG. 14, in a semiconductor memory device according to some embodiments, the source plate structure (105) may include a plate shape.

[0098] The source plate structure (105) may include a semiconductor layer (102) and a conductive layer (104). One end of the channel structure (CH) may penetrate the lower surface of the semiconductor layer (102). The upper surface of the semiconductor layer (102) may have a plane parallel to the first direction (D1) and the second direction (D2). The conductive layer (104) may be disposed on the semiconductor layer (102). The lower and upper surfaces of the conductive layer (104) may have planes parallel to the first direction (D1) and the second direction (D2).

[0099] FIGS. 15 and 16 are drawings for illustrating a semiconductor memory device according to some embodiments of the present disclosure. For convenience of explanation, the description will focus on configurations different from those described in FIGS. 1 through 9.

[0100] Referring to FIGS. 15 and 16, a semiconductor memory device according to some embodiments may further include a mold insulating layer (110).

[0101] A molded insulating layer (110) may be disposed between a plurality of gate electrodes (120), between a gate electrode (120) and a source plate structure (105), and between a plurality of gate electrodes (120) and a barrier film (150). A molded insulating layer (110) may be disposed on a channel structure (CH). For example, a molded insulating layer (110) may be disposed around a channel structure (CH) spaced far from a gate isolation trench (WCT). A molded insulating layer (110) may be disposed on a support structure (160). For example, a molded insulating layer (110) may be disposed around a support structure (160) spaced far from a gate isolation trench (WCT).

[0102] In some embodiments, the mold insulating layer (110) may be a portion that remains unremoved by the etching process. A plurality of gate electrodes (120) and a plurality of mold insulating layers (110) may be alternately stacked before forming an air gap (AG) between a plurality of gate electrodes (120). To form an air gap (AG) between a plurality of gate electrodes (120), the mold insulating layer (110) may be removed. In the process, the mold insulating layer (110) adjacent to the gate isolation trench (WCT) may be removed, while the mold insulating layer (110) spaced far from the gate isolation trench (WCT) may not be removed.

[0103] FIG. 17 is a drawing for illustrating a semiconductor memory device according to some embodiments of the present disclosure. For convenience of explanation, the description focuses on configurations different from those described in FIG. 1 to 9.

[0104] Referring to FIG. 17, in a semiconductor memory device according to some embodiments, a plurality of gate electrodes (120) may have a stepped shape on an extended region (EXT). A plurality of gate electrodes (120) may each extend with a different length in a first direction (D1) to form a stepped structure. Due to the stepped structure, a specific gate electrode (120) may include an end exposed by the gate electrode (120) disposed below the specific gate electrode (120). A word line contact (178) may be formed on the end of the gate electrode (120). The word line contact (178) may be connected to the gate electrode (120).

[0105] An air gap (AG) may be placed between a plurality of gate electrodes (120). The air gap (AG) may surround a portion of the word line contact (178). For example, the air gap (AG) may surround the word line contact (178) that is placed on top of the barrier film (150) among the word line contacts (178).

[0106] FIGS. 18 through 33 are drawings for illustrating a method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure. For reference, FIGS. 18, 20, 22, 24, 26, 28, 30, and 32 may correspond to a cross-sectional view cut along line AA of FIG. 1. FIGS. 19, 21, 23, 25, 27, 29, 31, and 33 may correspond to a cross-sectional view cut along lines BB and CC of FIG. 1. For convenience of explanation, configurations identical to those described in FIGS. 1 through 9 are omitted or briefly described.

[0107] Referring to FIGS. 18 and 19, a method for manufacturing a semiconductor memory device according to some embodiments may include forming a mold structure (MS), a channel structure (CH), a gate isolation structure (WCF), a free insulating layer (190_P), and a support structure (160) on a cell substrate (100).

[0108] The cell substrate (100) may include a semiconductor substrate, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the cell substrate (100) may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In some embodiments, the cell substrate (100) may include polysilicon (poly Si).

[0109] The cell substrate (100) may include a first surface (100_A) and a second surface (100_B) opposite to the first surface (100_A). The second surface (100_B) of the cell substrate (100) may be a surface on which a mold structure (MS) and a channel structure (CH) are placed. The first surface (100_A) of the cell substrate (100) may be referred to as the back side of the cell substrate (100). The second surface (100_B) of the cell substrate (100) may be referred to as the front side of the cell substrate (100).

[0110] A mold structure (MS) may be disposed on a second surface (100_B) of a cell substrate (100). The mold structure (MS) may include a plurality of mold insulating layers (110) and a plurality of gate electrodes (120) that are alternately stacked in a third direction (D3). Each mold insulating layer (110) and each gate electrode (120) may be a layered structure extending parallel to a first surface (100_A) of the cell substrate (100).

[0111] A channel structure (CH) may be placed on a cell array region (CAR). The channel structure (CH) may extend in a third direction (D3) and penetrate a mold structure (MS). One end of the channel structure (CH) may be placed within a cell substrate (100). In some embodiments, a first high dielectric constant insulating film (e.g., HK1 of FIG. 5) may be formed before the channel structure (CH) is formed. For example, a channel hole penetrating the mold structure (MS) may be formed, and the first high dielectric constant insulating film (HK1) may be formed within the channel hole. Then, an information storage film (140), a semiconductor pattern (148), and a filling pattern (149) may be formed in sequence on the first high dielectric constant insulating film (HK1).

[0112] The gate isolation structure (WCF) can penetrate the mold structure (MS). The gate isolation structure (WCF) can extend in a first direction (D1) and a third direction (D3). One end of the gate isolation structure (WCF) can be placed within the cell substrate (100).

[0113] A support structure (160) may be placed on an extended region (EXT). The support structure (160) may penetrate the mold structure (MS). In some embodiments, a third high dielectric constant insulating film (e.g., HK3 of FIG. 9) may be formed before forming the support structure (160). For example, a support structure hole may be formed to form the support structure (160). The support structure hole may include a vertical portion penetrating the mold structure (MS) and a horizontal portion positioned between the gate electrode (120). A third high dielectric constant insulating film (HK3) may be formed within the support structure hole. Subsequently, the support structure (160) may be formed on the third high dielectric constant insulating film (HK3).

[0114] The free insulating layer (190_P) can be placed below the channel structure (CH) and the mold structure (MS). The free insulating layer (190_P) can be placed between adjacent gate isolation structures (WCF).

[0115] Referring to FIGS. 20 and 21, a barrier film (150) can be formed on a gate separation structure (WCF) and a channel structure (CH).

[0116] Specifically, a portion of the free insulating layer (e.g., 190_P in FIG. 19 and 20) and the gate isolation structure (WCF) may be removed, and the lower surface of the channel structure (CH), the lower surface of the mold structure (MS), and the lower surface of the gate isolation structure (WCF) may be exposed. As a portion of the gate isolation structure (WCF) is removed, the lower surface of the gate isolation structure (WCF) may be positioned at a vertical level higher than the lower surface of the channel structure (CH). For example, the distance from the first surface (100_A) of the cell substrate (100) to the lower surface of the gate isolation structure (WCF) may be smaller than the distance from the first surface (100_A) of the cell substrate (100) to the lower surface of the channel structure (CH).

[0117] Next, a barrier film (150) may be formed along the lower surface of the gate isolation structure (WCF), the lower surface of the mold structure (MS), and the lower surface of the channel structure (CH). The barrier film (150) may include a material having an etch selectivity ratio with the mold insulating layer (110).

[0118] Referring to FIGS. 22 and 23, a word line contact (170), a contact spacer (172), a word line via (174), a bit line contact (136), a bit line (BL), a cell via (138), a first bonding pad (195), a cell string contact (176), a cell wiring structure (182), and a cell lower insulating film (190) may be formed.

[0119] In some embodiments, a second high dielectric constant insulating film (e.g., HK2 of FIG. 9) may be formed before the word line contact (170) is formed. For example, a word line contact hole may be formed to form the word line contact (170). The word line contact hole may penetrate a part of the mold structure (MS). The second high dielectric constant insulating film (HK2) may be formed within the word line contact hole. Subsequently, a contact spacer (172) and a word line contact (170) may be formed in sequence on the second high dielectric constant insulating film (HK2).

[0120] Referring to FIGS. 24 and 25, a peripheral circuit structure (PERI) and a cell structure (CELL) can be combined. The peripheral circuit structure (PERI) can be formed on a different wafer than the cell structure (CELL). A second bonding pad (295) of the peripheral circuit structure (PERI) and a first bonding pad (195) of the cell structure (CELL) can be bonded together.

[0121] Referring to FIGS. 26 and 27, a portion of the cell substrate (e.g., 100 in FIGS. 22 and 23) and the channel structure (CH) may be removed.

[0122] Specifically, the cell substrate (100) may be removed to expose the upper surface of the channel structure (CH), the upper surface of the gate isolation structure (WCF), the upper surface of the support structure (160), and the upper surface of the mold structure (MS). Subsequently, a portion of the channel structure (CH) may be removed. For example, a portion of the information storage film (140) may be removed to expose the semiconductor pattern (148) of the channel structure (CH).

[0123] Referring to FIGS. 28 and 29, a source plate structure (105) can be formed on a channel structure (CH), a support structure (160), a mold structure (MS), and a gate separation structure (WCF).

[0124] The source plate structure (105) may include a semiconductor layer (102) and a conductive layer (104). The semiconductor layer (102) may cover the upper surface of the channel structure (CH), the upper surface of the support structure (160), the upper surface of the mold structure (MS), and the upper surface of the gate isolation structure (WCF). For example, the semiconductor layer (102) may be in contact with the semiconductor pattern (148) of the channel structure (CH). The semiconductor layer (102) may be in contact with the mold insulating layer (110) placed at the top of the mold structure (MS). The conductive layer (104) may be formed on the semiconductor layer (102). The conductive layer (104) may extend along the profile of the semiconductor layer (102).

[0125] Referring to FIGS. 30 and 31, an opening (OP) is formed on the source plate structure (105), and the gate isolation structure (e.g., WCF of FIGS. 28 and 29) can be removed.

[0126] Specifically, an etching process may be performed on a source plate structure (105). Through the etching process, a portion of the source plate structure (105) may be removed, and an opening (OP) may be formed. The opening (OP) may expose a gate isolation structure (WCF). The depth of the opening (OP) formed by the etching process may vary.

[0127] Subsequently, an etching process may be performed on the opening (OP) to remove the gate isolation structure (WCF) and form a gate isolation trench (WCT). The gate isolation trench (WCT) may be defined as the trench remaining after the gate isolation structure (WCF) is removed. The gate isolation trench (WCT) may expose the side of the mold structure (MS) and a portion of the barrier film (150).

[0128] Referring to FIGS. 32 and 33, the mold insulating layer (e.g., 110 in FIGS. 30 and 31) can be removed and an air gap (AG) can be formed.

[0129] Specifically, an etching process may be performed on a mold structure (e.g., MS in FIG. 30 and 31) exposed by a gate isolation trench (WCT). The etching process may use an etchant having an etching selectivity on a mold insulating layer (e.g., 110 in FIG. 30 and 31). As a result, the mold insulating layer (110) of the mold structure (MS) is removed, and an air gap (AG) may be formed. The air gap (AG) may fill the space remaining after the mold insulating layer (110) is removed and the inside of the gate isolation trench (WCT).

[0130] The barrier film (150) can protect the cell bottom insulating film (190) during the etching process of removing the mold insulating layer (110). For example, the barrier film (150) may not be removed when the mold insulating layer (110) is removed, and the cell bottom insulating film (190) may not be exposed. As a result, the cell bottom insulating film (190) may not be removed.

[0131] In some embodiments, the channel structure (CH) may include a first high dielectric constant insulating film (e.g., HK1 of FIG. 5). The first high dielectric constant insulating film (HK1) may protect the channel structure (CH) during an etching process in which the mold insulating layer (110) is removed. The channel structure (CH) may not be removed during the etching process by the first high dielectric constant insulating film (HK1).

[0132] In some embodiments, a second high dielectric constant insulating film (e.g., HK2 of FIG. 9) may be disposed on the outer side of the contact spacer (172). The second high dielectric constant insulating film (HK2) can protect the contact spacer (172) during an etching process in which the mold insulating layer (110) is removed. The contact spacer (172) may not be removed during the etching process due to the second high dielectric constant insulating film (HK2).

[0133] In some embodiments, a third high dielectric constant insulating film (e.g., HK3 of FIG. 9) may be disposed on the outer surface of the support structure (160). The third high dielectric constant insulating film (HK3) may protect the support structure (160) during an etching process in which the mold insulating layer (110) is removed. The support structure (160) may not be removed by the third high dielectric constant insulating film.

[0134] Referring to FIGS. 2 and 3, a cell upper insulating film (180) may be formed on a source plate structure (105). The cell upper insulating film (180) may cover an opening (OP) of the source plate structure (105). By the cell upper insulating film (180), an air gap (AG) placed between the gate isolation trench (WCT) and a plurality of gate electrodes (120) may be blocked from the outside.

[0135] FIGS. 34 and 35 are drawings illustrating a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure. For reference, FIGS. 34 and 35 may correspond to FIGS. 18 and 19, respectively. For convenience of explanation, configurations identical to those described in FIGS. 18 to 33 are omitted or briefly described.

[0136] Referring to FIGS. 34 and 35, a method for manufacturing a semiconductor memory device according to some embodiments may include forming a mold structure (MS), a channel structure (CH), a gate isolation structure (WCF), a free insulating layer (190_P), and a support structure (160) on a cell substrate (100).

[0137] A method for manufacturing a semiconductor memory device according to some embodiments may include forming a mold structure (MS), a channel structure (CH), a gate isolation structure (WCF), a free insulating layer (190_P), and a support structure (160) on a cell substrate (100).

[0138] In some embodiments, the channel structure (CH) may include a first width-extending region (CH_ER). The first width-extending region (CH_ER) may be disposed at one end of the channel structure (CH). The first width-extending region (CH_ER) may be disposed within the cell substrate (100). The first width-extending region (CH_ER) may be formed by a first etch stop layer. For example, a first etch stop layer may be formed within the cell substrate (100), and a channel hole may be formed on the first etch stop layer to form the channel structure (CH). Then, the first etch stop layer may be removed, and the channel structure (CH) may be formed inside the channel hole. The first width-extending region (CH_ER) may be disposed in the portion where the first etch stop layer was removed.

[0139] The support structure (160) may include a second width expansion region (160_ER). The second width expansion region (160_ER) may be disposed at one end of the support structure (160). The second width expansion region (160_ER) may be disposed within the cell substrate (100). The second width expansion region (160_ER) may be formed by a second etch stop layer. For example, a second etch stop layer may be formed within the cell substrate (100), and a support structure hole may be formed on the second etch stop layer to form the support structure (160). Then, the second etch stop layer may be removed, and the support structure (160) may be formed inside the support structure hole. The second width expansion region (160_ER) may be disposed in the portion where the second etch stop layer was removed.

[0140] In some embodiments, the upper surface of the gate isolation structure (WCF) may be positioned at a lower vertical level than the upper surface of the channel structure (CH). For example, the distance from the first surface (100_A) of the cell substrate (100) to the upper surface of the gate isolation structure (WCF) may be greater than the distance from the first surface (100_A) of the cell substrate (100) to the upper surface of the channel structure (CH). Although the upper surface of the gate isolation structure (WCF) is depicted as being positioned at the same vertical level as the upper surface of the mold structure (MS), the present disclosure is not limited thereto. For example, the upper surface of the gate isolation structure (WCF) may be positioned at a different vertical level than the upper surface of the mold structure (MS).

[0141] The upper surface of the gate isolation structure (WCF) may be positioned at a vertical level lower than the upper surface of the support structure (160). For example, the distance from the first surface (100_A) of the cell substrate (100) to the upper surface of the gate isolation structure (WCF) may be greater than the distance from the first surface (100_A) of the cell substrate (100) to the upper surface of the support structure (160).

[0142] Next, the manufacturing process described in FIGS. 20 to 33 can be performed in the same way. As a result, the semiconductor memory device described in FIGS. 10 and 11 can be formed. For example, the source plate structure (105) may include a step (ST).

[0143] FIGS. 36 and 37 are drawings illustrating a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure. For reference, FIGS. 36 and 37 may correspond to FIGS. 18 and 19, respectively. For convenience of explanation, configurations identical to those described in FIGS. 18 through 35 are omitted or briefly described.

[0144] Referring to FIGS. 36 and 37, a method for manufacturing a semiconductor memory device according to some embodiments may include forming a mold structure (MS), a channel structure (CH), a gate isolation structure (WCF), a free insulating layer (190_P), and a support structure (160) on a cell substrate (100).

[0145] In some embodiments, the channel structure (CH) may include a first width expansion region (CH_ER). The first width expansion region (CH_ER) may be disposed at one end of the channel structure (CH). The first width expansion region (CH_ER) may be disposed within the cell substrate (100). The support structure (160) may include a second width expansion region (160_ER). The second width expansion region (160_ER) may be disposed at one end of the support structure (160). The second width expansion region (160_ER) may be disposed within the cell substrate (100).

[0146] The gate isolation structure (WCF) may include a third width expansion region (WCF_ER). The third width expansion region (WCF_ER) may be disposed at one end of the gate isolation structure (WCF). The third width expansion region (WCF_ER) may be disposed within the cell substrate (100). The third width expansion region (WCF_ER) may be formed by a third etch stop layer. For example, a third etch stop layer may be formed within the cell substrate (100), and a gate isolation structure trench may be formed on the third etch stop layer to form the gate isolation structure (WCF). Then, the third etch stop layer may be removed, and the gate isolation structure (WCF) may be formed inside the gate isolation structure trench. The third width expansion region (WCF_ER) may be disposed in the portion where the third etch stop layer was removed.

[0147] In some embodiments, the upper surface of the channel structure (CH) and the upper surface of the gate isolation structure (WCF) may be positioned at the same vertical level. For example, the distance from the first surface (100_A) of the cell substrate (100) to the upper surface of the channel structure (CH) may be the same as the distance from the first surface (100_A) of the cell substrate (100) to the upper surface of the gate isolation structure (WCF). However, the present disclosure is not limited thereto.

[0148] In some embodiments, the upper surface of the support structure (160) and the upper surface of the gate isolation structure (WCF) may be positioned at the same vertical level. For example, the distance from the first surface (100_A) of the cell substrate (100) to the upper surface of the support structure (160) may be the same as the distance from the first surface (100_A) of the cell substrate (100) to the upper surface of the gate isolation structure (WCF). However, the present disclosure is not limited thereto.

[0149] Next, the manufacturing process described in FIGS. 20 to 33 can be performed in the same way. As a result, the semiconductor memory device described in FIGS. 12 and 13 can be formed.

[0150] FIG. 38 is an exemplary block diagram for illustrating an electronic system according to some embodiments of the present disclosure.

[0151] Referring to FIG. 38, an electronic system (1000) according to an exemplary embodiment of the present disclosure may include a semiconductor memory device (1100) described above through FIG. 1 to FIG. 37 and a controller (1200) electrically connected to the semiconductor memory device (1100). The electronic system (1000) may be a storage device or an electronic device including a storage device, comprising one or more semiconductor memory devices (1100). For example, the electronic system (1000) may be a solid state drive device (SSD) comprising one or more semiconductor memory devices (1100), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device.

[0152] The semiconductor memory device (1100) may be, for example, a NAND flash memory device described above with reference to FIGS. 1 to 37. The semiconductor memory device (1100) may include a first structure (1100F) and a second structure (1100S) on the first structure (1100F). The first structure (1100F) may be a peripheral circuit structure including a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). The second structure (1100S) may be a memory cell structure including a bit line (BL), a common source line (CSL), word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and memory cell strings (CSTR) between the bit line (BL) and the common source line (CSL).

[0153] In the second structure (1100S), each memory cell string (CSTR) may include lower transistors (LT1, LT2) adjacent to a common source line (CSL), upper transistors (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiments.

[0154] In exemplary embodiments, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. The gate lower lines (LL1, LL2) may each be the gate electrodes of the lower transistors (LT1, LT2). The word lines (WL) may be the gate electrodes of the memory cell transistors (MCT), and the gate upper lines (UL1, UL2) may each be the gate electrodes of the upper transistors (UT1, UT2).

[0155] The common source line (CSL), the first and second gate lower lines (LL1, LL2), the word lines (WL), and the first and second gate upper lines (UL1, UL2) can be electrically connected to the decoder circuit (1110) through first connecting wires (1115) extending from the first structure (1100F) to the second structure (1100S). The bit lines (BL) can be electrically connected to the page buffer (1120) through second connecting wires (1125) extending from the first structure (1100F) to the second structure (1100S).

[0156] In the first structure (1100F), the decoder circuit (1110) and the page buffer (1120) can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit (1110) and the page buffer (1120) can be controlled by the logic circuit (1130). The semiconductor memory device (1100) can communicate with the controller (1200) through an input / output pad (1101) that is electrically connected to the logic circuit (1130). The input / output pad (1101) can be electrically connected to the logic circuit (1130) through an input / output connection wire (1135) that extends from the first structure (1100F) to the second structure (1100S).

[0157] The controller (1200) may include a processor (1210), a NAND controller (1220), and a host interface (1230). According to embodiments, the electronic system (1000) may include a plurality of semiconductor memory devices (1100), and in this case, the controller (1200) may control the plurality of semiconductor memory devices (1100).

[0158] The processor (1210) can control the overall operation of the electronic system (1000), including the controller (1200). The processor (1210) can operate according to a predetermined firmware and can access the semiconductor memory device (1100) by controlling the NAND controller (1220). The NAND controller (1220) may include a NAND interface (1221) that handles communication with the semiconductor memory device (1100). Through the NAND interface (1221), control commands for controlling the semiconductor memory device (1100), data to be written to the memory cell transistors (MCT) of the semiconductor memory device (1100), data to be read from the memory cell transistors (MCT) of the semiconductor memory device (1100), etc., can be transmitted. The host interface (1230) can provide communication functions between the electronic system (1000) and an external host. When a control command is received from an external host through the host interface (1230), the processor (1210) can control the semiconductor memory device (1100) in response to the control command.

[0159] FIG. 39 is an exemplary perspective view illustrating an electronic system including a semiconductor memory device according to some embodiments of the present disclosure. FIG. 40 is a schematic cross-sectional view cut along the VV line of FIG. 39.

[0160] Referring to FIG. 39, an electronic system (2000) according to an exemplary embodiment of the present invention may include a main board (2001), a controller (2002) mounted on the main board (2001), one or more semiconductor packages (2003), and a DRAM (2004). The semiconductor packages (2003) and the DRAM (2004) may be connected to the controller (2002) by wiring patterns (2005) formed on the main board (2001).

[0161] The main board (2001) may include a connector (2006) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2006) may vary depending on the communication interface between the electronic system (2000) and the external host. In exemplary embodiments, the electronic system (2000) may communicate with the external host according to any one of interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). In exemplary embodiments, the electronic system (2000) may operate by power supplied from the external host through the connector (2006). The electronic system (2000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (2002) and a semiconductor package (2003).

[0162] The main controller (2002) can write data to the semiconductor package (2003) or read data from the semiconductor package (2003), and can improve the operating speed of the electronic system (2000).

[0163] The DRAM (2004) may be a buffer memory to mitigate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM (2004) included in the electronic system (2000) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (2003). When the electronic system (2000) includes the DRAM (2004), the main controller (2002) may further include a DRAM controller for controlling the DRAM (2004) in addition to the NAND controller for controlling the semiconductor package (2003).

[0164] A semiconductor package (2003) may include a first semiconductor package (2003a) and a second semiconductor package (2003b) spaced apart from each other. The first semiconductor package (2003a) and the second semiconductor package (2003b) may each be a semiconductor package including a plurality of semiconductor chips (2200). The first semiconductor package (2003a) and the second semiconductor package (2003b) may each include a package substrate (2100), semiconductor chips (2200) on the package substrate (2100), adhesive layers (2300) disposed on the lower surface of each of the semiconductor chips (2200), a connecting structure (2400) electrically connecting the semiconductor chips (2200) and the package substrate (2100), and a molding layer (2500) covering the semiconductor chips (2200) and the connecting structure (2400) on the package substrate (2100).

[0165] The package substrate (2100) may be a printed circuit board including package upper pads (2130). Each semiconductor chip (2200) may include an input / output pad (2210). The input / output pad (2210) may correspond to the input / output pad (1101) of FIG. 24. Each of the semiconductor chips (2200) may include metal lines (3210) and channel structures (3220). Each of the semiconductor chips (2200) may include the semiconductor memory device described above with reference to FIGS. 1 through 37.

[0166] In some embodiments, the connection structure (2400) may be a bonding wire that electrically connects the input / output pad (2210) and the package upper pads (2130). Accordingly, in each of the first semiconductor package (2003a) and the second semiconductor package (2003b), the semiconductor chips (2200) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads (2130) of the package substrate (2100). In some embodiments, in each of the first semiconductor package (2003a) and the second semiconductor package (2003b), the semiconductor chips (2200) may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the bonding wire method connection structure (2400).

[0167] In some embodiments, the main controller (2002) and the semiconductor chips (2200) may be included in a single package. In some embodiments, the main controller (2002) and the semiconductor chips (2200) may be mounted on a separate interposer substrate different from the main substrate (2001), and the main controller (2002) and the semiconductor chips (2200) may be connected to each other by wiring formed on the interposer substrate.

[0168] In some embodiments, the package substrate (2100) may be a printed circuit board. The package substrate (2100) may include a package substrate body (2120), package upper pads (2130) disposed on the upper surface of the package substrate body (2120), lower pads (2125) disposed on the lower surface of the package substrate body (2120) or exposed through the lower surface, and internal wiring (2135) electrically connecting the upper pads (2130) and the lower pads (2125) inside the package substrate body (2120). The upper pads (2130) may be electrically connected to connection structures (2400). The lower pads (2125) may be connected to wiring patterns (2005) of the main board (2001) of the electronic system (2000) as shown in FIG. 39 through conductive connections (2800).

[0169] In an electronic system according to some embodiments, each of the semiconductor chips (2200) may include the semiconductor memory device described above using FIGS. 1 to 16. For example, each of the semiconductor chips (2200) may include a peripheral circuit structure (PERI) and a cell structure (CELL) stacked on the peripheral circuit structure (PERI). For example, the peripheral circuit structure (PERI) may include a peripheral circuit board (200) and a peripheral circuit wiring structure (280) described above using FIGS. 1 to 37. Also, for example, the cell structure (CELL) may include a plurality of gate electrodes (120), an air gap (AG), a gate isolation trench (WCT), a source plate structure (105), a cell upper insulating film (180), a barrier film (150), a cell lower insulating film (190), a channel structure (CH), a support structure (160), a word line contact (170), etc. described above using FIGS. 1 to 37.

[0170] Although the present invention has been described above by limited embodiments and drawings, the present invention is not limited thereto, and it is obvious that various modifications and variations are possible within the scope of the technical spirit of the present invention and the equivalent scope of the claims described below by those skilled in the art to which the present invention belongs. Explanation of the symbols

[0171] 105: Source plate structure 120: Multiple gate electrodes 150: Barrier 180: Cell upper insulating layer 190: Cell lower insulation layer WCT: Gate separation trench AG: Air gap CH: Channel structure

Claims

Claim 1 A semiconductor memory device comprising: a cell bottom insulating film including a cell array region and an extension region; a plurality of gate electrodes stacked spaced apart from each other on the cell bottom insulating film; a channel structure disposed on the cell array region and penetrating the plurality of gate electrodes; a word line contact disposed on the extension region and penetrating some of the gate electrodes of the plurality of gate electrodes; a gate separation trench penetrating the plurality of gate electrodes and extending in a first horizontal direction; an air gap disposed between the plurality of gate electrodes and within the gate separation trench; a source plate structure disposed on one end of the channel structure and extending in a second horizontal direction intersecting the first horizontal direction, including an opening connected to the gate separation trench; and a cell top insulating film disposed on the source plate structure and covering the opening, wherein the air gap is disposed on the cell array region and the extension region. Claim 2 A semiconductor memory device according to claim 1, further comprising: a barrier film extending along the upper surface of the cell lower insulating film; and a bit line contact penetrating the barrier film, disposed within the cell lower insulating film, and connected to the channel structure. Claim 3 A semiconductor memory device according to claim 2, further comprising: a bit line connected to the bit line contact, extending in the second horizontal direction, and disposed within the cell lower insulating film; a first bonding pad disposed on the lower surface of the cell lower insulating film; and a second bonding pad coupled to the first bonding pad. Claim 4 A semiconductor memory device according to claim 1, wherein the source plate structure comprises a first side disposed on the opening and a second side facing the first side in a second horizontal direction, and the first side comprises a first portion having a first slope and a second portion having a second slope different from the first slope. Claim 5 A semiconductor memory device according to claim 1, wherein the cell upper insulating film comprises a first protrusion disposed on the opening, and the first protrusion overlaps with the source plate structure in the second horizontal direction. Claim 6 A semiconductor memory device according to claim 5, wherein the lower surface of the first protrusion includes a curved surface. Claim 7 A semiconductor memory device according to claim 1, wherein the cell lower insulating film comprises a plate portion and a second protrusion protruding from the plate portion toward the gate separation trench. Claim 8 A semiconductor memory device according to claim 7, further comprising a barrier film extending along the upper surface of the plate portion and the upper surface of the second protrusion. Claim 9 A semiconductor memory device according to claim 7, wherein the distance from the lower surface of the cell lower insulating film to the upper surface of the second protrusion is greater than the distance from the lower surface of the cell lower insulating film to the lower surface of the channel structure. Claim 10 A semiconductor memory device according to claim 1, wherein the channel structure comprises a semiconductor pattern connected to the source plate structure, an information storage film surrounding the semiconductor pattern, and a first high dielectric constant insulating film surrounding the information storage film. Claim 11 A semiconductor memory device according to claim 1, further comprising a second high dielectric constant insulating film surrounding the word line contact. Claim 12 A semiconductor memory device according to claim 1, further comprising: a support structure disposed around the word line contact and penetrating the plurality of gate electrodes; and a third high dielectric constant insulating film disposed between the support structure and the air gap. Claim 13 A semiconductor memory device according to claim 1, wherein the source plate structure comprises a semiconductor layer connected to the channel structure and a conductive layer disposed on the semiconductor layer, and the cell upper insulating film is in contact with the conductive layer. Claim 14 A semiconductor memory device comprising: a cell bottom insulating film including a cell array region and an extension region; a barrier film disposed on the cell bottom insulating film; a plurality of gate electrodes stacked spaced apart from each other on the barrier film; a channel structure disposed on the cell array region and penetrating the plurality of gate electrodes; a word line contact disposed on the extension region and connected to one of the plurality of gate electrodes; a gate separation trench penetrating the plurality of gate electrodes and extending in a first horizontal direction; an air gap disposed in at least a portion between the plurality of gate electrodes and within the gate separation trench; a source plate structure disposed on one end of the channel structure and including an opening extending in a second horizontal direction intersecting the first horizontal direction and connected to the gate separation trench; and a cell top insulating film disposed on the source plate structure and covering the opening, wherein the air gap is disposed on the cell array region and the extension region. Claim 15 A semiconductor memory device according to claim 14, wherein the source plate structure comprises a first side disposed on the opening and a second side facing the first side in a second horizontal direction, and the first side comprises a first portion having a first slope and a second portion having a second slope different from the first slope. Claim 16 A semiconductor memory device according to claim 14, further comprising a mold insulating layer disposed in a portion between the plurality of gate electrodes, wherein the air gap surrounds the mold insulating layer. Claim 17 A semiconductor memory device according to claim 14, wherein the plurality of gate electrodes have a stepped shape on the extended region, and each of the plurality of gate electrodes has a different length in the first horizontal direction. Claim 18 A semiconductor memory device in claim 14, wherein the source plate structure includes a step and the air gap is disposed on the step. Claim 19 In claim 12, the air gap is disposed between the plurality of gate electrodes and the source plate structure, in a semiconductor memory device. Claim 20 A semiconductor memory device comprising: a main substrate; a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure on the main substrate; and a controller electrically connected to the semiconductor memory device on the main substrate, wherein the cell structure comprises: a cell lower insulating film including a cell array region and an extension region; a barrier film disposed on the cell lower insulating film; a plurality of gate electrodes stacked spaced apart from each other on the barrier film; a channel structure disposed on the cell array region and penetrating the plurality of gate electrodes; a word line contact disposed on the extension region and connected to one of the plurality of gate electrodes; a gate separation trench penetrating the plurality of gate electrodes and extending in a first horizontal direction; an air gap disposed between at least a portion of the plurality of gate electrodes and within the gate separation trench; and a source plate structure disposed on one end of the channel structure and including an opening extending in a second horizontal direction intersecting the first horizontal direction and connected to the gate separation trench. An electronic system comprising a cell upper insulating film disposed on the source plate structure and covering the opening, wherein the air gap is disposed on the cell array region and the extension region.

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