Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device comprises a substrate, an active pattern extending in a first horizontal direction on the substrate, a first nanosheet spaced perpendicularly from the upper surface of the active pattern, a second nanosheet spaced perpendicularly from the upper surface of the first nanosheet, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the upper surface of the active pattern and surrounding the first and second nanosheets, and a source / drain region disposed on at least one side of the gate electrode on the upper surface of the active pattern and in contact with each of the first and second nanosheets, wherein each of the first and second nanosheets comprises a first channel layer surrounded by the gate electrode and comprising a first MXene material, and a second channel layer in contact with the sidewall in the first horizontal direction of the first channel layer and comprising a second MXene material different from the first MXene material.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Specifically, the present invention relates to an MBCFET TM This relates to a semiconductor device including a Multi-Bridge Channel Field Effect Transistor. Background Technology

[0002] As one of the scaling techniques to increase the density of integrated circuit devices, a multi-gate transistor has been proposed in which a silicon body in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the silicon body.

[0003] Since these multi-gate transistors utilize a three-dimensional channel, they are easy to scale. In addition, current control capability can be improved without increasing the gate length of the multi-gate transistor. Furthermore, the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics using a channel layer containing a maxim material.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] Some embodiments of a semiconductor device according to the technical concept of the present invention for solving the above problem include a substrate, an active pattern extending in a first horizontal direction on the substrate, a first nanosheet spaced perpendicularly from the upper surface of the active pattern, a second nanosheet spaced perpendicularly from the upper surface of the first nanosheet, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the upper surface of the active pattern and surrounding the first and second nanosheets, and a source / drain region disposed on at least one side of the gate electrode on the upper surface of the active pattern and in contact with each of the first and second nanosheets, wherein each of the first and second nanosheets comprises a first channel layer surrounded by the gate electrode and comprising a first MXene material, and a second channel layer in contact with the sidewall in the first horizontal direction of the first channel layer and comprising a second MXene material different from the first MXene material.

[0007] Some other embodiments of a semiconductor device according to the technical concept of the present invention for solving the above problem include a substrate, an active pattern extending in a first horizontal direction on the substrate, a first nanosheet spaced perpendicularly from the upper surface of the active pattern, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the upper surface of the active pattern and surrounding the first nanosheet, and an internal spacer disposed on the sidewall of the gate electrode in the first horizontal direction between the upper surface of the active pattern and the lower surface of the first nanosheet, wherein the first nanosheet comprises a first channel layer surrounded by the gate electrode and containing a first MXene material, at least a portion of which is in contact with the internal spacer, and a second channel layer in contact with the sidewall of the first channel layer in the first horizontal direction and containing a second MXene material different from the first MXene material.

[0008] Some other embodiments of a semiconductor device according to the technical concept of the present invention for solving the above problem include: a substrate; an active pattern extending in a first horizontal direction on the substrate; a first nanosheet spaced perpendicularly from the upper surface of the active pattern; a second nanosheet spaced perpendicularly from the upper surface of the first nanosheet; a gate electrode extending in a second horizontal direction different from the first horizontal direction on the upper surface of the active pattern and surrounding the first and second nanosheets; an internal spacer disposed on a sidewall in the first horizontal direction of the gate electrode between the upper surface of the first nanosheet and the lower surface of the second nanosheet; and a source / drain region disposed on at least one side of the gate electrode on the upper surface of the active pattern and in contact with each of the first and second nanosheets, wherein each of the first and second nanosheets is surrounded by the gate electrode and comprises a first channel layer comprising a first MXene material and at least a portion of which is in contact with the internal spacer, and in contact with the sidewall in the first horizontal direction of the first channel layer, wherein the first MXene material is sulfurized It includes a second channel layer comprising a formed second MXene material, wherein the upper surface and the lower surface each contact the source / drain region.

[0009] Some embodiments of a method for manufacturing a semiconductor device according to the technical concept of the present invention for solving the above problem include forming a stacked structure comprising a sacrificial layer and a first layer alternately stacked on a substrate, wherein the first layer comprises a first MXene material, forming a dummy gate on the upper surface of the stacked structure, etching the stacked structure using the dummy gate as a mask to form a source / drain trench on the first horizontal sidewall of the remaining stacked structure, and forming a plurality of nanosheets by sulfurizing a portion of the remaining first layer exposed through the source / drain trench, wherein each of the plurality of nanosheets comprises a first channel layer comprising a first MXene material and a second channel layer comprising a second MXene material formed by sulfurizing the first MXene material, forming a source / drain region in contact with the uppermost surface and the lowermost surface of the second channel layer respectively inside the source / drain trench, etching the dummy gate and the sacrificial layer to form a gate trench, and forming a gate electrode surrounding the plurality of nanosheets inside the gate trench.

[0010] Other specific details of the present invention are included in the detailed description and drawings. Brief explanation of the drawing

[0011] FIG. 1 is a schematic layout diagram for explaining a semiconductor device according to some embodiments of the present invention. Figure 2 is a cross-sectional view of Figure 1 cut along the line AA'. Figure 3 is an enlarged view of the R1 region of Figure 2. Figure 4 is a cross-sectional view of Figure 1 cut along the BB' line. FIGS. 5 to 16 are intermediate step drawings for explaining a method for manufacturing a semiconductor device according to some embodiments of the present invention. FIG. 17 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present invention. Figure 18 is an enlarged view of the R2 region of Figure 17. FIG. 19 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present invention. FIG. 20 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention. Figure 21 is an enlarged view of the R3 area of ​​Figure 20. FIG. 22 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present invention. FIGS. 23 to 26 are intermediate step drawings for explaining a method for manufacturing a semiconductor device according to several other embodiments of the present invention. FIG. 27 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present invention. Figure 28 is an enlarged view of the R4 area of ​​Figure 27. FIG. 29 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present invention. Specific details for implementing the invention

[0012] Hereinafter, a semiconductor device according to several embodiments of the present invention will be described with reference to FIGS. 1 to 4.

[0013] FIG. 1 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments of the present invention. FIG. 2 is a cross-sectional view of FIG. 1 cut along the line AA'. FIG. 3 is an enlarged view of the R1 region of FIG. 2. FIG. 4 is a cross-sectional view of FIG. 1 cut along the line BB'.

[0014] Referring to FIGS. 1 to 4, a semiconductor device according to some embodiments of the present invention comprises a substrate (100), an active pattern (101), a field insulating film (105), first to third nanosheets (NW11, NW12, NW13), a gate electrode (G1), a gate spacer (121), a gate insulating film (122), a capping pattern (123), first and second source / drain regions (131, 132), an internal spacer (140), an etch stop film (150), an interlayer insulating film (160), first and second source / drain contacts (CA1, CA2), a silicide layer (SL), and a gate contact (CB).

[0015] The substrate (100) may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate (100) may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the technical concept of the present invention is not limited thereto. In the following, the first horizontal direction (DR1) and the second horizontal direction (DR2) may each be defined as a direction parallel to the upper surface of the substrate (100). The second horizontal direction (DR2) may be defined as a direction different from the first horizontal direction (DR1). The vertical direction (DR3) may be defined as a direction perpendicular to the first horizontal direction (DR1) and the second horizontal direction (DR2), respectively. That is, the vertical direction (DR3) may be defined as a direction perpendicular to the upper surface of the substrate (100).

[0016] The active pattern (101) may extend in a first horizontal direction (DR1) on the upper surface of the substrate (100). The active pattern (101) may protrude in a vertical direction (DR3) from the upper surface of the substrate (100). For example, the active pattern (101) may be part of the substrate (100) or may include an epitaxial layer grown from the substrate (100). A field insulating film (105) may be disposed on the upper surface of the substrate (100). The field insulating film (105) may surround the sidewalls of the active pattern (101). For example, the upper surface of the active pattern (101) may protrude in a vertical direction (DR3) above the upper surface of the field insulating film (105). However, the technical concept of the present invention is not limited thereto. In some other embodiments, the upper surface of the active pattern (101) may be formed on the same plane as the upper surface of the field insulating film (105). For example, the field insulating film (105) may include an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0017] A plurality of nanosheets (NW11, NW12, NW13) may be disposed on the upper surface of the active pattern (101). For example, the plurality of nanosheets (NW11, NW12, NW13) may include a first nanosheet (NW11), a second nanosheet (NW12), and a third nanosheet (NW13) that are stacked and spaced apart from each other in the vertical direction (DR3). The first nanosheet (NW11) may be spaced apart in the vertical direction (DR3) from the upper surface of the active pattern (101). The second nanosheet (NW12) may be spaced apart in the vertical direction (DR3) from the upper surface of the first nanosheet (NW11). The third nanosheet (NW13) may be spaced apart in the vertical direction (DR3) from the upper surface of the second nanosheet (NW12). In FIG. 2, a plurality of nanosheets (NW11, NW12, NW13) are shown stacked with spaced apart from each other in the vertical direction (DR3), but the technical concept of the present invention is not limited thereto. In some other embodiments, the plurality of nanosheets may include four or more nanosheets stacked with spaced apart from each other in the vertical direction (DR3).

[0018] Each of the plurality of nanosheets (NW11, NW12, NW13) may include a first channel layer (111) and a second channel layer (112). For example, each of the first nanosheet (NW11), the second nanosheet (NW12), and the third nanosheet (NW13) may include a first channel layer (111) and a second channel layer (112). The first channel layer (111) of each of the first nanosheet (NW11), the second nanosheet (NW12), and the third nanosheet (NW13) may be spaced apart from each other in the vertical direction (DR3). Additionally, the second channel layer (112) of each of the first nanosheet (NW11), the second nanosheet (NW12), and the third nanosheet (NW13) may be spaced apart from each other in the vertical direction (DR3). The second channel layer (112) may be in contact with both side walls in the first horizontal direction (DR1) of the first channel layer (111). For example, the first channel layer (111) and the second channel layer (112) contained in the same nanosheet may be placed at the same vertical level.

[0019] For example, the lower surface of the first channel layer (111) of the first nanosheet (NW11) may be formed on the same plane as the lower surface of the second channel layer (112) of the first nanosheet (NW11). The upper surface of the first channel layer (111) of the first nanosheet (NW11) may be formed on the same plane as the upper surface of the second channel layer (112) of the first nanosheet (NW11). Additionally, the lower surface of the first channel layer (111) of the second nanosheet (NW12) may be formed on the same plane as the lower surface of the second channel layer (112) of the second nanosheet (NW12). The upper surface of the first channel layer (111) of the second nanosheet (NW12) may be formed on the same plane as the upper surface of the second channel layer (112) of the second nanosheet (NW12). The lower surface of the first channel layer (111) of the third nanosheet (NW13) may be formed on the same plane as the lower surface of the second channel layer (112) of the third nanosheet (NW13). The upper surface of the first channel layer (111) of the third nanosheet (NW13) may be formed on the same plane as the upper surface of the second channel layer (112) of the third nanosheet (NW13).

[0020] For example, the first channel layer (111) may include a first MXene material. For example, the second channel layer (112) may include a second MXene material different from the first MXene material. Here, the MXene material is a material in which a metal and carbon are combined. The MXene material may have a hydrophilic surface. As a result, the gate insulating film (122) described below can be formed more stably on the surfaces of the first channel layer (111) and the second channel layer (112), respectively, which contain the MXene material, than on the surface of a nanosheet containing only silicon (Si). For example, the second MXene material is a material formed by sulfurizing the first MXene material. In some embodiments, the first MXene material may include Hf2CO2 or Hf2COS, and the second MXene material may include Hf2CS2. In some other embodiments, the first MXene material and the second MXene material may each include a metal other than hafnium (Hf).

[0021] For example, the first MXene materials, Hf2CO2 and Hf2COS, may have a bandgap similar to silicon (Si). As a result, the first channel layer (111) containing the first MXene material can function as a channel of a semiconductor device. For example, the second MXene material, Hf2CS2, may have higher metallic properties than Hf2CO2 and Hf2COS. As a result, the second MXene material, Hf2CS2, may have a lower bandgap than Hf2CO2 and Hf2COS. Therefore, when the second channel layer (112) containing the second MXene material functions as a channel of a semiconductor device, the electrical properties of the semiconductor device can be improved.

[0022] Consequently, a semiconductor device according to some embodiments of the present invention can stably form a gate insulating film (122) on the surface of a plurality of nanosheets (NW11, NW12, NW13) by each of the plurality of nanosheets (NW11, NW12, NW13) functioning as channels, each comprising a first channel layer (111) and a second channel layer (112) containing a MXene material. Additionally, a semiconductor device according to some embodiments of the present invention may include a first channel layer (111) containing a first MXene material and a second channel layer (112) formed by the first MXene material being sulfurized, each of the plurality of nanosheets (NW11, NW12, NW13) functioning as channels. The first channel layer (111) containing the first MXene material and the second channel layer (112) containing the second MXene material may function as channels having a bandgap similar to or lower than that of silicon (Si), thereby improving the electrical characteristics of the semiconductor device.

[0023] The gate electrode (G1) may extend in a second horizontal direction (DR2) on the active pattern (101) and the field insulating film (105). The gate electrode (G1) may surround each of the first to third nanosheets (NW11, NW12, NW13). For example, the gate electrode (G1) may surround the first channel layer (111) of each of the first to third nanosheets (NW11, NW12, NW13). For example, the gate electrode (G1) is titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum It may include at least one of nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. The gate electrode (G1) may include a conductive metal oxide, a conductive metal oxynitride, etc., and may include an oxidized form of the above-described material.

[0024] The gate spacer (121) may be disposed on both sidewalls in the first horizontal direction (DR1) of the gate electrode (G1) on the upper surface of the third nanosheet (NW13) and the upper surface of the field insulating film (105). The gate spacer (121) may extend into the second horizontal direction (DR2) along both sidewalls in the first horizontal direction (DR1) of the gate electrode (G1). For example, the gate spacer (121) may be in contact with the upper surface of the second channel layer (112) of the third nanosheet (NW13). For example, the gate spacer (121) may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof. However, the technical concept of the present invention is not limited thereto.

[0025] The first source / drain region (131) may be disposed on the first side of the gate electrode (G1) on the upper surface of the active pattern (101). The second source / drain region (132) may be disposed on the second side of the gate electrode (G1) on the upper surface of the active pattern (101). Each of the first to third nanosheets (NW11, NW12, NW13) may be in contact with the first and second source / drain regions (131, 132). For example, the second channel layer (112) of each of the first to third nanosheets (NW11, NW12, NW13) may be in contact with the first and second source / drain regions (131, 132). For example, the sidewall in the first horizontal direction (DR1) of the second channel layer (112) of each of the first to third nanosheets (NW11, NW12, NW13) may be in contact with the first and second source / drain regions (131, 132).

[0026] For example, the lower surface of the second channel layer (112) of each of the first to third nanosheets (NW11, NW12, NW13) may be in contact with the first and second source / drain regions (131, 132). For example, the upper surface of the second channel layer (112) of each of the first and second nanosheets (NW11, NW12) may be in contact with the first and second source / drain regions (131, 132). For example, the sidewall in the first horizontal direction (DR1) of the first channel layer (111) of each of the first to third nanosheets (NW11, NW12, NW13) does not come into contact with the first and second source / drain regions (131, 132).

[0027] The internal spacer (140) may be disposed on both sidewalls in the first horizontal direction (DR1) of the gate electrode (G1) between the upper surface of the active pattern (101) and the lower surface of the first nanosheet (NW11). The internal spacer (140) may be disposed on both sidewalls in the first horizontal direction (DR1) of the gate electrode (G1) between the upper surface of the first nanosheet (NW11) and the lower surface of the second nanosheet (NW12). The internal spacer (140) may be disposed on both sidewalls in the first horizontal direction (DR1) of the gate electrode (G1) between the upper surface of the second nanosheet (NW12) and the lower surface of the third nanosheet (NW13). The internal spacer (140) may be disposed between the gate electrode (G1) and the first source / drain region (131). An internal spacer (140) can be placed between the gate electrode (G1) and the second source / drain region (132).

[0028] For example, the sidewall of the first horizontal direction (DR1) of the internal spacer (140) may be in contact with the first and second source / drain regions (131, 132), respectively. The internal spacer (140) may be in contact with the first to third nanosheets (NW11, NW12, NW13), respectively. For example, the internal spacer (140) may be in contact with the lower surface of the first channel layer (111) of each of the first to third nanosheets (NW11, NW12, NW13). For example, the internal spacer (140) may be in contact with the upper surface of the first channel layer (111) of each of the first and second nanosheets (NW11, NW12). In FIGS. 2 and 3, the internal spacer (140) is shown not being in contact with the first channel layer (111), but the technical concept of the present invention is not limited thereto. In some other embodiments, the internal spacer (140) may be in contact with the upper and lower surfaces of the first channel layer (111). For example, the internal spacer (140) may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonate (SiOC), and combinations thereof. However, the technical concept of the present invention is not limited thereto.

[0029] A gate insulating film (122) may be placed between a gate electrode (G1) and a gate spacer (121). A gate insulating film (122) may be placed between a gate electrode (G1) and an active pattern (101). A gate insulating film (122) may be placed between a gate electrode (G1) and a field insulating film (105). A gate insulating film (122) may be placed between a gate electrode (G1) and the first channel layer (111) of each of the first to third nanosheets (NW11, NW12, NW13). For example, a gate insulating film (122) may be in contact with the first channel layer (111). A gate insulating film (122) may be placed between a gate electrode (G1) and an internal spacer (140). For example, a gate insulating film (122) may be in contact with the internal spacer (140). For example, the gate insulating film (122) may be spaced apart from the first and second source / drain regions (131, 132) respectively and in the first horizontal direction (DR1).

[0030] For example, the gate insulating film (122) may include at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. High dielectric constant materials may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0031] A semiconductor device according to some other embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating film (122) may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0032] Ferroelectric film materials can have negative capacitance, while paraelectric film materials can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance will be smaller than the capacitance of each individual capacitor. Conversely, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance will have a positive value and may be greater than the absolute value of each individual capacitance.

[0033] When a ferroelectric material film having negative capacitance and a paraelectric material film having positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor containing a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0034] Ferroelectric material films may have ferroelectric properties. Ferroelectric material films may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0035] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

[0036] When the ferroelectric material film contains hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0037] When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0038] When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% zirconium.

[0039] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0040] Ferroelectric and paraelectric film layers may contain the same material. Ferroelectric film layers possess ferroelectric properties, whereas paraelectric film layers may not. For example, if both ferroelectric and paraelectric film layers contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric film layer is different from the crystal structure of the hafnium oxide contained in the paraelectric film layer.

[0041] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness at which ferroelectric properties are exhibited may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0042] For example, the gate insulating film (122) may include a single ferroelectric material film. For another example, the gate insulating film (122) may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating film (122) may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0043] The etch stop layer (150) may be disposed on the sidewall of the first horizontal direction (DR1) of the gate spacer (121). The etch stop layer (150) may be disposed on the upper surface of each of the first and second source / drain regions (131, 132). Although not illustrated, the etch stop layer (150) may be disposed on the upper surface of the field insulating film (105). Additionally, although not illustrated, the etch stop layer (150) may be disposed on both sidewalls of the second horizontal direction (DR2) of each of the first and second source / drain regions (131, 132). For example, the etch stop layer (150) may be formed conformally. For example, the etch stop layer (150) may comprise at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0044] The capping pattern (123) may extend in a second horizontal direction (DR2) over each of the gate spacer (121), gate insulating film (122), gate electrode (G1), and etch stop film (150). For example, the lower surface of the capping pattern (123) may be in contact with the etch stop film (150). However, the technical concept of the present invention is not limited thereto. In some other embodiments, the sidewall of the capping pattern (123) may be in contact with the etch stop film (150). For example, the capping pattern (123) may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof. However, the technical concept of the present invention is not limited thereto.

[0045] An interlayer insulating film (160) may be disposed on an etch stop film (150). The interlayer insulating film (160) may surround the sidewalls of the capping pattern (123). For example, the upper surface of the interlayer insulating film (160) may be formed coplanar with the upper surface of the capping pattern (123). For example, the interlayer insulating film (160) may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Low-k materials include, for example, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethylCycloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB), DiAcetoxyDitertiaryButoxySiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polyimide nanofoams such as polypropylene oxide, CDO (Carbon Doped silicon Oxide), OSG (Organo Silicate) Glass), SiLK, Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, It may include mesoporous silica or a combination thereof, but the technical concept of the present invention is not limited thereto.

[0046] A first source / drain contact (CA1) may be disposed on a first source / drain region (131). The first source / drain contact (CA1) may be electrically connected to the first source / drain region (131) by penetrating the interlayer insulating film (160) and the etch stop film (150) in a vertical direction (DR3). A second source / drain contact (CA2) may be disposed on a second source / drain region (132). The second source / drain contact (CA2) may be electrically connected to the second source / drain region (132) by penetrating the interlayer insulating film (160) and the etch stop film (150) in a vertical direction (DR3). Each of the first and second source / drain contacts (CA1, CA2) may include a conductive material. The silicide layer (SL) may be disposed along the interface between the first source / drain contact (CA1) and the first source / drain region (131). Additionally, the silicide layer (SL) may be disposed along the interface between the second source / drain contact (CA2) and the second source / drain region (132). For example, the silicide layer (SL) may comprise a metal silicide material. The gate contact (CB) may be connected to the gate electrode (G1) by penetrating the capping pattern (123) in a vertical direction (DR3). The gate contact (CB) may comprise a conductive material.

[0047] Hereinafter, a method for manufacturing a semiconductor device according to some embodiments of the present invention will be described with reference to FIGS. 2 to 16.

[0048] FIGS. 5 to 16 are intermediate step drawings for explaining a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0049] Referring to FIGS. 5 and 6, a stacked structure (10) may be formed on a substrate (100). The stacked structure (10) may include a sacrificial layer (11) and a first layer (12) alternately stacked on the substrate (100). For example, a sacrificial layer (11) may be formed at the bottom of the stacked structure (10), and a first layer (12) may be formed at the top of the stacked structure (10). However, the technical concept of the present invention is not limited thereto. In some other embodiments, the sacrificial layer (11) may be formed at the top of the stacked structure (10). For example, the sacrificial layer (11) may include silicon germanium (SiGe). For example, the first layer (12) may include a first MXene material. For example, the first MXene material may include Hf2CO2 or Hf2COS. That is, the first layer (12) may contain the same material as the first channel layer (111) shown in FIGS. 2 to 4.

[0050] Next, a portion of the stacked structure (10) may be etched. While the stacked structure (10) is being etched, a portion of the substrate (100) may also be etched. Through this etching process, an active pattern (101) may be defined on the lower portion of the stacked structure (10) on the upper surface of the substrate (100). The active pattern (101) may extend in a first horizontal direction (DR1). Next, a field insulating film (105) may be formed on the upper surface of the substrate (100). The field insulating film (105) may surround the sidewalls of the active pattern (101). For example, the upper surface of the active pattern (101) may be formed higher than the upper surface of the field insulating film (105). Subsequently, a pad oxide film (20) may be formed to cover the upper surface of the field insulating film (105), the sidewall of the exposed active pattern (101), and the sidewall and upper surface of the stacked structure (10). For example, the pad oxide film (20) may be formed conformally. The pad oxide film (20) may include, for example, silicon oxide (SiO2).

[0051] Referring to FIGS. 7 and 8, a dummy gate (DG) and a dummy capping pattern (DC) extending in a second horizontal direction (DR2) can be formed on a pad oxide film (20) on a stacked structure (10) and a field insulating film (105). The dummy capping pattern (DC) can be placed on the dummy gate (DG). While the dummy gate (DG) and the dummy capping pattern (DC) are being formed, the remaining pad oxide film (20) can be removed, except for the portion that overlaps with the dummy gate (DG) in a vertical direction (DR3) on the substrate (100).

[0052] Subsequently, a spacer material layer (SM) may be formed to cover the sidewall of the dummy gate (DG), the sidewall and top surface of each dummy capping pattern (DC), the sidewall and top surface of the exposed stacked structure (10), and the top surface of the field insulating film (105). For example, the spacer material layer (SM) may be formed conformally. For example, the spacer material layer (SM) may include at least one of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon carbonitride (SiCN), silicon oxynitride (SiON), and combinations thereof.

[0053] Referring to FIG. 9, a stacked structure (10 in FIG. 7 and 8) can be etched using a dummy gate (DG) and a dummy capping pattern (DC) as a mask to form first and second source / drain trenches (ST1, ST2), respectively. For example, the first source / drain trench (ST1) can be formed on the first side of the stacked structure (10 in FIG. 7 and 8), and the second source / drain trench (ST2) can be formed on the second side of the stacked structure (10 in FIG. 7 and 8). For example, while the first and second source / drain trenches (ST1, ST2), respectively are being formed, the sacrificial layer (11) can be etched further in the first horizontal direction (DR1) than the first layer (12). That is, the sidewall in the first horizontal direction (DR1) of the remaining sacrificial layer (11) may be formed concavely toward the center of the remaining sacrificial layer (11) compared to the sidewall in the first horizontal direction (DR1) of the remaining first layer (12). For example, while the first and second source / drain trenches (ST1, ST2) are each formed, a portion of the spacer material layer (SM in FIG. 7 and 8) formed on the upper surface of the dummy capping pattern (DC) and the dummy capping pattern (DC) may be etched. For example, after the first and second source / drain trenches (ST1, ST2) are each formed, the spacer material layer (SM in FIG. 7 and 8) remaining on the sidewalls of the dummy capping pattern (DC) and the dummy gate (DG) may be defined as a gate spacer (121).

[0054] Referring to FIG. 10, internal spacers (140) may be formed on both side walls in the first horizontal direction (DR1) of the sacrificial layer (11). For example, internal spacers (140) may be formed on both side walls in the first horizontal direction (DR1) of the sacrificial layer (11) remaining between the upper surface of the active pattern (101) and the lower surface of the lowest first layer (12). Additionally, internal spacers (140) may be formed on both side walls in the first horizontal direction (DR1) of the sacrificial layer (11) remaining between adjacent first layers (12) in the vertical direction (DR3). For example, the first horizontal sidewall (DR1) of the internal spacer (140) exposed through each of the first and second source / drain trenches (ST1, ST2) may be formed concavely toward the center of the remaining sacrificial layer (11) than the first horizontal sidewall (DR1) of the remaining first layer (12).

[0055] Referring to FIG. 11, a portion of the remaining first layer (12 in FIG. 10) exposed through each of the first and second source / drain trenches (ST1, ST2) may be sulfurized to form first to third nanosheets (NW11, NW12, NW13). For example, the first layer (12 in FIG. 10) remaining unsulfurized may be defined as the first channel layer (111), and the layer formed by sulfurizing a portion of the first layer (12 in FIG. 10) may be defined as the second channel layer (112). That is, the first channel layer (111) may contain a first MXene material, and the second channel layer (112) may contain a second MXene material formed by sulfurizing the first MXene material. The second channel layer (112) may be exposed through the first and second source / drain trenches (ST1, ST2), respectively. For example, the second channel layer (112) may be in contact with both side walls in the first horizontal direction (DR1) of the first channel layer (111).

[0056] Referring to FIG. 12, a first source / drain region (131) may be formed inside a first source / drain trench (ST1 in FIG. 11), and a second source / drain region (132) may be formed inside a second source / drain trench (ST2 in FIG. 11). For example, each of the first and second source / drain regions (131, 132) may be in contact with a second channel layer (112) and an internal spacer (140). Subsequently, an etch stop layer (150) may be formed on the surface of each of the first and second source / drain regions (131, 132) and on the sidewall of the gate spacer (121). For example, the etch stop layer (150) may be formed conformally. Subsequently, an interlayer insulating film (160) may be formed on the etch stop layer (150). Next, a planarization process can be performed to expose the upper surface of the dummy gate (DG).

[0057] Referring to FIGS. 13 and 14, a dummy gate (DG in FIG. 12), a pad oxide (20 in FIG. 12), and a sacrificial layer (11 in FIG. 12) can each be etched. For example, the portion where the dummy gate (DG in FIG. 12), the pad oxide (20 in FIG. 12), and the sacrificial layer (11 in FIG. 12) are removed can be defined as a gate trench (GT).

[0058] Referring to FIGS. 15 and 16, a gate insulating film (122), a gate electrode (G1), and a capping pattern (123) may be sequentially formed inside a gate trench (GT of FIG. 13). The gate electrode (G1) may surround each of the first to third nanosheets (NW11, NW12, NW13). For example, the gate insulating film (122) may be in contact with the sidewall of the first horizontal direction (DR1) of the internal spacer (140).

[0059] Referring to FIGS. 2 to 4, a gate contact (CB) connected to a gate electrode (G1) can be formed by penetrating the capping pattern (123) in the vertical direction (DR3). Additionally, a first source / drain contact (CA1) electrically connected to a first source / drain region (131) can be formed by penetrating the interlayer insulating film (160) and the etching stop film (150) in the vertical direction (DR3). A second source / drain contact (CA2) electrically connected to a second source / drain region (132) can be formed by penetrating the interlayer insulating film (160) and the etching stop film (150) in the vertical direction (DR3). Additionally, a silicide layer (SL) may be formed on the interface between the first source / drain contact (CA1) and the first source / drain region (131) and on the interface between the second source / drain contact (CA2) and the second source / drain region (132). Through this manufacturing process, the semiconductor device illustrated in FIGS. 2 to 4 can be manufactured.

[0060] Hereinafter, a semiconductor device according to several other embodiments of the present invention will be described with reference to FIGS. 17 and 18. The description will focus on the differences from the semiconductor device illustrated in FIGS. 1 to 4.

[0061] FIG. 17 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present invention. FIG. 18 is an enlarged view of the R2 region of FIG. 17.

[0062] Referring to FIGS. 17 and 18, in a semiconductor device according to some other embodiments of the present invention, at least a portion of the internal spacer (140) may overlap with the second channel layer (212) in a vertical direction (DR3).

[0063] For example, each of the first to third nanosheets (NW21, NW22, NW23) may include a first channel layer (211) and a second channel layer (212). For example, the lower and upper surfaces of the second channel layer (212) of each of the first to third nanosheets (NW21, NW22, NW23) may be in contact with an internal spacer (140).

[0064] Hereinafter, a semiconductor device according to several other embodiments of the present invention will be described with reference to FIG. 19. The description will focus on the differences from the semiconductor device illustrated in FIG. 1 to 4.

[0065] FIG. 19 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present invention.

[0066] Referring to FIG. 19, a semiconductor device according to another embodiment of the present invention does not have an internal spacer.

[0067] For example, between the upper surface of the active pattern (101) and the lower surface of the first nanosheet (NW11), each of the first and second source / drain regions (331, 332) may be in contact with the gate insulating film (122). Between the upper surface of the first nanosheet (NW11) and the lower surface of the second nanosheet (NW12), each of the first and second source / drain regions (331, 332) may be in contact with the gate insulating film (122). Between the upper surface of the second nanosheet (NW12) and the lower surface of the third nanosheet (NW13), each of the first and second source / drain regions (331, 332) may be in contact with the gate insulating film (122).

[0068] Hereinafter, a semiconductor device according to several other embodiments of the present invention will be described with reference to FIGS. 20 to 22. The description will focus on the differences from the semiconductor device illustrated in FIGS. 1 to 4.

[0069] FIG. 20 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention. FIG. 21 is an enlarged view of the R3 region of FIG. 20. FIG. 22 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

[0070] Referring to FIGS. 20 to 22, a semiconductor device according to another embodiment of the present invention may have each of the first to third nanosheets (NW41, NW42, NW43) including a first channel layer (411), a second channel layer (412), and a third channel layer (413).

[0071] For example, the first nanosheet (NW41) may include two first channel layers (411) spaced apart in the vertical direction (DR3) and two second channel layers (412) spaced apart in the vertical direction (DR3). Additionally, the first nanosheet (NW41) may include a third channel layer (413) disposed between the two first channel layers (411) and between the two second channel layers (412). The first channel layer (411) may be in contact with both side walls in the first horizontal direction (DR1) of the second channel layer (412). For example, the upper and lower surfaces of the third channel layer (413) may each be in contact with the first channel layer (411) and the second channel layer (412), respectively. That is, the upper surface of the lower first channel layer (411) and the upper surface of the lower second channel layer (412) can be in contact with the lower surface of the third channel layer (413). Additionally, the lower surface of the upper first channel layer (411) and the lower surface of the upper second channel layer (412) can be in contact with the upper surface of the third channel layer (413). For example, both side walls in the first horizontal direction (DR1) of the third channel layer (413) can be in contact with the first and second source / drain regions (131, 132). For example, both side walls in the second horizontal direction (DR2) of the third channel layer (413) can be in contact with the gate insulating film (122). For example, the third channel layer (413) does not come into contact with the internal spacer (140). That is, the third channel layer (413) can be spaced apart from the internal spacer (140) in the vertical direction (DR3).

[0072] For example, the sidewall in the first horizontal direction (DR1) of the third channel layer (413) may have a continuous slope profile with the sidewall in the first horizontal direction (DR1) of the second channel layer (412). For example, the sidewall in the second horizontal direction (DR2) of the third channel layer (413) may have a continuous slope profile with the sidewall in the second horizontal direction (DR2) of the first channel layer (411). For example, the third channel layer (413) may include a material different from that of the first channel layer (411) and the second channel layer (412), respectively. In some embodiments, the third channel layer (413) may include a TMD (Transition Metal Dichalcogenides) material. For example, the third channel layer (413) may include MoS2, MoSe2, WS2, WSe2, HfS2, or HfSe2. In some other embodiments, the third channel layer (413) may include silicon (Si). For example, the second nanosheet (NW42) and the third nanosheet (NW43) may each have the same structure as the first nanosheet (NW41).

[0073] Hereinafter, a method for manufacturing a semiconductor device according to several other embodiments of the present invention will be described with reference to FIGS. 20 to 26. The description will focus on the differences from the method for manufacturing a semiconductor device illustrated in FIGS. 5 to 16.

[0074] FIGS. 23 to 26 are intermediate step drawings for explaining a method for manufacturing a semiconductor device according to several other embodiments of the present invention.

[0075] Referring to FIGS. 23 and 24, a stacked structure (40) may be formed on a substrate (100). The stacked structure (40) may include a sacrificial layer (11), a first layer (42), a second layer (43), and a first layer (42) sequentially stacked on the substrate (100). For example, a sacrificial layer (11) may be formed at the bottom of the stacked structure (40), and a first layer (42) may be formed at the top of the stacked structure (40). However, the technical concept of the present invention is not limited thereto. In some other embodiments, the sacrificial layer (11) may be formed at the top of the stacked structure (40).

[0076] For example, the sacrificial layer (11) may include silicon germanium (SiGe). For example, the first layer (42) may include a first MXene material. For example, the first MXene material may include Hf2CO2 or Hf2COS. That is, the first layer (42) may include the same material as the first channel layer (411) shown in FIGS. 20 to 22. The second layer (43) may include a different material from the first layer (42). For example, the second layer (43) may include a TMD (Transition Metal Dichalcogenides) material. That is, the second layer (43) may include the same material as the third channel layer (413) shown in FIGS. 20 to 22.

[0077] Next, a portion of the stacked structure (40) may be etched. While the stacked structure (40) is being etched, a portion of the substrate (100) may also be etched. Through this etching process, an active pattern (101) may be defined on the lower portion of the stacked structure (40) on the upper surface of the substrate (100). The active pattern (101) may extend in a first horizontal direction (DR1). Subsequently, a field insulating film (105) may be formed on the upper surface of the substrate (100). The field insulating film (105) may surround the sidewalls of the active pattern (101). For example, the upper surface of the active pattern (101) may be formed higher than the upper surface of the field insulating film (105). Subsequently, a pad oxide film (20) may be formed to cover the upper surface of the field insulating film (105), the sidewall of the exposed active pattern (101), and the sidewall and upper surface of the stacked structure (40). For example, the pad oxide film (20) may be formed conformally. The pad oxide film (20) may include, for example, silicon oxide (SiO2).

[0078] Referring to FIG. 25, after additionally performing the manufacturing process illustrated in FIG. 7 to 9, an internal spacer (140) may be formed on both side walls in the first horizontal direction (DR1) of the remaining sacrificial layer (11).

[0079] Referring to FIG. 26, a portion of the remaining first layer (42 in FIG. 25) exposed through each of the first and second source / drain trenches (ST1, ST2) may be sulfurized to form first to third nanosheets (NW41, NW42, NW43). For example, the first layer (42 in FIG. 25) remaining unsulfurized may be defined as the first channel layer (411), and the layer formed by sulfurizing a portion of the first layer (42 in FIG. 25) may be defined as the second channel layer (412). That is, the first channel layer (411) may contain a first MXene material, and the second channel layer (412) may contain a second MXene material formed by sulfurizing the first MXene material.

[0080] Additionally, the remaining second layer (43 in FIG. 25) may be defined as a third channel layer (413). That is, the third channel layer (413) may contain the same material as the second layer (43 in FIG. 25). The third channel layer (413) may contain a different material from the first channel layer (411) and the second channel layer (412), respectively. The second channel layer (412) and the third channel layer (413), respectively, may be exposed through the first and second source / drain trenches (ST1, ST2), respectively. For example, the second channel layer (412) may be in contact with both side walls in the first horizontal direction (DR1) of the first channel layer (411).

[0081] Referring to FIGS. 20 to 22, after additionally performing the manufacturing process illustrated in FIGS. 12 to 16, a gate contact (CB), first and second source / drain contacts (CA1, CA2), and a silicide layer (SL) may be formed. Through this manufacturing process, a semiconductor device illustrated in FIGS. 20 to 22 may be manufactured.

[0082] Hereinafter, a semiconductor device according to several other embodiments of the present invention will be described with reference to FIGS. 27 and 28. The description will focus on the differences from the semiconductor device shown in FIGS. 20 to 22.

[0083] FIG. 27 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention. FIG. 28 is an enlarged view of the R4 region of FIG. 27.

[0084] Referring to FIGS. 27 and 28, in a semiconductor device according to some other embodiment of the present invention, at least a portion of the internal spacer (140) may overlap with the second channel layer (512) in a vertical direction (DR3).

[0085] For example, each of the first to third nanosheets (NW51, NW52, NW53) may include a first channel layer (511), a second channel layer (512), and a third channel layer (413). For example, the bottom surface and the top surface of the second channel layer (212) of each of the first to third nanosheets (NW51, NW52, NW53) may be in contact with an internal spacer (140).

[0086] Hereinafter, a semiconductor device according to several other embodiments of the present invention will be described with reference to FIG. 29. The description will focus on the differences from the semiconductor device illustrated in FIG. 20 to 22.

[0087] FIG. 29 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present invention.

[0088] Referring to FIG. 29, a semiconductor device according to another embodiment of the present invention does not have an internal spacer.

[0089] For example, between the upper surface of the active pattern (101) and the lower surface of the first nanosheet (NW41), each of the first and second source / drain regions (631, 632) may be in contact with the gate insulating film (122). Between the upper surface of the first nanosheet (NW41) and the lower surface of the second nanosheet (NW42), each of the first and second source / drain regions (631, 632) may be in contact with the gate insulating film (122). Between the upper surface of the second nanosheet (NW42) and the lower surface of the third nanosheet (NW43), each of the first and second source / drain regions (631, 632) may be in contact with the gate insulating film (122).

[0090] Although embodiments according to the technical concept of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0091] 100: Substrate 101: Active Pattern 105: Field insulation film NW11, NW12, NW13: 1st to 3rd nanosheets 111: 1st channel layer 112: Second channel layer G1: Gate electrode 121: Gate Spacer 122: Gate insulating film 123: Capping pattern 131, 132: 1st and 2nd source / drain regions 140: Internal spacer 150: Etching stop layer 160: Interlayer insulation film CB: Gate Contact CA1, CA2: 1st and 2nd source / drain contacts SL: Silicide layer

Claims

Claim 1 A semiconductor device comprising: a substrate; an active pattern extending in a first horizontal direction on the substrate; a first nanosheet spaced perpendicularly from the upper surface of the active pattern; a second nanosheet spaced perpendicularly from the upper surface of the first nanosheet; a gate electrode extending in a second horizontal direction different from the first horizontal direction on the upper surface of the active pattern and surrounding the first and second nanosheets; and a source / drain region disposed on at least one side of the gate electrode on the upper surface of the active pattern and in contact with each of the first and second nanosheets, wherein each of the first and second nanosheets is surrounded by the gate electrode and comprises a first channel layer containing a first MXene material; and a second channel layer in contact with the sidewall in the first horizontal direction of the first channel layer and comprising a second MXene material different from the first MXene material. Claim 2 A semiconductor device according to claim 1, wherein the second MXene material is a material formed by the first MXene material being sulfurized. Claim 3 A semiconductor device according to claim 2, wherein the first MXene material comprises Hf2CO2 or Hf2COS, and the second MXene material comprises Hf2CS2. Claim 4 A semiconductor device according to claim 1, further comprising an internal spacer disposed on the first horizontal sidewall of the gate electrode, in contact with the uppermost surface of the first channel layer of the first nanosheet and the lowermost surface of the first channel layer of the second nanosheet, respectively. Claim 5 A semiconductor device according to claim 1, wherein each of the first and second nanosheets comprises: two first channel layers spaced apart in the vertical direction; two second channel layers spaced apart in the vertical direction; and a third channel layer disposed between the two first channel layers and between the two second channel layers, and comprising a material different from each of the first and second channel layers. Claim 6 In claim 5, the upper and lower surfaces of the third channel layer, respectively, are in contact with the first and second channel layers, respectively. Claim 7 A semiconductor device according to claim 5, further comprising a gate insulating film disposed between each of the first and second nanosheets and the gate electrode, and in contact with the second horizontal sidewall of the third channel layer. Claim 8 A semiconductor device comprising: a substrate; an active pattern extending in a first horizontal direction on the substrate; a first nanosheet spaced perpendicularly from the upper surface of the active pattern; a gate electrode extending in a second horizontal direction different from the first horizontal direction on the upper surface of the active pattern and surrounding the first nanosheet; and an internal spacer disposed on the sidewall of the gate electrode in the first horizontal direction between the upper surface of the active pattern and the lower surface of the first nanosheet, wherein the first nanosheet comprises: a first channel layer surrounded by the gate electrode and comprising a first MXene material, at least a portion of which is in contact with the internal spacer; and a second channel layer in contact with the sidewall of the first channel layer in the first horizontal direction and comprising a second MXene material different from the first MXene material. Claim 9 A semiconductor device according to claim 8, further comprising a source / drain region disposed on at least one side of the gate electrode on the upper surface of the active pattern and in contact with the sidewall of the internal spacer and the lowest surface of the second channel layer between the upper surface of the active pattern and the lower surface of the first nanosheet. Claim 10 In claim 8, at least a portion of the internal spacer overlaps the second channel layer in the vertical direction in a semiconductor device.

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