Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device is provided, comprising: a semiconductor substrate; a first stacked structure comprising a first material layer and a second material layer having different refractive indices and arranged alternately multiple times along a first direction on the semiconductor substrate, wherein a plurality of through holes are formed in the first direction; and a first anti-reflective layer disposed on the first stacked structure, comprising a first anti-reflective material and having a plurality of first pattern holes formed that are each connected to the plurality of through holes of the first stacked structure, wherein the light reflectance of the first anti-reflective layer is 25% or less.

Description

Technology Field

[0001] The disclosed embodiments relate to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Recently, starting with VNAND, memory devices have been evolving into forms where 3D memory cell structures are stacked in multiple layers. Measuring the structure, such as thickness or physical properties, of the thin films used in forming these multi-stack structures during the manufacturing process is essential for ensuring the performance of memory devices. Accordingly, internal measurement inspection methods for increasingly deep 3D memory structures are being sought. The problem to be solved

[0003] A semiconductor device having a structure capable of non-destructive testing during the manufacturing process and a method for manufacturing the same are provided. means of solving the problem

[0004] According to an embodiment, a semiconductor device is provided, comprising: a semiconductor substrate; a first stacked structure having a first material layer and a second material layer having different refractive indices and arranged alternately a plurality of times along a first direction on the semiconductor substrate, and a plurality of through holes formed in the first direction; and a first anti-reflective layer arranged on the first stacked structure, comprising a first anti-reflective material and having a plurality of first pattern holes formed that are each connected to the plurality of through holes of the first stacked structure, wherein the light reflectance of the first anti-reflective layer is 25% or less.

[0005] The average refractive index, n_eff_1, of the first anti-reflective layer is given by the following conditions:

[0006] 0.9* (n_eff_st1) 1 / 2 ≤ n_eff_1 ≤1.2* (n_eff_st1) 1 / 2

[0007] It can satisfy, where n_eff_st1 is the average refractive index of the first stacked structure.

[0008] The thickness of the first anti-reflective layer may be 80 nm or more and 200 nm or less.

[0009] The through hole formed in the first laminated structure and the first pattern hole formed in the first non-reflective layer may have the same width.

[0010] The first material layer comprises silicon oxide, and the second material layer may comprise silicon nitride.

[0011] The first anti-reflective material may include a material contained in the first material layer or the second material layer.

[0012] The above through hole may be cylindrical or slit-shaped.

[0013] The period in which the first material layer and the second material layer are alternately stacked may be 50 nm or less.

[0014] The arrangement period of the above plurality of through holes may be 200 nm or less.

[0015] The semiconductor device may further include: a second stacked structure disposed on the first non-reflective layer and comprising alternatingly stacked third and fourth material layers and having a plurality of through holes formed therein; a second non-reflective layer disposed between the first non-reflective layer and the second stacked structure, comprising a second non-reflective material and having a plurality of second pattern holes formed therein; and a third non-reflective layer disposed on the second stacked structure, comprising a third non-reflective material and having a plurality of third pattern holes formed therein.

[0016] The average refractive index, n_eff_2, of the above second anti-reflective layer is under the following conditions,

[0017] 1.0* (n_eff_st2) 1 / 2 ≤ n_eff_2 ≤1.2* (n_eff_st2) 1 / 2

[0018] It can satisfy, where n_eff_st2 is the average refractive index of the second stacked structure.

[0019] The average refractive index of the third anti-reflective layer, n_eff_3, is given by the following conditions:

[0020] 0.9* (n_eff_st2) 1 / 2 ≤ n_eff_3 ≤1.2* (n_eff_st2) 1 / 2

[0021] It can satisfy, where n_eff_st2 is the average refractive index of the second stacked structure.

[0022] The width of the second pattern hole may be less than or equal to the width of the first pattern hole.

[0023] The thickness of the second anti-reflective layer may be less than or equal to the thickness of the first anti-reflective layer.

[0024] The third material layer comprises silicon oxide, and the fourth material layer may comprise silicon nitride.

[0025] The first anti-reflective material and the second anti-reflective material may include the same material.

[0026] According to an embodiment, a semiconductor device is provided comprising: a plurality of memory blocks; and an anti-reflective layer disposed on the plurality of memory blocks, forming a pattern made of two or more materials having different refractive indices and having a first thickness, wherein each of the plurality of memory blocks includes a plurality of memory elements arranged along a first direction, and the plurality of memory blocks are arranged along a second direction perpendicular to the first direction, and the anti-reflective layer has a light reflectance of 25% or less.

[0027] According to an embodiment, a method for manufacturing a semiconductor device is provided, comprising the steps of: forming a stacked material layer by alternately stacking a first material layer and a second material layer with different refractive indices multiple times along a first direction; forming an anti-reflective material layer on the stacked material layer; and forming a through hole penetrating the anti-reflective material layer and the stacked material layer to form an anti-reflective layer and a stacked structure, wherein the material and thickness of the anti-reflective material layer are determined such that the reflectance of the anti-reflective layer is 25% or less.

[0028] The average refractive index, n_eff_1, of the above anti-reflective layer is given by the following conditions,

[0029] 0.9* (n_eff_st1) 1 / 2 ≤ n_eff_1 ≤1.2* (n_eff_st1) 1 / 2

[0030] It can satisfy the above, where n_eff_st1 is the average refractive index of the stacked structure.

[0031] The above semiconductor device manufacturing method may further include the step of forming a memory element within the through hole. Effects of the invention

[0032] The semiconductor device described above has a structure that enables optical non-destructive inspection of the three-dimensional stacked structure during the process of manufacturing a memory device having a three-dimensional stacked structure.

[0033] According to the semiconductor device manufacturing method described above, a semiconductor device with a low defect rate can be manufactured. Brief explanation of the drawing

[0034] FIG. 1 is a conceptual diagram illustrating the schematic configuration of a semiconductor device according to an embodiment and a non-destructive inspection method for the same. FIG. 2 is a perspective view showing the schematic configuration of a semiconductor device according to an embodiment. Figure 3 is a cross-sectional view of AA of Figure 2. Figure 4 is a graph showing the thickness of the anti-reflective layer provided in a semiconductor device according to an embodiment and the reflectance according to the wavelength of incident light. FIG. 5 is a cross-sectional view showing the schematic configuration of a semiconductor device according to another embodiment. FIGS. 6 to 8 are graphs showing the reflectance according to the wavelength of incident light and the thickness of the first, second, and third anti-reflective layers provided in the semiconductor device according to the embodiment of FIG. 5. FIG. 9 is a perspective view showing a schematic configuration of a semiconductor device according to another embodiment. FIG. 10 is a flowchart schematically illustrating a method for manufacturing a semiconductor device according to an embodiment. Specific details for implementing the invention

[0035] Hereinafter, embodiments will be described in detail with reference to the attached drawings. The described embodiments are merely illustrative, and various modifications are possible from these embodiments. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of explanation.

[0036] In the following, terms described as "upper" or "upper" may include not only those directly above in contact, but also those above without contact.

[0037] Terms such as first, second, etc., may be used to describe various components, but are used solely for the purpose of distinguishing one component from another. These terms do not limit the difference in the material or structure of the components.

[0038] A singular expression includes a plural expression unless the context clearly indicates otherwise. Furthermore, when a part is said to "include" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0039] Additionally, terms such as “...part,” “module,” etc., as described in the specification refer to a unit that processes at least one function or operation, and this may be implemented in hardware or software, or as a combination of hardware and software.

[0040] The use of the term “above” and similar descriptive terms may apply to both the singular and plural.

[0041] Unless there is an explicit statement that the steps constituting the method must be performed in the described order, they may be performed in a suitable order. Furthermore, the use of all exemplary terms (e.g., etc.) is merely intended to describe the technical concept in detail and, unless limited by the claims, such terms do not limit the scope of the rights.

[0042] FIG. 1 is a conceptual diagram illustrating the schematic configuration of a semiconductor device according to an embodiment and a non-destructive inspection method for the same.

[0043] The semiconductor device (SD) includes a semiconductor substrate (SU), a stacked structure (ST), and an anti-reflective layer (AR).

[0044] The stacked structure (ST) includes various material layers and patterns used in the process of forming memory elements that are stacked three-dimensionally. The stacked structure (ST) may include, for example, material layers having two or more different refractive indices, and these material layers may have fine shape dimensions in the range of tens to hundreds of nanometers.

[0045] An anti-reflective layer (AR) is provided to allow the interior of the laminated structure (ST) to be inspected by a non-destructive optical method, that is, to allow light irradiated from the optical transmitter to enter the interior of the laminated structure (ST). The reflectance of the anti-reflective layer (AR) may have a very small value close to zero. The reflectance of the anti-reflective layer (AR) may be 25% or less, 20% or less, 10% or less, or 5% or less. This reflectance refers to the reflectance with respect to the wavelength of light provided by the optical transmitter.

[0046] The anti-reflective layer (AR) may have a three-dimensional pattern composed of materials having two or more different refractive indices. The material, pattern, or thickness of the anti-reflective layer (AR) may be determined to suit the light reflectance described above, and the effective refractive index formed by the stacked structure (ST) may be taken into account. The thickness of the anti-reflective layer (AR) may be set based on a value corresponding to one-quarter of the wavelength of the light provided by the optical transmitter. For example, it may be 90% to 110% or 80% to 120% of one-quarter wavelength, provided that this is exemplary and not limited thereto. When the light provided by the optical transmitter is in the visible light or near-infrared wavelength band, the thickness of the anti-reflective layer (AR) may be in the range of approximately 80 nm to 200 nm.

[0047] When measuring the three-dimensional structure inside a stacked structure (ST) by an optical method, a method may be used in which light is supplied into the stacked structure (ST) and then changes in the phase distribution of the light emitted after passing through the stacked structure (ST). For optical inspection, an inspection device including an optical transmitter, an optical receiver, and an analysis unit may be used, as illustrated. That is, light supplied from the optical transmitter is incident on the stacked structure (ST), emitted after passing through the three-dimensional internal structure of the stacked structure (ST), and received by the optical receiver. In the analysis unit, the internal structure of the stacked structure (ST) can be analyzed by analyzing the phase delay of the light received by the optical receiver.

[0048] The light provided by the optical transmitter may be in the visible light or near-infrared wavelength band. The wavelength of the light used can be appropriately selected considering the reflectivity of the anti-reflective layer (AR).

[0049] During such optical inspection, a stacked structure (ST) containing multiple materials having a refractive index greater than 1 can provide Fabry-Perot resonance conditions for the light used for measurement. This resonance can degrade the resolution of the phase image for the light passing through the stacked structure (ST) and lower the SNR of the detection signal.

[0050] The anti-reflective layer (AR) provided in the semiconductor device (SD) according to the embodiment can have the effect of removing one of the reflective surfaces that provide such Fabry-Perot resonance, and accordingly, the accuracy of three-dimensional structure measurement can be improved.

[0051] In FIG. 1, an anti-reflective layer (AR) is shown as being provided on the upper part of the laminated structure (ST), but this is exemplary, and the anti-reflective layer (AR) may also be placed inside the laminated structure (ST), and the number may be changed to various multiple layers. The laminated structure (ST) may include a structure with a high aspect ratio, and for effective measurement, for example, after the measurement in the illustrated step is completed, additional laminated structures and anti-reflective layers may be formed, and the process of optically inspecting the added structures may be repeated.

[0052] FIG. 2 is a perspective view showing a schematic configuration of a semiconductor device according to an embodiment, and FIG. 3 is a cross-sectional view AA of FIG. 2.

[0053] A semiconductor device (1000) includes a semiconductor substrate (SU), a stacked structure (200) disposed on the semiconductor substrate (100), and an anti-reflective layer (300) disposed on the stacked structure (200).

[0054] The semiconductor substrate (100) may include various semiconductor materials. The semiconductor substrate (100) may include a silicon material and may include a silicon material doped with a p-type or n-type dopant. The semiconductor substrate (100) may provide a common source region for a semiconductor channel to be formed in a through-hole (HS) within a stacked structure (200).

[0055] A stacked structure (200) is a structure used in the process of forming a plurality of memory elements arranged along a first direction (Z direction). The stacked structure (200) includes a first material layer (10) and a second material layer (20) arranged along the first direction (Z direction). The first material layer (10) and the second material layer (20) may have different refractive indices. The first material layer (10) and the second material layer (20) may have different etching ratios. The first material layer (10) may include silicon oxide, and the second material layer (20) may include silicon nitride. However, this is exemplary and is not limited thereto. The first material layer (10) and the second material layer (20) are arranged alternately multiple times, and the period (p) in which the first material layer (10) and the second material layer (20) are repeated may be approximately 50 nm or less. This period may be the arrangement period of memory elements to be repeatedly formed along the first direction. These cycles can be determined according to the integration density to be implemented.

[0056] The laminated structure (200) is provided with a through hole (HS) that penetrates the first material layer (10) and the second material layer (20). As illustrated, the through hole (HS) may be cylindrical in shape, but is not limited thereto. If the through hole (HS) is cylindrical, the width of the through hole (HS) refers to the diameter. The interior of the through hole (HS) may be air with a refractive index of 1. Although the number of through holes (HS) is illustrated as nine, this is exemplary and can be changed to various other numbers. Material layers for memory elements may be subsequently formed inside the through hole (HS). A memory block to be manufactured may be defined as a unit of the through hole (HS). That is, one memory block may include a plurality of memory elements arranged in a first direction (Z direction), and the plurality of memory blocks may be arranged in a second direction (X direction) and a third direction (Y direction) perpendicular to the first direction.

[0057] The anti-reflective layer (300) comprises an anti-reflective material (90) and has a thickness t. The anti-reflective material (90) may comprise a material contained in the first material layer (10) or the second material layer (20). The anti-reflective material (90) may be, for example, silicon nitride or silicon oxide. However, this is exemplary and is not limited thereto.

[0058] A plurality of pattern holes (HP) may be formed in the non-reflective layer (300). The pattern holes (HP) may have the same shape as the through holes (HS) or may have a cylindrical shape. Each of the pattern holes (HP) may be connected to each of the through holes (HS) formed in the stacked structure (200). In FIG. 3, the width of the pattern hole (HP), whp, and the width of the through hole (HS), whs, are shown as the same, but this is for convenience of illustration and is not limited thereto. The width of the pattern hole (HP), whp, may be larger or smaller than the width of the through hole (HS), whs. The width of the through hole (HS), whs, is shown as constant, but it is not constant and may vary depending on the depth position. For example, the width may become narrower as it approaches the semiconductor substrate (100), which is a phenomenon that generally occurs in the etching process for forming the through hole (HS). In this case, the width of the pattern hole (HP) may be formed to a size corresponding to the average width of the through hole (HS).

[0059] The light reflectance of the non-reflective layer (300) may be 25% or less, or 20% or less, 10% or less, or 5% or less.

[0060] The average refractive index, n_eff_1, of the non-reflective layer (300) can satisfy the following conditions.

[0061] 0.9* (n_eff_st1) 1 / 2 ≤ n_eff_1 ≤1.2* (n_eff_st1) 1 / 2

[0062] n_eff_st1 is the average refractive index of the stacked structure (200).

[0063] The average refractive index of the laminated structure (200) can be calculated based on the refractive index of the first material layer (10), the refractive index of the second material layer (20), the refractive index inside the through hole (HS), and the detailed shape of the first material layer (10), the second material layer (20), and the through hole (HS).

[0064] The thickness t of the non-reflective layer (300) may be 80 nm or more and 200 nm or less. This thickness is for cases where the light source used for inspection is visible light or near-infrared light, and may be changed in consideration of wavelength and reflectance.

[0065] Figure 4 is a graph showing the thickness of the anti-reflective layer provided in a semiconductor device according to an embodiment and the reflectance according to the wavelength of incident light.

[0066] For cases where the thickness t of the anti-reflective layer (300) is 50 nm, 120 nm, 180 nm, or 230 nm, the reflectance for light in the wavelength range of 550 nm to 900 nm was computationally simulated. Referring to the graph, the wavelength range in which the reflectance is 25% or less appears differently depending on the thickness, for example, when t is 180 nm, the reflectance is 25% or less for light in the wavelength range from 700 nm to 900 nm.

[0067] FIG. 5 is a cross-sectional view showing the schematic configuration of a semiconductor device according to another embodiment.

[0068] The semiconductor device (1002) of the present embodiment comprises a semiconductor substrate (100), a first stacked structure (201) and a second stacked structure (202) arranged along a first direction (Z direction) on the semiconductor substrate (100), and further comprises a first anti-reflective layer (301) between the first stacked structure (201) and the second stacked structure (202), a second anti-reflective layer (302), and a third anti-reflective layer (303) on the second stacked structure (202).

[0069] Regarding the first stacked structure (201) and the first non-reflective layer (301), the description of the stacked structure (200) and the non-reflective layer (300) of the semiconductor device (1000) described above may be applied. That is, regarding the description of the first material layer (10), the second material layer (20), the through hole (HS1) and its width (whs1) forming the first stacked structure (201), the first non-reflective material (91), the pattern hole (HP1) and its width (whp1) forming the first non-reflective layer (301), and the thickness (t1) and effective refractive index of the first non-reflective layer (301), the description of the first material layer (10), the second material layer (20), the through hole (HS) and its width (whs) forming the stacked structure (200) described above, and the non-reflective material (90), the pattern hole (HP), and its width (whp) forming the non-reflective layer (300) may be applied.

[0070] The average refractive index, n_eff_2, of the second non-reflective layer (302) can satisfy the following conditions.

[0071] 1.0* (n_eff_st2) 1 / 2 ≤ n_eff_2 ≤1.2* (n_eff_st2) 1 / 2

[0072] Here, n_eff_st2 is the average refractive index of the second stacked structure (202).

[0073] A third non-reflective layer (303) may be disposed on the upper portion of the second laminated structure (202). To ensure that light inspecting the second laminated structure (202) is well incident on the second laminated structure (202), the third non-reflective layer (303) comprises a third non-reflective material (93) and has a thickness t3. The third non-reflective material (93) may be the same material as the second non-reflective material (92). A plurality of pattern holes (HP3) with a width of whp3 may be formed in the third non-reflective layer (303).

[0074] The average refractive index, n_eff_3, of the third non-reflective layer (303) can satisfy the following conditions.

[0075] 0.9* (n_eff_st2) 1 / 2 ≤ n_eff_3 ≤1.2* (n_eff_st2) 1 / 2

[0076] Here, n_eff_st2 is the average refractive index of the second stacked structure.

[0077] The width (whp2) of the pattern hole (HP2) of the second non-reflective layer (302) may be smaller than the width (whp1) of the pattern hole (HP1) of the first non-reflective layer (301), and the width (whp3) of the pattern hole (HP3) of the third non-reflective layer (303) may be larger than the width (whs3) of the through hole (HS2) of the second stacked structure (202). This is because when the pattern hole (HP2), the through hole (HS2), and the pattern hole (HP3) are formed by the same etching process, the etched width may be smaller as the depth position increases. However, this is exemplary and is not limited to the illustrated width.

[0078] Considering the widths formed in this way, the effective refractive index of the first anti-reflective layer (301), the effective refractive index of the second anti-reflective layer (302), and the effective refractive index of the third anti-reflective layer (303) may differ slightly from one another, and their thicknesses t1, t2, and t3 may also differ. For example, the thickness (t2) of the second anti-reflective layer (302) may be less than or equal to the thickness (t1) of the first anti-reflective layer (301). The sum of the thicknesses t1 and t2 may be determined based on approximately 1 / 4 wavelength and may be determined such that the reflectance is minimized in relation to t3.

[0079] FIGS. 6 to 8 are graphs showing the reflectance according to the wavelength of incident light and the thickness of the first, second, and third anti-reflective layers provided in the semiconductor device according to the embodiment of FIG. 5.

[0080] Figure 6 is a graph showing the reflectance according to wavelength as t1+t2 is varied to 230nm, 270nm, 310nm, and 350nm for the case where t3 is 125nm.

[0081] Referring to the graph, in the wavelength band indicated by the dotted box, when t1+t2 is 230 nm, the overall reflectance is 30% or less.

[0082] Figure 7 is a graph showing the reflectance according to wavelength as t1+t2 is varied to 230nm, 270nm, 310nm, and 350nm for the case where t3 is 150nm.

[0083] Referring to the graph, in the wavelength band indicated by the dotted box, when t1+t2 is 270 nm, the overall reflectance is 30% or less.

[0084] Figure 8 is a graph showing the reflectance according to wavelength as t1+t2 is varied to 230nm, 270nm, 310nm, and 350nm for the case where t3 is 175nm.

[0085] Referring to the graph, in the wavelength band indicated by the dotted box, when t1+t2 is 310nm and 310nm, the overall reflectance is 30% or less.

[0086] When referring to these computational simulation results, a suitable combination of thickness, t1, t2, and t3 can be selected by considering the wavelength and reflectance.

[0087] FIG. 9 is a perspective view showing a schematic configuration of a semiconductor device according to another embodiment.

[0088] The semiconductor device (1005) includes a semiconductor substrate (100), a stacked structure (205), and an anti-reflective layer (305).

[0089] The laminated structure (205) includes alternatingly laminated first material layers (10) and second material layers (20), and includes a through hole (HS5) that penetrates them and has a width of whs5.

[0090] The non-reflective layer (305) includes a non-reflective material (95) and a pattern hole (HP5) penetrating it and having a width of whp5.

[0091] The width of the through hole (HS5), whs5, and the width of the pattern hole (HP5), whp5, are depicted as being the same, but this is an example for convenience of illustration, and for example, whp5 may be larger or smaller than whs5. Alternatively, if the width of the through hole (HS5), whs5, is not constant depending on the depth position of the through hole (HS5), the width at an intermediate position or the average width may be applied to the width of the pattern hole (HP5), whp5.

[0092] The through hole (HS5) provided in the laminated structure (205) and the through hole (whp5) provided in the non-reflective layer (305) differ from the semiconductor device (1000) of FIG. 2 in that they have a slit shape, that is, a thin rectangular shape as shown, and the rest of the configuration is substantially the same.

[0093] FIG. 10 is a flowchart schematically illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0094] A stacked material layer can be formed by alternately stacking a first material layer and a second material layer with different refractive indices multiple times (S500).

[0095] The first material layer and the second material layer may be the first material layer (10) and the second material layer (20) described above, and the first material layer and the second material layer may be formed on a semiconductor substrate. The first material layer and the second material layer may be materials having different refractive indices and materials with different etching ratios. Either of the first material layer or the second material layer may be a sacrificial layer, that is, a portion of it may be removed in a subsequent process. Either of the first material layer or the second material layer may be silicon oxide and the other may be silicon nitride, but is not limited thereto. Deposition methods such as atomic layer deposition (ALD), metal organic atomic layer deposition (MOALD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), and physical vapor deposition (PVD) may be used to form the first material layer and the second material layer. The thickness of each layer, the alternating period, and the number of repetitions may be determined according to the number of memory cells to be manufactured and the integration density.

[0096] An anti-reflective material layer may be formed on the stacked material layer (S520). The anti-reflective material layer may be the same material as either the first material layer or the second material layer, but is not limited thereto. The anti-reflective material layer may also be formed by the deposition method described above.

[0097] A hole penetrating the anti-reflective material layer and the stacked material layer can be formed to form an anti-reflective layer and a stacked structure (S540). Photolithography and etching processes may be used to form such a hole. If the width of the hole to be formed within the anti-reflective material layer and the stacked material layer is the same, a single photolithography and etching process may be performed, and if necessary, multiple photolithography and etching processes may be performed. The shape of the through hole may vary, such as a cylindrical shape or a slit shape, and, for example, a stacked structure (200 in FIG. 2, 205 in FIG. 9) and an anti-reflective layer (300 in FIG. 2, 305 in FIG. 9) as described above may be manufactured.

[0098] The interior of the stacked structure can be measured by optical inspection (S560). For measuring the interior of the stacked structure, an optical device including an optical transmitter, an optical receiver, and an analysis unit as described in FIG. 1 may be used.

[0099] If necessary, steps S500 to S560 may be repeated. In the repeated steps, the details of the anti-reflective layer and the stacked structure may vary. According to this process, for example, as illustrated in FIG. 5, a semiconductor device (1002) having a first stacked structure (201), a second stacked structure (202), and first, second, and third anti-reflective layers (301, 302, 303) may be manufactured, or a semiconductor device having a structure in which additional stacked structures and anti-reflective layers are further stacked may be manufactured.

[0100] Next, an additional process for forming a stacked memory structure may be performed (S580). For example, additional material layers for memory elements may be formed within the through-hole formed in step S540, and a portion of the first material layer and the second material layer forming the stacked structure may be selectively removed. In the removed location, for example, an electrode material may be filled. Through this process, a plurality of memory elements may be formed along the direction of the through-hole, and a single memory block containing a plurality of memory elements may be defined as a unit of a single through-hole. The manufactured semiconductor device may be, for example, a VNAND device or a VS-DRAM (vertical stacked DRAM) device.

[0101] The semiconductor device and manufacturing method described above have been explained with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Therefore, the disclosed embodiments should be considered in an illustrative rather than a limiting sense. The scope of this specification is defined by the claims, not by the foregoing description, and all variations within the scope of equivalents should be interpreted as being included. Explanation of the symbols

[0102] SD, 1000, 1002, 1005 - Semiconductor devices SU, 100 - Semiconductor substrate 200, 201, 202, 205 - Laminated structure 300, 301, 302, 303, 305 - Anti-reflective layer

Claims

Claim 1 A semiconductor device comprising: a semiconductor substrate; a first stacked structure having a first material layer and a second material layer alternately arranged multiple times along a first direction and having different refractive indices, and having a plurality of through holes formed in the first direction; a first anti-reflective layer arranged on the first stacked structure, having a first anti-reflective material and having a plurality of first pattern holes formed that are each connected to the plurality of through holes of the first stacked structure; wherein the light reflectance of the first anti-reflective layer is 25% or less. Claim 2 In claim 1, the average refractive index of the first anti-reflective layer, n_eff_1, is given by the following condition, 0.9 * (n_eff_st1) 1 / 2 ≤ n_eff_1 ≤1.2 * (n_eff_st1) 1 / 2 A semiconductor device satisfying the condition. Here, n_eff_st1 is the average refractive index of the first stacked structure. Claim 3 A semiconductor device according to claim 1, wherein the thickness of the first anti-reflective layer is 80 nm or more and 200 nm or less. Claim 4 A semiconductor device according to claim 1, wherein the through hole formed in the first laminated structure and the first pattern hole formed in the first anti-reflective layer have the same width. Claim 5 A semiconductor device according to claim 1, wherein the first material layer comprises silicon oxide and the second material layer comprises silicon nitride. Claim 6 A semiconductor device according to claim 1, wherein the first anti-reflective material comprises a material included in the first material layer or the second material layer. Claim 7 In claim 1, the through hole is a semiconductor device having a cylindrical shape or a slit shape. Claim 8 A semiconductor device according to claim 1, wherein the period in which the first material layer and the second material layer are alternately stacked is 50 nm or less. Claim 9 A semiconductor device according to claim 1, wherein the arrangement period of the plurality of through holes is 200 nm or less. Claim 10 A semiconductor device according to claim 1, further comprising: a second stacked structure disposed on the first non-reflective layer and including a third material layer and a fourth material layer alternately stacked and having a plurality of through holes formed therein; a second non-reflective layer disposed between the first non-reflective layer and the second stacked structure and including a second non-reflective material and having a plurality of second pattern holes formed therein; and a third non-reflective layer disposed on the second stacked structure and including a third non-reflective material and having a plurality of third pattern holes formed therein. Claim 11 In item 10, the average refractive index of the second anti-reflective layer, n_eff_2, is given by the following condition: 1.0 * (n_eff_st2) 1 / 2 ≤ n_eff_2 ≤1.2 * (n_eff_st2) 1 / 2 A semiconductor device satisfying the condition. Here, n_eff_st2 is the average refractive index of the second stacked structure. Claim 12 In item 10, the average refractive index of the third anti-reflective layer, n_eff_3, is given by the following condition, 0.9 * (n_eff_st2) 1 / 2 ≤ n_eff_3 ≤1.2 * (n_eff_st2) 1 / 2 A semiconductor device satisfying the condition. Here, n_eff_st2 is the average refractive index of the second stacked structure. Claim 13 A semiconductor device according to claim 10, wherein the width of the second pattern hole is less than or equal to the width of the first pattern hole. Claim 14 A semiconductor device according to claim 10, wherein the thickness of the second anti-reflective layer is less than or equal to the thickness of the first anti-reflective layer, and the width of the pattern hole is less than or equal to the width of the first pattern hole. Claim 15 A semiconductor device according to claim 10, wherein the third material layer comprises silicon oxide and the fourth material layer comprises silicon nitride. Claim 16 A semiconductor device according to claim 10, wherein the first anti-reflective material and the second anti-reflective material comprise the same material. Claim 17 A semiconductor device comprising: a plurality of memory blocks; and an anti-reflective layer disposed on the plurality of memory blocks, forming a pattern made of two or more materials having different refractive indices and having a first thickness; wherein each of the plurality of memory blocks comprises a plurality of memory elements arranged along a first direction, and the plurality of memory blocks are arranged along a second direction perpendicular to the first direction, and the anti-reflective layer has a light reflectance of 25% or less. Claim 18 A method for manufacturing a semiconductor device comprising: a step of forming a stacked material layer by alternately stacking a first material layer and a second material layer with different refractive indices multiple times along a first direction; a step of forming an anti-reflective material layer on the stacked material layer; and a step of forming a through hole penetrating the anti-reflective material layer and the stacked material layer to form an anti-reflective layer and a stacked structure; wherein the material and thickness of the anti-reflective material layer are determined such that the reflectance of the anti-reflective layer is 25% or less. Claim 19 In paragraph 18, the average refractive index of the above anti-reflective layer, n_eff_1, is given by the following condition, 0.9 * (n_eff_st1) 1 / 2 ≤ n_eff_1 ≤1.2 * (n_eff_st1) 1 / 2 A method for manufacturing a semiconductor device satisfying the following: Here, n_eff_st1 is the average refractive index of the stacked structure. Claim 20 A method for manufacturing a semiconductor device, further comprising the step of forming a memory element within the through hole in claim 18.

Images