Three dimensional semiconductor device and method for manufacturing the same

Abstract

A three-dimensional semiconductor device according to the present invention comprises: first semiconductor patterns spaced apart from a substrate and spaced apart from each other in a first direction parallel to the upper surface of the substrate; second semiconductor patterns adjacent to the first semiconductor patterns in a second direction parallel to the upper surface of the substrate and spaced apart from each other in the first direction; first bit lines on first edge portions of the first semiconductor patterns; second bit lines on first edge portions of the second semiconductor patterns; and a shielding pattern between the first bit lines and the second bit lines, wherein the shielding pattern comprises first regions between the first bit lines and the second bit lines and second regions between the first regions, and with respect to the second direction, the width of each of the second regions of the shielding pattern is greater than the width of each of the first regions of the shielding pattern.

Description

Technology Field

[0001] The present invention relates to a three-dimensional semiconductor device and a method for manufacturing the same, and more specifically, to a three-dimensional semiconductor device with improved productivity and electrical characteristics. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are receiving significant attention as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include both memory and logic elements.

[0003] Recently, with the increasing speed and low power consumption of electronic devices, embedded semiconductor devices are also required to have fast operating speeds and / or low operating voltages. To meet these requirements, more highly integrated semiconductor devices are necessary. However, as the integration of semiconductor devices intensifies, their electrical characteristics and production yield may decrease. Accordingly, much research is being conducted to improve the electrical characteristics and production yield of semiconductor devices. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a three-dimensional semiconductor device with improved reliability and a method for manufacturing the same.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A three-dimensional semiconductor device according to some embodiments of the present invention comprises: a substrate; first semiconductor patterns disposed on the substrate and spaced apart from each other in a first direction parallel to the lower surface of the substrate; second semiconductor patterns adjacent to the first semiconductor patterns in a second direction parallel to the lower surface of the substrate and spaced apart from each other in the first direction; a lower liner pattern disposed on the substrate and extending in the first direction between the first semiconductor patterns and the second semiconductor patterns; an upper liner pattern extending in the first direction on the lower liner pattern; and bit lines disposed between the first semiconductor patterns and the upper liner pattern and between the second semiconductor patterns and the upper liner pattern, wherein the bit lines may extend in a third direction perpendicular to the first and second directions on the lower liner pattern.

[0007] A three-dimensional semiconductor device according to some embodiments of the present invention comprises: a substrate; first semiconductor patterns disposed on the substrate and spaced apart from each other in a first direction parallel to the lower surface of the substrate; bit lines on first sidewalls of the first semiconductor patterns; a data storage pattern on second sidewalls facing the first sidewalls of the first semiconductor patterns in a second direction parallel to the lower surface of the substrate; a lower liner pattern between the data storage pattern and the substrate; and an upper liner pattern between the data storage pattern and the lower liner pattern, wherein the lower liner pattern and the upper liner pattern may extend in the first direction.

[0008] A three-dimensional semiconductor device according to some embodiments of the present invention comprises: a substrate; first semiconductor patterns disposed on the substrate and spaced apart from each other in a first direction parallel to the lower surface of the substrate; second semiconductor patterns adjacent to the first edge portions of the first semiconductor patterns in a second direction parallel to the lower surface of the substrate; third semiconductor patterns adjacent to the second edge portions of the first semiconductor patterns in the second direction; a first lower liner pattern disposed on the substrate and extending in the first direction between the first semiconductor patterns and the second semiconductor patterns; a first upper liner pattern extending in the first direction on the first lower liner pattern; bit lines disposed extending in a third direction perpendicular to the first and second directions on the first edge portions of the first semiconductor patterns; and a data storage pattern extending along the third direction on the second edge portions of the first semiconductor patterns, wherein the bit lines may be disposed on the first lower liner pattern between the first edge portions and the first upper liner pattern.

[0009] A method for manufacturing a three-dimensional semiconductor device according to some embodiments of the present invention may include: forming first semiconductor patterns on a substrate that are spaced apart in a first direction parallel to the lower surface of the substrate; forming second semiconductor patterns adjacent to the first semiconductor patterns in a second direction parallel to the lower surface of the substrate and spaced apart from each other in the first direction; forming a first trench extending in the first direction between the first semiconductor patterns and the second semiconductor patterns; forming a lower liner film conformally covering the first trench; forming an upper liner film on the lower liner film that fills the first trench; etching a portion of the lower liner film so as to expose the sidewalls of the first semiconductor patterns; and forming bit lines on the sidewalls of the first semiconductor patterns.

[0010] According to some embodiments, the lower liner film may have etch selectivity with respect to the upper liner film.

[0011] According to some embodiments, forming the first trench may include exposing the sidewalls of the first semiconductor patterns and the sidewalls of the second semiconductor patterns.

[0012] According to some embodiments, the upper liner may include a void formed inside.

[0013] According to some embodiments, prior to forming the bit lines, a portion of the lower liner film may be further etched so as to expose the sidewalls of the second semiconductor patterns, and the bit lines may be disposed on the sidewalls of the second semiconductor patterns. Effects of the invention

[0014] According to the concept of the present invention, a lower liner pattern and an upper liner pattern may be disposed between bit lines and a substrate or between a data storage pattern and a substrate. In other words, the lower liner pattern and the upper liner pattern may be disposed within a trench between adjacent first and second semiconductor patterns. Although a void (or seam) may be formed within the upper liner pattern due to the high aspect ratio of the trench, the upper liner pattern may be a relatively rigid film compared to the lower liner pattern. As a result, the impact of the void can be minimized during the process of forming a trench and subsequently performing a cleaning process in the manufacturing process of a three-dimensional semiconductor device according to the present invention. Therefore, the reliability of the three-dimensional semiconductor device can be improved. Brief explanation of the drawing

[0015] FIG. 1 is a schematic circuit diagram showing a three-dimensional semiconductor device according to some embodiments of the present invention. FIGS. 2a, FIGS. 2b and FIGS. 2c are schematic perspective views of a three-dimensional semiconductor device according to some embodiments of the present invention. FIG. 3 is a plan view of a three-dimensional semiconductor device according to some embodiments of the present invention. Figure 4a is a cross-sectional view corresponding to line AA' in Figure 3. Figure 4b is a cross-sectional view corresponding to line BB' of Figure 3. FIGS. 5a and FIGS. 5b are cross-sectional views of a three-dimensional semiconductor device according to some embodiments of the present invention, corresponding to FIG. 4a. FIG. 6 is a plan view of a three-dimensional semiconductor device according to some embodiments of the present invention. Figure 7a is a cross-sectional view corresponding to the CC' line in Figure 6. FIG. 7b is a cross-sectional view of a three-dimensional semiconductor device according to some embodiments of the present invention, corresponding to FIG. 7a. FIGS. 8 to 27 are drawings illustrating a method for manufacturing a three-dimensional semiconductor device according to some embodiments of the present invention. FIGS. 28 and 29 are drawings illustrating a method for manufacturing a three-dimensional semiconductor device according to some embodiments of the present invention. Specific details for implementing the invention

[0016] Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings.

[0018] FIG. 1 is a schematic circuit diagram showing a three-dimensional semiconductor device according to some embodiments of the present invention.

[0019] Referring to FIG. 1, a three-dimensional semiconductor device may include a memory cell array (1), a row decoder (2), a sense amplifier (3), a column decoder (4), and control logic (5).

[0020] A memory cell array (1) may include word lines (WL), bit lines (BL), source lines (SL), and memory cells (MC). The memory cells (MC) may be arranged in three dimensions, and the memory cells (MC) may be connected to one word line (WL), one bit line (BL), and one source line (SL). In some embodiments, each of the memory cells (MC) may be composed of a single transistor comprising a memory film (or data storage film).

[0021] The row decoder (2) can decode an externally input address and select one of the word lines (WL) of the memory cell array (1). The address decoded by the row decoder (2) can be provided to a row driver (not shown), and the row driver can provide a predetermined voltage to the selected word line (WL) and the unselected word lines (WL), respectively, in response to the control of the control circuits.

[0022] The sense amplifier (3) can detect and amplify the voltage difference between the selected bit line (BL) and the reference bit line according to the address decoded from the column decoder (4) and output it.

[0023] The column decoder (4) can provide a data transmission path between the sense amplifier (3) and an external device (e.g., a memory controller). The column decoder (4) can decode an externally input address and select any one of the bit lines (BL).

[0024] The control logic (5) can generate control signals that control operations for writing or reading data to or from the memory cell array (1).

[0026] FIGS. 2a, FIGS. 2b and FIGS. 2c are schematic perspective views of a three-dimensional semiconductor device according to some embodiments of the present invention.

[0027] Referring to FIG. 2a, a three-dimensional semiconductor device may include a substrate (100), a peripheral circuit structure (PS) on the substrate (100), and a cell array structure (CS) on the peripheral circuit structure (PS).

[0028] The peripheral circuit structure (PS) may include core and peripheral circuits formed on the substrate (100). The core and peripheral circuits may include row and column decoders (2 and 4 in FIG. 1), sense amplifier (3 in FIG. 1), and control logic (5 in FIG. 1) as described with reference to FIG. 1.

[0029] The substrate (100) may have the form of a plate extending along a plane defined by a first direction (D1) and a second direction (D2). The first direction (D1) and the second direction (D2) are parallel to the upper surface of the substrate (100) and may intersect each other. For example, the first direction (D1) and the second direction (D2) may be horizontal directions that are orthogonal to each other. Peripheral circuit structures (PS) and cell array structures (CS) may be sequentially stacked on the substrate (100) in a third direction (D3) perpendicular to the upper surface of the substrate (100).

[0030] A cell array structure (CS) may include bit lines (BL), source lines (SL), and word lines (WL) and memory cells (MC) between them. Each of the memory cells (MC) may be connected to one word line (WL), one bit line (BL), and one source line (SL).

[0031] Referring to FIG. 2b, the semiconductor device may include a cell array structure (CS) on a substrate (100) and a peripheral circuit structure (PS) on the cell array structure (CS). The cell array structure (CS) may be placed between the substrate (100) and the peripheral circuit structure (PS). The peripheral circuit structure (PS) may include a core and peripheral circuits.

[0032] Referring to FIG. 2c, the semiconductor device may have a C2C (chip-to-chip) structure. A peripheral circuit structure (PS) may include a first substrate (100a). Lower metal pads (LMP) may be provided on the top of the peripheral circuit structure (PS). The lower metal pads (LMP) may be electrically connected to the core and peripheral circuits. The lower metal pads (LMP) may be bonded to upper metal pads (UMP) of a cell array structure (CS).

[0033] The cell array structure (CS) may include a second substrate (200a), and upper metal pads (UMP) may be provided at the bottom of the cell array structure (CS). The upper metal pads (UMP) may be electrically connected to bit lines (BL), source lines (SL), and word lines (WL). The upper metal pads (UMP) may be electrically connected to memory cells (MC).

[0035] FIG. 3 is a plan view of a three-dimensional semiconductor device according to some embodiments of the present invention. FIG. 4a is a cross-sectional view corresponding to line AA' of FIG. 3. FIG. 4b is a cross-sectional view corresponding to line BB' of FIG. 3.

[0036] Referring to FIGS. 3 and FIGS. 4a, a three-dimensional semiconductor device may include a substrate (100). For example, the substrate (100) may be a semiconductor substrate, an insulator substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate (100) may have the form of a plate extending along a plane defined by a first direction (D1) and a second direction (D2). The first direction (D1) and the second direction (D2) are directions parallel to the lower surface of the substrate (100) and may intersect each other. The third direction (D3) may be a direction perpendicular to the lower surface of the substrate (100). The first to third directions (D1, D2, D3) may be directions orthogonal to each other. For example, the substrate (100) may include a peripheral circuit structure (PS) described with reference to FIG. 2a and FIG. 2c.

[0037] A cell array structure (CS) may be provided on a substrate (100). In the drawings, a single cell array structure (CS) is shown on the substrate (100), but is not limited thereto. For example, the cell array structure (CS) may include a plurality of cell array structures (CS) adjacent to each other in a second direction (D2). Hereinafter, for convenience of explanation, a single cell array structure (CS) is described, but the following description may be applied equally to other cell array structures (CS).

[0038] The cell array structure (CS) may include a first stacked structure (ST1) and a second stacked structure (ST2) adjacent to each other in a second direction (D2). Each of the first stacked structure (ST1) and the second stacked structure (ST2) may include semiconductor patterns (SP), word lines (WL), and surrounding components. Each is described in detail below.

[0039] The semiconductor pattern (SP) can be spaced apart from the substrate (100) in a third direction (D3). In other words, the semiconductor pattern (SP) can be floating from the substrate (100). The semiconductor pattern (SP) can be extended along a second direction (D2) on the substrate (100). For example, the semiconductor pattern (SP) can have the form of a bar extending along the second direction (D2).

[0040] A semiconductor pattern (SP) may include a first edge portion (EA1) and a second edge portion (EA2) spaced apart in a second direction (D2), and a channel region (CH) between them. The channel region (CH) of the semiconductor pattern (SP) may be vertically superimposed with a word line (WL) described later. The first edge portion (EA1) of the semiconductor pattern (SP) may be connected to a bit line (BL) described later. The second edge portion (EA2) may be connected to a data storage pattern (DSP) described later. In this specification, the meaning of A and B being connected includes not only A and B being directly connected by contact, but also A and B being indirectly connected through C (e.g., a conductive component) between A and B. Here, component C may be a singular component or a plurality of components.

[0041] A semiconductor pattern (SP) may include at least one of a single-crystal semiconductor, a polycrystalline semiconductor, an oxide semiconductor, and a two-dimensional material. For example, the single-crystal semiconductor may be single-crystal silicon. For example, the polycrystalline semiconductor may be polysilicon. For example, the oxide semiconductor may be IGZO (Indium Gallium Zinc Oxide). For example, the two-dimensional material may be MoS2, WS2, MoSe2, or WSe2. In this specification, each of phrases such as “A or B”, “at least one of A and B”, “at least one of A or B”, “A, B or C”, “at least one of A, B and C”, and “at least one of A, B, or C” may include any one of the items listed together with the corresponding phrase, or all possible combinations thereof.

[0042] For example, each of the first and second edge portions (EA1, EA2) of the semiconductor pattern (SP) may include an impurity region doped with an impurity (e.g., n-type or p-type impurity) therein. The impurity region may constitute the source-drain region of the transistor.

[0043] A plurality of semiconductor patterns (SP) may be provided. The semiconductor patterns (SP) may be spaced apart from each other along a first direction (D1) and a third direction (D3). For example, the upper surfaces of the semiconductor patterns (SP) arranged along the first direction (D1) may be aligned with each other. The semiconductor patterns (SP) arranged along the third direction (D3) may be vertically overlapped with each other. For example, the side walls of the semiconductor patterns (SP) arranged along the third direction (D3) may be aligned with each other.

[0044] A semiconductor pattern (SP) may include first semiconductor patterns (SP1) provided within a first stacked structure (ST1) and second semiconductor patterns (SP2) provided within a second stacked structure (ST2). The first semiconductor patterns (SP1) may be spaced apart from each other along a first direction (D1) and a third direction (D3). The second semiconductor patterns (SP2) may be spaced apart from each other along a first direction (D1) and a third direction (D3). The first semiconductor patterns (SP1) may be spaced apart from each other in a second direction (D2) with respect to the second semiconductor patterns (SP2). The first edge portions (EA1) of the first semiconductor patterns (SP1) may be adjacent to the first edge portions (EA1) of the second semiconductor patterns (SP2) more than the second edge portions (EA2) of the second semiconductor patterns (SP2). Each of the first semiconductor patterns (SP1) may have a first sidewall (S1) and a second sidewall (S2) facing each other. The first sidewall (S1) may refer to the sidewall of the first edge portion (EA1), and the second sidewall (S2) may refer to the sidewall of the second edge portion (EA2). Each of the first sidewalls (S1) and the second sidewalls (S2) of the first semiconductor patterns (SP1) may be aligned along a third direction (D3). A bit line (BL), described later, may be placed on the first sidewalls (S1) of the first semiconductor patterns (SP1), and a data storage pattern (DSP), described later, may be placed on the second sidewalls (S2) of the first semiconductor patterns (SP1).

[0045] Word lines (WL) can extend along the first direction (D1) and surround channel regions (CH) of semiconductor patterns (SP) that are spaced apart from each other along the first direction (D1). Multiple word lines (WL) may be provided. Word lines (WL) can be spaced apart from each other in the third direction (D3).

[0046] A word line (WL) may include a gate insulation pattern (GI) surrounding a channel region (CH) of a semiconductor pattern (SP) and a gate pattern (GE) extending along a first direction (D1) on the gate insulation pattern (GI). For example, the gate insulation pattern (GI) may include a single film selected from a high-k film, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or a combination thereof. In this specification, a material having high-k is defined as a material having a dielectric constant higher than that of silicon oxide.

[0047] For example, the gate pattern (GE) may include at least one of Ti, TiN, TiSiN, TiON, W, WN, Mo, MoN, MoOxNy, Ta, TaN, Poly Si, Li, Na, K, Cs, Rb, Sr, Ba, Ca, Ce, Sm, Eu, Mg, Sc, Y, Hf, Tl, As, La, Nd, Gd, Tb, Lu, Th, U, Mn, Al, Ga, In, Pb, Cd, Bi, and Zr. For example, the gate pattern (GE) may be a single film or a composite film.

[0048] A first lower liner pattern (110) may be interposed between first semiconductor patterns (SP1) and second semiconductor patterns (SP2). In other words, the first lower liner pattern (110) may be provided within a trench defined between the first semiconductor patterns (SP1) and the second semiconductor patterns (SP2) adjacent in the second direction (D2). The first lower liner pattern (110) may extend in the first direction (D1). A portion of the first lower liner pattern (110) may overlap with bit lines (BL) in a planar view. The first lower liner pattern (110) may cover a portion of the upper surface of the substrate (100).

[0049] Referring to FIGS. 3, 4a, and 4b, the first lower liner pattern (110) may include a first horizontal portion (HP1) and a first vertical portion (VP1). The first horizontal portion (HP1) may refer to a portion that overlaps vertically with the first upper liner pattern (120). The first horizontal portion (HP1) may be provided between the first upper liner pattern (120) and the substrate (100). The first vertical portion (VP1) may refer to a portion that extends along the third direction (D3) from both ends of the second direction (D2) of the first horizontal portion (HP1). The first vertical portion (VP1) may extend along the third direction (D3) and may cover a portion of the side wall (120_S) of the first upper liner pattern (120).

[0050] The first vertical section (VP1) may include a first section (VP1a) that overlaps vertically with the bit line (BL) and a second section (VP1b) that does not overlap vertically with the first section (VP1a) and the bit line (BL). The second section (VP1b) may be adjacent to the first section (VP1a) in a first direction (D1). For example, the first section (VP1a) and the second section (VP1b) may be arranged alternately along the first direction (D1). The upper surface of the first section (VP1a) may be located at a lower level than the upper surface of the second section (VP1b). For example, the upper surface of the second section (VP1b) may form a co-plane with the upper surface of the bit line (BL).

[0051] A first upper liner pattern (120) may be disposed on a first lower liner pattern (110). The first upper liner pattern (120) may extend in a first direction (D1) on the first lower liner pattern (110). A bit line (BL) and a first lower liner pattern (110) may be disposed on the side wall (120_S) of the first upper liner pattern (120). For example, the first upper liner pattern (120) may include a first void (SM1) formed inside. The first void (SM1) may refer to a seam formed inside the first upper liner pattern (120). For another example, the first void (SM1) may not be formed inside the first upper liner pattern (120).

[0052] The first lower liner pattern (110) and the first upper liner pattern (120) may comprise different materials. For example, the first lower liner pattern (110) and the first upper liner pattern (120) may comprise materials with different resistance to etching. As an example, the first lower liner pattern (110) may comprise silicon oxide, and the first upper liner pattern (120) may comprise at least one of silicon nitride, silicon carbide, and polysilicon (Poly-Si). The first upper liner pattern (120) may further comprise silicon oxide.

[0053] Bit lines (BL) may be interposed between the first semiconductor patterns (SP1) and the second semiconductor patterns (SP2). Bit lines (BL) may be positioned between the first edge portions (EA1) of the first semiconductor patterns (SP1) and one sidewall (120_S) of the first upper liner pattern (120), and between the first edge portions (EA1) of the second semiconductor patterns (SP2) and the other sidewall (120_S) of the first upper liner pattern (120). Specifically, the bit lines (BL) may be extended along a third direction (D3) on the first lower liner pattern (110, the first vertical portion (VP1)) and extended onto the first edge portions (EA1) of the first semiconductor patterns (SP1). The bit lines (BL) may be connected along a second direction (D2) to the first edge portions (EA1) of the first semiconductor patterns (SP1). Bit lines (BL) can be extended along a third direction (D3) on a first lower liner pattern (110, the first vertical portion (VP1)) and can be extended along a third direction (D3) on the first edge portions (EA1) of the second semiconductor patterns (SP2). Bit lines (BL) can be connected along a second direction (D2) with the first edge portions (EA1) of the first semiconductor patterns (SP1).

[0054] For example, each bit line (BL) can connect adjacent first semiconductor patterns (SP1) and second semiconductor patterns (SP2) in the second direction (D2). In other words, in terms of cross-sectional area, the bit line (BL) can have an inverted U-shaped profile. For example, the bit lines (BL) can each cross the first lower liner pattern (110) and the first upper liner pattern (120) in the second direction (D2) and cover the upper surface of the first upper liner pattern (120), but are not limited thereto.

[0055] The bitline (BL) may be a single film comprising one material or a composite film comprising two or more materials. As an example, the bitline (BL) may include at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) and a metal silicide (e.g., a silicide of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0056] An interlayer insulating film (ILD) may be provided between word lines (WL) that are spaced apart from each other in a third direction (D3) and may be spaced apart. An interlayer insulating film (ILD) may be interposed between bit lines (BL) and word lines (WL) and may be spaced apart. An interlayer insulating film (ILD) may be interposed between semiconductor patterns (SP) that are spaced apart from each other in a third direction (D3). The sidewalls of the bottom layer interlayer insulating film (ILD) may be covered by a first lower liner pattern (110). The interlayer insulating film (ILD) may include an insulating material, and may include at least one of silicon oxide and silicon nitride, for example.

[0057] A data storage pattern (DSP) can be extended along the third direction (D3) on the sides of the second edge portions (EA2) of semiconductor patterns (SP) that are spaced apart from each other along the third direction (D3). The data storage pattern (DSP) can be connected to the second edge portions (EA2) of the semiconductor patterns (SP).

[0058] A data storage pattern (DSP) may include a storage electrode (SE), a plate electrode (PE), and a dielectric film (CIL) between them. As an example, a three-dimensional semiconductor device may be a dynamic random access memory (DRAM), in which case the data storage pattern (DSP) may be utilized as a capacitor. The storage electrode (SE) may be separated from the plate electrode (PE) by a dielectric film (CIL).

[0059] Each of the storage electrode (SE) and the plate electrode (PE) may include a conductive material. For example, each of the storage electrode (SE) and the plate electrode (PE) may include at least one of impurity-doped silicon (Si), impurity-doped silicon-germanium (SiGe), a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.), a metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.), titanium silicon nitride (e.g., TiSiN), titanium aluminum nitride (e.g., TiAlN), and tantalum aluminum nitride (e.g., TaAlN), etc.), a conductive oxide (e.g., PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo), and a metal silicide. Each of the storage electrode (SE) and the plate electrode (PE) may be a single membrane made of a single material or a composite membrane containing two or more materials.

[0060] For example, the dielectric film (CIL) may include at least one of metal oxides such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2, and dielectric materials with a perovskite structure such as SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and PLZT.

[0061] As another example, the data storage pattern (DSP) may be a variable resistance pattern that can be switched between two resistance states by an electrical pulse. In this case, the data storage pattern (DSP) may include a phase-change material, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials, in which the crystal state changes depending on the amount of current.

[0062] Although not shown in the drawing, a silicide pattern (not shown) may be provided between the storage electrode (SE) and the semiconductor pattern (SP). The silicide pattern may include a metal silicide (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). The storage electrode (SE) may be provided in multiple numbers, and the storage electrodes (SE) may be adjacent to each other in a third direction (D3).

[0063] A capping pattern (CP) may be provided between a word line (WL) and a data storage pattern (DSP) and may be separated therefrom. The capping pattern (CP) may include a first capping pattern (CP1) that conformally covers the word line (WL) and the semiconductor pattern (SP), and a second capping pattern (CP2) between the first capping pattern (CP1) and the data storage pattern (DSP). The capping pattern (CP) may include an insulating material, and may include, for example, at least one of silicon oxide and silicon nitride.

[0064] An upper insulating layer (UIL) may be provided on the upper surface of each of the first stacked structure (ST1) and the second stacked structure (ST2). The upper insulating layer (UIL) may cover a data storage pattern (DSP), word lines (WL), and bit lines (BL). The upper insulating layer (UIL) may comprise a single layer or a composite layer containing an insulating material. A plurality of upper wirings (not shown) may be included within the upper insulating layer (UIL). Some of the upper wirings may be electrically connected to the bit lines (BL), and others may be electrically connected to the capacitor structure (CAP).

[0066] FIGS. 5a and FIG. 5a are cross-sectional views of a three-dimensional semiconductor device according to some embodiments of the present invention, corresponding to FIG. 4a. For the sake of simplicity, explanations that overlap with the aforementioned content are omitted, and the differences from the aforementioned content are explained primarily.

[0067] Referring to FIG. 5a, the first upper liner pattern (120) may have a recessed upper surface (120_RU) facing the substrate (100). In other words, the first upper liner pattern (120) may have a shape with a recessed upper surface. For example, the recessed upper surface (120_RU) of the first upper liner pattern (120) may have a circular or elliptical shape in terms of planar view. For example, the recessed upper surface (120_RU) of the first upper liner pattern (120) may have a U-shape in terms of cross-sectional view.

[0068] Each of the bit lines (BL) may include a first protrusion (BLp) that protrudes toward the recessed upper surface (120_RU) of the first upper liner pattern (120). The first protrusion (BLp) may be part of the bit line (BL) and may extend along the third direction (D3) to cover the recessed upper surface (120_RU) of the first upper liner pattern (120). The first protrusion (BLp) of the bit line (BL) may be spaced apart from the first edge portions (EA1) of the first and second semiconductor patterns (SP1, SP2).

[0069] Referring to FIG. 5b, each bit line (BL) may include a first bit line (BL1) and a second bit line (BL2) spaced apart from each other along a second direction (D2). The first and second bit lines (BL1, BL2) facing each other along the second direction (D2) may be spaced apart from each other with the first upper liner pattern (120) and the upper insulating film (UIL) in between. The first bit lines (BL1) may be connected to the first edge portions (EA1) of the first semiconductor patterns (SP1) and may be spaced apart from each other along the first direction (D1). The second bit lines (BL2) may be connected to the first edge portions (EA1) of the second semiconductor patterns (SP2) and may be spaced apart from each other along the first direction (D1).

[0070] FIG. 6 is a plan view of a three-dimensional semiconductor device according to some embodiments of the present invention. FIG. 7a is a cross-sectional view corresponding to line CC' of FIG. 6.

[0071] The cell array structure (CS) may further include a third stacked structure (ST3) adjacent to the first stacked structure (ST1) in the second direction (D2). The third stacked structure (ST3) may include third semiconductor patterns (SP3), word lines (WL), and surrounding components.

[0072] The third semiconductor patterns (SP3) may include a first edge portion (EA1) and a second edge portion (EA2) spaced apart in a second direction (D2), and a channel region (CH) between them. The channel regions (CH) of the third semiconductor patterns (SP3) may be vertically overlapped with a word line (WL). The first edge portions (EA1) of the third semiconductor patterns (SP3) may be connected to bit lines (BL). The second edge portions (EA2) of the third semiconductor patterns (SP3) may be connected to a data storage pattern (DSP). The second edge portions (EA2) of the third semiconductor patterns (SP3) may be adjacent to the second sidewalls (S2) of the first semiconductor patterns (SP1) along the second direction (D2).

[0073] The third semiconductor patterns (SP3) may be spaced apart from each other along the first direction (D1) and the third direction (D3). For example, the upper surfaces of the third semiconductor patterns (SP3) arranged along the first direction (D1) may be aligned with each other. The third semiconductor patterns (SP3) arranged along the third direction (D3) may be vertically overlapped with each other. For example, the sidewalls of the third semiconductor patterns (SP3) arranged along the third direction (D3) may be aligned with each other. The third semiconductor patterns (SP3) may include at least one of a single-crystal semiconductor, a polycrystalline semiconductor, an oxide semiconductor, and a two-dimensional material.

[0074] Word lines (WL) can extend along the first direction (D1) and surround channel regions (CH) of third semiconductor patterns (SP3) that are spaced apart from each other along the first direction (D1). Multiple word lines (WL) may be provided. Word lines (WL) may be spaced apart from each other in the third direction (D3).

[0075] A data storage pattern (DSP) may be extended along the third direction (D3) on the sides of the second edge portions (EA2) of semiconductor patterns (SP) that are spaced apart from each other along the third direction (D3). The data storage pattern (DSP) may be connected to the second edge portions (EA2) of the first and third semiconductor patterns (SP1, SP3).

[0076] A data storage pattern (DSP) may include a storage electrode (SE), a plate electrode (PE), and a dielectric film (CIL) between them. As an example, a three-dimensional semiconductor device may be a dynamic random access memory (DRAM), in which case the data storage pattern (DSP) may be utilized as a capacitor. The storage electrode (SE) may be separated from the plate electrode (PE) by a dielectric film (CIL).

[0077] A second lower liner pattern (130) and a second upper liner pattern (140) may be provided between the data storage pattern (DSP) and the substrate (100). The second lower liner pattern (130) and the second upper liner pattern (140) may be provided between the plate electrodes (PE) and the substrate (100). The data storage pattern (DSP) may cover the upper surfaces of the second lower liner pattern (130) and the second upper liner pattern (140). For example, the plate electrodes (PE) may be vertically overlapped with the second lower liner pattern (130) and the second upper liner pattern (140).

[0078] The second lower liner pattern (130) extends along the first direction (D1) on the substrate (100) and can cover the upper surface of the substrate (100). The second lower liner pattern (130) may include a second horizontal portion (HP2) and a second vertical portion (VP2). The second horizontal portion (HP2) may be vertically overlapped with the second upper liner pattern (140), and the second vertical portion (VP2) may be a portion extending along the third direction (D3) from both ends of the second horizontal portion (HP2) according to the second direction (D2). The second vertical portion (VP2) may partially cover the side wall of the second upper liner pattern (140).

[0079] The second upper liner pattern (140) may extend along the first direction (D1) on the second lower liner pattern (130). A second horizontal portion (HP2) of the second lower liner pattern (130) may be interposed between the second upper liner pattern (140) and the substrate (100). A plate electrode (PE) may be disposed on the upper surface and side wall of the second upper liner pattern (140). For example, the second upper liner pattern (140) may include a second void (SM2) formed inside. The second void (SM2) may refer to a seam formed inside the second upper liner pattern (140). For another example, the second void (SM2) may not be formed inside the second upper liner pattern (140).

[0080] The second lower liner pattern (130) and the second upper liner pattern (140) may comprise different materials. For example, the second lower liner pattern (130) and the second upper liner pattern (140) may comprise materials with different resistance to etching. As an example, the second lower liner pattern (130) may comprise silicon oxide, and the second upper liner pattern (140) may comprise at least one of silicon nitride, silicon carbide, and polysilicon (Poly-Si). The second upper liner pattern (140) may further comprise silicon oxide.

[0081] A dielectric film (CIL) may be interposed between the second lower liner pattern (130) and the second upper liner pattern (140) and the plate electrode (PE). The dielectric film (CIL) may cover the side walls of the second lower liner pattern (130) and the second upper liner pattern (140).

[0083] FIG. 7b is a cross-sectional view of a three-dimensional semiconductor device according to some embodiments of the present invention, corresponding to FIG. 7a. For the sake of simplicity, explanations that overlap with the aforementioned content are omitted, and the differences from the aforementioned content are explained primarily.

[0084] Referring to FIG. 7b, the second upper liner pattern (140) may have a recessed upper surface (140_RU) facing the substrate (100). In other words, the second upper liner pattern (140) may have a shape with a recessed upper surface. For example, the recessed upper surface (140_RU) of the second upper liner pattern (140) may have a circular or elliptical shape in a planar view. For example, the recessed upper surface (140_RU) of the second upper liner pattern (140) may have a U-shape in a cross-sectional view.

[0085] The plate electrode (PE) may include a second protrusion (PEp) that protrudes toward the recessed upper surface (140_RU) of the second upper liner pattern (140). The second protrusion (PEp) may be part of the plate electrode (PE) and may extend along a third direction (D3) to cover the recessed upper surface (140_RU) of the second upper liner pattern (140). The second protrusion (PEp) of the plate electrode (PE) may be spaced apart from the second edge portions (EA2) of the first and third semiconductor patterns (SP1, SP3).

[0087] FIGS. 8 to 27 are drawings illustrating a method for manufacturing a three-dimensional semiconductor device according to some embodiments of the present invention. Specifically, FIGS. 9, 11, 13, 15, 17, 19, and 21 are plan views illustrating a three-dimensional semiconductor device according to some embodiments of the present invention and correspond to FIG. 3. FIGS. 10, 12, 14, 16, 18, 20, and 22 are cross-sectional views corresponding to line AA' of FIGS. 9, 11, 13, 15, 17, 19, and 21, respectively. FIGS. 23 and 25 are plan views illustrating a three-dimensional semiconductor device according to some embodiments of the present invention and correspond to FIG. 6. FIGS. 24 and 26 are cross-sectional views corresponding to line CC' of FIGS. 23 and 25, respectively. FIG. 27 is a cross-sectional view corresponding to FIG. 26.

[0088] Referring to FIG. 8, a substrate (100) may be prepared. Sacrificial layers (SAL) and active layers (ACL) may be formed to be alternately stacked on the substrate (100). Each of the sacrificial layers (SAL) and the active layers (ACL) may include a semiconductor material. The sacrificial layers (SAL) may include a material that has an etching selectivity ratio with respect to the active layers (ACL). Accordingly, when the sacrificial layers (SAL) are removed during the removal process described later, the active layers (ACL) may not be removed or may be removed only minimally. For example, the active layers (ACL) may include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the sacrificial layers (SAL) may include one other than the active layers (ACL) among silicon (Si), germanium (Ge), and silicon-germanium (SiGe). For example, the active layers (ACL) may comprise silicon (Si), and the sacrificial layers (SAL) may comprise silicon-germanium (SiGe). For example, with respect to the third direction (D3), the thickness of the sacrificial layers (SAL) may be greater than the thickness of the active layers (ACL), but is not limited thereto.

[0089] Referring to FIGS. 9 and 10, first holes (HL1) can be formed on a substrate (100) by removing a portion of each of the sacrificial layers (SAL) and the active layers (ACL). The first holes (HL1) can be formed adjacent to each other in a first direction (D1) and a second direction (D2). By the first holes (HL1), a portion of the upper surface of the substrate (100) can be exposed to the outside. Through the removal process, the sacrificial layers (SAL) and the active layers (ACL) can be formed to include regions extending elongatedly in the first direction (D1) and regions extending elongatedly in the second direction (D2).

[0090] The first pre-filling patterns (PF1) may cover the exposed portion of the upper surface of the substrate (100) and may be formed to fill the interior of the first holes (HL1). For example, the first pre-filling patterns (PF1) may include an insulating material. The first pre-filling patterns (PF1) may be formed to be adjacent to each other in a first direction (D1) and a second direction (D2).

[0091] By removing a portion of the regions of the sacrificial layers (SAL) and active layers (ACL) that extend elongated in the first direction (D1), second holes (HL2) can be formed on the substrate (100). The second holes (HL2) can be formed to extend along the first direction (D1). By the second holes (HL2), both sides of the sacrificial layers (SAL) and active layers (ACL) can be exposed to the outside. By the second holes (HL2), a portion of the upper surface of the substrate (100) can be exposed to the outside.

[0092] Referring to FIGS. 11 and 12, the exposed sides of the sacrificial layers (SAL) can be selectively removed through the second holes (HL2). Accordingly, first internal regions (INR1) can be formed between the active layers (ACL) arranged along the third direction (D3). During the removal process, a portion of each of the first pre-filling patterns (PF1) can be removed together. The sidewalls of the first pre-filling patterns (PF1) can be aligned with the sidewalls of the sacrificial layers (SAL).

[0093] A second pre-filling pattern (PF2) may be formed to fill the interior of the first internal regions (INR1), the region from which a portion of the first pre-filling patterns (PF1) has been removed, and the second holes (HL2). The second pre-filling pattern (PF2) may surround and cover the active layers (ACL) that do not vertically overlap with the sacrificial layers (SAL). The second pre-filling pattern (PF2) may comprise a single film or a composite film containing an insulating material. As an example, the second pre-filling pattern (PF2) may comprise at least one of silicon oxide and silicon nitride.

[0094] Referring to FIGS. 13 and 14, a third hole (HL3) can be formed on a substrate (100) by removing a region that extends elongatedly in a first direction (D1) among the sacrificial layers (SAL) and active layers (ACL). During the process of forming the third holes (HL3), one active layer (ACL) can be separated into semiconductor patterns (SP) that are adjacent to each other in the first direction (D1). The semiconductor pattern (SP) may include a first semiconductor pattern (SP1) and a second semiconductor pattern (SP2) that are adjacent to each other in a second direction (D2). Immediately after the formation of the third holes (HL3), the sacrificial layers (SAL) can be exposed to the outside again.

[0095] Through the third holes (HL3), the exposed sacrificial layers (SAL) can be completely removed from the substrate (100). Accordingly, second internal regions (INR2) can be formed between the second pre-filling pattern (PF2 in FIG. 12) and some regions of the active layers (ACL) that do not overlap. During the removal process, the first pre-filling patterns (PF1 in FIG. 13) can be completely removed from the substrate (100). Subsequently, the third pre-filling pattern (PF3) can be formed to fill the second internal regions (INR2), the region where the first pre-filling patterns (PF1 in FIG. 13) were removed, and the interior of the third holes (HL3). The third pre-filling pattern (PF3) may include a single film or a composite film comprising an insulating material. As an example, the third pre-filling pattern (PF3) may include at least one of silicon oxide and silicon nitride.

[0096] Subsequently, the second pre-filled pattern (PF2 in FIG. 12) can be removed from the substrate (100). Subsequently, a gate dielectric film (Gox) and a pre-gate conductive film (PGE) can be formed sequentially within the first internal regions (INR1), and these can form a pre-word line (PWL). The gate dielectric film (Gox) and the pre-gate conductive film (PGE) can be formed to conformally cover a portion of the semiconductor pattern (SP) in turn. The gate dielectric film (Gox) and the pre-gate conductive film (PGE) can be formed to surround and cover a portion of the semiconductor pattern (SP). One gate dielectric film (Gox) and one pre-gate conductive film (PGE) can be formed to surround and cover a portion of each of the semiconductor patterns (SP) that are adjacent to each other in the first and third directions (D1, D3). Subsequently, an interlayer insulating film (ILD) may be formed in the area where the first internal regions (INR1) and the second pre-filling pattern (PF2) have been removed. During the process of forming the interlayer insulating film (ILD), a pre-void (SMp) may be formed inside the interlayer insulating film (ILD). The pre-void (SMp) may, for example, refer to a seam formed during the process of filling a trench with a high aspect ratio.

[0097] Referring to FIGS. 15 and 16, a first mask pattern (MP1) may be formed on a semiconductor pattern (SP) and a third pre-filled pattern (PF3). The first mask pattern (MP1) may not be formed in the region between adjacent first and second semiconductor patterns (SP1, SP2). An etching process may be performed using the first mask pattern (MP1) as an etching mask, and a first trench (TR1) may be formed. The first trench (TR1) may extend in a first direction (D1) and may expose the sidewalls of the semiconductor pattern (SP) and the sidewalls of the interlayer insulating film (ILD).

[0098] Subsequently, a first lower liner pattern (110) and a first upper liner pattern (120) may be formed to conformally fill the first trench (TR1). Forming the first lower liner pattern (110) and the first upper liner pattern (120) may include conformally depositing a first lower liner film within the first trench (TR1), filling the first trench (TR1) with a first upper liner film, and performing a planarization process on the first lower liner film and the first upper liner film. Due to the high aspect ratio of the first trench (TR1), the first upper liner pattern (120) may include a first void (SM1) formed inside.

[0099] Referring to FIGS. 17 and 18, a fourth hole (HL4) can be formed between the semiconductor pattern (SP) and the first upper liner pattern (120). In the process of forming the fourth hole (HL4), a portion of the upper part of the first upper liner pattern (120) may be removed. The fourth hole (HL4) can be formed by removing a portion of the first lower liner pattern (110). After forming the fourth hole (HL4) and performing a cleaning process, the sidewalls of the interlayer insulating film (ILD) and the semiconductor pattern (SP) may be exposed again.

[0100] For example, due to the high aspect ratio of the first trench (TR1), voids (or seams) may be formed within the filler material during the process of filling the first trench (TR1). Consequently, dispersion control may not be achieved during subsequent processes of exposing the sidewalls of the semiconductor pattern (SP) and cleaning, as the voids may be exposed.

[0101] However, according to embodiments of the present invention, a first upper liner pattern (120) having a relatively hard film quality compared to the first lower liner pattern (110) and the interlayer insulating film (ILD) may be formed within the first trench (TR1). A first void (SM1, or seam) may be formed within the first upper liner pattern (120), and as the first upper liner pattern (120) has etch selectivity, the first void (SM1) may not be exposed to the outside. As a result, the influence of the first void (SM1) can be minimized during the manufacturing process of the three-dimensional semiconductor device. Therefore, the reliability of the three-dimensional semiconductor device can be improved.

[0102] Referring to FIGS. 19 and 20, bit lines (BL) that fill the fourth holes (HL4) can be formed. Forming the bit lines (BL) may include filling the fourth holes (HL4) with a conductive material and flattening the conductive material.

[0103] Referring to FIGS. 21 and 22, a first mask pattern (MP1) can be removed, and the upper surface of a semiconductor pattern (SP) can be exposed. Removing the first mask pattern (MP1) may include performing a planarization process. A third pre-filled pattern (PF3 in FIG. 20) can be removed from the substrate (100). During the removal process of the third pre-filled pattern (PF3 in FIG. 20), a portion of each of the gate dielectric film (Gox) and the pre-gate conductive film (PGE) may also be removed together. Accordingly, a single gate dielectric film (Gox) can be separated into a plurality of gate dielectric films (Gox) adjacent to each other in a third direction (D3). Additionally, a single pre-gate conductive film (PGE) can be separated into a plurality of gate patterns (GE) adjacent to each other in a third direction (D3). The gate dielectric film (Gox) and the gate pattern (GE) can form a word line (WL).

[0104] A capping pattern (CP) may be formed within the area where the third pre-filling pattern (PF3 in FIG. 18) has been removed. The capping pattern (CP) may include a first capping pattern (CP1) and a second capping pattern (CP2).

[0105] A second mask pattern (MP2) covering the semiconductor pattern (SP) and bit line (BL) may be formed. An etching process may be performed using the second mask pattern (MP2) as an etching mask, and a second trench (TR2) may be formed. The second trench (TR2) may be formed by removing a portion of the capping pattern (CP). The second trench (TR2) may extend in a first direction (D1) and may expose the sidewall of the semiconductor pattern (SP) and the sidewall of the capping pattern (CP).

[0106] Referring to FIGS. 23 and 24, first semiconductor patterns (SP1) and third semiconductor patterns (SP3) adjacent to the second direction (D2) may be provided. The third semiconductor patterns (SP3) and the word lines (WL) and capping pattern (CP) surrounding them may be formed in substantially the same manner as described above in FIGS. 8 through 22. A second mask pattern (MP2) may not be formed in the region between adjacent first and third semiconductor patterns (SP1, SP3). A second lower liner pattern (130) and a second upper liner pattern (140) that conformally fill the second trench (TR2) may be formed. Forming the second lower liner pattern (130) and the second upper liner pattern (140) may include conformally depositing a second lower liner film within a second trench (TR2), filling the second trench (TR2) with a second upper liner film, and performing a planarization process on the second lower liner film and the second upper liner film. Due to the high aspect ratio of the second trench (TR2), the second upper liner pattern (140) may include a second void (SM2) formed inside.

[0107] Referring to FIGS. 25 and 26, a portion of the second lower liner pattern (130) may be selectively removed. Removing a portion of the second lower liner pattern (130) may be performed through a dry etching process or a wet etching process. In the process of removing a portion of the second lower liner pattern (130), a portion of the second upper liner pattern (140) may also be removed.

[0108] Subsequently, a portion of the capping pattern (CP) may be removed. As a portion of the capping pattern (CP) is removed, the second edge portions (EA2) of the semiconductor pattern (SP) may be exposed. During the process of removing the capping pattern (CP) while exposing the second edge portions (EA2), a portion of the second lower liner pattern (130) may be further removed. A cleaning process may be performed on the second edge portions (EA2) of the semiconductor pattern (SP).

[0109] For example, due to the high aspect ratio of the second trench (TR2), voids (or seams) may be formed within the filler material (e.g., the third pre-filling pattern (PF3) of FIG. 20) during the process of filling the second trench (TR2). As a result, dispersion control may not be achieved because the voids are exposed during the process of exposing the sidewalls of the semiconductor pattern (SP) and during the cleaning process.

[0110] However, according to embodiments of the present invention, a second upper liner pattern (140) having a relatively hard film compared to the second lower liner pattern (130) and the capping pattern (CP) may be formed within the second trench (TR2). A second void (SM2, or seam) may be formed within the second upper liner pattern (140), and as the second upper liner pattern (140) has etch selectivity, the second void (SM2) may not be exposed to the outside. As a result, the impact of the second void (SM2) can be minimized during the manufacturing process of the three-dimensional semiconductor device. Therefore, the reliability of the three-dimensional semiconductor device can be improved.

[0111] Referring to FIG. 27, storage electrodes (SE) may be formed on the second edge portions (EA2) of semiconductor patterns (SP). For example, forming the storage electrodes (SE) may include forming silicide patterns (not shown) on the second edge portions (EA2) of semiconductor patterns (SP), and forming the storage electrodes (SE) through an SEG process using the silicide patterns as seeds. As a result, a portion of the semiconductor pattern (SP) adjacent to the storage electrode (SE) may be referred to as the second edge portion (EA2).

[0112] A dielectric film (CIL) can be formed to conformally cover the storage electrodes (SE). A plate electrode (PE) can be formed to fill the space between the storage electrodes (SE). As the storage electrodes (SE), dielectric film (CIL), and plate electrode (PE) are formed, a data storage pattern (DSP) can be formed.

[0113] Referring again to FIGS. 3, FIGS. 4a, FIGS. 6, and FIGS. 7a, the second mask pattern (MP2) can be removed, and the upper surface of the semiconductor pattern (SP) can be exposed. An upper insulating film (UIL) covering the data storage pattern (DSP), bit line (BL), and semiconductor pattern (SP) can be formed.

[0115] FIGS. 28 and 29 are drawings illustrating a method for manufacturing a three-dimensional semiconductor device according to some embodiments of the present invention. Specifically, FIG. 28 is a cross-sectional view corresponding to FIG. 18, and FIG. 29 is a cross-sectional view corresponding to FIG. 20.

[0116] Referring to FIG. 28, after the formation process of the first lower liner pattern (110) and the first upper liner pattern (120) described with reference to FIG. 15 and FIG. 16, a portion of the first upper liner pattern (120) may be further removed during the process of forming the fourth holes (HL4). For example, a portion of the first upper liner pattern (120) may be removed so that the first void (SM1 in FIG. 16) of the first upper liner pattern (120) is exposed to the top. As a result, the first upper liner pattern (120) may have a recessed upper surface (120_RU). However, the first void (SM1 in FIG. 16) of the first upper liner pattern (120) may not be exposed in a horizontal direction or in a direction toward the substrate (100).

[0117] Referring to FIG. 29, bit lines (BL) may be formed within the fourth holes (HL4). Each of the bit lines (BL) may include a first protrusion (BLp) that protrudes toward the recessed upper surface (120_RU) of the first upper liner pattern (120). The first protrusion (BLp) of each of the bit lines (BL) may cover the recessed upper surface (120_RU) of the first upper liner pattern (120).

[0118] The above description of the embodiments of the present invention provides examples for explaining the present invention. Accordingly, the present invention is not limited to the above embodiments, and it is evident that many modifications and changes are possible within the technical scope of the present invention, such as combining the above embodiments by those skilled in the art. Explanation of the symbols

[0119] 100: Substrate SP1: First semiconductor pattern SP2: Second Semiconductor Pattern SP3: The Third Semiconductor Pattern 110: First lower liner pattern 120: First upper liner pattern 130: Second lower liner pattern 140: Second upper liner pattern BL: Beatline

Claims

Claim 1 A three-dimensional semiconductor device comprising: a substrate; first semiconductor patterns disposed on the substrate and spaced apart from each other in a first direction parallel to the lower surface of the substrate; second semiconductor patterns adjacent to the first semiconductor patterns in a second direction parallel to the lower surface of the substrate and spaced apart from each other in the first direction; a lower liner pattern disposed on the substrate and extending in the first direction between the first semiconductor patterns and the second semiconductor patterns; an upper liner pattern extending in the first direction on the lower liner pattern; and bit lines disposed between the first semiconductor patterns and the upper liner pattern, and between the second semiconductor patterns and the upper liner pattern, wherein the bit lines extend in a third direction perpendicular to the first and second directions on the lower liner pattern. Claim 2 A three-dimensional semiconductor device according to claim 1, wherein the lower liner pattern comprises a horizontal portion vertically overlapping with the upper liner pattern and a vertical portion protruding in a third direction perpendicular to the first and second directions from both ends of the second direction of the horizontal portion, wherein the vertical portion partially covers the side wall of the upper liner pattern. Claim 3 A three-dimensional semiconductor device according to paragraph 2, wherein the vertical portion includes a first portion vertically overlapping with the bit line in a planar view and a second portion adjacent to the first portion in the first direction, and the upper surface of the first portion is located at a lower level than the upper surface of the second portion. Claim 4 A three-dimensional semiconductor device according to claim 1, wherein the upper liner pattern and the lower liner pattern comprise different materials. Claim 5 A three-dimensional semiconductor device according to claim 1, wherein the bit lines connect the first semiconductor patterns and the second semiconductor patterns adjacent to each other in the second direction, and the bit lines cross the lower liner pattern and the upper liner pattern. Claim 6 A three-dimensional semiconductor device according to claim 1, further comprising word lines extending in the first direction across the first and second semiconductor patterns, wherein the word lines are spaced apart from the upper liner pattern in the second direction. Claim 7 A three-dimensional semiconductor device according to claim 1, wherein the upper liner pattern has an upper surface recessed toward the substrate, and each of the bit lines includes a protrusion protruding toward the recessed upper surface of the upper liner pattern. Claim 8 A three-dimensional semiconductor device according to claim 1, wherein each of the bit lines includes a first bit line and a second bit line spaced apart from each other along the second direction, and the upper liner pattern is disposed between the first bit line and the second bit line. Claim 9 In claim 1, the upper liner pattern is a three-dimensional semiconductor device comprising a void formed therein. Claim 10 A three-dimensional semiconductor device comprising: a substrate; first semiconductor patterns disposed on the substrate and spaced apart from each other in a first direction parallel to the lower surface of the substrate; bit lines on first sidewalls of the first semiconductor patterns; data storage patterns on second sidewalls facing the first sidewalls of the first semiconductor patterns in a second direction parallel to the lower surface of the substrate; a lower liner pattern between the data storage pattern and the substrate; and an upper liner pattern between the data storage pattern and the lower liner pattern, wherein the lower liner pattern and the upper liner pattern extend in the first direction.

Images