Clock and data recovery circuit and data driver circuit with the same

Abstract

A clock data recovery circuit according to one embodiment of the present specification includes a bang-bang phase detector, a charge pump unit, and a voltage-controlled oscillator. The bang-bang phase detector detects an edge of a clock training pattern in a clock training interval and outputs an edge detection signal to a charge pump unit, thereby having an alignment function that aligns the sampling timing order of a multi-phase clock signal based on the edge of the clock training pattern. In a data interval, it can output output data having a predetermined order by sampling a received signal by each of a plurality of clock signals among the aligned multi-phase clock signals.

Description

Technology Field

[0001] This specification relates to a clock data recovery circuit having an automatic data alignment function and a data driving circuit having the same. Background Technology

[0002] In a display driving device, the data driving circuit (or source driving circuit) can receive digital image data from the timing controller, convert it into an analog data voltage, and supply it to the display panel.

[0003] The timing controller and data driving circuit can transmit and receive video data and various control information through a high-speed serial interface.

[0004] The data driving circuit includes a clock data recovery circuit that recovers clock and data from a signal received via high-speed serial communication. The data driving circuit includes a data alignment logic circuit and utilizes the data recovered from the clock data recovery circuit by aligning it symbol by symbol.

[0005] Data driving circuits require simplified circuit configuration and low power consumption. The problem to be solved

[0006] The present specification provides a clock data recovery circuit having an automatic data alignment function.

[0007] The present specification provides a data driving circuit that can simplify circuit configuration and reduce power consumption by utilizing a clock data recovery circuit having an automatic data alignment function. means of solving the problem

[0008] A clock data recovery circuit according to one embodiment of the present specification includes a bang-bang phase detector that detects a phase difference between a received signal and a multi-phase clock signal and outputs an output signal corresponding to the phase difference, a charge pump unit that outputs a control voltage by charging and discharging a loop filter based on the output signal of the bang-bang phase detector, and a voltage-controlled oscillator that generates and outputs the multi-phase clock signal having multiple phases and an oscillation frequency adjusted according to the control voltage. The bang-bang phase detector has an alignment function that detects an edge of a clock training pattern in a clock training interval and outputs an edge detection signal to the charge pump unit to align the sampling timing order of the multi-phase clock signal based on the edge of the clock training pattern, and can output output data having a predetermined order by sampling the received signal by each of a plurality of clock signals among the aligned multi-phase clock signals in a data interval.

[0009] According to one embodiment, the bang-bang phase detector includes a phase comparison unit, and the phase comparison unit may include a sampling unit that samples and latches the received signal by each of the multi-phase clock signals and outputs a plurality of sampling data, a phase difference detection unit that compares the plurality of sampling data with each other and outputs a plurality of detection signals indicating whether there is a phase difference, and a buffer unit that buffers each of the plurality of sampling data and outputs the restored data.

[0010] According to one embodiment, the bang-bang phase detector further includes a pulse generator and a first output unit, wherein the pulse generator outputs a plurality of up signals and a plurality of down signals having 1UI based on the plurality of detection signals output from the phase comparison unit, and the first output unit outputs a first up output signal by performing a logical OR operation on the plurality of up signals and outputs a first down output signal by performing a logical OR operation on the plurality of down signals.

[0011] According to one embodiment, the bang-bang phase detector can detect the edge detection signal by using data sampled by a first specific clock signal for aligning with the edge of the clock training pattern among the multi-phase clock signals, and data sampled by a second specific clock signal having a phase difference of 1.5 UI with the first specific clock signal.

[0012] In one embodiment, the multi-phase clock signal includes first to sixth clock signals that are sequentially delayed with a phase difference of 0.5 UI, and the bang-bang phase detector can align the falling edge of the clock training pattern with the sampling timing of the second clock signal.

[0013] According to one embodiment, the bang-bang phase detector further includes first and second edge detection units, and the first edge detection unit may output a first edge detection signal having a pulse width of 1 UI in the overlap interval of the second inverted sampling data of the second sampling data sampled by the second clock signal and the fifth sampling data sampled by the fifth clock signal. The first edge detection unit may include a first edge detection unit that outputs a first edge information signal by performing a logical AND operation on the second inverted sampling data and the fifth sampling data, and a first pulse generation unit that outputs the first edge detection signal by performing a logical AND operation on the first edge information signal, the second clock signal, and a fourth inverted clock signal of the fourth clock signal having a phase difference of 1 UI with the second clock signal. The first edge detection unit can increase the speed of the multi-phase clock signal by outputting the first edge detection signal when the sampling timing of the second clock signal is slower than the falling edge of the clock training pattern within the range of 0.0 UI to 1.5 UI.

[0014] The second edge detection unit may output a second edge detection signal having a pulse width of 1 UI in the overlap interval of the second sampling data and the fifth inverted sampling data of the fifth sampling data. The second edge detection unit may include a second edge detection unit that outputs a second edge information signal by performing a logical AND operation on the second sampling data and the fifth inverted sampling data, and a second pulse generation unit that outputs the second edge detection signal by performing a logical AND operation on the second edge information signal, the fifth clock signal, and a first inverted clock signal of the first clock signal having a phase difference of 1 UI with the fifth clock signal. The second edge detection unit may reduce the speed of the multi-phase clock signal by outputting the second edge detection signal when the sampling timing of the second clock signal is faster than the falling edge of the clock training pattern within the range of 0.0 UI to 1.5 UI.

[0015] The bang-bang phase detector according to one embodiment further includes a second output unit, wherein the second output unit outputs a second up output signal by performing a logical OR operation on the first edge detection signal from the first edge detection unit and the first up output signal from the first output unit, and outputs a second down output signal by performing a logical OR operation on the second edge detection signal from the second edge detection unit and the first down output signal from the first output unit.

[0016] The first and second edge detection units can be enabled by an edge detection enable signal during the clock training interval of each horizontal blank period.

[0017] A data driving circuit according to one embodiment of the present specification may include a serial-to-parallel converter including the clock data recovery circuit, and a data driving unit that converts image data output from the serial-to-parallel converter into a data voltage and outputs it.

[0018] The above serial-to-parallel converter may include a serial-to-parallel converter circuit that converts the output of the clock data recovery circuit into a parallel form, a decoder that decodes the output of the serial-to-parallel converter circuit, and a pixel alignment logic circuit that aligns the output of the decoder in pixel units. Effects of the invention

[0019] A clock data recovery circuit according to one embodiment of the present specification can perform a data alignment operation in a bang-bang phase detector even if the phase difference between the data and the clock is greater than 1 UI, thereby aligning and maintaining the phase of a specific clock based on the edge of a clock training pattern. Accordingly, the clock data recovery circuit according to one embodiment can output data in which the order of data bits is aligned at the symbol level by fixing the order of data sampled by a multi-phase clock.

[0020] In a data driving circuit according to one embodiment of the present specification, the clock data recovery circuit has an automatic data alignment function, so the data alignment logic circuit according to the comparative example is unnecessary, thereby simplifying the circuit configuration, reducing the circuit size, and reducing power consumption. Brief explanation of the drawing

[0021] FIG. 1 is a block diagram schematically showing the configuration of a data driving circuit according to one embodiment of the present specification. FIG. 2 is a block diagram schematically showing the configuration of a serial-to-parallel converter according to one embodiment of the present specification. FIG. 3 is a block diagram schematically showing the configuration of a serial-parallel converter according to a comparative example of the present specification. FIG. 4 is a timing diagram illustrating a sequence of transmission signals received by a data driving circuit according to one embodiment of the present specification. FIGS. 5 to 7 are drawings for explaining the edge detection operation of a bang-bang phase detector according to one embodiment of the present specification. FIG. 8 is a circuit diagram illustrating the configuration of a bang-bang phase detector according to one embodiment of the present specification. FIG. 9 is a timing diagram for explaining the edge detection operation of the first edge detection unit illustrated in FIG. 8. FIG. 10 is a timing diagram for explaining the edge detection operation of the second edge detection unit illustrated in FIG. 8. FIG. 11 is a timing diagram illustrating data output from a clock data recovery circuit according to a comparative example of the present specification. FIG. 12 is a timing diagram illustrating data output from a clock data recovery circuit according to one embodiment of the present specification. Specific details for implementing the invention

[0022] The advantages and features of this specification and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of this specification, and this specification is defined only by the scope of the claims.

[0023] Throughout the specification, the same reference numerals refer to the same components. Additionally, in describing this specification, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions would unnecessarily obscure the essence of this specification.

[0024] Where terms such as 'comprising,' 'having,' 'consisting of,' etc. are used in this specification, other parts may be added unless 'only' is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0025] In interpreting the components, even if there is no separate explicit description of the error range, it is interpreted as including the error range.

[0026] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using terms such as "on," "upper," "lower," "next to," or "adjacent," unless terms such as "immediately," "directly," or "nearby" are used, one or more other parts may be located between the two parts.

[0027] In the case of an explanation of a temporal relationship, for example, when a temporal sequence is explained using 'after', 'following', 'next', 'before', etc., it may include cases where the sequence is not continuous unless 'immediately' or 'directly' is used.

[0028] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this specification.

[0029] The term “at least one” should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of “at least one of the first item, the second item and the third item” may mean not only the first item, the second item or the third item individually, but also all combinations of items that can be presented from two or more of the first item, the second item and the third item.

[0030] The features of each of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0031] Hereinafter, preferred embodiments of the present specification will be described with reference to the attached drawings. The scale of the components shown in the drawings may differ from the actual scale for the convenience of explanation and is therefore not limited to the scale shown in the drawings.

[0032] FIG. 1 is a block diagram schematically showing the configuration of a data driving circuit according to one embodiment of the present specification, FIG. 2 is a block diagram schematically showing the configuration of a serial-parallel converter according to one embodiment of the present specification, and FIG. 3 is a block diagram schematically showing the configuration of a serial-parallel converter according to a comparative example of the present specification.

[0033] Referring to FIG. 1, a data driving circuit (1) according to one embodiment can drive data lines of a display device. The data driving circuit (1) may include a Serial to Parallel Converter (10), a Shift Register (30), a latch unit (40) including a 2-Line Latch, a Digital-to-Analog (D / A) Converter (50), and a Multi-Channel Output Circuit (60). The Shift Register (30), the latch unit (40), the Digital-to-Analog (D / A) Converter (50), and the Multi-Channel Output Circuit (60) may be represented as a data driving unit.

[0034] The serial-to-parallel converter (10) can receive a transmission signal (DATAP / DATAN) in the form of a differential signal transmitted via a high-speed serial interface through a transmission lane from the timing controller of the display device. The serial-to-parallel converter (10) can recover and output clock signals, image data, and control signals from the received transmission signal (DATAP / DATAN). The serial-to-parallel converter (10) according to one embodiment may include a clock data recovery circuit (CDR) illustrated in FIG. 2. The clock data recovery circuit (CDR) according to one embodiment can output data in which bits are aligned in order at the symbol level using a bang-bang phase detector (PD+Align) (120) having an automatic data alignment function. A detailed explanation thereof will be provided later.

[0035] The shift register (30) can sequentially output a plurality of sampling signals to the latch unit (40) while sequentially shifting the source start pulse provided from the serial-parallel converter (10) according to the source shift clock.

[0036] The latch unit (40) may include a 2-line latch unit comprising a first line latch unit and a second line latch unit. The first line latch unit of the latch unit (40) may sequentially latch image data (R, G, B) transmitted from the serial-to-parallel converter (10) via a data bus in response to a sampling signal from the shift register (30) in subpixel units. The first line latch unit may sequentially latch image data of one horizontal line and then simultaneously output the latched image data to the second line latch unit. The second line latch unit may simultaneously latch multi-channel image data from the first line latch unit and simultaneously output it to the D / A converter (50).

[0037] The D / A converter (50) can convert multi-channel image data supplied from the latch unit (40) into an analog data voltage using a plurality of gamma voltages (GMA) and output the multi-channel data voltage to the multi-channel output circuit (60).

[0038] The multi-channel output circuit (60) may be equipped with a multi-channel output buffer. The multi-channel output circuit (60) may buffer the multi-channel data voltage supplied from the D / A converter (50) and output the multi-channel data voltage (OUT1~OUTm) to a display panel.

[0039] Referring to FIG. 2, a serial-to-parallel converter (1) according to one embodiment may include a receiver (100) and a control logic unit (110). The receiver (100) may include an equalizer (EQ), a clock data recovery circuit (CDR), a serial-to-parallel converter circuit (S2P), etc. The control logic unit (110) may include a decoder (112) and a pixel alignment logic circuit (114).

[0040] The equalizer (EQ) can compensate for transmission line loss of the received signal (DATAP / DATAN) transmitted through the transmission lane and can output the compensated received signal (RXO) to the clock data recovery circuit (104).

[0041] The clock data recovery circuit (CDR) receives the received signal (RXO) through an equalizer (EQ), recovers the clock and data from the received signal (RXO), and outputs them to the serial-to-parallel conversion circuit (S2P).

[0042] The clock data recovery circuit (CDR) may use a phase-locked loop (PLL) circuit equipped with a bang-bang phase detector (PD+Align) (120) having an automatic data alignment function, a charge pump (CP), a loop filter (LF), and a voltage-controlled oscillator (VCO).

[0043] A Bang-Bang Phase Detector (120) can detect the phase difference between a received signal (RXO) and a multi-phase clock signal, i.e., an N-phase (N-Phase, where N is an integer greater than or equal to 2) clock signal (CK0~CK(N-1)), and generate an up signal (UP) or down signal (DN) corresponding to the phase difference and output it to a charge pump unit (CP).

[0044] For example, the bang-bang phase detector (PD) can output a high-level up signal (UP) if at least one of the N-phase clock signals (CK0 to CK(N-1)) is out of phase (out of speed) compared to the received signal (RXO). The bang-bang phase detector (PD) can output a high-level down signal (DN) if at least one of the N-phase clock signals (CK0 to CK(N-1)) is out of phase (out of speed) compared to the received signal (RXO).

[0045] N-phase clock signals (CK0~CK(N-1)) aligned sequentially with the same frequency and constant phase difference can be generated in a voltage-controlled oscillator (VCO) and fed back.

[0046] The bang-bang phase detector (120) can output data sampled by each of a plurality of clock signals having a phase difference of 1UI interval among the N-phase clock signals (CK0~CK(N-1)) from the received signal (RXO) to a serial-to-parallel conversion circuit (S2P).

[0047] According to one embodiment, the bang-bang phase detector (120) can detect the edge of the clock training pattern during the clock training interval of the horizontal blank period for each horizontal period of the display mode and generate an up signal (UP) or down signal (DN) to control the speed of the N-phase clock signal (CK0~CK(N-1)). Accordingly, the bang-bang phase detector (120) can maintain the sampling timing of each of the plurality of clock signals in order based on the edge of the clock training pattern. Therefore, the data bits sampled from the receiving signal (RXO) by each of the plurality of clock signals maintaining the aligned sampling timing in the bang-bang phase detector (120) are aligned in order at the symbol level, thus having an automatic data alignment function. In one embodiment, the bang-bang phase detector (120) can perform a data alignment operation using the clock training pattern even during the vertical blank period.

[0048] A bang-bang phase detector (120) according to one embodiment detects edge information of a clock training pattern input as a received signal (RXO) during a clock training interval and can output an up signal (UP) or a down signal (DN) according to the edge information. Accordingly, the bang-bang phase detector (120) can match the edge of the clock training pattern with the phase of a predetermined specific clock among the N-phase clock signals (CK0~CK(N-1)). Therefore, as the sampling timing of each of the plurality of clock signals is aligned and maintained at a predetermined position in the bang-bang phase detector (120), the order of data bits sampled by each of the plurality of clock signals can also be fixed in a predetermined order. Therefore, the bang-bang phase detector (120) can output data in which data bits are aligned in order at the symbol level from the received signal (RX).

[0049] The charge pump unit (CP) outputs current according to the up signal (UP) or down signal (DN) from the bang-bang phase detector (PD) to charge and discharge the loop filter (LF), thereby the loop filter (LF) can generate a control voltage (VCTRL) proportional to the current of the charge pump unit (CP) and output it to the voltage-controlled oscillator (VCO). The loop filter (LF) may have a low-pass filter structure composed of a plurality of resistors and capacitors connected to the charge pump unit (CP), and can remove high-frequency noise components from the control voltage (VCTRL).

[0050] A voltage-controlled oscillator (VCO) can adjust the oscillation frequency according to the control voltage (VCTRL) and generate and output N-phase clock signals (CK0 to CK(N-1)). The voltage-controlled oscillator (VCO) can generate and output N-phase clock signals (CK0 to CK(N-1)) with an oscillation frequency proportional to the control voltage (VCTRL) and sequentially delayed phases. The voltage-controlled oscillator (VCO) can increase the oscillation frequency as the control voltage (VCTRL) increases, and decrease the oscillation frequency as the control voltage (VCTRL) decreases. The number (N) of N-phase clock signals (CK0 to CK(N-1)) generated by the voltage-controlled oscillator (VCO) can be varied.

[0051] The serial-parallel conversion circuit (108) can convert data supplied in a serial form from the bang-bang phase detector (120) of the clock data recovery unit (104) into a parallel form and output it to the control logic unit (110).

[0052] In the control logic unit (110), the decoder (112) can decode data supplied from the serial-to-parallel conversion circuit (108) and output it to the pixel alignment logic circuit (114).

[0053] The pixel alignment logic circuit (114) can align the data supplied from the decoder (112) by pixel and output pixel-unit image data.

[0054] Referring to FIG. 3, the serial-parallel converter (10') according to the comparative example may include a receiver (2) and a control logic unit (4). The receiver (2) may include an equalizer (EQ'), a clock data recovery circuit (CDR'), and a serial-parallel converter circuit (S2P'). The clock data recovery circuit (CDR') may include a bang-bang phase detector (PD'), a charge pump unit (CP'), a loop filter (LF'), and a voltage-controlled oscillator (VCO'). The control logic unit (4) may include a data alignment logic circuit (6), a decoder (7), and a pixel alignment logic circuit (8). The serial-parallel converter (10') according to the comparative example separately includes a data alignment logic circuit (6) that aligns data output from the receiver (2) in symbol units.

[0055] On the other hand, in the serial-parallel converter (10) according to one embodiment of the present specification illustrated in FIG. 2, the bang-bang phase detector (120) of the clock data recovery circuit (CDR) has an automatic data alignment function, so the data alignment logic circuit (6) according to the comparative example is unnecessary. Accordingly, the serial-parallel converter (10) and the data driving circuit (1) including the clock data recovery circuit (CDR) according to one embodiment of the present specification can reduce the circuit size by simplifying the circuit configuration compared to the comparative example, as well as reduce power consumption.

[0056] FIG. 4 is a timing diagram illustrating a sequence of transmission signals received by a data driving circuit according to one embodiment of the present specification, and FIG. 5 to 7 are diagrams for explaining the edge detection operation of a bang-bang phase detector according to one embodiment of the present specification.

[0057] Referring to FIGS. 1, 2 and 4, a data driving circuit (1) according to one embodiment can receive a transmission signal (DATAP / DATAN) through a transmission lane from a timing controller after the power supply (VCC) is turned on.

[0058] The data driving circuit (1) can perform a clock locking operation using a clock training pattern (CT) during an initial clock training period (CTP). The clock data recovery unit (CDR) of the data driving circuit (1) can perform a clock locking operation in which the frequency and phase of the clock training pattern (CT), which is a received signal (RXO), are tracked and aligned by an N-phase clock signal (CK0~CK(N-1)), and can generate a locked N-phase clock signal (CK0~CK(N-1)).

[0059] Each vertical active period (Vactive) of frames (F1, F2) may include a plurality of horizontal periods (H1~H(N)) in which a plurality of horizontal line data (HL1~HL(N)) are transmitted. Each horizontal period (Hi, i=1~N) may include a clock training period (P1), a setting information (H-PKT) period (P2), and an image data (RGB) period (P3). The clock data recovery circuit (CDR) may operate in clock tracking mode during the clock training period (P1) and in edge tracking mode during the setting information (H-PKT) period (P2) and the image data (RGB) period (P3). The clock training period (P1) and the setting information (H-PKT) period (P2) may be included in the horizontal blank period (Hblank) of each horizontal period (HLi, i=1~N). The image data (RGB) interval (P3) may be the horizontal active period (Hactive) of each horizontal period (Hi, i=1~N).

[0060] The clock data recovery circuit (CDR) can perform a data alignment function by detecting the edge of the clock training pattern (CT) in the clock training interval (P1) for each horizontal period (Hi, i=1~N) and adjusting the speed (frequency) of the N-phase clock signal (CK0~CK(N-1)), thereby aligning the sampling timing of each N-phase clock signal (CK0~CK(N-1)) to a predetermined position based on the clock training pattern (CT).

[0061] Referring to FIG. 5, the sampling points of the 6-phase clocks (CK0, CK1, CK2, CK3, CK4, CK5) for the clock training pattern (CT) and data (D<8:0>) are shown in the bang-bang phase detector (120, FIG. 2) when in an ideal locking state.

[0062] For example, the clock training pattern (CT) may be a pattern that repeats periodically with a low level of 4 UI and a high level of 5 UI in one cycle, and the data per symbol unit may have 9-bit data (D<8:0>), but is not limited thereto. For example, the voltage-controlled oscillator (VCO, FIG. 2) may generate 6-phase clock signals (CK0, CK1, CK2, CK3, CK4, CK5), but is not limited thereto.

[0063] The 6-phase clock signals (CK0~CK5) may have a form that is sequentially delayed at intervals of 0.5 (Unit Interval) and periodically cycles. Each of the 6-phase clock signals (CK0~CK5) may have a period of 3 UI consisting of a high level of 1.5 UI (Unit Interval) and a low level of 1.5 UI. The 6-phase clock signals (CK0~CK5) may each be defined as the 1st to 6th clock signals.

[0064] The clock training pattern (CT) can be set such that the falling edge is located between data bits D0 and D1, and the rising edge is located between data bits D4 and D5.

[0065] The sampling timing of each clock signal CK0, CK2, and CK4 can be set to be located at the center of each data bit D0, D1, and D2. The sampling timing of each clock signal CK1, CK3, and CK5 can be set to be located at the edge between data bits D0 and D1, the edge between D1 and D2, and the edge between D2 and D3, respectively.

[0066] The bang-bang phase detector (120) can sample and output data bits D0, D1, and D2 in the first cycle, respectively, by clock signals CK0, CK2, and CK4 having a 1UI interval, can sample and output data bits D3, D4, and D5 in the second cycle, respectively, and can sample and output data bits D6, D7, and D8 in the third cycle, respectively.

[0067] In this way, when the sampling timing of the clock signal CK1 is aligned with the falling edge of the clock training pattern (CT), the bang-bang phase detector (120) can output data (D<8:0>) in which the data bits D0~D8 are aligned in order in a symbol unit.

[0068] To this end, the bang-bang phase detector (120) can detect the falling edge of the clock training pattern (CT) in the clock training interval and perform a data alignment function that aligns the rising edge, which is the sampling timing of the clock signal CK1, to the falling edge of the clock training pattern (CT).

[0069] The bang-bang phase detector (120) may be equipped with a first edge detection unit (162) and a second edge detection unit (172) for detecting the falling edge of the clock training pattern (CT). Each of the first and second edge detection units (162, 172) can detect the edge of the clock training pattern (CT) by determining whether the data S1 (second sampling data) and S4 (fifth sampling data), respectively sampled by clock signals CK1 (second clock signal) and CK4 (fifth clock signal), are identical, and can output the first and second edge information signals (UP_PRE, DN_PRE), respectively.

[0070] The first edge detection unit (162) can detect the falling edge of the clock training pattern (CT) when the clock speed is slow and output the first edge information signal (UP_PRE). The second edge detection unit (172) can detect the falling edge of the clock training pattern (CT) when the clock speed is fast and output the second edge information signal (DN_PRE).

[0071] Referring to FIG. 6, when the speed of the 6-phase clock signals (CK0~CK5) is faster than the clock training pattern (CT), the second edge detection unit (172) outputs a second edge information signal (DN_PRE).

[0072] When the speed of the 6-phase clock signals (CK0~CK5) is faster than the clock training pattern (CT), the second edge detection unit (172) can detect the edge of the clock training pattern (CT) when data S1 sampled by the clock signal CK1 is at a high level and data S4 sampled by the clock signal CK4 is at a low level, that is, when the inverted data of S4 is the same as the high-level S1, and can output a high-level second edge information signal (DN_PRE). The bang-bang phase detector (120) can output a down signal (DN) to slow down the clock speed based on the second edge information signal (DN_PRE). For example, the bang-bang phase detector (120) can output a 1UI pulse as a down signal (DN) having an overlapping interval of data S1 (second sampling data) sampled by the clock signal CK1 (second clock signal) and inverted data (fifth inverted sampling data) of data S4 sampled by the clock signal CK4 (fifth clock signal).

[0073] The second edge detection unit (172) can detect the falling edge of the clock training pattern (CT) and output a second edge information signal (DN_PRE) when the phase of the clock signal CK4 is faster than the falling edge of the clock training pattern (CT) within a range of 0.0 UI to 1.5 UI. Accordingly, the bang-bang phase detector (120) can perform a data alignment function to align the rising edge of the clock signal CK1 to the falling edge of the clock training pattern (CT) as shown in FIG. 5 by outputting a down signal (DN) within a range of 0.0 UI to 1.5 UI to slow down the clock speed.

[0074] Referring to FIG. 7, when the speed of the 6-phase clock signals (CK0~CK5) is slower than the clock training pattern (CT), the first edge detection unit (162) outputs the first edge information signal (UP_PRE).

[0075] When the speed of the 6-phase clock signals (CK0~CK5) is slower than that of the clock training pattern (CT), the first edge detection unit (162) can detect an edge of the clock training pattern (CT) when data S4 sampled by the clock signal CK4 is at a high level and data S1 sampled by the clock signal CK1 is at a low level, that is, when the inverted data of S1 is the same as the high-level S4, and can output a high-level first edge information signal (UP_PRE). The bang-bang phase detector (120) can output an up signal (UP) to quickly adjust the clock speed based on the first edge information signal (UP_PRE). For example, the bang-bang phase detector (120) can output a 1UI pulse as an up signal (UP) having an overlapping interval of data S4 (5th sampling data) sampled by the clock signal CK4 (5th clock signal) and inverted data (2nd inverted sampling data) of data S1 sampled by the clock signal CK1 (2nd clock signal).

[0076] The first edge detection unit (162) can detect the falling edge of the clock training pattern (CT) and output the first edge information signal (UP_PRE) when the phase of the clock signal CK1 is slower than the falling edge of the clock training pattern (CT) within a range of 0.0 UI to 1.5 UI. Accordingly, the bang-bang phase detector (120) can perform a data alignment function to align the rising edge of the clock signal CK1 with the falling edge of the clock training pattern (CT) as shown in FIG. 5 by outputting an up signal (UP) within a range of 0.0 UI to 1.5 UI to quickly adjust the clock speed.

[0077] FIG. 8 is a circuit diagram illustrating the configuration of a bang-bang phase detector according to one embodiment of the present specification.

[0078] Referring to FIG. 8, a bang-bang phase detector (120) according to one embodiment may include a phase comparison unit (130), a pulse generation unit (140), a first output unit (150), a first edge detection unit (160), a second edge detection unit (170), and a second output unit (180).

[0079] A bang-bang phase detector (120) according to one embodiment may receive a receiving signal (RXO) from an equalizer (EQ) shown in FIG. 2 and may receive an N-phase clock signal, for example, 6-phase clock signals CK0, CK1, CK2, CK3, CK4, CK5 from a voltage-controlled oscillator (VCO), but is not limited thereto.

[0080] The phase comparison unit (130) may include a sampling unit (132), a buffer unit (134), and a phase difference detection unit (136).

[0081] The sampling unit (132) may include first to sixth samplers (21 to 26) configured to sample the received signal (RXO) by each of the six-phase clock signals CK0 to CK5 and output sampling data S0 to S5 respectively. For example, each of the first to sixth samplers (21 to 26) may be a data flip-flop.

[0082] Each of the first to sixth samplers (21 to 26) can sample and latch the received signal (RXO) input to the data terminal at the rising edge of each of the six-phase clock signals CK0 to CK5 input to the clock terminal, and output the sampled data S0 to S5 through the output terminal.

[0083] The phase difference detection unit (136) may include first to sixth phase difference detectors (61 to 66) configured to output detection signals X0 to X5, respectively, indicating whether there is a phase difference by comparing sampling data S0 to S5 with each other. For example, each of the first to sixth phase difference detectors (61 to 66) may be an Exclusive OR (hereinafter XOR) gate.

[0084] Each of the first to fifth phase difference detectors (61 to 65) can output a detection signal X(n-1) indicating whether there is a phase difference by comparing the n-th sampling data S(n-1, n=1 to 5) with the n+1-th second sampling data Sn. The sixth phase difference detector (66) can output a detection signal X5 indicating whether there is a phase difference by comparing sampling data S5 and S0. Each phase difference detector (6n, n=1 to 6) can output a low-level detection signal X(n-1) indicating that there is no phase difference if the two sampling data being compared are the same, and a high-level detection signal X(n-1) indicating that there is a phase difference if the two sampling data are different.

[0085] The buffer section (134) may include first to sixth buffers (41 to 46) configured to buffer and output sampling data S0 to S5, respectively. Each of the first to sixth buffers (41 to 46) may include two inverter gates (31, 32). The first inverter gate (31) of each of the first to sixth buffers (41 to 46) may invert the sampling data S0 to S5, respectively, and output inverted sampling data SB0 to SB5, respectively.

[0086] The first buffer (51) buffers data S0 sampled by the clock signal CK0 and the first data bit (DATA <0> ) can be output. The third buffer (53) buffers data S2 sampled by the clock signal CK2 and the second data bit DATA <1> It can output. The fifth buffer (55) buffers data S4 sampled by the clock signal CK4 and the third data bit DATA <3> It can output.

[0087] The pulse generation unit (140) may include first to sixth 1UI extractors (141 to 146) configured to generate a 1UI pulse by logic processing each of detection signals X0 to X5 from the phase comparison unit (130) with two clock signals having adjacent phases. For example, each of the first to sixth 1UI extractors (141 to 146) may be an AND gate.

[0088] Each of the first to sixth 1UI extractors (141 to 146) can generate a 1UI pulse in which the high levels of the first to third inputs overlap by performing a logical AND operation on a first input of any one of detection signals X0 to X5 from the phase comparison unit (10) and a second and third input, which are two clocks having a phase difference of 0.5UI interval among the six-phase clock signals CK0 to CK5, and output a down signal (DN1 to DN3) or an up signal (UP1 to UP3). Each of the first to sixth 1UI extractors (141 to 146) can extract and output a 1UI pulse from at least one high-level detection signal in which a phase difference is detected among the detection signals X0 to X5.

[0089] The second and third inputs supplied to each of the first to sixth 1UI extractors (141 to 146) may be two clocks having a phase difference of 0.5UI sequentially with one clock CK (n-1) used in the phase comparison unit (10) for the first input, the phase difference detection signal X (n-1).

[0090] For example, the first UI extractor (141) can output a first up signal (UP1) by performing a logical AND operation on the detection signal X0, clock signals CK1, and CK2. The second UI extractor (142) can output a first down signal (DN1) by performing an AND operation on the detection signal X1, clock signals CK2, and CK3. The third UI extractor (143) can output a second up signal (UP2) by performing a logical AND operation on the detection signal X2, clock signals CK3, and CK4. The fourth UI extractor (144) can output a second down signal (DN2) by performing a logical AND operation on the detection signal X3, clock signals CK4, and CK5. The fifth UI extractor (145) can output a third up signal (UP3) by performing a logical AND operation on the detection signal X4, clock signals CK5, and CK0. The 6th UI extractor (146) can output a 3rd down signal (DN3) by performing a logical AND operation on the detection signal X5, clock signals CK0 and CK1.

[0091] The first output unit (150) may include first and second OR gates (151, 152). The first and second OR gates (151, 152) may be enabled by a lock signal (LOCK) indicating a locking state.

[0092] The first OR gate (151) can output a first up output signal (UP_PD) by performing a logical OR operation on up signals (UP1~UP3) output from the pulse generator (140). The first OR gate (151) can output a high-level first up output signal (UP_PD) when at least one of the up signals (UP1~UP3) is a high pulse.

[0093] The second OR gate (152) can output a first down output signal (DN_PD) by performing a logical OR operation on down signals (DN1~DN3) output from the pulse generator (140). The second OR gate (152) can output a high-level first down output signal (DN_PD) when at least one of the down signals (DN1~DN3) is a high pulse.

[0094] The first edge detection unit (160) may include a first edge detection unit (162) and a first pulse generation unit (164). For example, each of the first edge detection unit (162) and the first pulse generation unit (164) may be an AND gate.

[0095] The first edge detection unit (162) can output a first edge information signal (UP_PRE) by performing a logical AND operation on the inverted sampling data SB1 (second inverted sampling data) of the sampling data S1 (second sampling data) by the clock signal CK1 (second clock signal) in the phase comparison unit (130) and the sampling data S4 (fifth sampling data) by the clock signal CK4 (fifth clock signal).

[0096] The first pulse generation unit (164) can generate a first edge detection signal (UP_ED) by performing a logical AND operation on the first edge information signal (UP_PRE), the clock signal CK1, and the clock signal CK3 (the fourth inverted clock signal) inverted through the inverter (163), thereby masking the first edge information signal (UP_PRE) with a pulse width of 1UI. The clock signal CK1 may be the sampling clock of the sampling data S1 input to the first edge detection unit (162). Since the clock signal CK3 (the fourth clock signal) has a phase difference of 1UI interval with the clock signal CK1, the inverted clock signal CK3 may have a high overlap period of 1UI with the clock signal CK1. Accordingly, the first pulse generation unit (164) can generate a first edge detection signal (UP_ED) having a pulse width of 1UI from the first edge information signal (UP_PRE).

[0097] The second edge detection unit (170) may include a second edge detection unit (172) and a second pulse generation unit (174).

[0098] The second edge detection unit (172) can output a second edge information signal (DN_PRE) by performing a logical AND operation on the sampling data S1 by the clock signal CK1 in the phase comparison unit (130) and the inverted sampling data SB4 (the fifth inverted sampling data) of the sampling data S4 by the clock signal CK4.

[0099] The second pulse generator (174) can generate a second edge detection signal (DN_ED) by performing a logical AND operation on the second edge information signal (DN_PRE), the clock signal CK4, and the clock signal CK0 (first inverted clock signal) inverted through the inverter (173), thereby masking the second edge information signal (DN_PRE) with a pulse width of 1UI. The clock signal CK4 may be the sampling clock of the inverted sampling data SB4 input to the second edge detection unit (172). Since the clock signal CK0 (first clock signal) has a phase difference of 1UI interval with the clock signal CK4 (fifth clock signal), the inverted clock signal CK0 may have a high overlap period of 1UI with the clock signal CK4. Accordingly, the second pulse generator (174) can generate a second edge detection signal (DN_ED) having a pulse width of 1UI from the second edge information signal (DN_PRE).

[0100] The first and second pulse generators (172, 174) can be enabled during the clock training period of each horizontal blank period by the edge detection enable signal (ED_DN). Additionally, the first and second pulse generators (172, 174) can also be enabled during the clock training period of each vertical blank period by the edge detection enable signal (ED_DN).

[0101] The second output unit (180) may include third and fourth OR gates (181, 182).

[0102] The third OR gate (181) can output a second up output signal (UP) by performing a logical OR operation on the first up output signal (UP_PD) output from the first OR gate (151) of the first output unit (150) and the first edge detection signal (UP_ED) output from the first edge detection unit (160). The third OR gate (181) can output a second up output signal (UP) at a high level when at least one of the first up output signal (UP_PD) and the first edge detection signal (UP_ED) is a high pulse.

[0103] The fourth OR gate (182) can output a second down output signal (DN) by performing a logical OR operation on the first down output signal (DN_PD) output from the second OR gate (152) of the first output unit (150) and the second edge detection signal (DN_ED) output from the second edge detection unit (170). The fourth OR gate (182) can output a high-level second down output signal (DN) when either the first down output signal (DN_PD) or the second edge detection signal (DN_ED) is a high pulse.

[0104] FIG. 9 is a timing diagram for explaining the edge detection operation of the first edge detection unit illustrated in FIG. 8.

[0105] Referring to FIG. 9, when the speed of the clock signal (CK0~CK5) is slower than the clock training pattern (CT), the first edge detection unit (160) outputs the first edge detection signal (UP_ED).

[0106] When the speed of the clock signal (CK0~CK5) is slower than the clock training pattern (CT), the first edge detection unit (162) can output a first edge information signal (UP_PRE) of high level in the same overlapping interval where the data S4 sampled by CK4 is at a high level (1) and the inverted sampled data SB1 of the data S1 sampled by CK1 is at a high level (1).

[0107] The first pulse generation unit (164) can generate a first edge detection signal (UP_ED) having a pulse width of 1UI, in which a high-level first edge information signal (UP_PRE), a high level of a clock signal CK1, and a high level of an inverted clock signal CK3 overlap.

[0108] FIG. 10 is a timing diagram for explaining the edge detection operation of the second edge detection unit illustrated in FIG. 8.

[0109] Referring to FIG. 9, when the speed of the clock signal (CK0~CK5) is faster than the clock training pattern (CT), the second edge detection unit (170) outputs a second edge detection signal (DN_ED).

[0110] When the speed of the clock signal (CK0~CK5) is faster than the clock training pattern (CT), the second edge detection unit (172) can output a second edge information signal (DN_PRE) at a high level in the same overlapping interval where the data S1 sampled by CK1 is at a high level (1) and the inverted sampled data SB4 of the data S4 sampled by CK4 is at a high level (1).

[0111] The second pulse generation unit (174) can generate a second edge detection signal (DN_ED) having a pulse width of 1UI, in which a high-level second edge information signal (DN_PRE), a high level of a clock signal CK4, and a high level of an inverted clock signal CK0 overlap.

[0112] FIG. 11 is a timing diagram illustrating data output from a clock data recovery circuit according to a comparative example of the present specification, and FIG. 12 is a timing diagram illustrating data output from a clock data recovery circuit according to an embodiment of the present specification.

[0113] Referring to FIG. 11, when the phase difference between the clock signal CK0 and the data D0 is aligned to be greater than 1UI, the clock data recovery circuit according to the comparative example samples D8, D0, and D1 in the first cycle of the clock signals CK0, CK2, and CK4 from the received signal (RXO) and outputs data DATA <0> , DATA <1> , DATA <2> It can be output as such, and D2, D3, and D4 can be sampled and output in the second cycle, and D5, D6, and D7 can be sampled and output in the third cycle. Accordingly, since the clock data recovery circuit according to the comparative example outputs data bits in a changed order as D8~D7, it can be seen that a separate data alignment logic circuit is required.

[0114] Referring to FIG. 12, a clock data recovery circuit according to one embodiment of the present specification performs a data alignment operation based on the edges of a clock training pattern (CT) during a clock training interval as previously described, thereby aligning and maintaining the sampling timing of clock signals CK0, CK2, and CK4 to the center of each of D0, D1, and D3 of the received signal (RXO). Accordingly, the clock data recovery circuit according to one embodiment samples D0, D1, and D2 from the received signal (RXO) in the first cycle of the clock signals CK0, CK2, and CK4 to produce output data DATA <0> , DATA <1> , DATA <2> It can be output as such, and D3, D4, and D5 can be sampled and output in the second cycle, and D6, D7, and D8 can be sampled and output in the third cycle. Therefore, since the clock data recovery circuit according to one embodiment outputs data in which the data bits D0~D8 are aligned in order at the symbol level, it can be seen that the data alignment logic circuit according to the comparative example is unnecessary.

[0115] As described above, a clock data recovery circuit according to one embodiment of the present specification can perform a data alignment operation in a bang-bang phase detector even if the phase difference between the data and the clock is greater than 1 UI, thereby aligning and maintaining the phase of a specific clock based on the edge of the clock training pattern. Accordingly, the clock data recovery circuit according to one embodiment can output data in which the order of data bits is aligned at the symbol level by fixing the order of data sampled by the multi-phase clock.

[0116] In a data driving circuit according to one embodiment of the present specification, the clock data recovery circuit has an automatic data alignment function, so the data alignment logic circuit according to the comparative example is unnecessary, thereby simplifying the circuit configuration, reducing the circuit size, and reducing power consumption.

[0117] A data driving circuit according to one embodiment of the present specification may be applied to various display devices, including a liquid crystal display device and an electroluminescence display device. An electroluminescence display device may be any one of an organic light-emitting diode (OLED) display device, a quantum-dot light-emitting diode (QD) display device, an inorganic light-emitting diode (ILED) display device, or a micro light-emitting diode (MLED) display device.

[0118] Features, structures, effects, etc. described in the various examples of this specification described above are included in at least one example of this specification and are not necessarily limited to only one example. Furthermore, features, structures, effects, etc. exemplified in at least one example of this specification may be combined or modified and implemented in other examples by a person with ordinary knowledge in the field to which the technical concept of this specification belongs. Accordingly, contents related to such combinations and modifications should be interpreted as being included within the technical scope or scope of rights of this specification.

[0119] It will be obvious to those skilled in the art that the specification described above is not limited to the aforementioned embodiments and attached drawings, and that various substitutions, modifications, and changes are possible within the scope of the technical concept of the specification. Therefore, the scope of the specification is defined by the claims set forth below, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the specification. Explanation of the symbols

[0120] 1: Data driving circuit 10: Serial-to-parallel converter 30: Shift register 40: Latch 50: Digital-to-analog converter 60: Multi-channel output circuit 100: Receiver 110: Control logic section EQ: Equalizer CDR: Clock Data Recovery Circuit 120: Bang-bang phase detector CP: Charge pump unit LF: Loop filter VCO: Voltage-controlled oscillator S2P: Series-to-Parallel Conversion Circuit 112: Decoder 114: Pixel alignment logic circuit 130: Phase Comparator 132: Sampling section 134: Buffer section 136: Phase difference detection unit 140: Pulse generator 150: First output section 160: First edge detection unit 162: First edge detection unit 164: First pulse generator 170: Second edge detection unit 172: Second edge detection unit 174: Second pulse generator

Claims

Claim 1 A clock data recovery circuit comprising: a bang-bang phase detector that detects a phase difference between a received signal and a multi-phase clock signal and outputs an output signal corresponding to the phase difference; a charge pump unit that charges and discharges a loop filter based on the output signal of the bang-bang phase detector to output a control voltage; and a voltage-controlled oscillator that generates and outputs the multi-phase clock signal having multiple phases and an oscillation frequency adjusted according to the control voltage, wherein the bang-bang phase detector has an alignment function that detects an edge of a clock training pattern in a clock training interval and outputs an edge detection signal to the charge pump unit to align the sampling timing order of the multi-phase clock signal based on the edge of the clock training pattern, and in a data interval, samples the received signal by each of a plurality of clock signals among the aligned multi-phase clock signals to output output data having a predetermined order. Claim 2 A clock data recovery circuit according to claim 1, wherein the bang-bang phase detector includes a phase comparison unit, and the phase comparison unit includes: a sampling unit that samples and latches the received signal by each of the multi-phase clock signals and outputs a plurality of sampling data; a phase difference detection unit that compares the plurality of sampling data with each other and outputs a plurality of detection signals indicating whether there is a phase difference; and a buffer unit that buffers each of the plurality of sampling data and outputs the recovered data. Claim 3 A clock data recovery circuit according to claim 2, wherein the bang-bang phase detector further comprises a pulse generator and a first output unit, the pulse generator outputs a plurality of up signals and a plurality of down signals having 1UI based on the plurality of detection signals output from the phase comparison unit, and the first output unit outputs a first up output signal by performing a logical OR operation on the plurality of up signals and outputs a first down output signal by performing a logical OR operation on the plurality of down signals. Claim 4 In claim 3, the bang-bang phase detector is a clock data recovery circuit that detects an edge detection signal using data sampled by a first specific clock signal for aligning with the edge of the clock training pattern among the multi-phase clock signals, and data sampled by a second specific clock signal having a phase difference of 1.5 UI with respect to the first specific clock signal. Claim 5 In claim 1, the multi-phase clock signal includes first to sixth clock signals that are sequentially delayed with a phase difference of 0.5 UI, and the bang-bang phase detector is a clock data recovery circuit that aligns the falling edge of the clock training pattern with the sampling timing of the second clock signal. Claim 6 In claim 5, the bang-bang phase detector further comprises first and second edge detection units, and the first edge detection unit is a clock data recovery circuit that outputs a first edge detection signal having a pulse width of 1UI in the overlap interval of the second inverted sampling data of the second sampling data sampled by the second clock signal and the fifth sampling data sampled by the fifth clock signal. Claim 7 A clock data recovery circuit according to claim 6, wherein the first edge detection unit comprises: a first edge detection unit that outputs a first edge information signal by performing a logical AND operation on the second inverted sampling data and the fifth sampling data; and a first pulse generation unit that outputs the first edge detection signal by performing a logical AND operation on the first edge information signal, the second clock signal, and a fourth inverted clock signal of the fourth clock signal having a phase difference of 1UI with the second clock signal. Claim 8 In claim 6, the first edge detection unit is a clock data recovery circuit that increases the speed of the multi-phase clock signal by outputting the first edge detection signal when the sampling timing of the second clock signal is slower than the falling edge of the clock training pattern within the range of 0.0 UI to 1.5 UI. Claim 9 In claim 6, the second edge detection unit is a clock data recovery circuit that outputs a second edge detection signal having a 1UI pulse width in the overlap interval of the second sampling data and the fifth inverted sampling data of the fifth sampling data. Claim 10 A clock data recovery circuit according to claim 9, wherein the second edge detection unit comprises: a second edge detection unit that outputs a second edge information signal by performing a logical AND operation on the second sampling data and the fifth inverted sampling data; and a second pulse generation unit that outputs the second edge detection signal by performing a logical AND operation on the second edge information signal, the fifth clock signal, and a first inverted clock signal of the first clock signal having a phase difference of 1UI with the fifth clock signal. Claim 11 In claim 10, the second edge detection unit is a clock data recovery circuit that outputs the second edge detection signal to reduce the speed of the multi-phase clock signal when the sampling timing of the second clock signal is faster than the falling edge of the clock training pattern within the range of 0.0 UI to 1.5 UI. Claim 12 A clock data recovery circuit according to claim 9, wherein the bang-bang phase detector further comprises a second output unit, and the second output unit outputs a second up output signal by performing a logical OR operation on the first edge detection signal from the first edge detection unit and the first up output signal from the first output unit, and outputs a second down output signal by performing a logical OR operation on the second edge detection signal from the second edge detection unit and the first down output signal from the first output unit. Claim 13 In claim 9, the first and second edge detection units are clock data recovery circuits enabled by an edge detection enable signal in the clock training interval of each horizontal blank period. Claim 14 A data driving circuit comprising: a serial-to-parallel converter including a clock data recovery circuit of any one of claims 1 to 13; and a data driving unit that converts image data output from the serial-to-parallel converter into a data voltage and outputs it. Claim 15 In claim 14, the serial-to-parallel converter comprises: a serial-to-parallel converter circuit that converts the output of the clock data recovery circuit into a parallel form; a decoder that decodes the output of the serial-to-parallel converter circuit; and a pixel alignment logic circuit that aligns the output of the decoder in pixel units, for a data driving circuit.

Images