Multi-die bridge assemblies and methods for three-dimensional packaging

Abstract

Multi-die bridge assembly and method for three-dimensional packaging. This architecture creates a multi-die (MD) bridge assembly by assembling two or more integrated circuit dies and a bridge component. Means for attaching the bridge component to the die may be hybrid bonding, solder bumps, thermal compression bonding, or a combination thereof. The created MD bridge assembly may undergo performance testing before being attached to a substrate. Attaching the MD bridge assembly to a substrate may include fitting a portion of the bridge component to a cavity within the substrate and attaching the bridge component to the bottom of the cavity using a plurality of other attachment options.

Description

Background Technology

[0001] Efforts to improve bump density, power efficiency, speed, and bandwidth in semiconductor packaging are ongoing. However, available methodologies and architectures supporting 3D packaging cause technical difficulties and higher costs in manufacturing. Therefore, improved architectures and methods for three-dimensional (3D) semiconductor packaging are desired. Brief explanation of the drawing

[0002] FIG. 1 is a simplified cross-sectional example of a multi-die bridge assembly including a bridge component and two integrated circuit dies according to various embodiments. FIG. 2a depicts FIG. 1, in which a bridge component is hybridly bonded to two integrated circuit dies according to various embodiments. FIG. 2b depicts FIG. 1, in which a bridge component is solder-bonded to two integrated circuit dies according to various embodiments. FIG. 3a depicts FIG. 1 in which different bridge components are hybridly bonded to two integrated circuit dies according to various embodiments. FIG. 3b depicts FIG. 1, in which different bridge components are solder-bonded to two integrated circuit dies according to various embodiments. FIG. 4a illustrates mold encapsulation on the lower surface / rear surface of an integrated circuit component in a hybrid bonded bridge embodiment according to various embodiments. FIG. 4b illustrates mold encapsulation on the lower surface / rear side of an integrated circuit component in a solder-bonded bridge embodiment according to various embodiments. FIG. 5a illustrates a multi-die bridge assembly with ball pitch solder pads according to various embodiments. FIG. 5b illustrates a multi-die bridge assembly configured for hybrid bonding in a cavity, having ball-pitch solder pads for two integrated circuit dies according to various embodiments. FIG. 6a illustrates a multi-die bridge assembly including a glass frame according to various embodiments. FIG. 6b illustrates an inverted multi-die bridge assembly according to various embodiments, in which a bridge component is on top and the lower surface or back surface of two integrated circuit dies is prepared for solder attachment. FIG. 7 illustrates a substrate having a cavity for bonding to a multi-die bridge assembly according to various embodiments. FIG. 8 illustrates the substrate of FIG. 7, in which an embodiment of a multi-die bridge assembly according to various embodiments is soldered in the cavity. FIG. 9 illustrates the substrate of FIG. 7 in which an embodiment of a multi-die bridge assembly according to various embodiments is hybridly bonded in a cavity. FIG. 10 illustrates a cavity-free substrate in which a multi-die bridge assembly is inverted and solder-bonded on an upper surface according to various embodiments. FIG. 11 illustrates an exemplary method for a multi-die bridge assembly according to various embodiments. FIG. 12 is a plan view of wafers and dies that may be included in a microelectronic assembly according to any of the embodiments disclosed in this specification. FIG. 13 is a simplified cross-sectional view showing an implementation of an integrated circuit on a die that may be included in various embodiments according to any of the embodiments disclosed in this specification. FIG. 14 is a side cross-sectional view of a microelectronic assembly that may include any of the embodiments disclosed in this specification. FIG. 15 is a block diagram of an exemplary electrical device that may include any of the embodiments disclosed in this specification. Specific details for implementing the invention

[0003] There is growing interest in three-dimensional (3D) semiconductor packaging architectures and methodologies to provide significant improvements in bump density, power efficiency, speed, and bandwidth. Many proposed solutions rely on die-to-die (D2D) and / or die-to-wafer (D2W) bonding methods and architectures. However, many available D2D and D2W methods and architectures face manufacturing difficulties and high costs.

[0004] For example, in D2D or D2W assemblies, multiple disparate dies, various pitch dimensions, and bonding types (e.g., solder and hybrid bonding) may need to be integrated. One technical challenge of D2D and D2W bonding is the complexity and high cost of the required copper-to-copper bonding technology.

[0005] Another technical challenge is the implementation and performance of bridge components. Bridge components are used to operably combine heterogeneous integrated circuit dies and often incorporate multiple pitch and bonding applications. Passive bridge components provide only an electrical path or signal route between dies on a single surface. While passive bridge components are easier to manufacture and less expensive, they cannot achieve the maximum current (Imax) required by many applications. Active bridge components often include through silicon vias (TSVs) that route power and ground between surfaces to improve Imax; however, technical challenges such as drilling, alignment, cavity filling, and soldering remain. Therefore, continuous improvements in methods and architectures for 3D semiconductor packaging are desired.

[0006] The embodiments described herein provide technical solutions to these technical challenges in the form of multi-die bridge assemblies and methods for 3D packaging. Some of the embodiments utilize hybrid bonding (HB), also referred to as hybrid bonding interconnects (HBI) or direct bond interconnects (DBI). HBI is a packaging technology that generally involves bringing together the surfaces of two semiconductor devices under applied pressure and / or at high temperatures, resulting in dielectric-to-dielectric bonding and metal-to-metal bonding, as a die stacking solution. HBI advantageously enables "small" pitches (defined herein as less than 10 micrometers plus / - 10%, and in some cases, less than 1 micrometer plus / - 10%). However, for various reasons, many substrates remain solder-attached components having solder-based interconnects for electrical communication with IC dies. Accordingly, some of the embodiments of the multi-die bridge components described below integrate hybrid bonding interconnect (HBI) components and solder attachment components. This concept is elaborated in more detail below.

[0007] Exemplary embodiments are described below in connection with the drawings below, where similar numbers in the drawings indicate similar elements. Unless otherwise noted, the drawings are not necessarily drawn to scale but may be referenced for the spatial orientation and relative positioning of features. As can be understood, specific terms such as "ceiling" and "floor," as well as specific terms such as "upper," "uppermost," "lower," "above," "below," "bottom," and "top," refer to directions relative to the viewing of the referenced drawings. Additionally, terms such as "front," "back," "rear," "side," "vertical," and "horizontal" may describe the orientation and / or position of parts of a component within a consistent but arbitrary reference frame, which becomes clear by referring to the text describing the component under discussion and the associated drawings. These terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0008] As used herein, the term “adjacent” refers to layers or components that are in direct physical contact with each other without a layer or component between them. For example, layer X adjacent to layer Y refers to a layer that is in direct physical contact with layer Y. In contrast, as used herein, the phrase(s) “located on” (or, alternatively, in the context of a first layer or component located on a second layer or component, “located below,” “located on / above,” or “located next to”) include (i) a configuration in which the first layer or component is physically attached directly to (i.e., adjacent to) the second layer or component, and (ii) a configuration in which the first layer or component is attached (e.g., coupled) to the second layer or component through one or more interposed layers or components.

[0009] The following detailed description is not intended to limit the application and use of the disclosed technology. It may be apparent that new embodiments can be practiced without all the details described herein. For brevity, well-known structures and devices may be illustrated in block diagram form to facilitate their description.

[0010] FIGS. 1 through 6b provide various non-limiting examples of embodiments of a multi-die bridge assembly for 3D packaging. Many of the objects in the images are repeated, and similar objects are intended to perform the same function or have the same feature across the images, regardless of whether they are labeled or not.

[0011] FIG. 1 is a simplified cross-sectional example of a multi-die bridge assembly (100) comprising a bridge component (102) and two integrated circuit dies (die (106) (IC 1) and die (110) (IC 2)). The dies (106 and 110) may be unpackaged integrated circuit dies and may alternatively be referred to as a chip, chiplet, chip complex, or chiplet complex. While the terms die, chip, and chiplet may be used interchangeably, the term chiplet is sometimes used to refer to an integrated circuit die that implements a subset of the functions of a larger integrated circuit component. Although the example depicts chiplets as having uniform dimensions, in reality, chiplet dimensions (as well as thickness) and shapes may vary between chiplets; Furthermore, the chiplets may vary depending on their type / function (e.g., compute, memory, I / O, power management (controlling power delivery and / or providing power to components). Additionally, the multi-die bridge assembly (100) may have any shape, such as substantially square, substantially rectangular, or substantially circular.

[0012] Die (106) and Die (110) are stabilized within an encapsulant. The encapsulant may include a molding compound, a dielectric material, a metal, a ceramic, a plastic, or a combination thereof. To simplify the discussion of features, the encapsulant was omitted from the examples in FIG. 2, FIG. 3, and FIG. 4, but in reality, the corresponding embodiment would have an encapsulant.

[0013] The multi-die bridge assembly (100) has a bottom surface (105 / 205 / 305 / 405) (in the drawing) and a top surface (107). The dies (106 / 206 / 306 / 406 / 506 / 606) have input / output contact regions (120-1) (I / O (120-1)) (also I / O (220-1 / 320-1 / 420-1 / 520-1 / 620-1)) that interface with a substrate, arranged with a bump pitch larger than the hybrid bond interconnect (HBI) bump pitch. In a non-limiting example, the bump pitch (BP) may be 110 to 86 micrometers for the first IC and 110 to 95 micrometers for the second IC. In another example, the solder bump is greater than or equal to 25 micrometers and the HBI bump pitch is less than 25 micrometers. In some embodiments, the HBI bump may be 10 micrometers, and in other embodiments, the HBI bump may be 2 micrometers. The die (110 / 210 / 310 / 410 / 510 / 610) similarly has an input / output contact area (120-2) (I / O(120-2)) (also I / O(220-2 / 320-2 / 420-2 / 520-2 / 620-2)) that interfaces with a substrate, arranged generally at the bump pitch. In some embodiments, I / O(120-1) and I / O(120-2) include solder bumps attached thereto.

[0014] The bridge component (102 / 202 / 302 / 402 / 502 / 602) is intended to provide one or more electrical paths between the die (106) and the die (110), as indicated by the curved cartoon arrow. The bridge component (102 / 202 / 302 / 402 / 502 / 602) may be embodied as a conventional silicon bridge, an organic bridge, a glass bridge, or a combination thereof. As used herein, the passive bridge component is limited to the electrical path between the die (106) and the die (110), whereas the active bridge component may further include transistors, logic, and / or memory in addition to the electrical path. Electrical communication between the die (106) and the die (110) is facilitated by the attachment means (125) through these electrical paths in the bridge component (102 / 202 / 302 / 402 / 502 / 602). As described in more detail below, the attachment means may be a solder bump using solder material, hybrid bonding (HB), first-level interconnect thermal compression bonding (TCB) microball, or plating.

[0015] A die (106) has an I / O structure (108) for communicating with a die (110) via a bridge component (102) on a first portion of its upper surface, and a die (110) has a similar I / O structure (112) for communicating with a die (106) via a bridge component (102) on a first portion of its upper surface. A collective I / O structure for supporting die-to-die (or wafer-to-wafer) communication is referred to herein as an attachment means (125). The attachment means on the upper surface of the bridge component (102) is separated into a first portion for attaching to the first die (106) and a second portion for the second die (110). As can be understood, when the attachment means is a solder bump, the upper surface of the I / O structure (108 and 112) and the bridge component (102) is configured for the solder bump, and when the attachment means is a hybrid bonding (HB), the upper surface of the I / O structure and the bridge component (102) is configured for the HB, etc. In the case of the bridge component, when the attachment means (125) is a solder bump or a microbump field (225-2 / 325-2 / 425-2), the solder bump pitch (BP) may be in the range of 45 micrometers ± 10% to 55 micrometers ± 10%. In another embodiment, the solder bump pitch may be in the range of 25 to 35 micrometers. When the attachment means (125) is an HBI, the HBI pitch on the bridge component (102) is much smaller, in the range of 1 to 10 micrometers.

[0016] An optional cartoon arrow (123) indicates an electrical path between the first surface (103) of the bridge component (102) and the second surface (105) of the bridge component (102). The optional cartoon arrow (123) generally indicates a through-silicon via (TSV) or through-glass via (TGV) with an internal conductive material for power and ground routing. In various embodiments, but not always, when the optional cartoon arrow (123) is omitted, the bridge component (102) is a "passive bridge component." Likewise, in various embodiments, but not always, when the bridge component (102) includes the optional cartoon arrow (123), the bridge component (102) is an "active bridge component." In practice, the optional cartoon arrow (123) is often used to allow power to be routed into the bridge component (102) from a source located at the bottom of a cavity in the substrate. The electrical path or routing indicated by the optional cartoon arrow (123) can reduce the number of substrate routing layers and improve product yield.

[0017] The multi-die bridge assembly (200) of FIG. 2a shows that the bridge component (202) is hybrid-bonded to two integrated circuit dies, and the multi-die bridge assembly (230) of FIG. 2b shows that the bridge component (202) is solder-bonded to two integrated circuit dies. The bottom surfaces of die IC 1 and IC 2 (corresponding to the top surface (107) of FIG. 1) face the top of the page because they were flipped during manufacturing. Die (106 / 206 / 306 / 406) has a top surface (209 / 309 / 409) and a bottom surface (211 / 311 / 411); die (110 / 210 / 310 / 410) has a top surface (213 / 313 / 413 / 513) and a bottom surface (215 / 315 / 415 / 515).

[0018] With emphasis on FIG. 2a, when the attachment means (125) is implemented as a hybrid bonding interface (HBI) (225-1), the die (106) and the die (110) each include an HB surface. As mentioned, the dies (206 / 306 / 406 / 506 / 606 and 208 / 308 / 408 / 508 / 608) are inverted, and thus the HB surface appears as the lower surface of the die in a multi-die bridge assembly.

[0019] The HB surface of the die (206 / 306 / 406) is defined by a hybrid bond contact (208 / 308 / 408) surrounded by an insulating material (often, a dielectric material). The HB surface of the die (210 / 310 / 410) is defined by a hybrid bond contact (212 / 312 / 412) surrounded by an insulating material (this does not necessarily have to be the same dielectric material used in the die (206 / 306 / 406)). Likewise, the bridge component (202 / 302 / 402) includes an insulating material and is defined by a first surface (203) and a second surface (205).

[0020] The insulating material in the bridge component, IC 1 and / or IC 2, may be any dielectric material, such as a suitable nitride or oxide, e.g., silicon dioxide (SiO2), carbon-doped silicon dioxide (a material containing silicon, oxygen, and carbon, also known as C-doped SiO2, CDO, or organic silicate glass), fluorine-doped silicon dioxide (a material containing fluorine, silicon, and oxygen, also known as F-doped SiO2, fluorosilicate glass), or hydrogen-doped silicon dioxide (a material containing silicon, oxygen, and hydrogen, also known as H-doped SiO2). In some embodiments, the dielectric layer comprises a photo-imageable dielectric (PID). In some embodiments, the dielectric layer comprises an Ajinomoto Build-Up film (often referred to as ABF), which is a material comprising an organic resin matrix having different types of fillers (e.g., silica fillers of different sizes, or hollow fillers of different sizes) to control the coefficient of thermal expansion (CTE) and / or electrical properties (e.g., dielectric constant (Dk), and / or dissipation factor (insertion loss) (Df)).

[0021] In some embodiments, it is advantageous for the dielectric layer in the bridge component to have a CTE that matches the CTE of the integrated circuit die (IC 1 and IC 2) (e.g., the CTE of silicon) or to have a CTE that matches the CTE of the substrate or PCB. In some embodiments, the dielectric material may have a CTE that is close to the CTE of silicon (e.g., within 10%). In other embodiments, the dielectric material may be any type of epoxy molding compound.

[0022] Returning to the discussion of the HB interface (225-1), the first die (106 / 206 / 306) comprises an upper surface (209 / 309 / 409), on which there is an insulating material and a plurality of HB contacts, and the second die (210 / 310 / 410) comprises another insulating material having another plurality of HB contacts (212 / 312 / 412) inside. On the surface (209 / 309 / 409) and the surface (213 / 313 / 413), the HB contacts are exposed and the dielectric is exposed; that is, on the HB surface(s), the dielectric material is adjacent to the metal / Cu hybrid bonding contacts. The HB contacts (208 / 308 / 408) and the HB contacts (212 / 312 / 412) may be metal and may include copper. In various embodiments, at least one hybrid bonding contact (208 / 308 / 408) and at least one hybrid bonding contact (212 / 312 / 412) are exposed at the HB interface (225-1).

[0023] When the attachment means (125) is HB, as in the HB interface (225-1), the first surface (203) comprises a plurality of HB contacts (first metal contacts (204-1 / 304-1 / 404-1)) on the first surface (203), and the plurality of first metal contacts are composed of a first region (first metal contacts (204-1 / 304-1 / 404-1)) and a second region (second first metal contacts (204-2 / 304-2 / 404-2)). As indicated by the cartoon arrow in FIG. 1, the bridge component provides at least one electrical path (240 / 340 / 440 / 540 / 640) between the first first metal contact (204-1) in the first region and the second first metal contact (204-2) in the second region. The second surface (205) can be configured to be attached to the substrate.

[0024] In the multi-die bridge assembly (200), as illustrated, the die (206) is hybrid-bonded to the bridge component (202) and the die (210) is hybrid-bonded to the bridge component (202). Accordingly, at the HB interface (225-1), the insulating or dielectric material of the die (106) and the insulating or dielectric material of the die (110) are bonded to the insulating or dielectric material of the bridge component (202) (e.g., in the SEM image, dielectric materials SiOx to SiOx, SiOxNy to SiOxNy, etc. will be visible), the HB contact (208) is bonded to the HB contact (204-1), and the HB contact (212) is bonded to the HB contact (204-2). There is no solder material at this HB interface (225-1).

[0025] FIG. 2b has all the same components and objects as FIG. 2a, except for the implementation of the attachment means (125). In FIG. 2b, the attachment means is a solder bump or microbump field (225-2 / 325-2 / 425-2). The first die (206 / 306 / 406) is soldered to the bridge component (202 / 302 / 402) using the solder bump (232 / 332 / 432), and the second die (210 / 310 / 410) is soldered to the bridge component (202 / 302 / 402) using the solder bump (234 / 334 / 434).

[0026] The multi-die bridge assembly (300) of FIG. 3a depicts a bridge component hybridly bonded to two integrated circuit dies. FIG. 3a has the same components and objects as FIG. 2a, with the addition of at least one contact (320-3 / 420-3) on a second surface (305 / 405) that provides an electrical path to a first surface (303 / 403) (implementing the cartoon arrow (123) of FIG. 1). When assembled into a package with a substrate, power and ground can be routed through these electrical paths from the second surface (305) to the integrated circuits within the die (106) and die (110), respectively.

[0027] The multi-die bridge assembly (330) of FIG. 3b depicts a bridge component solder-bonded to two integrated circuit dies according to various embodiments. FIG. 3b has the same components and objects as FIG. 2b, with the addition of at least one contact (320-3) on a second surface (305) that provides an electrical path to a first surface (303).

[0028] The multi-die bridge assembly (400) of FIG. 4a depicts a multi-die bridge assembly (300) with mold encapsulation (424) over the lower surface / rear of die (406) and die (410). As in FIG. 2a and FIG. 3a, the bridge component (402) is hybrid-bonded to die (406) and die (410). The multi-die bridge assembly (430) of FIG. 4b depicts a multi-die bridge assembly (330) with mold encapsulation (424) over the lower surface / rear of die (406) and die (410) in an embodiment of the solder-bonded bridge component (402), and additionally, illustrates an underfill (436) between the bridge component and the upper surfaces (409 and 413). The underfill surrounds the solder bumps (432 and 434). Various underfill materials can be used, and generally, they are (electrically) non-conductive and reduce thermomechanical stress. Underfill materials can take the form of liquid pre-polymers containing fillers such as silica, alumina, or boron nitride. The underfill can be cured to solidify.

[0029] FIGS. 5A and 5B provide two non-limiting examples of multi-die bridge assemblies (500 and 530) ready to be assembled onto a substrate. The depicted bridge component (502) is a bridge component having a TSV or TGV. The multi-die bridge assembly (500) includes a ball pitch solder pad (520-1) on a first die (506), a ball pitch solder pad (520-2) on a second die (510), and a ball pitch solder pad (526) on a second surface of the bridge component (502) (the "bottom" in the drawing, the part that can be fitted into a cavity in the substrate). FIG. 5B illustrates a multi-die bridge assembly (530) configured for hybrid bonding in a cavity (HB contact (536)), having ball pitch solder pads (520-1 and 520-2) configured to solder two integrated circuit dies to the substrate.

[0030] In FIG. 6a, the embodiment (600) depicts an embodiment (500) with an added glass frame (628). In a plan view, the glass frame (628) may look like a glass ladder or a glass door with several open windows or cavities. The glass frame (also referred to herein as a glass structure) is intended to provide structural stability to the die (606) and the die (610). Within the cavity in the glass structure, individual dies are located, and the dies are surrounded by an encapsulating agent (624).

[0031] In FIG. 6b, an embodiment of a multi-die bridge assembly (630) illustrates that some applications may invert the multi-die bridge assembly (630) so that the multi-die bridge assembly (630) is attached to a substrate on the bottom or back surface (solder bump (650-2) on die (610) and solder bump (650-1) on die (606).

[0032] The foregoing is not an exhaustive list of combinations that may be found in multi-die bridge components. A person skilled in the art will understand that additional multi-die bridge assembly embodiments not illustrated are supported based on the drawings and descriptions contained herein. For example, refer to Table 1. In addition to the variations provided in Table 1, embodiments may include a glass frame. Additionally, as part of the thermal management solution, a thermal conduction layer interface material (TIM) (not shown) may be positioned over the encapsulator and / or over the dies (106 / 206 / 306 / 406 / 506 / 606) and dies (110 / 210 / 310 / 410 / 510 / 610). The TIM may be any suitable material, such as a thermal compound filled with silver particles, thermal grease, phase change material, indium foil, or a graphite sheet. The thermal management solution may be a conformal solution that accommodates height differences in the integrated circuit dies that the thermal management solution cools. For example, the thermal management solution may include a substantially planar cooling component having a TIM of varying thickness between the cooling component and the integrated circuit dies. In another example, the cooling component is non-planar, and the profile of the cooling component may vary depending on the thickness of the integrated circuit dies that the cooling component cools. In this embodiment, the TIM may have a substantially uniform thickness between the cooling component and the integrated circuit dies of varying thicknesses. The thermal management solution may also include an integrated heat spreader.

[0033]

[0034] A multi-die (MD) assembly may be attached to a substrate. This is illustrated with reference to FIGS. 7, 8, 9, and 10. FIG. 7 illustrates a substrate (700 / 870 / 970 / 1070) comprising one or more dielectric layers (724) in which redistribution layer (RDL) conductive traces (728) are patterned inside. Various embodiments of the substrate may also have a glass layer (702 / 802 / 902 / 1002) or a glass core and a dielectric layer (730 / 830 / 930 / 1030) located on the lower surface of the glass core (702 / 802 / 902 / 1002) in which RDL conductive traces and vias (726 / 728, 826 / 828, 926 / 928 and 1026 / 1028) are patterned inside.

[0035] The dielectric layers (724 and 730) may be suitable dielectrics as described above. The conductive materials used for the conductive contacts, HB contacts (e.g., 208, 212, 204), and RDL traces and vias (728 / 728) may include metals (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or combinations thereof) or other suitable conductive materials.

[0036] The substrate (700) exemplifies a glass layer (702 / 802 / 902 / 1002) or a glass core patterned with through holes or a plurality of glass through-vias (TGV) (704 / 804 / 904 / 1004). The glass layer (702 / 802 / 902 / 1002) may comprise glass (as used herein, glass is an alkali-free alkaline earth boro-aluminosilicate glass, e.g., glass containing aluminum, oxygen, boron, silicon, and alkaline earth metals (e.g., beryllium, magnesium, calcium, strontium, barium, radium), e.g., glass containing SiO2, Al2O3, B2O3, and MgO), or photosensitive glass (photomachineable or photostructurable glass). In some embodiments, the photosensitive glass may be a glass belonging to the lithium-silicate series of glasses (e.g., glass containing lithium, silicon, and oxygen) containing metal particles such as gold, silver, or other suitable metal particles. The glass layer (702) or glass core may comprise a plurality of glass sheets bonded together with an adhesive layer. In various embodiments, for example, on a substrate (700) having a Z height (in the drawing) in the range of about 10 millimeters (mm) to 500 mm, the glass layer (702) may have a thickness (Z height) in the range of about 20 micrometers to about 1.5 millimeters, + / -10%. The TGV (704) is a volume in which a conductive material is disposed in the volume, sufficient to enable electrical communication from the upper surface (703) to the lower surface, with the glass removed. As exemplified in the embodiment of the substrate (700), the TGV (704) is substantially perpendicular to the upper surface (703) of the glass layer (702).In an embodiment in which a panel is manufactured at once, the X length and the corresponding Y length (defining the area in a top-down view or plan view) may be in the range of a first length (e.g., X) in the range of 10 millimeters to 500 millimeters and a second length (e.g., Y) in the range of 10 millimeters to 500 millimeters, and the first length is perpendicular to the second length;

[0037] In embodiments of the substrate (700, 870 and 970), the cavity (701) is formed on the upper surface (703) of the substrate. As can be understood, the cavity portion of the substrate comprises a smaller width, area, or volume of the entire substrate under discussion. The drawing reflects a cross-sectional view where the portion for the dielectric cavity is depicted as a width; however, in a top-down view, the portion for the dielectric cavity will be seen as an area. The dielectric cavity is created in the substrate by removing the dielectric material to a predetermined depth. A laser drill or ablation process may be used to remove the dielectric material and create the dielectric cavity. The cavity walls are substantially straight (i.e., 90 degrees ± 20 degrees from perpendicular to the upper surface of the glass layer (702); however, in other embodiments, the cavity walls may be 90 degrees ± 10 degrees) and may have an internal taper reflecting the drill or ablation process used to open the cavity. Additional manufacturing may include laser drilling on the lower surface (705 / 805 / 905 / 1005), SR lamination after via / solder bump plating, SRO opening, and solder ball attachment.

[0038] FIG. 8 is a semiconductor package (800) with a multi-die bridge component attached. The reader will recognize IC 1, IC 2, and an encapsulator (824 / 924), as well as an attachment means (825 / 925). IC 1 and IC 2 are soldered to the upper surface of a substrate (870 / 970) using solder bumps (882 / 982). The multi-die bridge component includes a bridge component (872 / 972) having a TSV or TGV, which is soldered to the bottom of the cavity as illustrated. An underfill material (860 / 960) extends across the entire upper surface of the substrate (870) and leads into the cavity surrounding the bridge component (872 / 972). To identify this embodiment in an SEM or TEM image, this underflow will be examined to determine if it contains the same material throughout. An opening for a solder bump can be created on the lower surface (805).

[0039] FIG. 9 depicts objects and components that are largely identical to those in FIG. 8. In an embodiment (900), the multi-die bridge assembly is attached to the substrate using hybrid bonding within the cavity (in the case of the bridge) and to the substrate (970) using solder bonding outside the cavity (in the case of die 1 and die 2 to the substrate). In another embodiment, the multi-die bridge component may include a passive bridge component attached to the bottom of the cavity with an adhesive material. An opening for a solder bump may be created on the bottom surface (905).

[0040] The embodiment (1000) of FIG. 10 depicts an inverted embodiment of a multi-die bridge assembly (630) soldered to the upper surface (1003) of a substrate (1070) (see solder attachment (1020-1) and solder attachment (1020-2)). An underfill (not shown) may be added prior to additional manufacturing steps. An opening for a solder bump may be created on the lower surface (1005).

[0041] The above embodiment can provide functions associated with conventional monolithic system-on-chip (SoC) in a multi-die package assembly. Additionally, overmolding and thermal solutions (not shown) may be added.

[0042] FIG. 11 illustrates a method for a multi-die bridge assembly for 3D semiconductor packaging. The method (1100) includes the step of assembling a first integrated circuit (IC) die and a second IC die on a carrier with an adhesive or bond film (in 1102). In 1104, an encapsulating agent or mold compound layer is overlaid on the first IC and the second IC. In some embodiments, a dielectric material layer is sandwiched between the first IC, the second IC and the encapsulating agent layer.

[0043] In 1106, the carrier is detached from the assembly. In 1108, the bridge component is attached to the first part of the first IC and the first part of the second IC to create a multi-die bridge assembly. In 1110, the multi-die bridge assembly is tested to determine whether it has passed a performance metric.

[0044] In 1112, after the multi-die bridge assembly passes a performance metric, a substrate is attached to the multi-die bridge assembly. In 1112, if the substrate has a cavity, the multi-die bridge assembly is attached to the substrate so that the bridge component is placed in the cavity. As described in detail above, there are various methods for attaching the bridge component to the cavity, e.g., hybrid bonding, solder bump bonding, adhesive or bond film, thermal compression bonding, etc. In some embodiments, the substrate does not have a cavity, and the multi-die bridge assembly is attached to the substrate as described in relation to FIG. 10. Upon completion of 1112, the component is referred to as a package assembly.

[0045] In 1114, optional additional assembly may be performed to create a system package. The system package may include one or more package assemblies from 1112, and / or other integrated circuit components and / or active or passive electronic components.

[0046] Accordingly, various non-limiting embodiments of multi-die assemblies and methods for 3D packaging have been described. The embodiments are not limited to consistent underfill across the entire MD bridge component and between the bridge component and the substrate, and / or combined HB and solder attachments, but exhibit distinct features in SEM images. The following description provides additional details and context regarding various die and package assemblies and device configurations that can be created based on or using the provided embodiments.

[0047] FIG. 12 is a top view of a wafer (1200) and dies (1202) that may be included in any of the embodiments disclosed herein. The wafer (1200) may be composed of a semiconductor material and may include one or more dies (1202) formed on the surface of the wafer (1200). After the manufacturing of an integrated circuit component on the wafer (1200) is completed, the wafer (1200) may undergo a singulation process, wherein the dies (1202) are separated from each other to provide individual "chips" or become packaged integrated circuit components. An individual die (1202) containing an integrated circuit component may include one or more transistors (e.g., some of the transistors (1340) of FIG. 13 discussed below) that support a circuit for routing an electrical signal to a transistor, a passive component (e.g., a signal trace, a resistor, a capacitor, or an inductor) and / or any other integrated circuit component. In some embodiments, the wafer (1200) or die (1202) may include a memory device (e.g., a random access memory (RAM) device such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Additionally, a plurality of devices may be combined on a single die (1202). For example, a memory array formed by a plurality of memory devices may be formed on the same die (1202) as a processor unit (e.g., the processor unit (1502) of FIG. 15) or other logic configured to store information in the memory device or to execute instructions stored in the memory array.In some embodiments, the die (1202) may be attached to a wafer (1200) containing other dies, and the wafer (1200) is subsequently singulated, and this manufacturing process is referred to as die-to-wafer assembly technology.

[0048] FIG. 13 is a side cross-sectional view of an integrated circuit (1300) that may be included in any of the embodiments disclosed herein. One or more of the integrated circuits (1300) may be included in one or more dies (1202) (Fig. 12). An integrated circuit device (1300) may be formed on a die substrate (1302) (e.g., the wafer (1200) of FIG. 12) and may be included in a die (e.g., the die (1202) of FIG. 12).

[0049] The die substrate (1302) may be a semiconductor substrate composed of a semiconductor material system, for example, an n-type or p-type material system (or a combination of both). The die substrate (1302) may comprise a crystalline substrate formed using, for example, bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate (1302) may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additional materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate (1302). Although several examples of materials on which the die substrate (1302) can be formed are described herein, any material that can serve as a basis for the integrated circuit (1300) may be used. The die substrate (1302) may be part of a singulated die (e.g., the dies (1202) of FIG. 12) or a wafer (e.g., the wafer (1200) of FIG. 12).

[0050] The integrated circuit (1300) may include one or more device layers (1304) disposed on a die substrate (1302). The device layer (1304) may include features of one or more transistors (1340) (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate (1302). The transistor (1340) may include, for example, one or more source and / or drain (S / D) regions (1320), a gate (1322) that controls current flow between the S / D regions (1320), and one or more S / D contacts (1324) that route electrical signals to / from the S / D regions (1320).

[0051] The gate (1322) may be formed of at least two layers, namely a gate dielectric and a gate electrode. The gate dielectric may comprise a single layer or a stack of layers. One or more layers may comprise silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may comprise elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k dielectric materials that may be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when a high dielectric constant material is used, an annealing process may be performed on the gate dielectric to improve the quality of the gate dielectric.

[0052] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor (1340) is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as a barrier layer, may be included for other purposes.

[0053] For PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0054] In some embodiments, when viewed in cross-section of the transistor (1340) along the source-channel-drain direction, the gate electrode may comprise a “U” shaped structure including a bottom portion substantially parallel to the surface of the die substrate (1302) and two sidewall portions substantially perpendicular to the top surface of the die substrate (1302). In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate (1302) and does not include a sidewall portion substantially perpendicular to the top surface of the die substrate (1302). In other embodiments, the gate electrode may comprise a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may comprise one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0055] In some embodiments, pairs of sidewall spacers may be formed on opposing sides of a gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and include deposition processes and etching processes. In some embodiments, multiple pairs of spacers may be used; for example, two pairs of sidewall spacers, three pairs of sidewall spacers, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0056] The S / D region (1320) may be formed within the die substrate (1302) adjacent to the gate (1322) of the individual transistor (1340). The S / D region (1320) may be formed, for example, using an implantation / diffusion process or an etching / deposition process. In the former process, a dopant such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate (1302) to form the S / D region (1320). An annealing process may follow the ion implantation process to activate the dopant and diffuse it further into the die substrate (1302). In the latter process, the die substrate (1302) may first be etched to form a recess at the location of the S / D region (1320). Subsequently, an epitaxial deposition process may be performed to fill the recess with the material used to manufacture the S / D region (1320). In some embodiments, the S / D region (1320) may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with a dopant such as boron, arsenic, or phosphorus. In some embodiments, the S / D region (1320) may be formed using one or more alternative semiconductor materials such as germanium or a Group III-V material or alloy. In additional embodiments, one or more metal layers and / or metal alloy layers may be used to form the S / D region (1320).

[0057] Electrical signals, such as power and / or input / output (I / O) signals, may be routed to and / or from a device of the device layer (1304) (e.g., a transistor (1340)) through one or more interconnect layers (exemplified in FIG. 13 as interconnect layers (1306 to 1310)) disposed on the device layer (1304). For example, electrically conductive features of the device layer (1304) (e.g., a gate (1322) and an S / D contact (1324)) may be electrically coupled to an interconnect structure (1328) of the interconnect layers (1306 to 1310). One or more interconnect layers (1306 to 1310) may form a metallization stack (also referred to as an "ILD stack") (1319) of the integrated circuit (1300).

[0058] The interconnect structure (1328) may be arranged within the interconnect layers (1306 to 1310) to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the specific configuration of the interconnect structure (1328) depicted in FIG. 13. Although a specific number of interconnect layers (1306 to 1310) is depicted in FIG. 13, embodiments of the present disclosure include an integrated circuit having more or fewer interconnect layers than depicted.

[0059] In some embodiments, the interconnect structure (1328) may include lines (1328a) and / or vias (1328b) filled with an electrically conductive material such as metal. The lines (1328a) may be arranged to route electrical signals in a direction in a plane substantially parallel to the surface of the die substrate (1302) on which the device layer (1304) is formed. For example, the lines (1328a) may route electrical signals in a direction entering and exiting the ground and / or across the ground. The vias (1328b) may be arranged to route electrical signals in a direction in a plane substantially perpendicular to the surface of the die substrate (1302) on which the device layer (1304) is formed. In some embodiments, the vias (1328b) may electrically connect lines (1328a) of different interconnect layers (1306 to 1310) together.

[0060] The interconnect layers (1306 to 1310) may include a dielectric material (1326) disposed between interconnect structures (1328), as illustrated in FIG. 13. In some embodiments, the dielectric material (1326) disposed between interconnect structures (1328) in different interconnect layers among the interconnect layers (1306 to 1310) may have different compositions; in other embodiments, the composition of the dielectric material (1326) between different interconnect layers (1306 to 1310) may be the same. The device layer (1304) may also include a dielectric material (1326) disposed between the transistor (1340) and the bottom layer of the metal wiring stack. The dielectric material (1326) included in the device layer (1304) may have a different composition from the dielectric material (1326) included in the interconnect layers (1306 to 1310); in another embodiment, the composition of the dielectric material (1326) in the device layer (1304) may be the same as the dielectric material (1326) included in any one of the interconnect layers (1306 to 1310).

[0061] A first interconnect layer (1306) (referred to as metal 1 or "M1") may be formed directly on the device layer (1304). In some embodiments, the first interconnect layer (1306) may include a line (1328a) and / or a via (1328b), as illustrated. A line (1328a) of the first interconnect layer (1306) may be coupled to a contact (e.g., an S / D contact (1324)) of the device layer (1304). A via (1328b) of the first interconnect layer (1306) may be coupled to a line (1328a) of the second interconnect layer (1308).

[0062] A second interconnect layer (1308) (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer (1306). In some embodiments, the second interconnect layer (1308) may include vias (1328b) for connecting lines of the interconnect structure (1328) of the second interconnect layer (1308) with lines (1328a) of the third interconnect layer (1310). Although lines (1328a) and vias (1328b) are structurally depicted as lines within individual interconnect layers for clarity, in some embodiments, lines (1328a) and vias (1328b) may be structurally and / or materially continuous (e.g., filled simultaneously during a dual-damascene process).

[0063] A third interconnect layer (1310) (referred to as metal 3 or “M3”) (and, optionally, additional interconnect layers) may be formed continuously on the second interconnect layer (1308) according to similar techniques and configurations described in relation to the second interconnect layer (1308) or the first interconnect layer (1306). In some embodiments, an interconnect layer “higher up” (i.e., further away from the device layer (1304) in the metal wiring stack (1319) within the integrated circuit (1300) may be thicker than an interconnect layer further down in the metal wiring stack (1319), and lines (1328a) and vias (1328b) in the interconnect layer higher up may be thicker than lines and vias in the interconnect layer further down.

[0064] The integrated circuit (1300) may include a solder resist material (1334) (e.g., polyimide or a similar material) formed on interconnect layers (1306 to 1310) and one or more conductive contacts (1336). In FIG. 13, the conductive contacts (1336) are illustrated as taking the form of bond pads. The conductive contacts (1336) may be electrically coupled to the interconnect structure (1328) and configured to route electrical signals of the transistor(s) (1340) to an external device. For example, a solder bond may be formed on one or more conductive contacts (1336) to mechanically and / or electrically couple an integrated circuit die containing the integrated circuit (1300) with another component (e.g., a printed circuit board). The integrated circuit (1300) may include additional or alternative structures for routing electrical signals from interconnect layers (1306 to 1310); for example, the conductive contact (1336) may include other similar features (e.g., a post) for routing electrical signals to an external component.

[0065] In some embodiments where the integrated circuit (1300) is a double-sided die, the integrated circuit (1300) may include another metal wiring stack (not shown) on the opposite side of the device layer(s) (1304). This metal wiring stack may include a number of interconnect layers as discussed above with reference to interconnect layers (1306 to 1310) to provide an electrically conductive path (e.g., including conductive lines and vias) between the device layer(s) (1304) and an additional conductive contact (not shown) on the opposite side of the integrated circuit (1300) from the conductive contact (1336).

[0066] In another embodiment where the integrated circuit (1300) is a double-sided die, the integrated circuit (1300) may include one or more through-silicon vias (TSVs) passing through the die substrate (1302); these TSVs may come into contact with device layer(s) (1304) and may provide an electrically conductive path between the device layer(s) (1304) and an additional conductive contact (not shown) on the opposite side of the integrated circuit (1300) from the conductive contact (1336). In some embodiments, a TSV extending through a substrate may be used to route power and ground signals from a conductive contact on the opposite side of the integrated circuit (1300) from a conductive contact (1336) to a transistor (1340) and any other component integrated in the die of the integrated circuit (1300), and a metal wiring stack (1319) may be used to route I / O signals from a conductive contact (1336) to a transistor (1340) and any other component integrated in the die of the integrated circuit (1300).

[0067] A plurality of integrated circuits (1300) may be stacked, and one or more TSVs within individual stacked devices provide a connection between one of the devices and any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies may be stacked on a base integrated circuit die, and TSVs within the HBM die may provide a connection between the individual HBM and the base integrated circuit die. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine-pitch solder bumps (microbumps).

[0068] FIG. 14 is a side cross-sectional view of a microelectronic assembly (1400) that may include any of the embodiments disclosed herein. The microelectronic assembly (1400) includes a plurality of integrated circuit components disposed on a circuit board (1402) (which may be a mother board, system board, main board, etc.). The microelectronic assembly (1400) may include a component disposed on a first face (1440) of the circuit board (1402) and an opposing second face (1442) of the circuit board (1402); generally, the component may be disposed on one or both of the faces (1440 and 1442).

[0069] In some embodiments, the circuit board (1402) may be a printed circuit board (PCB) comprising a plurality of metal (or interconnect) layers separated from one another by a layer of dielectric material and interconnected by electrically conductive vias. Individual metal layers include conductive traces. Any one or more of the metal layers may be formed into a desired circuit pattern (optional together with other metal layers) to route electrical signals between components coupled to the circuit board (1402). In other embodiments, the circuit board (1402) may be a non-PCB substrate. The microelectronic assembly (1400) illustrated in FIG. 14 includes a package-on-interposer structure (1436) coupled to a first surface (1440) of the circuit board (1402) by a coupling component (1416). The coupling component (1416) can electrically and mechanically bond the package-on-interposer structure (1436) to the circuit board (1402) and may include a solder ball (as shown in FIG. 14), a pin (e.g., part of a pin grid array (PGA)), a contact (e.g., part of a land grid array (LGA)), a male and female part of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0070] The package-on-interposer structure (1436) may include an integrated circuit component (1420) coupled to the interposer (1404) by a coupling component (1418). The coupling component (1418) may take any form suitable for the application, such as the form discussed above in relation to the coupling component (1416). Although a single integrated circuit component (1420) is shown in FIG. 14, multiple integrated circuit components may be coupled to the interposer (1404); in fact, additional interposers may be coupled to the interposer (1404). The interposer (1404) may provide an interposing substrate used to bridge the circuit board (1402) and the integrated circuit component (1420).

[0071] The integrated circuit component (1420) may be a packaged or unpackaged integrated circuit component comprising one or more integrated circuit dies (e.g., die (1202) of FIG. 12, integrated circuit (1300) of FIG. 13) and / or one or more other suitable components.

[0072] The unpackaged integrated circuit component (1420) includes solder bumps attached to contacts on the die. The solder bumps allow the die to be attached directly to the interposer (1404). In an embodiment where the integrated circuit component (1420) includes a plurality of integrated circuit dies, the dies may be of the same type (homogeneous multi-die integrated circuit component) or two or more different types (heterogeneous multi-die integrated circuit component). In addition to including one or more processor units, the integrated circuit component (1420) may include additional components such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controller, or memory controller. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separated from the integrated circuit die containing the processor unit. These individual integrated circuit dies may be referred to as "chiplets." In an embodiment in which an integrated circuit component comprises a plurality of integrated circuit dies, interconnections between the dies may be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate, or a combination thereof. The packaged multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0073] The interposer (1404) may extend the connections to a wider pitch or reroute the connections to different connections. For example, the interposer (1404) may allow an integrated circuit component (1420) to be coupled to a ball grid array (BGA) conductive contact set of a coupling component (1416) and coupled to a circuit board (1402). In the embodiment illustrated in FIG. 14, the integrated circuit component (1420) and the circuit board (1402) are attached to opposite sides of the interposer (1404); in another embodiment, the integrated circuit component (1420) and the circuit board (1402) may be attached to the same side of the interposer (1404). In some embodiments, three or more components may be interconnected through the interposer (1404).

[0074] In some embodiments, the interposer (1404) may be formed as a PCB comprising a plurality of metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer (1404) may be formed from a polymer material such as epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic filler, ceramic material, or polyimide. In some embodiments, the interposer (1404) may be formed from an alternative hard or soft material that may include the same materials described above for use as semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer (1404) may include a metal interconnect (1408) and vias (1410), including but not limited to: a through-hole via (1410-1) (extending from a first surface (1450) of the interposer (1404) to a second surface (1454) of the interposer (1404); a blind via (1410-2) (extending from a first surface (1450) or a second surface (1454) of the interposer (1404) to an inner metal layer); and a buried via (1410-3) (connecting the inner metal layers).

[0075] In some embodiments, the interposer (1404) may include a silicon interposer. A silicon through-via (TSV) extending through the silicon interposer may connect a connection on a first surface of the silicon interposer to a second surface opposite the silicon interposer. In some embodiments, the interposer (1404) including the silicon interposer may further include one or more routing layers for routing a connection on the first surface of the interposer (1404) to a second surface opposite the interposer (1404).

[0076] The interposer (1404) may further include an embedded device (1414) comprising both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the interposer (1404). The package-on-interposer structure (1436) may take the form of any of the package-on-interposer structures known in the art.

[0077] The integrated circuit assembly (1400) may include an integrated circuit component (1424) that is coupled to a first surface (1440) of the circuit board (1402) by a coupling component (1422). The coupling component (1422) may take the form of any of the embodiments discussed above in relation to the coupling component (1416), and the integrated circuit component (1424) may take the form of any of the embodiments discussed above in relation to the integrated circuit component (1420).

[0078] The integrated circuit assembly (1400) illustrated in FIG. 14 includes a package-on-package structure (1434) that is coupled to a second side (1442) of a circuit board (1402) by a coupling component (1428). The package-on-package structure (1434) may include an integrated circuit component (1426) and an integrated circuit component (1432) that are coupled together by a coupling component (1430) such that the integrated circuit component (1426) is positioned between the circuit board (1402) and the integrated circuit component (1432). The coupling component (1428 and 1430) may take the form of any of the embodiments of the coupling component (1416) discussed above, and the integrated circuit component (1426 and 1432) may take the form of any of the embodiments of the integrated circuit component (1420) discussed above. The package-on-package structure (1434) can be configured according to any of the package-on-package structures known in the art.

[0079] FIG. 15 is a block diagram of an exemplary electric device (1500) that may include one or more of the embodiments disclosed herein. For example, any suitable component among the components of the electric device (1500) may include a microelectronic assembly (1400), an integrated circuit component (1420), an integrated circuit (1300), an integrated circuit die (1202), or one or more of the structures disclosed herein. Although FIG. 15 illustrates that a number of components are included in the electric device (1500), any one or more of these components may be omitted or duplicated as suitable for the application. In some embodiments, some or all of the components included in the electric device (1500) may be attached to one or more motherboards, main boards, printed circuit boards, or system boards. In some embodiments, one or more of these components are manufactured on a single system-on-a-chip (SoC) die. In various embodiments, the electric device (3000) is enclosed by a housing or integrated with a housing.

[0080] Additionally, in various embodiments, the electric device (1500) may not include one or more of the components illustrated in FIG. 15, but the electric device (1500) may include an interface circuit for coupling to one or more components. For example, the electric device (1500) may not include a display device (1506), but may include a display device interface circuit (e.g., a connector and driver circuit) that can be coupled to the display device (1506). In another set of examples, the electric device (1500) may not include an audio input device (1524) or an audio output device (1508), but may include an audio input or output device interface circuit (e.g., a connector and support circuit) that can be coupled to the audio input device (1524) or the audio output device (1508).

[0081] The electrical device (1500) may include one or more processor units (1502) (e.g., one or more processor units). As used herein, the terms “processor unit,” “processing unit,” or “processor” may refer to any device or any part of a device that processes electronic data from registers and / or memory and converts said electronic data into other electronic data that can be stored in registers and / or memory. The processor units (1502) may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), acceleration processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processing units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor unit. Therefore, the processor unit may be referred to as an XPU (or xPU).

[0082] The electrical device (1500) may include memory (1504), and the memory (1504) itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-volatile memory), solid-state memory, and / or a hard drive. In some embodiments, the memory (1504) may include memory located on the same integrated circuit die as the processor unit (1502). This memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0083] In some embodiments, the electric device (1500) may include one or more processor units (1502) that are heterogeneous or asymmetric with respect to other processor units (1502) within the electric device (1500). There may be various differences between the processor units (1502) within the system in terms of a wide range of performance metrics, including architecture, microarchitecture, thermal, power consumption characteristics, etc. These differences themselves may effectively manifest as asymmetry and heterogeneity between the processor units (1502) within the electric device (1500).

[0084] In some embodiments, the electric device (1500) may include a communication component (1512) (e.g., one or more communication components). For example, the communication component (1512) may manage wireless communication for data transmission with the electric device (1500). The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., capable of communicating data using electromagnetic radiation modulated through a nonsolid medium. The term “wireless” does not imply that the associated device does not include any wire, although in some embodiments, it may not.

[0085] The communication component (1512) may implement any of a number of wireless standards or protocols, including but not limited to IEEE (Institute for Electrical and Electronic Engineers) standards including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), any revisions, updates, and / or revisions (e.g., the Advanced LTE project, the UMB (ultra mobile broadband) project (also referred to as "3GPP2"), etc.) and the LTE (Long-Term Evolution) project. An IEEE 802.16 compliant BWA (Broadband Wireless Access) network is generally referred to as a WiMAX network, which is an abbreviation for Worldwide Interoperability for Microwave Access, a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standard. The communication component (1512) can operate according to GSM (Global System for Mobile Communication), GPRS (General Packet Radio Service), UMTS (Universal Mobile Telecommunications System), HSPA (High Speed ​​Packet Access), E-HSPA (Evolved HSPA), or LTE networks. The communication component (1512) can operate according to EDGE (Enhanced Data for GSM Evolution), GERAN (GSM EDGE Radio Access Network), UTRAN (Universal Terrestrial Radio Access Network), or E-UTRAN (Evolved UTRAN).The communication component (1512) may operate according to any other wireless protocol designated as CDMA (Code Division Multiple Access), TDMA (Time Division Multiple Access), DECT (Digital Enhanced Cordless Telecommunications), EV-DO (Evolution-Data Optimized), and derivatives thereof, as well as 3G, 4G, 5G, and beyond. In other embodiments, the communication component (1512) may operate according to other wireless protocols. The electric device (1500) may include an antenna (1522) for facilitating wireless communication and / or receiving other wireless communication (such as AM or FM radio transmission).

[0086] In some embodiments, the communication component (1512) may manage wired communication, such as electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As mentioned above, the communication component (1512) may include a number of communication components. For example, the first communication component (1512) may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and the second communication component (1512) may be dedicated to longer-range wireless communications such as GPS (global positioning system), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication component (1512) may be dedicated to wireless communication, and the second communication component (1512) may be dedicated to wired communication.

[0087] The electric device (1500) may include a battery / power circuit (1514). The battery / power circuit (1514) may include one or more energy storage devices (e.g., a battery or a capacitor) and / or a circuit for connecting a component of the electric device (1500) to an energy source (e.g., an AC line power source) separated from the electric device (1500).

[0088] The electrical device (1500) may include a display device (1506) (or a corresponding interface circuit as discussed above). The display device (1506) may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0089] The electric device (1500) may include an audio output device (1508) (or a corresponding interface circuit as discussed above). The audio output device (1508) may include any embedded or wired or wirelessly connected external device that generates an auditory indicator, such as a speaker, headset, or earbuds.

[0090] The electric device (1500) may include an audio input device (1524) (or a corresponding interface circuit as discussed above). The audio input device (1524) may include any embedded, wired, or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device having a MIDI (musical instrument digital interface) output). The electric device (1500) may include a GNSS (Global Navigation Satellite System) device (1518) (or a corresponding interface circuit as discussed above), such as a GPS (Global Positioning System) device. The GNSS device (1518) may communicate with a satellite-based system and, as is known in the art, may determine the geolocation of the electric device (1500) based on information received from one or more GNSS satellites.

[0091] The electric device (1500) may include another output device (1510) (or a corresponding interface circuit as discussed above). Examples of the other output device (1510) may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to another device, or an additional storage device.

[0092] The electrical device (1500) may include another input device (1520) (or a corresponding interface circuit as discussed above). Examples of other input devices (1520) may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monocular or stereoscopic camera), a cursor control device such as a trackball, a trackpad, a touchpad, a keyboard, or a mouse, a stylus, a touchscreen, a proximity sensor, a microphone, a barcode reader, a QR (Quick Response) code reader, an electrocardiogram (ECG) sensor, a photoplethysmogram (PPG) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0093] The electric device (1500) may have any desired form factor, such as a handheld or mobile electric device (e.g., cell phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, 2-in-1 convertible computer, portable all-in-one computer, netbook computer, ultrabook computer, PDA (personal digital assistant), ultra-mobile personal computer, portable gaming console, etc.), desktop electric device, server, rack-level computing solution (e.g., blade, tray, or sled computing system), workstation or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, stationary gaming console, smart television, vehicle control unit, digital camera, digital video recorder, wearable electric device or embedded computing system (e.g., a computing system that is part of a vehicle, smart home appliance, consumer electronics or equipment, or manufacturing equipment). In some embodiments, the electric device (1500) may be any other electronic device that processes data. In some embodiments, the electric device (1500) may include a number of individual physical components. Given the range of devices that the electric device (1500) may represent as in various embodiments, in some embodiments, the electric device (1500) may be referred to as a computing device or a computing system.

[0094] Although at least one embodiment has been presented in the foregoing detailed description, it should be understood that a vast number of variations exist. It should also be understood that the disclosed embodiment is merely an example and is not intended to limit the scope, applicability, or configuration of the present disclosure in any way. Rather, the foregoing detailed description will provide a convenient roadmap for implementing the disclosed embodiment to those skilled in the art. Various changes may be made to the function and arrangement of elements without departing from the scope of the present disclosure as set forth in the appended claims and their legal equivalents.

[0095] As used herein, the term “electronic component” may refer to an active electronic circuit (e.g., processing unit, memory, storage device, FET) or a passive electronic circuit (e.g., resistor, inductor, capacitor).

[0096] As used herein, the term “integrated circuit component” may refer to an electronic component configured on a semiconductor material to perform a function. An integrated circuit (IC) component may include one or more of any computing system components described or referenced herein, or any other computing system components such as a processor unit (e.g., a system-on-chip (SoC), a processor core, a graphics processor unit (GPU), an accelerator, a chipset processor), an I / O controller, a memory, or a network interface controller, and may include one or more additional active or passive devices such as a capacitor, an isolation capacitor, a resistor, an inductor, a fuse, a diode, a transformer, a sensor, an electrostatic discharge (ESD) device, and a memory device.

[0097] Non-limiting examples of unpackaged integrated circuit components include a single monolithic integrated circuit die; the die may include solder bumps attached to contacts on the die. When present on the die, the solder bumps or other conductive contacts may allow the die to be directly attached to a printed circuit board (PCB) or other substrate.

[0098] Non-limiting examples of packaged integrated circuit components include one or more integrated circuit dies mounted on a package substrate, and the integrated circuit dies and the package substrate are encapsulated by a casing material such as metal, plastic, glass, or ceramic. Often, the casing includes an integrated heat spreader (IHS); and the packaged integrated circuit component often has bumps, leads, or pins attached to the package substrate (directly or by wires attaching bumps, leads, or pins to the package substrate) to attach the packaged integrated circuit component to a printed circuit board (or motherboard or baseboard) or other components.

[0099] As used herein, phrases such as “Examples,” “Various Examples,” “Some Examples,” etc. indicate that some embodiments may have some, all, or none of the features described for other embodiments. “First,” “Second,” “Third,” etc. describe a common object and represent different instances of a similar object being referenced; unless specifically stated otherwise, they do not imply a given order in terms of time or space, order, or any other manner. According to the patent application terminology, “connected” indicates elements that are in direct physical or electrical contact with each other, and “coupled” indicates elements that cooperate or interact with each other; the coupled elements may or may not be in direct physical or electrical contact. Additionally, terms such as “comprising,” “including,” and “having” are used as synonyms to indicate non-exclusive inclusion.

[0100] As used in this application and claims, a list of items linked by the term "at least one of" or "one or more of" may mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C. Likewise, the phrase "one or more of A, B, and C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0101] As used in this application and claims, when a list of items enumerated or mentioned as having characteristics, features, etc. follows the phrases "individual of" or "respective of," it means that all items in the list possess the mentioned or enumerated characteristics, features, etc. For example, the phrases "individual of A, B, or C include a sidewall" or "each of A, B, or C includes a sidewall" mean that A includes a sidewall, B includes a sidewall, and C includes a sidewall.

[0102] The operating theories, scientific principles, or other theoretical descriptions presented herein in relation to the apparatus or method of the present disclosure are provided for better understanding and are not intended to limit the scope. The apparatus and method in the appended claims are not limited to such apparatus and method that function in the manner described by such operating theories.

[0103] The following examples relate to additional examples of the technology disclosed in this specification.

[0104] yes

[0105] Example 1 is a semiconductor assembly comprising a bridge component defined by a first surface and a second surface, the first surface comprising a plurality of first metal contacts on the first surface, the plurality of first metal contacts comprising a first region and a second region; the bridge component providing at least one electrical path between a first first metal contact in the first region and a second first metal contact in the second region; a first die comprising a first upper surface, the first upper surface having a second insulating material and a plurality of second metal contacts; the first upper surface being in a first region of the first surface, the first insulating material being directly bonded to the second insulating material and some of the first metal contacts being directly bonded to their respective second metal contacts; a second die comprising a second upper surface, the second upper surface having a third insulating material and a plurality of third metal contacts; The second upper surface is in the second region of the first surface, the first insulating material is directly bonded to the third insulating material, and other first metal contacts are directly bonded to their respective third metal contacts.

[0106] Example 2 includes the subject of Example 1 and further includes at least one contact on a second surface that provides an electrical path to the first surface.

[0107] Example 3 includes the subject of Example 1, where the first die includes a processing or graphics integrated circuit and the second die includes a memory device.

[0108] Example 4 includes the subject of Example 1, where the first insulating material, the second insulating material, and the third insulating material are dielectric materials.

[0109] Example 5 includes the subject of Example 1, wherein a plurality of first metal contacts, a plurality of second metal contacts and a plurality of third metal contacts include copper.

[0110] Example 6 includes the subject of Example 1, where a plurality of first metal contacts, a plurality of second metal contacts and a plurality of third metal contacts are hybrid bond conductive contacts.

[0111] Example 7 includes the subject of Example 2 and further includes one or more solder bumps attached to the second surface.

[0112] Example 8 includes the subject of Example 1 or Example 2, wherein the first die further has a first lower surface, the second die further has a second lower surface, and further includes a mold compound overlaid on the first lower surface and the second lower surface.

[0113] Example 9 includes the subject of Example 8 and further includes dielectric material layers between the mold compound and the first lower surface and between the mold compound and the second lower surface.

[0114] Example 10 includes the subject of Example 8 and further includes an underfill between the first surface and the first upper surface, and an underfill between the first surface and the second upper surface.

[0115] Example 11 includes the subject of Example 8 and further includes a glass structure between the first die and the second die—the glass structure is in contact with the first surface of the bridge component.

[0116] Example 12 is a semiconductor package comprising the subject of Example 1, and further comprises a substrate comprising one or more dielectric layers—each dielectric layer comprising its own redistribution layer (RDL)—the substrate comprising a cavity formed on a top surface—and a semiconductor assembly attached to the substrate—a bridge component being within the cavity, and a first top surface and a second top surface extending across the top surface.

[0117] Example 13 is a semiconductor package comprising the subject of Example 2, and further comprises a substrate comprising one or more dielectric layers—each dielectric layer comprising its own redistribution layer (RDL)—the substrate comprising a cavity formed on a top surface; a solder material layer within the cavity; and a semiconductor assembly attached to the substrate—the bridge component being attached to the solder material layer within the cavity via solder bumps, and the first top surface and the second top surface extending across the top surface.

[0118] Example 14 includes the subject of Example 13 and further includes a first upper surface and a first surface, a cavity and a bridge component, and an underfill material located between a second upper surface and a first surface.

[0119] Example 15 is a semiconductor package comprising the subject of Example 2, and further comprises a substrate comprising one or more dielectric layers—each dielectric layer comprising its own redistribution layer (RDL)—the substrate comprises a cavity formed on a top surface, the cavity comprising a dielectric material having a metal pad; and a semiconductor assembly attached to the substrate—bridge components are attached to their respective metal pads through direct bonding of at least one contact in the cavity, and the dielectric material is directly bonded to a first insulating material in a second surface, wherein the first top surface and the second top surface extend across the top surface.

[0120] Example 16 is a semiconductor package comprising the subject of Example 1, and further comprises a substrate comprising one or more dielectric layers—each dielectric layer comprising its own redistribution layer (RDL); a first die comprising a first bottom surface; a second die comprising a second bottom surface; and a semiconductor assembly on the substrate—the first bottom surface and the second bottom surface are attached to the top surface of the substrate via solder bumps.

[0121] Example 17 is a semiconductor package of any one of Examples 12 to 16, wherein the substrate comprises a glass layer having a thickness in the range of 20 micrometers to 1.4 millimeters, a first length in the range of 10 millimeters to 500 millimeters, and a second length in the range of 10 millimeters to 500 millimeters, the first length being perpendicular to the second length; and the glass layer comprises a plurality of glass through-vias.

[0122] Example 18 is a package assembly comprising: a processing unit die having a first upper surface and a first lower surface; a memory die having a second upper surface and a second lower surface; and a multi-die bridge assembly comprising a bridge component attached to a first portion of the first upper surface and a first portion of the second upper surface of the memory die on the first surface—the bridge component comprises a plurality of paths for electrical communication between the processing unit die and the memory die; and a substrate comprising one or more dielectric layers—each dielectric layer comprises its own redistribution layer (RDL)—the substrate comprises a cavity formed on the upper surface; wherein the multi-die bridge assembly is attached to the substrate such that the bridge component is in the cavity, and the second portion of the first upper surface and the second portion of the second upper surface extend across the upper surface.

[0123] Example 19 includes the subject of Example 18, where the bridge component is attached to the first part of the first upper surface and the first part of the second upper surface of the memory die through hybrid bonding on the first surface.

[0124] Example 20 includes the subject of Example 18, where the second part of the first upper surface and the second part of the second upper surface are hybrid bonded to the top surface.

[0125] Example 21 is a method comprising the steps of: assembling a first integrated circuit (IC) die and a second IC die on a carrier with a bond film; placing a mold compound layer on the first IC and the second IC; separating the carrier; creating a multi-die bridge assembly by attaching a bridge component to a first part of the first IC and a first part of the second IC; testing the multi-die bridge assembly to determine whether it passes a performance metric; and creating a package assembly by attaching a substrate to the multi-die bridge assembly when the multi-die bridge assembly passes the performance metric.

[0126] Example 22 includes the subject of Example 21, where the bridge component includes any combination of one or more of silicon, organic materials and glass.

[0127] Example 23 includes the subject of Example 21 or Example 22, wherein the substrate has a cavity and attaching the substrate to a multi-die bridge assembly includes placing a bridge component in the cavity.

[0128] Example 24 includes the subject of any one of Examples 21 to 23, wherein attaching the bridge component to the first part of the first IC and the first part of the second IC is achieved by hybrid bonding.

[0129] Example 25 includes the subject of any one of Examples 21 to 23, wherein attaching the bridge component to the first part of the first IC and the first part of the second IC is achieved by solder bumps.

[0130] Example 26 includes the subject of any one of Examples 21 to 25 and further includes the step of assembling two or more package assemblies into a system package.

Claims

Claim 1 A multi-die bridge assembly comprising: a bridge component having a top side above a bottom side and side walls between the top side and the bottom side, wherein the bridge component has through silicon vias (TSVs) within it; a first via spaced laterally from the side wall of the bridge component; a second via below the bottom side of the bridge component, wherein one of the TSVs of the bridge component overlaps perpendicularly with the second via and is coupled to the second via; a third via below the first via and coupled to the first via such that the first via overlaps perpendicularly with the third via, wherein the third via is spaced laterally from the second via and the third via has a width greater than the width of the second via; a first trace below the second via and coupled to the second via, and a third trace below the third via and the third A second trace coupled to a via - said second trace is spaced laterally from said first trace -; a fourth via located below said first trace and coupled to said first trace - said fourth via does not overlap vertically with said second via -; a fifth via located below said second trace and coupled to said second trace - said fifth via overlaps vertically with said third via -; a first integrated circuit (IC) die coupled vertically above the upper side of said bridge component and coupled vertically above said first via - said first IC die has a first thickness -; a second IC die coupled vertically above the upper side of said bridge component and spaced laterally from said first IC die - said second IC die has a second thickness smaller than said first thickness -;A multi-die bridge assembly comprising an encapsulant on the second IC die. Claim 2 In claim 1, the encapsulating agent is a multi-die bridge assembly located between the second IC die and the first IC die. Claim 3 In claim 1, the encapsulation agent is a multi-die bridge assembly located on the first IC die. Claim 4 In claim 1, the encapsulation agent is a multi-die bridge assembly along the sides of the first IC die. Claim 5 A multi-die bridge assembly according to claim 1, wherein the first via has a bottom surface at a level above the bottom side of the bridge component. Claim 6 A multi-die bridge assembly according to claim 1, further comprising a sixth via vertically positioned between the first via and the third via. Claim 7 A multi-die bridge assembly according to claim 1, further comprising a sixth via located transversely between the first via and the bridge component. Claim 8 A multi-die bridge assembly comprising: a component having an upper side above a lower side and sidewalls between the upper side and the lower side, wherein the component has a through silicon via (TSV) therein; a first conductive structure spaced laterally from the sidewall of the component; a second conductive structure below the lower side of the component, wherein the TSV of the component is perpendicularly superimposed with the second conductive structure and coupled to the second conductive structure; a third conductive structure below the first conductive structure and coupled to the first conductive structure such that the first conductive structure is perpendicularly superimposed with the third conductive structure, wherein the third conductive structure is spaced laterally from the second conductive structure and the third conductive structure has a width greater than the width of the second conductive structure; a first conductive trace below the second conductive structure and coupled to the second conductive structure, and a second conductive trace below the third conductive structure and coupled to the third conductive structure, wherein the second conductive trace is spaced laterally from the first conductive trace. -; A fourth conductive structure located below the first conductive trace and coupled to the first conductive trace - the fourth conductive structure does not overlap perpendicularly with the second conductive structure -; A fifth conductive structure located below the second conductive trace and coupled to the second conductive trace - the fifth conductive structure overlaps perpendicularly with the third conductive structure -; A first integrated circuit (IC) die coupled perpendicularly above the upper side of the component and coupled perpendicularly above the first conductive structure - the first IC die has a first thickness -; A second IC die coupled perpendicularly above the upper side of the component and spaced laterally from the first IC die - the second IC die has a second thickness smaller than the first thickness -;A multi-die bridge assembly comprising an encapsulation agent on the second IC die. Claim 9 In claim 8, the encapsulation agent is a multi-die bridge assembly located between the second IC die and the first IC die. Claim 10 In paragraph 8, the encapsulation agent is a multi-die bridge assembly located on the first IC die. Claim 11 In claim 8, the encapsulation agent is a multi-die bridge assembly along the sides of the first IC die. Claim 12 In claim 8, the first conductive structure is a multi-die bridge assembly having a bottom surface at a level above the bottom side of the component. Claim 13 A multi-die bridge assembly according to claim 8, further comprising a sixth conductive structure perpendicularly positioned between the first conductive structure and the third conductive structure. Claim 14 A method for manufacturing a multi-die bridge assembly, comprising the steps of: providing a bridge component having an upper side above a lower side and side walls between the upper side and the lower side, wherein the bridge component has through silicon vias (TSVs) within it; forming a first via spaced laterally from the side wall of the bridge component; forming a second via below the lower side of the bridge component, wherein one of the TSVs of the bridge component overlaps perpendicularly with the second via and is coupled to the second via; forming a third via below the first via and coupled to the first via such that the first via overlaps perpendicularly with the third via, wherein the third via is spaced laterally from the second via and the third via has a width greater than the width of the second via; a first trace below the second via and coupled to the second via, and a trace below the third via and coupled to the third via A step of forming a second trace - said second trace is spaced laterally from the first trace -; a step of forming a fourth via located below the first trace and coupled to the first trace - said fourth via does not overlap perpendicularly with the second via -; a step of forming a fifth via located below the second trace and coupled to the second trace - said fifth via overlaps perpendicularly with the third via -; a step of coupling a first integrated circuit (IC) die to the upper side of the bridge component and to the first via - said first IC die is perpendicularly above the bridge component and the first via, and said first IC die has a first thickness -;A method comprising the step of coupling a second IC die to the upper side of the bridge component, wherein the second IC die is vertically positioned above the bridge component and spaced laterally from the first IC die, and the second IC die has a second thickness smaller than the first thickness; and the step of forming an encapsulant on the second IC die.; Claim 15 In paragraph 14, the method wherein the encapsulating agent is located between the second IC die and the first IC die. Claim 16 In paragraph 14, the method, wherein the encapsulating agent is on the first IC die. Claim 17 In paragraph 14, the method wherein the encapsulating agent is located along the sides of the first IC die. Claim 18 In paragraph 14, the method wherein the first via has a bottom surface at a level above the bottom side of the bridge component. Claim 19 A method according to claim 14, further comprising the step of forming a sixth via vertically between the first via and the third via. Claim 20 A method according to claim 14, further comprising the step of forming a sixth via transversely between the first via and the bridge component.

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