Adaptive power modes using memory usage patterns

Abstract

Methods, systems, and devices include receiving a power-down notification by the memory subsystem. In response to receiving the power-down notification, a memory usage pattern for the memory subsystem is retrieved. A power mode is selected using the current time and the memory usage pattern. The selected power mode is enabled.

Description

Technology Field

[0001] The present disclosure generally relates to managing power consumption in a memory subsystem, and more specifically to adaptive power modes that use memory usage patterns. Background Technology

[0002] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may use the memory subsystem to store data in memory devices and to retrieve data from memory devices. Brief explanation of the drawing

[0003] The present disclosure will be more fully understood from the accompanying drawings of specific details for carrying out the invention provided below and various embodiments of the present disclosure. However, the drawings are not intended to limit the present disclosure to specific embodiments, but are merely for illustrative and illustrative purposes. FIG. 1 illustrates an exemplary computing system including a memory subsystem according to some embodiments of the present disclosure. FIG. 2 illustrates a graph of exemplary memory usage patterns for a memory subsystem used to select a power mode according to some embodiments of the present disclosure. FIG. 3 is a flowchart of an exemplary method for selecting a power mode using memory usage patterns according to some embodiments of the present disclosure. FIG. 4 is another flowchart of an exemplary method for selecting a power mode using memory usage patterns according to some embodiments of the present disclosure. FIG. 5 is a block diagram of an exemplary computer system in which embodiments of the present disclosure can be operated. Specific details for implementing the invention

[0004] Aspects of the present disclosure relate to adaptive power modes that use memory usage patterns in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices and memory modules are described below in connection with FIG. 1. Generally, a host system may utilize a memory subsystem comprising one or more components, such as memory devices that store data. The host system may provide data to be stored in the memory subsystem and may request data to be retrieved from the memory subsystem.

[0005] A memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. An example of a non-volatile memory device is a NAND (negative-and) memory device. Other examples of non-volatile memory devices are described below in relation to Fig. 1. The dies within the package may be assigned to one or more channels for communicating with a memory subsystem controller. Each die may consist of one or more planes. The planes may be grouped into logical units identified by a LUN (logical unit number). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks, which are groups of memory cells for storing data. A cell is an electronic circuit that stores information.

[0006] Depending on the cell type, a cell can store one or more bits of binary information and has various logical states corresponding to the number of bits stored. Logical states can be represented by binary values, such as "0" and "1", or combinations of these values. There are various types of cells, such as single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs). For example, an SLC can store 1 bit of information and has two logical states, while a QLC can store 16 bits of information and has four logical states.

[0007] In conventional memory systems, memory devices use different power modes for different activities. For example, memory devices use higher power modes when performing memory operations than when idle (e.g., when not performing memory operations). Memory devices in lower power modes consume less power than memory devices in higher power modes, at the cost of taking longer to perform memory operations when the memory subsystem receives memory commands. For example, a memory device that is powered off when the memory subsystem receives a memory command will take longer to reach a state ready to complete the memory command than a memory device that is in standby mode when the memory subsystem receives the command. Conventional memory systems select power modes based on the components of the memory system to attempt to optimize power consumption, boot time, and other related variables. For example, memory systems with slower boot-up times will use standby mode more frequently than memory systems with faster boot-up times. Similarly, memory systems more sensitive to power consumption (e.g., memory systems for battery-operated devices) will be powered off more frequently than memory systems not sensitive to power consumption (e.g., desktop computers). However, the actual use of these memory systems does not always match idealized or expected usage. This results in inefficiencies regarding power consumption, boot times, and other related variables.

[0008] Aspects of the present disclosure address the aforementioned and other defects by selecting a power mode based on memory usage patterns for a memory subsystem. For example, the memory subsystem tracks the times of received memory commands to determine memory usage patterns for memory devices. The memory subsystem uses memory usage patterns to select an optimal power mode for the current time based on the expected activity of the memory devices. For example, the memory subsystem reduces power consumption by shutting off memory devices during times associated with non-use. Similarly, the memory subsystem reduces the time required for the system to be ready (e.g., boot-up time) and reduces power consumption associated with powering on memory devices by placing memory devices in standby mode during times associated with higher usage. Thus, the memory subsystem optimizes power consumption, boot-up time, and other variables by using a power mode that depends on the tracked memory usage patterns for memory devices.

[0009] FIG. 1 illustrates an exemplary computing system (100) comprising a memory subsystem (110) according to some embodiments of the present disclosure. The memory subsystem (110) may include media such as one or more volatile memory devices (e.g., memory device (140)), one or more non-volatile memory devices (e.g., memory device (130)), or a combination thereof.

[0010] The memory subsystem (110) may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory modules (NVDIMM).

[0011] The computing system (100) may include computing devices such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other means of transportation), an Internet of Things (IoT) capable device, an embedded computer (e.g., one included in a vehicle, industrial equipment, or a network commercial device), or any other computing device including a memory and processing device.

[0012] A computing system (100) includes a host system (120) coupled to one or more memory subsystems (110). In some embodiments, the host system (120) is coupled to different types of memory subsystems (110). FIG. 1 illustrates an example of a host system (120) coupled to one memory subsystem (110). As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without components interposed), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0013] The host system (120) may include processing devices such as a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe (peripheral component interconnect express) controller, a SATA (serial advanced technology attachment) controller). The host system (120) uses a memory subsystem (110) and, for example, writes data to the memory subsystem (110) and reads data from the memory subsystem (110).

[0014] A host system (120) may be coupled to a memory subsystem (110) via a physical host interface. Examples of physical host interfaces include, but are not limited to, a SATA interface including an mSATA (mini-SATA) interface, a PCIe interface including an mPCIE (mini PCIe) interface, a Non-Volatile Memory Express (NVMe) interface, a universal serial bus (USB) interface, a Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Advanced Host Controller (AHCI) interface, an Open NAND Flash Interface (ONFI) interface, a Double Data Rate (DDR) interface, a Low Power Double Data Rate (LPDDR) interface, any other interface, and / or combinations of these interfaces. A physical host interface may be used to transmit data between the host system (120) and the memory subsystem (110). The host system (120) may additionally use an NVMe interface to access components (e.g., memory devices (130 and 140)) when the memory subsystem (110) is coupled to the host system (120) by a PCIe interface. The physical host interface may provide an interface for transmitting control, address, data, and other signals between the memory subsystem (110) and the host system (120). FIG. 1 illustrates a memory subsystem (110) as an example.Generally, the host system (120) can access multiple memory subsystems through the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0015] The memory devices (130 and 140) may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device (140)) may be, but are not limited to, RAM (random-access memory), such as DRAM (dynamic random-access memory), SDRAM (synchronous dynamic random-access memory), VRAM (video random-access memory), and cache memory.

[0016] Some examples of non-volatile memory devices (e.g., memory device (130)) include NAND (negative-and) type flash memory devices and write-in-place type memory devices, such as a 3D cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance, together with a stackable cross-grid data access array. Additionally, unlike many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, such that the non-volatile memory cells can be programmed without the non-volatile memory cells being erased beforehand. NAND type flash memory includes, for example, 2D NAND and 3D NAND.

[0017] Although nonvolatile memory devices such as NAND type memory (e.g., 2D NAND, 3D NAND) and 3D cross-point arrays of nonvolatile memory cells are described, the memory device (130) may be based on any other type of nonvolatile memory, such as ROM (read-only memory), PCM (phase change memory), magnetic selection memory, other chalcogenide-based memories, FeTRAM (ferroelectric transistor random-access memory), FeRAM (ferroelectric random-access memory), MRAM (magneto random-access memory), STT (Spin Transfer Torque)-MRAM, NRAM (nano-RAM), SONOS (silicon-oxide-nitride-oxide-silicon) memory, CBRAM (conductive bridging RAM), RRAM (resistive random-access memory), OxRAM (oxide-based RRAM), NOR (negative-or) flash memory, and EPROM (erasable programmable read-only memory), including EEPROM (electrically erasable programmable read-only memory). there is.

[0018] A memory subsystem controller (115) (or controller (115) for simplification) may communicate with memory devices (130) to perform operations such as reading data, writing data, or erasing data from memory devices (130) and other such operations (e.g., in response to commands scheduled on a command bus by the controller (115)). The memory subsystem controller (115) may include hardware such as one or more integrated circuits and / or individual components, buffer memory, or a combination thereof. The hardware may include a digital circuit section having dedicated (i.e., hard-coded) logic for performing the operations described herein. The buffer memory of the subsystem controller (115) may include any of the volatile or non-volatile memory types mentioned above, including combinations thereof. The memory subsystem controller (115) may be a microcontroller, a special purpose logic circuit (e.g., FPGA (field programmable gate array), ASIC (application specific integrated circuit), etc.), or other suitable processor.

[0019] The memory subsystem controller (115) may include a processing device (117) (processor) configured to execute instructions stored in the memory subsystem (110) (e.g., stored in local memory (119)). In some examples, the local memory (119) of the memory subsystem controller (115) includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem (110), including handling communication between the memory subsystem (110) and the host system (120).

[0020] In some embodiments, the local memory (119) may include memory registers that store memory pointers, fetched data, etc. The local memory (119) may also include read-only memory (ROM) for storing microcode. Although the exemplary memory subsystem (110) in FIG. 1 is illustrated as including a memory subsystem controller (115), in other embodiments of the present disclosure, the memory subsystem (110) may not include a memory subsystem controller (115) and instead rely on external control (e.g., provided by an external host, or by a processing device or controller separate from the memory subsystem (110).

[0021] Generally, the memory subsystem controller (115) may receive commands or operations from the host system (120) and may convert the commands or operations into instructions or appropriate commands to achieve desired access to memory devices (e.g., memory devices (130 and / or 140)). The memory subsystem controller (115) may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translation between a logical address (e.g., logical block address (LBA) and / or namespace) associated with memory devices (memory devices (130 and / or 140)) and a physical address (e.g., physical block address). The memory subsystem controller (115) may further include a host interface circuit for communicating with the host system (120) via a physical host interface. The host interface circuit is the host Commands received from the system can be converted into command instructions for accessing memory devices (e.g., memory devices (130 and / or 140)), as well as responses associated with memory devices can be converted into information for the host system (120).

[0022] The memory subsystem (110) may also include additional circuitry or components not exemplified. In some embodiments, the memory subsystem (110) may include an address circuitry (e.g., row decoder and column decoder) and a cache or buffer (e.g., DRAM) capable of receiving an address from a memory subsystem controller (115) and decoding the address to access memory devices (e.g., memory devices (130 and / or 140)).

[0023] In some embodiments, memory devices (e.g., memory devices (130 and / or 140)) include local media controllers (135) that operate with a memory subsystem controller (115) to perform operations on one or more memory cells of the memory devices (e.g., memory devices (130 and / or 140)). An external controller (e.g., memory subsystem controller (115)) may manage the memory devices externally (e.g., perform media management operations on the memory devices (130 and / or 140)). In some embodiments, the memory device (e.g., memory device (130)) is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller (135)) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0024] The memory subsystem (110) includes an adaptive power cycling component (113) that selects a power mode for the memory subsystem (110) using memory usage patterns. In some embodiments, a controller (115) includes at least a portion of the adaptive power cycling component (113). For example, the controller (115) may include a processing device (117) configured to execute instructions stored in local memory (119) for performing the operations described herein. In some embodiments, the adaptive power cycling component (113) is part of a host system (120), an application, or an operating system.

[0025] The adaptive power cycling component (113) monitors memory usage patterns and uses the memory usage patterns to select a power mode for the memory subsystem. Additional details regarding the operation of the adaptive power cycling component (113) are described below.

[0026] FIG. 2 illustrates a graph of exemplary memory usage patterns for a memory subsystem according to some embodiments of the present disclosure. An adaptive power cycling component (113) tracks received memory commands to determine a usage pattern, such as a weekday usage pattern (210) and / or a weekend usage pattern (215), as illustrated in the memory usage pattern graph (205). For example, a host system (e.g., the host system (120) of FIG. 1) transmits memory commands to a memory subsystem (e.g., the memory subsystem (110) of FIG. 1). Examples of memory commands may include read, write, and erase memory commands. While processing each command, the memory subsystem stores the received memory commands in the command queue of the memory subsystem, and the adaptive power cycling component (113) tracks the timestamps of the memory commands in the command queue. For example, the memory subsystem temporarily stores received commands containing timestamps in local memory (e.g., local memory (119) of FIG. 1), and the adaptive power cycling component (113) reads the timestamps of the received commands from local memory to generate and store a memory usage pattern.

[0027] In some embodiments, the adaptive power cycling component (113) updates a stored count for received memory commands based on the timestamps of the received memory commands. For example, the adaptive power cycling component (113) maintains a count for the number of memory commands received in each hourly block of each day, such as between 8 a.m. and 9 a.m. on Monday, in local memory (e.g., local memory (119)). In response to the memory subsystem (110) receiving a memory command at 8:35 a.m. on Monday, the adaptive power cycling component (113) updates the stored count by adding 1. In these embodiments, the adaptive power cycling component (113) can track counts for different subdivisions of time. For example, the adaptive power cycling component (113) can track counts for 15-minute intervals, 30-minute intervals, 1-hour intervals, etc. Additionally, in these embodiments, the adaptive power cycling component (113) can track counts for different days of the week.

[0028] FIG. 2 illustrates a memory usage pattern graph (205) showing X marks for timestamps of memory commands tracked by an adaptive power cycling component (113). As illustrated in the embodiment illustrated in FIG. 2, all tracked memory commands received during the week (e.g., Monday through Friday) are received between the hours of 8 a.m. and 6 p.m. Accordingly, in this embodiment, the adaptive power cycling component (113) determines a weekday usage pattern (210) using the timestamps of the received memory commands (e.g., X marks on the memory usage pattern graph (205)). For example, the adaptive power cycling component (113) determines a weekday usage pattern (210) having peak times (220) between 8 a.m. and 6 p.m. because the timestamps of all received commands fall within the peak time (220). In some embodiments, the adaptive power cycling component (113) determines a weekday usage pattern (210) having a peak time (220) in response to determining that the count of memory commands during the week between the times of 8 a.m. and 6 p.m. satisfies a threshold. For example, the peak time threshold may be the number of commands received at a given interval, and the adaptive power cycling component (113) may use the threshold to identify one or more intervals on a given day of the week having activity levels that reach or exceed the threshold.

[0029] In some embodiments, the adaptive power cycling component (113) determines different memory usage patterns for different days of the week. For example, as illustrated in FIG. 2, most of the tracked memory commands received during the weekend (e.g., Saturday and Sunday) are received between the hours of 6 pm and 8 pm. In this embodiment, the adaptive power cycling component (113) determines a weekend usage pattern (215) having a peak time (225) between 6 pm and 8 pm because most of all received commands are within the peak time (225). In some embodiments, the adaptive power cycling component (113) determines the peak time based on the number of commands received during a time interval satisfying a threshold. For example, the adaptive power cycling component (113) determines a weekend usage pattern (215) having a peak time (225) based on receiving more than ten memory commands in a two-hour interval.

[0030] In some embodiments, the adaptive power cycling component (113) updates the memory usage pattern. For example, the memory subsystem (110) receives new memory commands from the host system (120), and the adaptive power cycling component (113) updates the stored counts based on the timestamps of the new memory commands and updates the memory usage pattern based on the updated counts. In some embodiments, the adaptive power cycling component (113) clears the counts for the received memory commands after a threshold amount of time. For example, the adaptive power cycling component (113) clears the counts after a week so that the memory usage pattern reflects the current memory usage.

[0031] FIG. 3 is a flowchart of an exemplary method (300) for selecting a power mode using memory usage patterns according to some embodiments of the present disclosure. The method (300) may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of the device, integrated circuit, etc.), software (e.g., instructions operated or executed on the processing device), or a combination thereof. In some embodiments, the method (300) is performed by the adaptive power cycling component (113) of FIG. 1. Although illustrated in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Accordingly, not all processes are required in all embodiments. Other process flows are also possible.

[0032] In operation 305, the processing device determines whether to power down. For example, the adaptive power cycling component (113) monitors the voltage supply from the host system (120) and, in response to the determination that the voltage supply satisfies a threshold, determines that the memory subsystem (110) is powering down. In some embodiments, the adaptive power cycling component (113) determines that a specific memory device is powering down. For example, the adaptive power cycling component (113) determines that the memory device (140) is powering down by monitoring the voltage supply to the memory device (140). In some embodiments, the processing device determines to power down based on memory usage patterns. For example, the adaptive power cycling component (113) determines that the peak time (220) has ended and there is a possibility that there are no more memory commands. In some embodiments, rather than deciding to power down, the processing device decides to power up. For example, the adaptive power cycling component (113) decides to power up based on a memory usage pattern indicating that the peak time (220) is starting. In some embodiments, the adaptive power cycling component (113) decides to power down in response to receiving a power down notification from the host system (120). If the processing device decides to power down, the method (300) proceeds to operation (310). If the processing device decides not to power down, the method (300) returns to operation (305) to wait for a trigger for power down or change other power modes.

[0033] In operation (310), the processing device retrieves a memory usage pattern. For example, the adaptive power cycling component (113) retrieves a memory usage pattern from local memory (119). In some embodiments, the processing device retrieves a memory usage pattern based on the current time and / or day of the week. For example, the adaptive power cycling component (113) retrieves a weekday usage pattern (210) if the current time is a weekday, but retrieves a weekend usage pattern (215) if the current time is a weekend. In some embodiments, the processing device determines a memory usage pattern. For example, the adaptive power cycling component (113) determines a memory usage pattern as described above with reference to FIG. 2.

[0034] In operation (315), the processing device selects a power mode using a memory usage pattern. For example, the adaptive power cycling component (113) selects a power mode based on the current time and the retrieved memory usage pattern. In some embodiments, the selected power mode is one of a power-off mode, a low power mode, and an active idle mode. For example, the adaptive power cycling component (113) selects a power mode by comparing a stored count of the number of received memory commands in the memory usage pattern with thresholds for different power modes. For example, if the count is less than one command, the adaptive power cycling component (113) selects a power-off power mode; if the count is between one and seven memory commands, the adaptive power cycling component (113) selects a low power mode; and if the count is greater than seven, the adaptive power cycling component (113) selects an active idle power mode.

[0035] In some embodiments, the adaptive power cycling component (113) uses different thresholds depending on the day of the week or week. For example, the adaptive power cycling component (113) uses different thresholds for lower power mode and active idle mode during weekdays than on weekends. In some embodiments, the adaptive power cycling component (113) uses different thresholds for lower power mode and active idle mode based on time. For example, the adaptive power cycling component (113) uses one set of thresholds between the hours of 7 a.m. and 12 p.m. and another set of thresholds between 12 p.m. and 8 p.m.

[0036] In some embodiments, during the most active peak times, the adaptive power cycling component (113) selects an active idle power mode so that the memory subsystem (110) is active and waits for memory commands from the host system (120). Continuing from the example above, the adaptive power cycling component (113) selects an active idle power mode when the stored memory command count is greater than 7. Active idle is a power mode that has higher power consumption than the power off mode and low power mode, but causes the memory subsystem (110) to start processing received memory commands with a shorter boot time than both the power off mode and low power mode. Thus, the adaptive power cycling component (113) selects an active idle mode for times when the adaptive power cycling component (113) expects high usage. For example, in the embodiment illustrated in FIG. 2, the adaptive power cycling component (113) selects an active idle mode during peak time (220) and peak time (225).

[0037] In some embodiments, during intermediate peak times, the adaptive power cycling component (113) selects a low power mode so that the memory subsystem (110) operates at a standby current (ISB) that is lower than the standby current provided during active idle mode but higher than the current provided during power off mode. Continuing with the example above, the adaptive power cycling component (113) selects a lower power mode when the stored memory command count is less than 7 but greater than 0. Thus, the low power mode is a power mode that has power consumption greater than the power off mode and less than the active idle mode, but has a boot time that is smaller than the power off mode and greater than the active idle mode. Thus, the adaptive power cycling component (113) selects a low power mode for times when the adaptive power cycling component (113) anticipates potential use but does not anticipate high use. For example, in the embodiment illustrated in FIG. 2, the adaptive power cycling component (113) selects a low power mode on weekends between 8 a.m. and 10 a.m. and between 3 p.m. and 4 p.m., because the count of memory commands received during those times is greater than 0 but less than 7.

[0038] In some embodiments, when not during peak hours, the adaptive power cycling component (113) selects a power off mode to turn off the supply voltage (VCC) of the memory subsystem. For example, the adaptive power cycling component (113) selects a power off mode when the stored memory command count is 0. Thus, the power off mode is a power mode that has less power consumption than both the low power mode and the active idle mode, but has a slower boot time than both the low power mode and the active idle mode. Thus, the adaptive power cycling component (113) selects a low power mode during times when activity is not expected. For example, in the embodiment illustrated in FIG. 2, the adaptive power cycling component (113) selects a power off mode between the hours of 8 pm and 8 am.

[0039] Although illustrated with only three power mode options, the method (300) may use various different power mode options having different expected power consumptions, boot-up times, and similar variables. In these embodiments, the adaptive power cycling component (113) selects a power mode based on the expected use of the memory subsystem (110) using a memory usage pattern.

[0040] In some embodiments, the processing device selects a power mode based on the physical memory devices. For example, some memory devices have higher power consumption than other memory devices when in low power or active idle power mode. Accordingly, in these embodiments, the adaptive power cycling component (113) selects an appropriate power mode based on the memory devices (e.g., power consumption characteristics of the memory devices). For example, in the embodiment illustrated in FIG. 2, the adaptive power cycling component (113) selects a power-off power mode for the SSD memory device between 8 a.m. and 10 a.m. on the weekend, but selects a low power mode for the MNAND memory device during the same time interval because the power leakage during the low power mode for the SSD memory device is significantly higher than that for the MNAND device. In some embodiments, an identifier or other indication of power consumption for the physical memory device is predetermined and stored in local memory (e.g., local memory (119) in FIG. 1). In these embodiments, the adaptive power cycling component (113) can retrieve the identifier from local memory when selecting a power mode.

[0041] If the processing device selects the power-off power mode, the method (300) proceeds to operation (320). If the processing device selects the low power mode, the method (300) proceeds to operation (325). If the processing device selects the active idle power mode, the method (300) proceeds to operation (330).

[0042] In operation (320), the processing device turns off the supply voltage. For example, the adaptive power cycling component (113) causes the memory subsystem (110) to turn off the supply voltage. In some embodiments, the adaptive power cycling component (113) causes the memory subsystem (110) to turn off the supply voltage for the memory device. For example, the adaptive power cycling component (113) causes the memory subsystem (110) to turn off the supply voltage for the memory device (140). In some embodiments, the adaptive power cycling component (113) causes the memory subsystem (110) to turn off the supply voltage for both the application-specific integrated circuit (ASIC) and the NAND memory device. In some embodiments, the memory subsystem (110) turns off the supply voltage (VCC) and the signal supply voltage (VCCQ).

[0043] In operation (325), the processing device enables low standby current. For example, the adaptive power cycling component (113) causes the memory subsystem (110) to operate using low standby current. In some embodiments, the adaptive power cycling component (113) causes the memory subsystem (110) to turn off the supply voltage for the NAND memory device but keep the supply voltage for the ASIC on. In some embodiments, the memory subsystem (110) turns off the supply voltage (VCC) but continues to provide the signal supply voltage (VCCQ) to provide low standby current to the memory device. In these embodiments where the memory device (140) is an MNAND device, the memory subsystem (110) turns off the supply voltage (VCC) but continues to provide the signal supply voltage (VCCQ) to prepare the memory device (140) to exit low power mode. In other embodiments, such as when the memory device (140) is an SSD device, the memory subsystem (110) turns off both the supply voltage (VCC) and the signal supply voltage (VCCQ). In some embodiments, the memory subsystem (110) provides a lower supply voltage to the memory device (140). For example, the power management circuit of the memory subsystem (110) provides a supply voltage (VCC) that is smaller than the supply voltage (VCC) provided during active idle mode.

[0044] In operation (330), the processing device enables standby current. For example, the adaptive power cycling component (113) causes the memory subsystem (110) to operate using standby current until the memory subsystem (110) receives a memory command. In some embodiments, the memory subsystem (110) provides both the supply voltage (VCC) and the signal supply voltage (VCCQ) during the active idle mode. The adaptive power cycling component (113) causes the memory subsystem (110) to provide a higher standby current than the lower standby current provided in the low power mode.

[0045] FIG. 4 is another flowchart of an exemplary method (400) for selecting a power mode using memory usage patterns according to some embodiments of the present disclosure. The method (400) may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of the device, integrated circuit, etc.), software (e.g., instructions operated or executed on the processing device), or a combination thereof. In some embodiments, the method (400) is performed by the adaptive power cycling component (113) of FIG. 1. Although illustrated in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Accordingly, not all processes are required in all embodiments. Other process flows are also possible.

[0046] In operation 405, the processing device receives a power-down notification. For example, the memory subsystem (110) receives a power-down notification from the host system (120). In some embodiments, the adaptive power cycling component (113) determines that the memory subsystem (110) is powering down by monitoring the voltage supply from the host system (120) and determines that the memory subsystem (110) is powering down in response to detecting that the voltage supply satisfies a threshold value. In some embodiments, the adaptive power cycling component (113) determines that a specific memory device is powering down. For example, the adaptive power cycling component (113) determines that the memory device (140) is powering down by monitoring the voltage supply to the memory device (140). Further details regarding receiving the power-down notification are discussed with reference to FIG. 3.

[0047] In operation (410), the processing device searches for a memory usage pattern in response to receiving a power down notification. For example, the adaptive power cycling component (113) searches for a memory usage pattern stored in local memory (119) in response to receiving a power down notification. In some embodiments, the adaptive power cycling component (113) determines the memory usage pattern by maintaining a stored count of memory commands received per interval based on timestamps for these memory commands. For example, the adaptive power cycling component (113) determines memory usage patterns as described above with reference to FIGS. 2 and FIGS. 3.

[0048] In operation (415), the processing device selects a power mode using the current time and memory usage pattern. For example, the adaptive power cycling component (113) retrieves a count from the memory usage pattern for the current time interval and the current day of the week. Then, the adaptive power cycling component (113) selects a power mode in response to whether the count satisfies or does not satisfy a threshold count. Returning to the examples above, the adaptive power cycling component (113) selects a power mode of power down when the count is less than 1, a power mode of low power when the count is between 1 and 7, and a power mode of active idle when the count is greater than 7.

[0049] In operation (420), the processing device enables the selected power mode. For example, the adaptive power cycling component (113) sets the supply voltage, signal supply voltage, and / or standby current based on the selected power mode. Further details regarding enabling the selected power mode are discussed with reference to FIG. 3.

[0050] FIG. 5 illustrates an exemplary machine of a computer system (500) on which a set of instructions for causing the machine to perform one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system (500) may correspond to a host system (e.g., the host system (120) of FIG. 1) that includes, is coupled to, or utilizes a memory subsystem (e.g., the memory subsystem (110) of FIG. 1) or may be used to perform the operations of a controller (e.g., to run an operating system to perform operations corresponding to the adaptive power cycling component (113) of FIG. 1). In alternative embodiments, the machine may be connected to other machines (e.g., networked) via a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0051] A machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, smart device, web device, server, network router, switch or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is exemplified, the term “machine” should also be taken to include any group of machines that execute a set of instructions (or a number of sets) individually or jointly for performing any one or more of the methodologies discussed herein.

[0052] An exemplary computer system (500) includes a processing device (502) communicating with each other via a bus (530), a main memory (504) (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory (506) (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system (518).

[0053] The processing device (502) represents one or more general-purpose processing devices, such as a microprocessor or a central processing unit. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device (502) may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), or a network processor. The processing device (502) is configured to execute instructions (526) for performing the operations and steps discussed herein. The computer system (500) may further include a network interface device (508) for communicating through a network (520).

[0054] The data storage system (518) may include a machine-readable storage medium (524) (also known as a computer-readable medium) in which one or more instruction sets (526) or software implementing any one or more of the methodologies or functions described herein are stored. The instructions (526) constituting the machine-readable storage medium may also reside in the processing device (502) and / or the main memory (504) in whole or at least partially during execution by the computer system (500), the main memory (504), and the processing device (502). The machine-readable storage medium (524), the data storage system (518), and / or the main memory (504) may correspond to the memory subsystem (10) of FIG. 1.

[0055] In one embodiment, the instructions (526) include instructions for implementing a function corresponding to an adaptive power cycling component (e.g., the adaptive power cycling component (113) of FIG. 1). Although the machine-readable storage medium (524) is depicted as a single medium in an exemplary embodiment, the term “machine-readable storage medium” should be taken to include a single medium or multiple media storing sets of one or more instructions (e.g., instructions (526)). The term “machine-readable storage medium” should also be taken to include any medium capable of storing or encoding a set of instructions for execution by a machine and enabling the machine to perform one or more of the methodologies of the present disclosure. Accordingly, the term “machine-readable storage medium” should be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0056] Some parts of the specific details for carrying out the prior art invention have been presented in relation to algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are methods used by those skilled in the field of data processing to most effectively convey the details of their work to other skilled in the field. An algorithm is conceived herein, and generally, as a self-consistent sequence of operations that yields a desired result. The operations are those that require physical manipulation of physical quantities. These quantities generally, though not necessarily, take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been found that, primarily for reasons of general usage, it is sometimes convenient to represent these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0057] However, it should be noted that all such and similar terms must be associated with appropriate physical quantities and are merely convenient labels applied to such quantities. The present disclosure may describe operations and procedures of a computer system, or a similar electronic computing device that manipulates data represented as physical (electronic) quantities within the registers and memories of a computer system, and converts it into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0058] Additionally, the present disclosure relates to an apparatus for performing the operations described herein. Such an apparatus may include a general-purpose computer that may be specially configured for intended purposes or which is selectively enabled or reconfigured by a computer program stored in the computer. For example, a computer system or other data processing system, such as a controller (115), may perform computer implementation methods (300 and 400) in response to its processor executing a computer program (e.g., a sequence of instructions) contained in memory or other non-transient machine-readable storage media. Such computer program may be stored in a computer-readable storage media, such as but not limited to floppy disks, optical disks, CD-ROMs, and magneto-optical disks coupled to a computer system bus, read-only memory (ROM), random-access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of disk including any type of medium suitable for storing electronic instructions.

[0059] The algorithms and displays presented in this specification are not inherently related to any specific computer or other device. Various general-purpose systems may be used with programs according to the teachings in this specification, or it may be found convenient to configure a device more specialized to perform the methods. The structures of such various systems will appear as presented in the description below. Furthermore, this disclosure is not described by reference to any specific programming language. It will be understood that various programming languages ​​may be used to implement the teachings of this disclosure as described in this specification.

[0060] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium storing instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (computer)-readable storage medium, such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

[0061] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made without departing from the broader spirit and scope of the embodiments of the present disclosure, as set forth in the following claims. Accordingly, the present specification and drawings should be regarded as exemplary rather than having a limiting meaning.

Claims

Claim 1 A method comprising: receiving a power down notification by a memory subsystem; searching for a memory usage pattern for the memory subsystem in response to receiving the power down notification; selecting one of a plurality of power modes using a current time and the memory usage pattern; and enabling the selected power mode. Claim 2 A method according to claim 1, further comprising the step of determining the memory usage pattern using timestamps for a plurality of commands received by the memory subsystem. Claim 3 A method according to claim 2, further comprising: receiving a new command by the memory subsystem; and updating the memory usage pattern based on the new command in response to receiving the new command. Claim 4 A method according to claim 1, wherein the memory usage pattern includes a plurality of memory usage patterns for different days, and the step of selecting the power mode is additionally based on the current day of the week. Claim 5 A method according to claim 1, wherein the plurality of power modes include power modes for different operating currents, and the step of enabling the selected power mode includes the step of causing the memory subsystem to operate using the operating current associated with the selected power mode. Claim 6 A method according to claim 1, wherein the step of selecting the power mode includes determining that the memory subsystem is in a peak time based on the memory usage pattern and the current time, and the step of enabling the selected power mode includes placing the memory subsystem in a standby state in response to determining that the memory subsystem is in a peak time. Claim 7 A method according to claim 1, wherein the step of selecting the power mode includes the step of determining that the memory subsystem is not at a peak time based on the memory usage pattern and the current time, and the step of enabling the selected power mode includes the step of shutting down the memory subsystem in response to the determination that the memory subsystem is not at a peak time. Claim 8 A non-transient computer-readable storage medium comprising instructions, wherein, when the instructions are executed by a processing device, the processing device receives a power-down notification by a memory subsystem; in response to receiving the power-down notification, searches for a memory usage pattern for the memory subsystem; selects one of a plurality of power modes using a current time and the memory usage pattern; and enables the selected power mode. Claim 9 In paragraph 8, the processing device also determines the memory usage pattern using timestamps for a plurality of commands received by the memory subsystem, a non-transient computer-readable storage medium. Claim 10 In claim 9, the processing device also receives a new command by the memory subsystem; and updates the memory usage pattern based on the new command in response to receiving the new command, a non-transient computer-readable storage medium. Claim 11 In paragraph 8, the memory usage pattern comprises a plurality of memory usage patterns for different days, and the selection of the power mode is additionally based on the current day of the week, a non-transient computer-readable storage medium. Claim 12 A non-transient computer-readable storage medium according to claim 8, wherein the plurality of power modes include power modes for different operating currents, and enabling the selected power mode includes causing the memory subsystem to operate using the operating current associated with the selected power mode. Claim 13 A non-transient computer-readable storage medium, wherein, in claim 8, selecting the power mode includes determining that the memory subsystem is in a peak time based on the memory usage pattern and the current time, and enabling the selected power mode includes placing the memory subsystem in a standby state in response to determining that the memory subsystem is in a peak time. Claim 14 A non-transient computer-readable storage medium, wherein, in claim 8, selecting the power mode includes determining that the memory subsystem is not at a peak time based on the memory usage pattern and the current time, and enabling the selected power mode includes shutting down the memory subsystem in response to determining that the memory subsystem is not at a peak time. Claim 15 A system comprising: a plurality of memory devices; and a processing device operably coupled to the plurality of memory devices, wherein the processing device is Determining the memory usage pattern for the memory subsystem using timestamps for a plurality of commands received by the memory subsystem. Receives a power down notification by the memory subsystem; In response to receiving the above power down notification, search for memory usage patterns for the memory subsystem; Select one power mode among a plurality of power modes using the current time and the memory usage pattern above; and A system that enables the above-mentioned selected power mode. Claim 16 In paragraph 15, the processing device also receives a new command by the memory subsystem; and in response to receiving the new command, updates the memory usage pattern based on the new command, a system. Claim 17 In paragraph 15, the above memory usage pattern includes multiple memory usage patterns for different days, and the power mode selection is additionally based on the current day of the week, the system. Claim 18 A system according to claim 15, wherein the plurality of power modes include power modes for different operating currents, and enabling the selected power mode includes causing the memory subsystem to operate using the operating current associated with the selected power mode. Claim 19 A system according to claim 15, wherein selecting the power mode includes determining that the memory subsystem is at a peak time based on the memory usage pattern and the current time, and enabling the selected power mode includes placing the memory subsystem in a standby state in response to determining that the memory subsystem is at a peak time. Claim 20 A system according to claim 15, wherein selecting the power mode comprises determining that the memory subsystem is not at a peak time based on the memory usage pattern and the current time, and enabling the selected power mode comprises shutting down the memory subsystem in response to determining that the memory subsystem is not at a peak time.

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