Display panel

Abstract

A display panel according to one embodiment of the present invention comprises: a first initialization voltage line extending in a first direction and transmitting a first initialization voltage in the display area; a second initialization voltage line extending in the first direction and transmitting a second initialization voltage in the display area; a first transistor connected to the first initialization voltage line and a pixel electrode of a first light-emitting diode emitting a first color, which is disposed in a first pixel area of ​​the display area; and a second transistor connected to the second initialization voltage line and a pixel electrode of a second light-emitting diode emitting a second color, which is disposed in a second pixel area adjacent to the first pixel area.

Description

Technology Field

[0001] The present invention relates to a display panel and a display device equipped with the same, and more specifically, to a display panel comprising pixels that emit different colors and a display device equipped with the same. Background Technology

[0002] Generally, an organic light-emitting display device comprises a plurality of pixels including organic light-emitting diodes and thin-film transistors. The (sub)pixels emitting different colors may have different electrical characteristics depending on the light-emitting layer constituting the organic light-emitting diode. The problem to be solved

[0003] The embodiments of the present invention aim to provide a display panel with improved image quality characteristics and a display device equipped therewith by compensating for the electrical characteristics of organic light-emitting diodes for each pixel emitting different colors. However, this objective is exemplary and does not limit the scope of the present invention. means of solving the problem

[0004] A display panel according to one embodiment of the present invention, comprising a display area and a peripheral area outside the display area, comprises: a first initialization voltage line extending in a first direction and transmitting a first initialization voltage in the display area; a second initialization voltage line extending in the first direction and transmitting a second initialization voltage in the display area; and a first transistor disposed in a first pixel area of ​​the display area and comprising a pixel electrode of a first light-emitting diode emitting a first color, a first semiconductor layer connected to the first initialization voltage line, and a first gate electrode. and a second transistor comprising a pixel electrode of a second light-emitting diode that emits a second color and is disposed in a second pixel region adjacent to the first pixel region, and a second semiconductor layer and a second gate electrode connected to the second initialization voltage line; wherein the first initialization voltage line is in direct contact with the first semiconductor layer and the second initialization voltage line is connected to the second semiconductor layer through a connecting electrode.

[0005] In one embodiment, the first initialization voltage line and the second initialization voltage line may be placed on different layers.

[0006] In one embodiment, the first transistor and the second transistor may be line-symmetric with respect to a boundary line in a second direction perpendicular to the first direction.

[0007] In one embodiment, the first initialization voltage line may be extended in a zigzag shape.

[0008] In one embodiment, the first initialization voltage line may include a first part and a second part parallel to the second initialization voltage line in a planar manner, and a third part that crosses the first initialization voltage line and connects the first part and the second part.

[0009] In one embodiment, the second initialization voltage line may be placed in a layer between the second gate electrode of the second transistor and the first initialization voltage line.

[0010] In one embodiment, the connecting electrode and the first initialization voltage line may be placed on the same layer.

[0011] In one embodiment, the display panel further comprises a third transistor including a pixel electrode of a third light-emitting diode that emits a third color, a third semiconductor layer connected to the second initialization voltage line, and a third gate electrode, which is disposed in a third pixel area adjacent to the second pixel area, and the second initialization voltage line may be connected to the third semiconductor layer through the connection electrode.

[0012] In one embodiment, the display panel may further include: a first initial voltage supply line that extends in a second direction perpendicular to the first direction and supplies the first initial voltage to the first initial voltage line; and a second initial voltage supply line that extends in the second direction and supplies the second initial voltage to the second initial voltage line.

[0013] In one embodiment, the display panel is disposed in the peripheral area and further includes a scan driving circuit that supplies a scan signal to the first gate electrode of the first transistor and the second gate electrode of the second transistor; and the first initialization voltage supply line and the second initialization voltage supply line may overlap with the scan driving circuit.

[0014] A display panel according to one embodiment of the present invention, comprising a display area and a peripheral area outside the display area, comprises: a first initialization voltage line extending in a first direction and transmitting a first initialization voltage in the display area; a second initialization voltage line extending in the first direction and transmitting a second initialization voltage in the display area; and a first transistor disposed in a first pixel area of ​​the display area and comprising a pixel electrode of a first light-emitting diode emitting a first color, a first semiconductor layer connected to the first initialization voltage line, and a first gate electrode. and a second transistor comprising a pixel electrode of a second light-emitting diode that emits a second color and is disposed in a second pixel region adjacent to the first pixel region, and a second semiconductor layer and a second gate electrode connected to the second initialization voltage line; wherein at least one of the first initialization voltage and the second initialization voltage has a value at a temperature higher than the reference temperature and a value at a temperature lower than the reference temperature.

[0015] In one embodiment, the first initialization voltage line and the second initialization voltage line may be placed on different layers.

[0016] In one embodiment, the first transistor and the second transistor may be line-symmetric with respect to a boundary line in a second direction perpendicular to the first direction.

[0017] In one embodiment, the first initialization voltage line may be extended in a zigzag shape.

[0018] In one embodiment, the first initialization voltage line may include a first part and a second part parallel to the second initialization voltage line in a planar manner, and a third part that crosses the first initialization voltage line and connects the first part and the second part.

[0019] In one embodiment, the second initialization voltage line may be placed in a layer between the second gate electrode of the second transistor and the first initialization voltage line.

[0020] In one embodiment, the first initialization voltage line is in direct contact with the first semiconductor layer, the second initialization voltage line is connected to the second semiconductor layer through a connecting electrode, and the connecting electrode and the first initialization voltage line may be disposed on the same layer.

[0021] In one embodiment, the display panel further comprises a third transistor including a pixel electrode of a third light-emitting diode that emits a third color, a third semiconductor layer connected to the second initialization voltage line, and a third gate electrode, which is disposed in a third pixel area adjacent to the second pixel area, and the second initialization voltage line may be connected to the third semiconductor layer through the connection electrode.

[0022] In one embodiment, the display panel may further include: a first initial voltage supply line that extends in a second direction perpendicular to the first direction and supplies the first initial voltage to the first initial voltage line; and a second initial voltage supply line that extends in the second direction and supplies the second initial voltage to the second initial voltage line.

[0023] In one embodiment, the display panel is disposed in the peripheral area and further includes a scan driving circuit that supplies a scan signal to the first gate electrode of the first transistor and the second gate electrode of the second transistor; and the first initialization voltage supply line and the second initialization voltage supply line may overlap with the scan driving circuit. Effects of the invention

[0024] According to one embodiment of the present invention, a display panel with improved image quality characteristics and a display device equipped therewith can be realized by compensating for the electrical characteristics of organic light-emitting diodes for each pixel emitting a different color. Of course, the scope of the present invention is not limited by such effects. Brief explanation of the drawing

[0025] FIG. 1 is a perspective view schematically illustrating a display device according to one embodiment. FIG. 2 is a plan view schematically showing a display panel according to one embodiment. FIG. 3 is a schematic diagram showing a pixel according to one embodiment. FIG. 4 is a schematic diagram showing the connection between a pixel and an initialization voltage line according to one embodiment. FIG. 5 is an equivalent circuit diagram of a pixel circuit according to one embodiment. FIG. 6 is a schematic arrangement diagram showing the light-emitting regions of a plurality of pixels according to one embodiment. FIG. 7 is a diagram schematically showing the connection relationship between a pixel and an initialization voltage line according to one embodiment. FIG. 8 is a schematic layout diagram illustrating the positions of elements constituting a pixel according to one embodiment. Figure 9 is a cross-sectional view taken along I-I' of Figure 8. FIG. 10 is a cross-sectional view taken along II-II' of FIG. 8. FIGS. 11 to 25 are layout diagrams schematically illustrating the elements of FIG. 8 layer by layer. FIG. 26 is a diagram showing the arrangement of the first initialization voltage line and the second initialization voltage line in a display area according to one embodiment. FIGS. 27 to 29 are schematic diagrams illustrating the connection relationship between a pixel and an initialization voltage line according to one embodiment. FIG. 30 is a diagram showing the arrangement of the first initialization voltage line and the second initialization voltage line in a display area according to one embodiment. FIG. 31 is an equivalent circuit diagram of a pixel circuit according to one embodiment. FIGS. 32 and FIGS. 33 are drawings showing the arrangement of elements corresponding to the pixel circuit of FIG. 31. FIGS. 34 to 43 are equivalent circuit diagrams of a pixel circuit according to one embodiment. FIG. 44 is a diagram schematically illustrating the operation of transmitting an initialization voltage according to temperature to a display panel according to one embodiment. Specific details for implementing the invention

[0026] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0027] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0028] In the following embodiments, when various components such as layers, films, regions, and plates are described as being "on" another component, this includes not only cases where they are "directly on" another component, but also cases where other components are interposed between them. Additionally, for convenience of explanation, the size of components in the drawings may be exaggerated or reduced. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and therefore the present invention is not necessarily limited to what is illustrated.

[0029] In the following embodiments, "planar" means when the target part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the target part is viewed from the side. In the following embodiments, "overlapping" of the first component with the second component means that the first component is located above or below the second component.

[0030] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to three axes in an orthogonal coordinate system and can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0031] FIG. 1 is a perspective view schematically illustrating a display device according to one embodiment. FIG. 2 is a plan view schematically illustrating a display panel according to one embodiment. FIG. 3 is a diagram schematically illustrating a pixel according to one embodiment. FIG. 4 is a diagram schematically illustrating the connection between a pixel and an initialization voltage line according to one embodiment.

[0032] A display device according to embodiments of the present invention is a device for displaying video or still images, and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic notebooks, e-books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs). In addition, a display device according to one embodiment can be used in wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). In addition, the display device according to one embodiment can be used as a Center Information Display (CID) placed on the instrument panel of a vehicle, the center fascia or dashboard of a vehicle, a room mirror display replacing a side mirror of a vehicle, an entertainment device for the rear seat of a vehicle, or a display placed on the back of the front seat.

[0033] Referring to FIG. 1, the display device (1) may have an edge of a first direction and an edge of a second direction. Here, the first direction and the second direction may be directions that intersect each other. For example, the first direction and the second direction may be at an acute angle to each other. As another example, the first direction and the second direction may be at an obtuse angle to each other or may be orthogonal. Below, we will describe in detail focusing on the case where the first direction and the second direction are orthogonal to each other. For example, the first direction may be the x direction or the -x direction, and the second direction may be the y direction or the -y direction. A third direction perpendicular to the first direction and the second direction may be the z direction or the -z direction.

[0034] The display device (1) may include a display area (DA) and a peripheral area (PA) outside the display area (DA). The display device (1) may provide a predetermined image using light emitted from a plurality of pixels (PX) arranged in the display area (DA). The peripheral area (PA) is an area arranged on the outer edge of the display area (DA) and may be a type of non-display area where pixels are not arranged. The display area (DA) may be entirely surrounded by the peripheral area (PA).

[0035] In the following description, an organic light-emitting display device is used as an example to illustrate an embodiment of the present invention, but the display device of the present invention is not limited thereto. As another embodiment, the display device of the present invention may be an inorganic light-emitting display (inorganic light-emitting display or inorganic EL display device) or a display device such as a quantum dot light-emitting display. For example, the light-emitting layer of a display element included in the display device may include an organic material or an inorganic material. Additionally, the display device may include a light-emitting layer and a quantum dot located on the path of light emitted from the light-emitting layer.

[0036] Referring to FIG. 2, the display device (1) includes a display panel (10), and a cover window (not shown) that protects the display panel (10) may be further disposed on the upper part of the display panel (10).

[0037] Various components forming the display panel (10) may be placed on a substrate (100). The substrate (100) may include a display area (DA) and a peripheral area (PA) surrounding the display area (DA).

[0038] A plurality of pixels (PX) may be arranged in a display area (DA). Each pixel (PX) may include a display element. The display element may be connected to a pixel circuit that drives the pixel (PX). The display element may include an organic light-emitting diode or a quantum dot organic light-emitting diode, etc. Each pixel (PX) may emit light of, for example, red, green, blue, or white through an organic light-emitting diode (OLED). The plurality of pixels (PX) may include a first pixel (PX1) that emits light of a first color, a second pixel (PX2) that emits light of a second color, and a third pixel (PX3) that emits light of a third color. For example, the first pixel (PX1) may be a red pixel, the second pixel (PX2) may be a green pixel, and the third pixel (PX3) may be a blue pixel.

[0039] Referring to FIG. 3, each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may include a pixel circuit (PC) connected to a gate line (GL) and a data line (DL), and an organic light-emitting diode (OLED) as a display element connected to the pixel circuit (PC). The pixel circuit (PC) may include a driving unit (DRC) and an initialization unit (AIC). The organic light-emitting diode (OLED) includes a pixel electrode (first electrode, anode) and a counter electrode (second electrode, cathode), and the counter electrode may receive a second power supply voltage (ELVSS). The organic light-emitting diode (OLED) can display an image by receiving a driving current from the driving unit (DRC) and emitting light.

[0040] The driving unit (DRC) is connected to the first power supply voltage line (PL) and is activated by a scan signal (SCAN) supplied from the gate line (GL), and can generate and output a driving current corresponding to a data signal (DATA) supplied from the data line (DL). The organic light-emitting diode (OLED) can emit light with a brightness corresponding to the driving current delivered from the driving unit (DRC). The driving unit (DRC) may include a plurality of transistors and capacitors. The initialization unit (AIC) may be connected to the organic light-emitting diode (OLED) and the initialization voltage line (VL). The initialization unit (AIC) can initialize the organic light-emitting diode (OLED) by delivering an initialization voltage (Vaint) from the initialization voltage line (VL) to the organic light-emitting diode (OLED). The specific configuration and structure of the circuit elements of the driving unit (DRC) and the initialization unit (AIC) will be described below in various embodiments.

[0041] Changes in brightness may occur due to residual voltage in an organic light-emitting diode (OLED), and this can be more noticeable in low-gradation displays at high temperatures. For example, an organic light-emitting diode (OLED) may emit light at a brightness higher than the black brightness. An embodiment of the present invention can minimize changes in brightness of an organic light-emitting diode (OLED) at low gradations by initializing the organic light-emitting diode (OLED) through an initialization unit (AIC).

[0042] The material characteristics of the organic light-emitting diodes (OLEDs) of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may differ. Accordingly, when the initialization voltage is set according to the material characteristics of one color pixel, color changes may occur in other color pixels. In one embodiment, the display device (1) may set the initialization voltage applied to each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) differently according to the material characteristics of the organic light-emitting diodes (OLEDs). For example, the display device (1) may separately provide an initialization voltage line connected to the first pixel (PX1) and an initialization voltage line connected to the second pixel (PX2) and the third pixel (PX3) so that different initialization voltages are applied, thereby improving the low-gradation brightness change and color change issues caused by the material influence of the organic light-emitting diodes (OLEDs).

[0043] In one embodiment, the display device (1) may set different initialization voltages applied to each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) depending on the temperature. For example, the display device (1) may set different initialization voltages applied to the first initialization voltage line connected to the first pixel (PX1) at high temperature and different initialization voltages applied to the first initialization voltage line at normal temperature. The display device (1) may set different initialization voltages applied to the second initialization voltage line connected to the second pixel (PX2) and the third pixel (PX3) at high temperature and different initialization voltages applied to the second initialization voltage line at normal temperature. Accordingly, issues regarding low grayscale brightness change and color change at high temperatures can be improved.

[0044] When the pixel (PX) illustrated in FIG. 3 is the first pixel (PX1), the initialization voltage line (VL) may be the first initialization voltage line (VL1), and the initialization voltage (Vaint) may be the first initialization voltage (Vaint1). When the pixel (PX) illustrated in FIG. 3 is the second pixel (PX2) or the third pixel (PX), the initialization voltage line (VL) may be the second initialization voltage line (VL2), and the initialization voltage (Vaint) may be the second initialization voltage (Vaint2). FIG. 4 illustrates an example in which the first pixel (PX1) is connected to the first initialization voltage line (VL1) which supplies the first initialization voltage (Vaint1), and the second pixel (PX2) and the third pixel (PX3) are connected to the second initialization voltage line (VL2) which supplies the second initialization voltage (Vaint2).

[0045] Various wirings that transmit electrical signals to be applied to the display area (DA), outer circuits electrically connected to pixel circuits, and pads to which printed circuit boards or driver IC chips are attached may be located in the peripheral area (PA). For example, a first scan driving circuit (SDRV1), a second scan driving circuit (SDRV2), a terminal section (PAD), a driving voltage supply line (11), a common voltage supply line (13), and an initialization voltage supply line (15) may be arranged in the peripheral area (PA).

[0046] The first scan driving circuit (SDRV1) can apply a scan signal, which is a gate control signal, to the pixel circuits through the gate line (GL). The first scan driving circuit (SDRV1) can apply a light emission control signal to the pixel circuits through the light emission control line (EL). The second scan driving circuit (SDRV2) may be located on the opposite side of the first scan driving circuit (SDRV1) with respect to the display area (DA) and may be approximately parallel to the first scan driving circuit (SDRV1). Some of the pixel circuits of the pixels (PX) of the display area (DA) may be electrically connected to the first scan driving circuit (SDRV1), and the rest may be electrically connected to the second scan driving circuit (SDRV2). The second scan driving circuit (SDRV2) may be omitted.

[0047] A terminal portion (PAD) may be disposed on one side of the substrate (100). The terminal portion (PAD) may be exposed without being covered by an insulating layer and connected to a display circuit board (30). A display driving portion (32) may be disposed on the display circuit board (30). The display driving portion (32) may be formed in the form of one or more integrated circuit chips and mounted on the display circuit board (30).

[0048] The display driving unit (32) can generate a control signal to be transmitted to the first scan driving circuit (SDRV1) and the second scan driving circuit (SDRV2). The display driving unit (32) generates a data signal, and the generated data signal can be transmitted to the pixel circuits of the pixels (PX) through the fan-out line (FW) and the data line (DL) connected to the fan-out line (FW).

[0049] The display driving unit (32) can supply a first power supply voltage (ELVDD) to a first power supply voltage supply line (11) and can supply a second power supply voltage (ELVSS) to a second power supply voltage supply line (13). The first power supply voltage (ELVDD) is applied to the pixel circuits of pixels (PX) through a first power supply voltage line (PL) connected to the first power supply voltage supply line (11), and the second power supply voltage (ELVSS) can be applied to the opposing electrodes of the display elements through the second power supply voltage supply line (13).

[0050] The first power supply voltage line (11) is connected to the terminal section (PAD) and may be provided extending in the x-direction from the lower side of the display area (DA). The second power supply voltage line (13) is connected to the terminal section (PAD) and has a loop shape with one side open, so that it can partially surround the display area (DA).

[0051] The display driving unit (32) can supply an initial voltage to the initial voltage supply line (15). The initial voltage supply line (15) may include a first initial voltage supply line (15a) and a second initial voltage supply line (15b). Each of the first initial voltage supply line (15a) and the second initial voltage supply line (15b) is connected to a terminal unit (PAD) and may be arranged to extend along the y-direction in a manner that at least surrounds the left and right sides of the display area (DA). The first initial voltage supply line (15a) and the second initial voltage supply line (15b) may be arranged spaced apart from each other and overlap the first scan driving circuit (SDRV1) and the second scan driving circuit (SDRV2). The first initial voltage supply line (15a) may be connected to the first initial voltage lines (VL1) of the display area (DA). The second initialization voltage supply line (15b) can be connected to the second initialization voltage lines (VL2) of the display area (DA). The first initialization voltage (Vaint1) can be applied to the pixel circuits of the first pixels (PX1) through the first initialization voltage line (VL1) connected to the first initialization voltage supply line (15a). The second initialization voltage (Vaint2) can be applied to the pixel circuits of the second pixels (PX1) and the third pixels (PX3) through the second initialization voltage line (VL2) connected to the second initialization voltage supply line (15b). The display driving unit (32) can generate the first initialization voltage (Vaint1) and the second initialization voltage (Vaint2) differently depending on the temperature and output them to the display panel (10).

[0052] FIG. 5 is an equivalent circuit diagram of a pixel circuit according to one embodiment.

[0053] Referring to FIG. 5, the pixel circuit (PC) may include a driving unit (DRC) comprising first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) and a capacitor (Cst), and an initialization unit (AIC) comprising an initialization transistor (TB). The pixel circuit (PC) may be connected to a data line (DL), a first gate line (GWL), a second gate line (GIL), a third gate line (GCL), a fourth gate line (GBL), and a light emission control line (EL). Additionally, the pixel circuit (PC) may be connected to an initialization voltage line (VL), a node initialization voltage line (VIL), and a first power supply voltage line (PL). The pixel circuit (PC) may be connected to an organic light-emitting diode (OLED) as a display element.

[0054] In FIG. 5, among the first to seventh transistors (T1 to T7), the third transistor (T3) and the fourth transistor (T4) are N-type transistors, and the rest are P-type transistors. Depending on the type of transistor (N-type or P-type) and / or operating conditions, the first terminal of the transistor may be a source electrode or a drain electrode, and the second terminal may be an electrode different from the first terminal. For example, if the first terminal is a source electrode, the second terminal may be a drain electrode.

[0055] The first transistor (T1) can be connected between the first power supply voltage line (PL) and the organic light-emitting diode (OLED). The first transistor (T1) can be connected between the first node (N1) and the third node (N3). The first transistor (T1) can be connected to the first power supply voltage line (PL) via the fifth transistor (T5) and electrically connected to the organic light-emitting diode (OLED) via the sixth transistor (T6). The first transistor (T1) may include a gate electrode connected to the second node (N2), a first terminal connected to the first node (N1), and a second terminal connected to the third node (N3). The first power supply voltage line (PL) can transmit the first power supply voltage (ELVDD) to the first transistor (T1). The first transistor (T1) acts as a driving transistor and can receive a data signal (DATA) according to the switching operation of the second transistor (T2) and supply a driving current (Ioled) to the organic light-emitting diode (OLED).

[0056] The second transistor (T2) (data writing transistor) can be connected between the data line (DL) and the first node (N1). The second transistor (T2) can be connected to the first power supply voltage line (PL) via the fifth transistor (T5). The second transistor (T2) may include a gate electrode connected to the first gate line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second transistor (T2) can perform a switching operation in which it is turned on according to the first scan signal (GW) received through the first gate line (GWL) and transmits the data signal (DATA) transmitted to the data line (DL) to the first node (N1).

[0057] The third transistor (T3) (compensation transistor) can be connected between the second node (N2) and the third node (N3). The third transistor (T3) can be electrically connected to an organic light-emitting diode (OLED) via the sixth transistor (T6). The third transistor (T3) may include a gate electrode connected to the third gate line (GCL), a first terminal connected to the second node (N2), and a second terminal connected to the third node (N3). The third transistor (T3) can compensate the threshold voltage of the first transistor (T1) by turning on according to the third scan signal (GC) received through the third gate line (GCL) and diode-connecting the first transistor (T1).

[0058] The fourth transistor (T4) (node ​​initialization transistor) can be connected between the second node (N2) and the node initialization voltage line (VIL). The fourth transistor (T4) may include a gate electrode connected to the second gate line (GIL), a first terminal connected to the second node (N2), and a second terminal connected to the node initialization voltage line (VIL). The fourth transistor (T4) can be turned on according to the second scan signal (GI) received through the second gate line (GIL) to transmit an initialization voltage (Vint) to the gate electrode of the first transistor (T1) and initialize the gate electrode of the first transistor (T1).

[0059] The fifth transistor (T5) (first light-emitting control transistor) may be connected between the first power supply voltage line (PL) and the first node (N1). The sixth transistor (T6) (second light-emitting control transistor) may be connected between the third node (N3) and the organic light-emitting diode (OLED). The fifth transistor (T5) may include a gate electrode connected to the light-emitting control line (EL), a first terminal connected to the first power supply voltage line (PL), and a second terminal connected to the first node (N1). The sixth transistor (T6) may include a gate electrode connected to the light-emitting control line (EL), a first terminal connected to the third node (N3), and a second terminal connected to the pixel electrode of the organic light-emitting diode (OLED). The fifth transistor (T5) and the sixth transistor (T6) are simultaneously turned on according to the light emission control signal (EM) received through the light emission control line (EL), and a driving current flows to the organic light-emitting diode (OLED).

[0060] The seventh transistor (T7) (bias transistor) can be connected between the first node (N1) and the bias voltage line (VBL). The seventh transistor (T7) may include a gate electrode connected to the fourth gate line (GBL), a first terminal connected to the bias voltage line (VBL), and a second terminal connected to the first node (N1). The seventh transistor (T7) is turned on according to the fourth scan signal (GB) received through the fourth gate line (GBL) to apply a bias voltage (VOBS) to the first terminal of the first transistor (T1), thereby pre-setting a voltage suitable for the subsequent operation of the first transistor (T1) at the first terminal.

[0061] The capacitor (Cst) may include a first electrode connected to the gate electrode of the first transistor (T1) and a second electrode connected to the first power supply voltage line (PL). The capacitor (Cst) can maintain the voltage applied to the gate electrode of the first transistor (T1) by storing and maintaining a voltage corresponding to the difference between the voltages across the first power supply voltage line (PL) and the gate electrode of the first transistor (T1).

[0062] The initialization transistor (TB) may be connected between the organic light-emitting diode (OLED) and the initialization voltage line (VL). The initialization transistor (TB) may include a gate electrode connected to the fourth gate line (GBL), a second terminal of the sixth transistor (T6), a first terminal connected to the pixel electrode of the organic light-emitting diode (OLED), and a second terminal connected to the initialization voltage line (VL). The initialization transistor (TB B ) can be turned on according to the fourth scan signal (GB) received through the fourth gate line (GBL) to deliver an initialization voltage (Vaint) to the pixel electrode of the organic light-emitting diode (OLED) and initialize the pixel electrode of the organic light-emitting diode (OLED). The initialization transistor (TB) can be turned on simultaneously with the seventh transistor (T7) according to the fourth scan signal (GB).

[0063] If the pixel (PX) shown in FIG. 5 is the first pixel (PX1), the initialization voltage line (VL) may be the first initialization voltage line (VL1) and the initialization voltage (Vaint) may be the first initialization voltage (Vaint1). If the pixel (PX) shown in FIG. 5 is the second pixel (PX2) or the third pixel (PX), the initialization voltage line (VL) may be the second initialization voltage line (VL2) and the initialization voltage (Vaint) may be the second initialization voltage (Vaint2).

[0064] The organic light-emitting diode (OLED) includes a pixel electrode and a counter electrode, and the counter electrode can receive a second power supply voltage (ELVSS). The organic light-emitting diode (OLED) receives a driving current from the first transistor (T1) and emits light to display an image.

[0065] FIG. 6 is a schematic arrangement diagram showing the light-emitting regions of a plurality of pixels according to one embodiment.

[0066] A plurality of pixels arranged in a display area (DA) may include a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3). The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may be arranged repeatedly according to a predetermined pattern in the x direction and the y direction. The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may each include a pixel circuit and an organic light-emitting diode (OLED) electrically connected to the pixel circuit. The organic light-emitting diode (OLED) of each pixel may be placed on the upper layer of the pixel circuit. The organic light-emitting diode (OLED) may be placed directly above the pixel circuit to overlap it, or it may be placed offset from the pixel circuit to partially overlap the pixel circuit of another pixel placed in an adjacent row and / or column.

[0067] FIG. 6 shows the pixel electrode (PE) and light-emitting region of each of the first pixel (PX1), second pixel (PX2), and third pixel (PX3). The light-emitting region is an area where the light-emitting layer of an organic light-emitting diode (OLED) is placed. The light-emitting region can be defined by the opening of the pixel definition layer. This will be described later. Each pixel electrode (PE) may include a first region (PEA1) corresponding to the light-emitting region and a second region (PEA2) surrounding the first region.

[0068] In the first column (M1), the first light-emitting region (EA1) of the first pixel (PX1) and the third light-emitting region (EA3) of the third pixel (PX3) may be arranged alternately in the y direction. In the second column (M2), the second light-emitting region (EA2) of the second pixel (PX2) may be arranged repeatedly in the y direction. The first column (M1) and the second column (M2) alternate in the x direction, and the arrangement of the first light-emitting region (EA1) of the first pixel (PX1) and the third light-emitting region (EA3) of the third pixel (PX3) in adjacent first columns (M1) may be opposite.

[0069] In the first sub-row (SN1) of each row (N), the first light-emitting region (EA1) of the first pixel (PX1) and the third light-emitting region (EA3) of the third pixel (PX3) may be arranged alternately in the x-direction, and in the second sub-row (SN2), the second light-emitting region (EA2) of the second pixel (PX2) may be arranged repeatedly in the x-direction. That is, in each row (N), the first light-emitting region (EA1) of the first pixel (PX1), the second light-emitting region (EA2) of the second pixel (PX2), the third light-emitting region (EA3) of the third pixel (PX3), and the second light-emitting region (EA2) of the second pixel (PX2) may be arranged repeatedly in a zigzag pattern.

[0070] The first light-emitting region (EA1) of the first pixel (PX1), the second light-emitting region (EA2) of the second pixel (PX2), and the third light-emitting region (EA3) of the third pixel (PX3) may have different areas. In one embodiment, the third light-emitting region (EA3) of the third pixel (PX3) may have a larger area than the first light-emitting region (EA1) of the first pixel (PX1). Additionally, the third light-emitting region (EA3) of the third pixel (PX3) may have a larger area than the second light-emitting region (EA2) of the second pixel (PX2). The first light-emitting region (EA1) of the first pixel (PX1) may have a larger area than the second light-emitting region (EA2) of the second pixel (PX2). In another embodiment, the third light-emitting region (EA3) of the third pixel (PX3) may have the same area as the first light-emitting region (EA1) of the first pixel (PX1). The present invention is not limited thereto. For example, various embodiments are possible, such as the first light-emitting region (EA1) of the first pixel (PX1) being larger than the second light-emitting region (EA2) of the second pixel (PX2) and the third light-emitting region (EA3) of the third pixel (PX3).

[0071] The first to third light-emitting regions (EA1, EA2, EA3) may have shapes such as squares, octagons, polygons, circles, or ellipses, and polygons may also include shapes with rounded corners (vertices).

[0072] In one embodiment, the first pixel (PX1) may be a red pixel (R) that emits red light, the second pixel (PX2) may be a green pixel (G) that emits green light, and the third pixel (PX3) may be a blue pixel (B) that emits blue light.

[0073] FIG. 7 is a diagram schematically showing the connection relationship between a pixel and an initialization voltage line according to one embodiment.

[0074] Referring to FIG. 7, the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) arranged in the same row may share the first gate line (GWL), the second gate line (GIL), the third gate line (GCL), the fourth gate line (GBL), the light emission control line (EL), the bias voltage line (VBL), and the node initialization voltage line (VIL). In one embodiment, different initialization voltages may be applied to the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) by considering the light emission characteristics of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3). For example, the first pixel (PX1) may be connected to the first initialization voltage line (VL1) so that the initialization transistor (TB) can receive the first initialization voltage (Vaint1) from the first initialization voltage line (VL1). Each of the remaining second pixel (PX2) and third pixel (PX3) is connected to the second initialization voltage line (VL2), so that the initialization transistor (TB) can receive the second initialization voltage (Vaint2) from the second initialization voltage line (VL2).

[0075] FIG. 8 is a layout diagram schematically illustrating the positions of elements constituting a pixel according to one embodiment. FIG. 9 is a cross-sectional view taken along I-I' of FIG. 8. FIG. 10 is a cross-sectional view taken along II-II' of FIG. 8. FIG. 11 to 25 are layout diagrams schematically illustrating the elements of FIG. 8 layer by layer. FIG. 16 is a plan view in which the elements of FIG. 11 to 15 are superimposed. FIG. 17 is a plan view as part of FIG. 16, illustrating the first to seventh transistors (T1 to T7), initialization transistor (TB), and capacitor (Cst) of the first pixel area (PXA1).

[0076] According to the pixel arrangement shown in FIG. 6, a first pixel area (PXA1) in which a pixel circuit of a first pixel (PX1) or a third pixel (PX3) is disposed in each row on the substrate (100) and a second pixel area (PXA2) in which a pixel circuit of a second pixel (PX2) is disposed may be repeated in the x direction. Since the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) each include an initialization transistor (TB), the initialization transistor (TB) of the first pixel (PX1) or the third pixel (PX3) may be disposed in the first pixel area (PXA1), and the initialization transistor (TB) of the second pixel (PX2) may be disposed in the second pixel area (PXA2). The pixel circuit placed in the first pixel area (PXA1) and the pixel circuit placed in the second pixel area (PXA2) may be line-symmetric with respect to the boundary line (IBL). Accordingly, the initialization transistor (TB) placed in the first pixel area (PXA1) and the initialization transistor (TB) placed in the second pixel area (PXA2) may be line-symmetric with respect to the boundary line (IBL).

[0077] Hereinafter, an example is described in which the pixel circuit of the first pixel (PX1) is placed in the first pixel area (PXA1) and the pixel circuit of the second pixel (PX2) is placed in the second pixel area (PXA2). Since identical elements are placed in each layer of the first pixel area (PXA1) and the second pixel area (PXA2), for the convenience of explanation, the explanation will focus on the elements of the pixel circuit placed in the first pixel area (PXA1).

[0078] As illustrated in FIGS. 9 to 11, a buffer layer (101) may be disposed on a substrate (100), and a first semiconductor layer (SACT) may be disposed on the buffer layer (101). The first semiconductor layer (SACT) may include a silicon semiconductor. The first semiconductor layer (SACT) may include a first sub-semiconductor layer (SACT1) and a second sub-semiconductor layer (SACT2) separated from the first sub-semiconductor layer (SACT1). The first sub-semiconductor layer (SACT1) of the first pixel area (PXA1) may be integrally formed by being connected to the first sub-semiconductor layer (SACT1) of the second pixel area (PXA2). The second sub-semiconductor layer (SACT2) may be electrically connected to the first sub-semiconductor layer (SACT1) as described below.

[0079] The first sub-semiconductor layer (SACT1) may have a curved shape of various forms. The first sub-semiconductor layer (SACT1) may include the channel region, source region on both sides of the channel region, and drain region of each of the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the initialization transistor (TB). The second sub-semiconductor layer (SACT2) may include the channel region, source region, and drain region of the seventh transistor (T7).

[0080] Referring to FIG. 17, the first sub-semiconductor layer (SACT1) may include a channel region (121a), a source region (123a), and a drain region (125a) of the first transistor (T1), a channel region (121b), a source region (123b), and a drain region (125b) of the second transistor (T2), a channel region (121e), a source region (123e), and a drain region (125e) of the fifth transistor (T5), a channel region (121f), a source region (123f), and a drain region (125f) of the sixth transistor (T6), and a channel region (121h), a source region (123h), and a drain region (125h) of the initialization transistor (TB). The second sub-semiconductor layer (SACT2) may include the channel region (121g), source region (123g), and drain region (125g) of the seventh transistor (T7). The channel region (121a) of the first transistor (T1) can be formed long by having a curve, so that the driving range of the gate voltage applied to the gate electrode can be widened. Various embodiments such as 'ㄷ', 'ㄹ', 'S', 'M', and 'W' are possible for the shape of the channel region (121a) of the first transistor (T1).

[0081] As illustrated in FIGS. 9, 10 and 12, a first insulating layer (102) is disposed over a first semiconductor layer (SACT1) on a buffer layer (101), a gate electrode (131a) of a first transistor (T1) is disposed on the first insulating layer (102) in an island shape, and a node initialization voltage line (VIL), a first gate line (GWL), a light emission control line (EL), and a fourth gate line (GBL) can be disposed extending in the x direction.

[0082] Referring to FIG. 17, the gate electrode (131a) of the first transistor (T1) may be the lower electrode (CE1), which is the first electrode of the capacitor (Cst). The gate electrode (131b) of the second transistor (T2) may be a portion of the first gate line (GWL) that intersects (overlaps) with the first sub-semiconductor layer (SACT1). The gate electrode (131e) of the fifth transistor (T5) and the gate electrode (131f) of the sixth transistor (T6) may be portions of the light emission control line (EL) that intersects with the first sub-semiconductor layer (SACT1). The gate electrode (131g) of the seventh transistor (T7) may be a portion of the fourth gate line (GBL) that intersects with the second sub-semiconductor layer (SACT2). The gate electrode (131h) of the initialization transistor (TB) may be a part of the fourth gate line (GBL) that intersects the first sub-semiconductor layer (SACT1).

[0083] As illustrated in FIGS. 9, 10 and 13, a second insulating layer (103) is disposed on a first insulating layer (102), and an electrode voltage line (HL), a lower gate line (GIL1) of a second gate line (GIL), and a lower gate line (GCL1) of a third gate line (GCL) may be disposed on the second insulating layer (103) and extended in the x direction.

[0084] A portion of the electrode voltage line (HL) can cover the lower electrode (CE1) of the capacitor (Cst) as the upper electrode (CE2), which is the second electrode of the capacitor (Cst). The upper electrodes (CE2) of the capacitors (Cst) of the same row of pixel circuits can be connected to each other by the electrode voltage line (HL). An opening (SOP) can be formed in the upper electrode (CE2) of the capacitor (Cst).

[0085] As illustrated in FIGS. 9, 10 and 14, a third insulating layer (104) may be disposed on a second insulating layer (103), and a second semiconductor layer (OACT) may be disposed on the third insulating layer (104). The second semiconductor layer (OACT) may include an oxide semiconductor. The second semiconductor layer (OACT) of the first pixel area (PXA1) may be connected to the second semiconductor layer (OACT) of the second pixel area (PXA2) and formed integrally. The second semiconductor layer (OACT) may include a channel area, a source area, and a drain area of ​​the third transistor (T3) and the fourth transistor (T4), respectively.

[0086] Referring to FIG. 17, the second semiconductor layer (OACT) may include a channel region (151c), a source region (153c), and a drain region (155c) of the third transistor (T3), and a channel region (151d), a source region (153d), and a drain region (155d) of the fourth transistor (T4).

[0087] That is, the channel region, source region, and drain region of each of the first to seventh transistors (T1 to T7) and the initialization transistor (TB) can be understood as being parts of the semiconductor layer. The source region and drain region of the semiconductor layer may correspond to the first terminal (or second terminal) and the second terminal (or first terminal) of the transistor described in FIG. 5, respectively. Depending on the case, the source region or drain region may be interpreted as the source electrode or drain electrode of the transistor. For example, the source electrode and drain electrode of the first transistor (T1) may correspond to the source region (123a) and drain region (125a) doped with impurities near the channel region (121a), respectively.

[0088] As illustrated in FIGS. 9, 10 and 15, a fourth insulating layer (105) is disposed on a third insulating layer (104), and an upper gate line (GIL2) of a second gate line (GIL), an upper gate line (GCL2) of a third gate line (GCL), a second initialization voltage line (VL2), and a bias voltage line (VBL) may be disposed on the fourth insulating layer (105) and extended in the x-direction.

[0089] Referring to FIG. 17, the gate electrode of the third transistor (T3) may be a part of the third gate line (GCL) that intersects (overlaps) with the second semiconductor layer (OACT). The gate electrode of the third transistor (T3) may include a lower gate electrode (141c) which is part of the lower gate line (GCL1) of the third gate line (GCL) and an upper gate electrode (161c) which is part of the upper gate line (GCL2). The gate electrode of the fourth transistor (T4) may include a lower gate electrode (141d) which is part of the lower gate line (GIL1) of the second gate line (GIL) and an upper gate electrode (161d) which is part of the upper gate line (GIL2). That is, the third transistor (T3) and the fourth transistor (T4) may have a dual gate structure having control electrodes on the upper and lower parts, respectively, of the second semiconductor layer (OACT).

[0090] The second initialization voltage line (VL2) can be superimposed on the light emission control line (EL). The bias voltage line (VBL) can be superimposed on the fourth gate line (GBL).

[0091] As illustrated in FIGS. 9, 10 and 18, a fifth insulating layer (106) may be disposed on a fourth insulating layer (105), and a first initialization voltage line (VL1) may be disposed extending in the x-direction on the fifth insulating layer (106). Additionally, connecting electrodes (171 to 179) may be disposed on the fourth insulating layer (105).

[0092] FIG. 19 is a plan view in which the elements of FIG. 11 through 15 and FIG. 18 are superimposed. FIG. 20 is an enlarged view of section A of FIG. 19. FIG. 21 is a cross-sectional view taken along III-III' and IV-IV' of FIG. 20. FIG. 22 is an enlarged view of section B of FIG. 19. FIG. 23 is a cross-sectional view taken along VV' and VI-VI' of FIG. 22. Hereinafter, FIG. 19 through 23 will be described together with reference.

[0093] The first initialization voltage line (VL1) can be electrically connected to the drain region (125h) of the initialization transistor (TB) in the first pixel region (PXA1) where the pixel circuit of the first pixel (PX1) is placed. The first initialization voltage line (VL1) can be electrically connected to the drain region (125h) of the initialization transistor (TB) of the first pixel (PX1) through a contact hole (67) penetrating the first to fourth insulating layers (102 to 105).

[0094] The first initialization voltage line (VL1) may have a curve and extend in a zigzag shape in the x-direction. The first initialization voltage line (VL1) may include a first part (VA1) and a second part (VA2) extending in the x-direction, and a third part (VA3) extending in the y-direction and connecting the first part (VA1) and the second part (VA2). The first part (VA1) and the second part (VA2) are spaced apart in the y-direction, and a light emission control line (EL) and a second initialization voltage line (VL2) may be placed between the first part (VA1) and the second part (VA2) on a plane. The first part (VA1) may partially overlap the first electrode (CE1) and the second electrode (CE2) of the capacitor (Cst). The second part (VA2) may partially overlap the fourth gate line (GBL) and the bias voltage line (VBL). The third part (VA3) crosses the second initialization voltage line (VL2) and a portion of it may overlap the second initialization voltage line (VL2).

[0095] The first initialization voltage line (VL1) may further include a fourth part (VAP) protruding from the second part (VA2) or the third part (VA3) at the location where the second part (VA2) and the third part (VA3) meet. The fourth part (VAP) may be provided only in the first pixel area (PXA1) where the first pixel (PX1) is placed among the first pixel areas (PXA1). The fourth part (VAP) may overlap with the semiconductor layer of the initialization transistor (TB) of the first pixel (PX1) (e.g., the drain area (125h) of the initialization transistor (TB)) and may make direct contact through the contact hole (67).

[0096] One end of the connecting electrode (171) can be electrically connected to the second semiconductor layer (OACT) by contacting the second semiconductor layer (OACT) through a contact hole (51). Referring to FIG. 18, one end of the connecting electrode (171) can be electrically connected to the source region (153c) of the third transistor (T3) and the drain region (155d) of the fourth transistor (T4) through a contact hole (51) penetrating the fourth and fifth insulating layers (105 and 106). The other end of the connecting electrode (171) can be electrically connected to the gate electrode (131a) of the first transistor (T1) through a contact hole (52) penetrating the second to fifth insulating layers (103 to 106). Meanwhile, the contact hole (52) is spaced apart from the edge of the opening (SOP) within the opening (SOP) of the second electrode (CE2) of the capacitor (Cst), so that the connecting electrode (171) can be electrically insulated from the second electrode (CE2).

[0097] The connecting electrode (172) can be electrically connected to the drain region (125a) of the first transistor (T1) and the source region (123f) of the sixth transistor (T6) through a contact hole (53) penetrating the first to fifth insulating layers (102 to 106). The connecting electrode (172) can be electrically connected to the drain region (155c) of the third transistor (T3) through a contact hole (54) penetrating the fourth and fifth insulating layers (105 and 106).

[0098] The connecting electrode (173) can be electrically connected to the source region (123b) of the second transistor (T2) through a contact hole (55) that penetrates the first to fifth insulating layers (102 to 106).

[0099] The connecting electrode (174) can be electrically connected to the source region (123e) of the fifth transistor (T5) through a contact hole (56) penetrating the first to fifth insulating layers (102 to 106). The connecting electrode (174) can be electrically connected to the electrode voltage line (HL) through a contact hole (57) penetrating the third to fifth insulating layers (104 to 106).

[0100] The connecting electrode (175) can be electrically connected to the node initialization voltage line (VIL) through a contact hole (58) penetrating the second to fifth insulating layers (103 to 106). The connecting electrode (175) can be electrically connected to the drain region (155d) of the fourth transistor (T4) through a contact hole (59) penetrating the fourth and fifth insulating layers (105 and 106).

[0101] The connecting electrode (176) can be electrically connected to the source region (123a) of the first transistor (T1) and the drain region (125e) of the fifth transistor (T5) through a contact hole (60) penetrating the first to fifth insulating layers (102 to 106). The connecting electrode (176) can be electrically connected to the drain region (125g) of the seventh transistor (T7) through a contact hole (61) penetrating the first to fifth insulating layers (102 to 106).

[0102] The connecting electrode (177) can be electrically connected to the drain region (125f) of the sixth transistor (T6) through a contact hole (62) penetrating the first to fifth insulating layers (102 to 106).

[0103] The connecting electrode (178) may be placed in the first pixel area (PXA1) where the pixel circuit of the third pixel (PX3) is placed among the second pixel area (PXA2) and the first pixel area (PXA1) where the pixel circuit of the second pixel (PX2) is placed. The connecting electrode (178) may be electrically connected to the drain area (125h) of the initialization transistor (TB) of the second pixel (PX2) and the third pixel (PX3) through a contact hole (64) penetrating the first to fourth insulating layers (102 to 105). The connecting electrode (178) may be electrically connected to the second initialization voltage line (VL2) through a contact hole (63) penetrating the fifth insulating layer (106). The connecting electrode (178) overlaps the semiconductor layer of the initialization transistor (TB) and can be directly contacted through the contact hole (64), and overlaps the second initialization voltage line (VL2) and can be directly contacted through the contact hole (63).

[0104] The connecting electrode (179) can be electrically connected to the source region (123g) of the seventh transistor (T7) through a contact hole (65) penetrating the first to fifth insulating layers (102 to 106). The connecting electrode (179) can be electrically connected to the bias voltage line (VBL) through a contact hole (66) penetrating the fifth insulating layer (106).

[0105] As illustrated in FIGS. 9, 10 and 24, a sixth insulating layer (107) is disposed on a fifth insulating layer (106), a connecting electrode (181) is disposed on the sixth insulating layer (107), and a data line (DL) and a first power supply voltage line (PL) may be disposed extending in the y direction. Various conductive layers may be further disposed on the sixth insulating layer (107).

[0106] The data line (DL) is electrically connected to the connecting electrode (173) through a contact hole (81) penetrating the sixth insulating layer (107), and can be electrically connected to the source region (123b) of the second transistor (T2).

[0107] The first power supply voltage line (PL) can be electrically connected to the connecting electrode (174) through a contact hole (82) penetrating the sixth insulating layer (107). Accordingly, the first power supply voltage line (PL) extended in the y direction is connected to the electrode voltage line (HL) extended in the x direction, so that the first power supply voltage line (PL) can have a mesh structure. In one embodiment, as shown in FIG. 24, the first power supply voltage line (PL) may be interrupted in some pixel areas of the display area (DA). This is exemplary, and the first power supply voltage line (PL) may be extended in the y direction without any interruption in the display area (DA).

[0108] The connecting electrode (181) is electrically connected to the connecting electrode (172) through a contact hole (83) penetrating the sixth insulating layer (107), and can be electrically connected to the source region (123f) of the sixth transistor (T6).

[0109] As illustrated in FIGS. 9, 10 and 25, a seventh insulating layer (108) may be disposed on a sixth insulating layer (107), and a pixel electrode may be disposed on the seventh insulating layer (108). FIG. 25 illustrates a pixel electrode (PE1) of a first pixel (PX1), a pixel electrode (PE2) of a second pixel (PX2), and a pixel electrode (PE3) of a third pixel (PX3). Each pixel electrode (PE1, PE2, PE3) may include a first region corresponding to a light-emitting region and a second region surrounding the first region.

[0110] The pixel electrode (PE1) can be electrically connected to the connecting electrode (181) through a contact hole (91) penetrating the seventh insulating layer (108) and electrically connected to the first transistor (T1) through the sixth transistor (T6). The contact hole (91) can overlap with the second region of the pixel electrode (PE1).

[0111] An eighth insulating layer (109), which is a pixel defining layer, may be disposed on a pixel electrode (PE1). The eighth insulating layer (109) serves to define a pixel by having an opening (OP) corresponding to the light-emitting region of each pixel. A light-emitting layer (EML) may be disposed in the opening (OP) of the eighth insulating layer (109), and a counter electrode (CAT) may be disposed on the light-emitting layer (EML). The pixel electrode (PE1), the light-emitting layer (EML), and the counter electrode (CAT) may constitute an organic light-emitting diode. The counter electrode (CAT) may be formed integrally in a plurality of organic light-emitting diodes and may correspond to a plurality of pixel electrodes. Although not illustrated, at least one additional functional layer may be disposed on the upper and / or lower layer of the light-emitting layer (EML).

[0112] FIG. 26 is a diagram showing the arrangement of the first initialization voltage line (VL1) and the second initialization voltage line (VL2) in a display area according to one embodiment.

[0113] Referring to FIG. 26, in the display area (DA), a pixel circuit of the first pixel (PX1) or the third pixel (PX3) may be placed in the first pixel area (PXA1) according to the pixel arrangement of FIG. 6, and a pixel circuit of the second pixel (PX2) may be placed in the second pixel area (PXA2). That is, an initialization transistor (TB) of the first pixel (PX1) or an initialization transistor (TB) of the third pixel (PX3) may be placed in the first pixel area (PXA1), and an initialization transistor (TB) of the second pixel (PX2) may be placed in the second pixel area (PXA2). The first pixel (PX1) may be a red pixel (R), the second pixel (PX2) may be a green pixel (G), and the third pixel (PX3) may be a blue pixel (B). A first column (M1) in which the pixel circuits of the first pixel (PX1) and the third pixel (PX3) are alternately arranged in the y direction, and a second column (M2) in which the pixel circuits of the second pixel (PX2) are repeatedly arranged in the y direction can alternate in the x direction.

[0114] In each row, the first initialization voltage line (VL1) and the second initialization voltage line (VL2) may be placed on different layers, respectively. For example, as shown in FIG. 21, the first initialization voltage line (VL1) may be placed on the fifth insulating layer (106), and as shown in FIG. 23, the second initialization voltage line (VL2) may be placed on the fourth insulating layer (105). The second initialization voltage line (VL2) may be placed on the layer between the gate electrode (131h) of the initialization transistor (TB) and the first initialization voltage line (VL1). In another embodiment, the second initialization voltage line (VL2) may be placed on the same layer as the upper electrode of the capacitor (Cst).

[0115] The first initialization voltage line (VL1) may be extended in the x-direction in a zigzag shape in which the first part (VA1), the third part (VA3), and the second part (VA2) are repeated in sequence. The first initialization voltage line (VL1) may include a fourth part (VAP) that is electrically connected to the initialization transistor (TB) in the first pixel area (PXA1) where the initialization transistor (TB) of the first pixel (PX1) is placed. The fourth part (VAP) of the first initialization voltage line (VL1) overlaps with the semiconductor layer of the initialization transistor (TB) and may make direct contact with the semiconductor layer of the initialization transistor (TB) through a contact hole (CH1) (e.g., the contact hole (67) in FIG. 20).

[0116] The first initial voltage line (VL1) can be electrically connected to the first initial voltage supply line (15a) in the surrounding area (PA). For example, in the surrounding area (PA), the first initial voltage supply line (15a) may be placed on the sixth insulating layer (107) and electrically connected to the first initial voltage line (VL1) extending from the display area (DA) through a contact hole (41) penetrating the sixth insulating layer (107).

[0117] The second initialization voltage line (VL2) can be electrically connected to the initialization transistor (TB) through the connecting electrode (CL) in each pixel area where the connecting electrode (CL) (e.g., the connecting electrode (178) of FIG. 22) is placed, for example, in the second pixel area (PXA2) where the initialization transistor (TB) of the second pixel (PX2) is placed and in the first pixel area (PXA1) where the initialization transistor (TB) of the third pixel (PX3) is placed. The connecting electrode (CL) can be electrically connected to the semiconductor layer of the initialization transistor (TB) through the contact hole (CH2) (e.g., the contact hole (63) of FIG. 22) and can be electrically connected to the second initialization voltage line (VL2) through the contact hole (CH3) (e.g., the contact hole (64) of FIG. 22).

[0118] The second initial voltage line (VL2) can be electrically connected to the second initial voltage supply line (15b) in the peripheral area (PA). For example, in the peripheral area (PA), the second initial voltage supply line (15b) may be placed on the same layer as the data line (DL), i.e., on the sixth insulating layer (107), and may be electrically connected to the second initial voltage line (VL2) extending from the display area (DA) through a contact hole (42) penetrating the third to sixth insulating layers (104 to 107). The width of the first initial voltage supply line (15a) may be greater than the width of the second initial voltage supply line (15b).

[0119] In each row (N1, N2), the pair of first pixel region (PXA1) in which the fourth part (VAP) of the first initialization voltage line (VL1) is connected to the initialization transistor (TB) and the pair of second pixel region (PXA2) in which the second initialization voltage line (VL2) is connected to the initialization transistor (TB) through the connecting electrode (CL) and the pair of first pixel region (PXA1) and second pixel region (PXA2) in which the second initialization voltage line (VL2) is connected to the initialization transistor (TB) through the connecting electrode (CL) may alternate.

[0120] In the first column (M1), a first pixel region (PXA1) in which the fourth part (VAP) of the first initialization voltage line (VL1) is connected to the initialization transistor (TB) and a first pixel region (PXA1) in which the second initialization voltage line (VL2) is connected to the initialization transistor (TB) through the connecting electrode (CL) may alternate. In the second column (M2), a second pixel region (PXA2) in which the second initialization voltage line (VL2) is connected to the initialization transistor (TB) through the connecting electrode (CL) may be repeated.

[0121] The aforementioned embodiment is an example in which the initialization transistor (TB) of the first pixel (PX1), which is a red pixel (R), is connected to the first initialization voltage line (VL1), and the initialization transistor (TB) of the second pixel (PX2), which is a green pixel (G), and the initialization transistor (TB) of the third pixel (PX3), which is a blue pixel (B), are connected to the second initialization voltage line (VL2). The pixel electrode of the organic light-emitting diode (OLED) of the first pixel (PX1) is electrically connected to the first initialization voltage line (VL1) via the initialization transistor (TB) to receive the first initialization voltage (Vaint1), and the pixel electrode of the organic light-emitting diode (OLED) of the second pixel (PX2) and the pixel electrode of the organic light-emitting diode (OLED) of the third pixel (PX3) are electrically connected to the second initialization voltage line (VL2) via the initialization transistor (TB) to receive the second initialization voltage (Vaint2). Embodiments of the present invention are not limited thereto.

[0122] FIGS. 27 to 29 are schematic diagrams illustrating the connection relationship between a pixel and an initialization voltage line according to one embodiment.

[0123] In one embodiment, as shown in FIG. 27, the pixel circuit of the second pixel (PX2), which is a green pixel (G), is connected to the first initialization voltage line (VL1), and the pixel circuit of the first pixel (PX1), which is a red pixel (R), and the pixel circuit of the third pixel (PX3), which is a blue pixel (B), can be connected to the second initialization voltage line (VL2). The pixel electrode of the organic light-emitting diode (OLED) of the second pixel (PX2) is electrically connected to the first initialization voltage line (VL1) via the initialization transistor (TB) to receive the first initialization voltage (Vaint1), and the pixel electrode of the organic light-emitting diode (OLED) of the first pixel (PX1) and the pixel electrode of the organic light-emitting diode (OLED) of the third pixel (PX3) are electrically connected to the second initialization voltage line (VL2) via the initialization transistor (TB) to receive the second initialization voltage (Vaint2).

[0124] In one embodiment, as shown in FIG. 28, the pixel circuit of the third pixel (PX3), which is a blue pixel (B), is connected to the first initialization voltage line (VL1), and the pixel circuit of the first pixel (PX1), which is a red pixel (R), and the pixel circuit of the second pixel (PX2), which is a green pixel (G), can be connected to the second initialization voltage line (VL2). The pixel electrode of the organic light-emitting diode (OLED) of the third pixel (PX3) is electrically connected to the first initialization voltage line (VL1) via the initialization transistor (TB) to receive the first initialization voltage (Vaint1), and the pixel electrode of the organic light-emitting diode (OLED) of the first pixel (PX1) and the pixel electrode of the organic light-emitting diode (OLED) of the second pixel (PX2) are electrically connected to the second initialization voltage line (VL2) via the initialization transistor (TB) to receive the second initialization voltage (Vaint2).

[0125] In one embodiment, as shown in FIG. 29, the pixel circuit of the first pixel (PX1), which is a red pixel (R), may be connected to the first initialization voltage line (VL1), the pixel circuit of the second pixel (PX2), which is a green pixel (G), may be connected to the second initialization voltage line (VL2), and the pixel circuit of the third pixel (PX3), which is a blue pixel (B), may be connected to the third initialization voltage line (VL3).

[0126] The first initialization voltage line (VL1), the second initialization voltage line (VL2), and the third initialization voltage line (VL3) may be placed on different layers. For example, the second initialization voltage line (VL2) may be placed between the second insulating layer (103) and the third insulating layer (104), the third initialization voltage line (VL3) may be placed between the fourth insulating layer (105) and the fifth insulating layer (106), and the first initialization voltage line (VL1) may be placed between the fifth insulating layer (106) and the sixth insulating layer (107). At this time, the second initialization voltage line (VL2) and the third initialization voltage line (VL3) may be placed overlapping with the light-emitting control line (EL).

[0127] The pixel electrode of the organic light-emitting diode (OLED) of the first pixel (PX1) is electrically connected to the first initialization voltage line (VL1) via the initialization transistor (TB) to receive the first initialization voltage (Vaint1), the pixel electrode of the organic light-emitting diode (OLED) of the second pixel (PX2) is electrically connected to the second initialization voltage line (VL2) via the initialization transistor (TB) to receive the second initialization voltage (Vaint2), and the pixel electrode of the organic light-emitting diode (OLED) of the third pixel (PX3) is electrically connected to the third initialization voltage line (VL3) via the initialization transistor (TB) to receive the third initialization voltage (Vaint3).

[0128] FIG. 30 is a diagram showing the arrangement of a first initialization voltage line (VL1) and a second initialization voltage line (VL2) in a display area according to one embodiment. FIG. 30 is an embodiment in which, as shown in FIG. 27, the initialization transistor (TB) of the second pixel (PX2), which is a green pixel (G), is connected to the first initialization voltage line (VL1), and the initialization transistor (TB) of the first pixel (PX1), which is a red pixel (R), and the initialization transistor (TB) of the third pixel (PX3), which is a blue pixel (B), are connected to the second initialization voltage line (VL2).

[0129] The embodiment of FIG. 30 is different from the embodiment shown in FIG. 26 in that the pixel in which the first initialization voltage line (VL1) and the second initialization voltage line (VL2) are connected is different, and the arrangement of other elements is similar. For example, the first initialization voltage line (VL1) may be placed between the fifth insulating layer (106) and the sixth insulating layer (107), and the second initialization voltage line (VL2) may be placed between the fourth insulating layer (105) and the fifth insulating layer (106) while overlapping with the light emission control line (EL).

[0130] The first initialization voltage line (VL1) may extend in the x-direction in a zigzag shape. The first initialization voltage line (VL1) may include a fourth part (VAP) that is electrically connected to the initialization transistor (TB) in the second pixel area (PXA2) where the initialization transistor (TB) of the second pixel (PX2) is placed. The fourth part (VAP) of the first initialization voltage line (VL1) overlaps with the semiconductor layer of the initialization transistor (TB) and can make direct contact with the semiconductor layer of the initialization transistor (TB) through a contact hole (CH1). The first initialization voltage line (VL1) receives the first initialization voltage (Vaint1) from the first initialization voltage supply line (15a) of the peripheral area (PA) and can transmit it to the pixel electrode of the organic light-emitting diode (OLED) through the initialization transistor (TB).

[0131] The second initialization voltage line (VL2) can be electrically connected to the initialization transistor (TB) through the connection electrode (CL) in the first pixel area (PXA1) where the initialization transistor (TB) of the first pixel (PX1) is placed and in the first pixel area (PXA1) where the initialization transistor (TB) of the third pixel (PX3) is placed. The second initialization voltage line (VL2) can receive the second initialization voltage (Vaint2) from the second initialization voltage supply line (15b) of the peripheral area (PA) and transmit it to the pixel electrode of the organic light-emitting diode (OLED) through the initialization transistor (TB) connected to the connection electrode (178).

[0132] In each row, a first pixel region (PXA1) in which the fourth part (VAP) of the first initialization voltage line (VL1) is connected to the initialization transistor (TB) and a second pixel region (PXA2) in which the second initialization voltage line (VL2) is connected to the initialization transistor (TB) through the connecting electrode (CL) may alternate. In the first column (M1), the first pixel region (PXA1) in which the fourth part (VAP) of the first initialization voltage line (VL1) is connected to the initialization transistor (TB) may be repeated. In the second column (M1), the second pixel region (PXA2) in which the second initialization voltage line (VL2) is connected to the initialization transistor (TB) through the connecting electrode (CL) may be repeated.

[0133] FIG. 31 is an equivalent circuit diagram of a pixel circuit according to one embodiment. FIG. 32 and FIG. 33 are diagrams showing the arrangement of elements corresponding to the pixel circuit of FIG. 31.

[0134] Referring to FIG. 31, in the driving circuit portion (DRC) of the pixel circuit (PC), the first transistor (T1) may include a gate electrode connected to the second node (N2) and a gate electrode (BG) receiving the first power supply voltage (ELVDD). The rest of the configuration is the same as the pixel circuit shown in FIG. 5.

[0135] Referring to FIG. 32, a conductive layer (BML) may be arranged in a mesh structure extending in the x and y directions between the substrate (100) and the buffer layer (101) or between the buffer layer (101) and the first semiconductor layer (SACT). The conductive layer (BML) may include a lower gate electrode (BG), which is a region corresponding to the gate electrode (131a) of the first transistor (T1) of each pixel region, a horizontal portion (BMLH) extending in the x direction, and a vertical portion (BMLV) extending in the y direction. The lower gate electrode (BG) may face the gate electrode (131a) with the semiconductor layer in between. The conductive layer (BML) may receive a first power supply voltage (ELVDD). As shown in FIG. 33, an insulating layer may be disposed on top of the conductive layer (BML), and devices may be disposed on top of the insulating layer as shown in FIG. 11 to FIG. 18.

[0136] The pixel circuit (PC) according to an embodiment of the present invention is not limited to the number of transistors and capacitors and the circuit design described with reference to FIGS. 5 and FIGS. 31, and the number and circuit design can be varied. For example, the transistors of the pixel circuit including the initialization transistor (TB) may be P-type transistors, the transistors of the pixel circuit may be N-type transistors, and transistors and / or capacitors may be omitted and / or added.

[0137] FIGS. 34 to 43 are equivalent circuit diagrams of a pixel circuit according to one embodiment. Hereinafter, the differences from the pixel circuit of FIG. 5 or the pixel circuit of FIG. 31 will be explained mainly, and the description of other identical configurations will be omitted.

[0138] The pixel circuit (PC) shown in FIG. 34 is a modified example of the pixel circuit (PC) shown in FIG. 5 in which the third transistor (T3) and the fourth transistor (T4) are P-type transistors, the third transistor (T3) includes a third-1 transistor (T3-1) and a third-2 transistor (T3-2) connected in series, and the fourth transistor (T4) includes a fourth-1 transistor (T4-1) and a fourth-2 transistor (T4-2) connected in series. The other component configurations are the same as those of the pixel circuit in FIG. 5.

[0139] The pixel circuit (PC) illustrated in FIG. 35 is a modified example of the pixel circuit (PC) illustrated in FIG. 5 in which the seventh transistor (T7) is omitted, the third transistor (T3) and the fourth transistor (T4) are P-type transistors, the third transistor (T3) includes a third-1 transistor (T3-1) and a third-2 transistor (T3-2) connected in series, and the fourth transistor (T4) includes a fourth-1 transistor (T4-1) and a fourth-2 transistor (T4-2) connected in series. The gate electrode of the third transistor (T3) and the gate electrode of the initialization transistor (TB) are connected to the first gate line and can be controlled by the first scan signal (GW). The other component configurations are the same as those of the pixel circuit in FIG. 5.

[0140] The pixel circuit (PC) shown in FIG. 36 is a modified example of the pixel circuit (PC) shown in FIG. 31 in which the seventh transistor (T7) is omitted and a capacitor (Cb) is added between the gate electrode of the first transistor (T1) and the gate electrode of the second transistor (T2). The fourth scan signal (GB) supplied to the gate electrode of the initialization transistor (TB) may be the first scan signal (GW(n-1)) of the previous row. The other component configurations are the same as those of the pixel circuit in FIG. 31.

[0141] The pixel circuit (PC) illustrated in FIG. 37 is a modified example of the pixel circuit (PC) illustrated in FIG. 5 in which the seventh transistor (T7) is omitted, the third transistor (T3) and the fourth transistor (T4) are P-type transistors, the third transistor (T3) includes a third-1 transistor (T3-1) and a third-2 transistor (T3-2) connected in series, and the fourth transistor (T4) includes a fourth-1 transistor (T4-1) and a fourth-2 transistor (T4-2) connected in series. The gate electrode of the third transistor (T3) and the gate electrode of the initialization transistor (TB) are connected to the first gate line and can be controlled by the first scan signal (GW). The fourth transistor (T4) and the initialization transistor (TB) are connected to the same initialization voltage line (VL), so that the fourth transistor (T4) transmits the initialization signal (Vaint) to the gate electrode of the first transistor (T1), and the initialization transistor (TB) transmits the initialization signal (Vaint) to the pixel electrode of the organic light-emitting diode (OLED). The rest of the device configuration is the same as the pixel circuit of FIG. 5.

[0142] The pixel circuit (PC) shown in FIG. 38 is an example in which the seventh transistor (T7) is omitted from the pixel circuit (PC) shown in FIG. 5, and the first to sixth transistors (T1 to T6) and the initialization transistor (TB) are modified into N-type transistors. Node (Na) is a node where the first terminal of the first transistor (T1) and the second terminal of the fifth transistor (T5) are connected. Node (Nb) is a node where the gate electrode of the first transistor (T1), the second terminal of the third transistor (T3), and the second terminal of the fourth transistor (T4) are connected. Node (Nc) is a node where the second terminal of the first transistor (T1), the second terminal of the second transistor (T2), and the first terminal of the sixth transistor (T6) are connected.

[0143] Each of the first to sixth transistors (T1 to T6) and the initialization transistor (TB) may further include a lower gate electrode. The lower gate electrode of the first transistor (T1) may be connected to the node (Nc) and connected to its second terminal. Each of the second to sixth transistors (T1 to T6) and the initialization transistor (TB) may have its lower gate electrode connected to its gate electrode. The first terminal of the second transistor (T2) may be connected to a data line, and the second terminal may be connected to the node (Nc). The first terminal of the third transistor (T3) may be connected to the node (Na), and the second terminal may be connected to the node (Nb). The first terminal of the fourth transistor (T4) may be connected to a voltage line supplying a reference voltage (VREF), and the second terminal may be connected to the node (Nb). The first terminal of the fifth transistor (T5) is connected to the first power supply voltage line that supplies the first power supply voltage (ELVDD), and the second terminal can be connected to the node (Na). The first terminal of the sixth transistor (T6) is connected to the node (Nc), and the second terminal can be connected to the pixel electrode of the organic light-emitting diode (OLED). The first terminal of the initialization transistor (TB) is connected to the initialization voltage line, and the second terminal can be connected to the first electrode of the capacitor (Cst) and the pixel electrode of the organic light-emitting diode (OLED). The capacitor (Cst) can be connected between the node (Nb) and the pixel electrode of the organic light-emitting diode (OLED). The gate electrode of the third transistor (T3) and the gate electrode of the second transistor (T2) are connected to the first gate line and can be controlled by the first scan signal (GW).

[0144] The pixel circuit (PC) illustrated in FIG. 39 is a modified example of the pixel circuit (PC) illustrated in FIG. 5 in which the seventh transistor (T7) is omitted, the third transistor (T3) and the fourth transistor (T4) are P-type transistors, the third transistor (T3) includes a third-1 transistor (T3-1) and a third-2 transistor (T3-2) connected in series, the fourth transistor (T4) includes a fourth-1 transistor (T4-1) and a fourth-2 transistor (T4-2) connected in series, the fifth transistor (T5) includes a fifth-1 transistor (T5-1) and a fifth-2 transistor (T5-2) connected in series, and an eighth transistor (T8) is added. The eighth transistor (T8) can be connected between the intermediate node (N4) of the fifth-first transistor (T5-1) and the fifth-second transistor (T5-2) and the voltage line supplying the holding voltage (VSUS). The gate electrode of the eighth transistor (T8) can be controlled by the inversion signal (EMB) of the light emission control signal (EM). The capacitor (Cst) can be connected between the intermediate node (N4) and the gate electrode of the first transistor (T1). The gate electrode of the third transistor (T3) and the gate electrode of the second transistor (T2) can be connected to the first gate line and controlled by the first scan signal (GW). The fourth scan signal (GB) supplied to the gate electrode of the initialization transistor (TB) can be the second scan signal (GI(n+1)) of the next row. The other component configurations are identical to the pixel circuit of Fig. 5.

[0145] The pixel circuit (PC) illustrated in FIG. 40 is an example in which an 8th transistor (T8) and a 9th transistor (T9) are added to the pixel circuit (PC) illustrated in FIG. 38. Each of the 8th transistor (T8) and the 9th transistor (T9) further includes a lower gate electrode, and the lower gate electrode may be connected to its own gate electrode. The 8th transistor (T8) may be connected between the node (Nd) to which the lower gate electrode of the 1st transistor (T1) is connected and the pixel electrode of the organic light-emitting diode (OLED). The gate electrode of the 8th transistor (T8) may be connected to a light-emitting control line that supplies a light-emitting control signal (EM). The 9th transistor (T9) may be connected between the node (Nd) to which the lower gate electrode of the 1st transistor (T1) is connected and a voltage line that supplies a control voltage (VBML). The gate electrode of the ninth transistor (T9) can be controlled by the fourth scan signal (GB) supplied to the gate electrode of the initialization transistor (TB).

[0146] The pixel circuit (PC) shown in FIG. 41 is an example in which an 8th transistor (T8) and a capacitor (Chod) are added to the pixel circuit (PC) shown in FIG. 5, and the 3rd transistor (T3) and 4th transistor (T4) are modified into P-type transistors. The light emission control signal (EM1) applied to the gate electrode of the 5th transistor (T5) and the light emission control signal (EM2) applied to the gate electrode of the 6th transistor (T6) can be applied with different values. The capacitor (Chod) is connected between the 2nd terminal of the 2nd transistor (T2) and the gate electrode of the 1st transistor (T1), and the capacitor (Cst) can be connected between the 1st power supply voltage line and the 2nd terminal of the 2nd transistor (T2). The eighth transistor (T8) can be connected between a voltage line applying a reference voltage (VREF) and the second terminal of the second transistor (T2). The gate electrode of the eighth transistor (T8) can be controlled by a third scan signal (GC) applied from the third gate line.

[0147] The pixel circuit (PC) illustrated in FIG. 42 is a modified example of the pixel circuit (PC) illustrated in FIG. 38 in which the third transistor (T3) and the sixth transistor (T6) are omitted, a capacitor (Chold) is added, the second transistor (T2) is connected between the data line and the gate electrode of the first transistor (T1), and the gate electrode of the initialization transistor (TB) is controlled by the second scan signal (GI). The capacitor (Chold) can be connected between the first power supply voltage line and the pixel electrode of the organic light-emitting diode (OLED). The gate electrode of the fourth transistor (T4) can be controlled by the fifth scan signal (GR).

[0148] The pixel circuit (PC) illustrated in FIG. 43 is a modified example of the pixel circuit (PC) illustrated in FIG. 5 in which the driving circuit (DRC) includes a first transistor (T1), a second transistor (T2), and a capacitor (Cst). The second transistor (T2) may be connected between a data line and the gate electrode of the first transistor (T1), and the capacitor (Cst) may be connected between a first power supply voltage line and the gate electrode of the first transistor (T1).

[0149] FIG. 44 is a diagram schematically illustrating the operation of transmitting an initialization voltage according to temperature to a display panel according to one embodiment.

[0150] Referring to FIG. 44, the display device (1) may include a display panel (10), a display driving unit (32), and a sensor (40).

[0151] The sensor (40) may be embedded in the display device (1). The sensor (40) may include at least one light sensor that detects external light intensity, a light sensor that detects light intensity, a temperature sensor that detects external temperature or the temperature of the display device (1).

[0152] The display driving unit (32) may include a voltage generating unit (35) and a data driving circuit (37).

[0153] The data driving circuit (37) can generate a data signal (DATA) and transmit it to the data lines (DL) of the display panel (10).

[0154] The voltage generation unit (35) can determine the temperature based on detection information transmitted from the sensor (40). The voltage generation unit (35) can generate different initialization voltages (Vaint) depending on the temperature and output them to the display panel (10). The voltage generation unit (35) can determine that a temperature higher than the reference temperature is a high temperature, and a temperature lower than the reference temperature is a normal temperature. If the voltage generation unit (35) determines that the temperature is a high temperature, it can generate and output a first initialization voltage (Vaint1) and a second initialization voltage (Vaint2) corresponding to the high temperature, and if the temperature is determined to be a normal temperature, it can generate and output a first initialization voltage (Vaint1) and a second initialization voltage (Vaint2) corresponding to the normal temperature.

[0155] In one embodiment, the voltage generating unit (35) may generate and output a first initialization voltage (Vaint1) and a second initialization voltage (Vaint2) differently depending on the temperature of the display device (1). For example, at least one of the first initialization voltage (Vaint1) and the second initialization voltage (Vaint2) output by the voltage generating unit (35) may have different values ​​at a first temperature (high temperature) and a second temperature (normal temperature). Among the first initialization voltage (Vaint1) and the second initialization voltage (Vaint2), the first initialization voltage (Vaint1) may be different at the first temperature and the second temperature. Among the first initialization voltage (Vaint1) and the second initialization voltage (Vaint2), the second initialization voltage (Vaint2) may be different at the first temperature and the second temperature. The first initialization voltage (Vaint1) and the second initialization voltage (Vaint2) may each be different at the first temperature and the second temperature.

[0156] The display driving unit (32) is equipped with a memory, and the voltage generating unit (35) can determine whether the temperature corresponding to the detection information received from the sensor (40) is a high temperature or a normal temperature by using a lookup table that indicates the relationship between the detection information and the temperature stored in the memory.

[0157] In the memory, an initialization voltage (Vaint) at high temperature and an initialization voltage (Vaint) at normal temperature may be stored for each color pixel. In another embodiment, the memory may store initialization voltages (Vaint) for multiple temperatures for each color pixel. The voltage generation unit (35) may generate a first initialization voltage (Vaint1) and a second initialization voltage (Vaint2) for each color pixel selected according to the temperature of the display device (1) from the memory and output them to the first initialization voltage supply line (15a) and the second initialization voltage supply line (15b) of the display panel (10), respectively.

[0158] Meanwhile, in the embodiments of the present invention, the pixel array can be understood as an array of light-emitting regions. The pixel array according to the embodiments of the present invention is not limited to the above array. For example, the present invention may be applied to a pixel array having a stripe array, a mosaic array, or a delta array. In addition, the present invention may be applied to a pixel array structure further comprising white pixels that emit white light.

[0159] Embodiments of the present invention apply different initialization voltages to one electrode of each organic light-emitting diode that emits different colors, thereby resolving the problem of degraded image quality characteristics caused by different electrical characteristics due to differences in the material characteristics of the organic light-emitting diodes.

[0160] As such, the present invention has been described with reference to an embodiment illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0161] 100: Substrate 101: Buffer layer 102 to 109: 1st to 8th insulating layers VL, VL1, VL2: Initialization voltage lines VIL: Node initialization voltage line TB: Initialization transistor

Claims

Claim 1 A display panel comprising: a first pixel circuit; and a second pixel circuit adjacent to the first pixel circuit; wherein each of the first pixel circuit and the second pixel circuit comprises: a driving transistor that outputs a driving current to a display element; a first transistor that includes a first semiconductor layer and transmits a first initialization voltage to the gate electrode of the driving transistor; and a second transistor that includes a second semiconductor layer and transmits a second initialization voltage to the pixel electrode of the display element; wherein the first initialization voltage supplied to the first pixel circuit and the first initialization voltage supplied to the second pixel circuit are the same, and the second initialization voltage supplied to the first pixel circuit and the second initialization voltage supplied to the second pixel circuit are different from each other, and the first semiconductor layer comprises an oxide semiconductor. Claim 2 In claim 1, the second semiconductor layer comprises a silicon semiconductor, forming a display panel. Claim 3 A display panel according to claim 1, wherein the second semiconductor layer comprises an oxide semiconductor. Claim 4 A display panel according to claim 1, wherein the display element connected to the first pixel circuit emits light of a first color, and the display element connected to the second pixel circuit emits light of a third color. Claim 5 A display panel according to claim 1, wherein the first transistors of the first pixel circuit and the second pixel circuit are connected to a first initialization voltage line that transmits the first initialization voltage, the second transistor of the first pixel circuit is connected to a second initialization voltage line that transmits the second initialization voltage, and the second transistor of the second pixel circuit is connected to a third initialization voltage line that transmits the second initialization voltage. Claim 6 In paragraph 5, the second initialization voltage line and the third initialization voltage line are arranged on different layers of the display panel. Claim 7 A display panel according to claim 5, wherein the second initialization voltage line is connected by direct contact to the second semiconductor layer of the second transistor of the first pixel circuit, and the third initialization voltage line is connected to the second semiconductor layer of the second transistor of the second pixel circuit using a connecting electrode. Claim 8 A display panel further comprising: a first initial voltage supply line disposed in a peripheral area outside the display area and supplying the second initial voltage to the second initial voltage line; and a second initial voltage supply line disposed in the peripheral area and supplying the second initial voltage to the third initial voltage line. Claim 9 A display panel according to claim 1, wherein the second initialization voltage at a temperature higher than the reference temperature and the second initialization voltage at a temperature lower than the reference temperature are different. Claim 10 A display panel according to claim 1, wherein the first pixel circuit and the second pixel circuit are line-symmetric with respect to the boundary line between the first pixel circuit and the second pixel circuit. Claim 11 A display panel according to claim 1, wherein the gate electrode of the first transistor is connected to a first gate line that transmits a first scan signal, and the gate electrode of the second transistor is connected to a second gate line that transmits a second scan signal. Claim 12 A display panel according to claim 1, further comprising: a conductive layer between a substrate and a semiconductor layer of the driving transistor; a first insulating layer between the substrate and the conductive layer; and a second insulating layer between the conductive layer and the semiconductor layer of the driving transistor. Claim 13 In paragraph 12, the channel region of the semiconductor layer of the driving transistor overlaps the conductive layer, forming a display panel. Claim 14 In Clause 12, the conductive layer is a display panel that receives a constant voltage. Claim 15 A display panel comprising a plurality of pixels; and a voltage generation unit for supplying a first initialization voltage and a second initialization voltage to the plurality of pixels; wherein the plurality of pixels include a first pixel and a second pixel, and each of the first pixel and the second pixel includes a pixel circuit and a display element connected to the pixel circuit, and the pixel circuit includes a first transistor that outputs a driving current to the display element, and a second transistor that includes a second semiconductor layer and transmits the first initialization voltage to the gate electrode of the first transistor. An electronic device comprising: a third transistor that transmits the second initialization voltage to a pixel electrode of the display element, wherein the first initialization voltage supplied to the first pixel and the first initialization voltage supplied to the second pixel are identical, the second initialization voltage supplied to the first pixel and the second initialization voltage supplied to the second pixel are different from each other, and the second semiconductor layer comprises an oxide semiconductor. Claim 16 In paragraph 15, the above third semiconductor layer comprises a silicon semiconductor, an electronic device. Claim 17 In claim 15, the electronic device wherein the third semiconductor layer comprises an oxide semiconductor. Claim 18 An electronic device according to claim 15, wherein the display element of the first pixel emits light of a first color, and the display element of the second pixel emits light of a third color. Claim 19 An electronic device according to claim 15, wherein the second transistors of the first pixel and the second pixel are connected to a first initialization voltage line that transmits the first initialization voltage, the third transistor of the first pixel is connected to a second initialization voltage line that transmits the second initialization voltage, and the third transistor of the second pixel is connected to a third initialization voltage line that transmits the second initialization voltage. Claim 20 An electronic device according to claim 19, further comprising a sensor for detecting temperature; wherein the voltage generating unit generates the second initialization voltage differently depending on the temperature.

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