Display apparatus

Abstract

The present invention provides a display device capable of displaying high-quality images while reducing the area of ​​dead space, comprising: a first semiconductor layer disposed on a substrate; a first gate layer located above the first semiconductor layer and including a driving gate electrode; a second gate layer located above the first gate layer and including a capacitor upper electrode; a first connection electrode layer located above the second gate layer and including a transmission line; a second connection electrode layer located above the first connection electrode layer and including a horizontal connection line extended in the first direction; and a third connection electrode layer located above the second connection electrode layer and including a vertical connection line extended in the second direction intersecting the first direction.

Description

Technology Field

[0001] Embodiments of the present invention relate to a display device, and more specifically, to a display device capable of displaying high-quality images while reducing the area of ​​dead space. Background Technology

[0002] Generally, in display devices such as organic light-emitting diode (OLED) displays, thin-film transistors are placed in each pixel to control the brightness of each pixel. These thin-film transistors control the brightness of the corresponding pixel according to the transmitted data signal, etc.

[0003] Data signals are transmitted to each (sub)pixel through data wiring from a driving unit located in the peripheral area outside the display area. The problem to be solved

[0004] Conventional display devices had a problem in that the area where the driving unit and other components were located was large, or the area extending from the driving unit to the display area was large. As a result, there was a problem in that the dead space, where display elements are not placed, was excessively large.

[0005] The present invention aims to solve various problems, including those mentioned above, by providing a display device capable of displaying high-quality images while reducing the area of ​​dead space. However, this objective is exemplary and does not limit the scope of the present invention. means of solving the problem

[0006] According to one aspect of the present invention, a display device is provided comprising: a first semiconductor layer disposed on a substrate; a first gate layer located above the first semiconductor layer and including a driving gate electrode; a second gate layer located above the first gate layer and including a capacitor upper electrode; a first connection electrode layer located above the second gate layer and including a transmission line; a second connection electrode layer located above the first connection electrode layer and including a horizontal connection line extended in the first direction; and a third connection electrode layer located above the second connection electrode layer and including a vertical connection line extended in the second direction intersecting the first direction.

[0007] A second semiconductor layer located between the second gate layer and the first connection electrode layer, and a third gate layer located between the second semiconductor layer and the first connection electrode layer and including a compensation gate electrode may be further provided.

[0008] The third gate layer may further include a gate wiring extended in the first direction.

[0009] The above gate wiring may intersect with the above vertical connection wiring.

[0010] The first semiconductor layer comprises polysilicon, and the second semiconductor layer may comprise an oxide semiconductor.

[0011] The third connecting electrode layer further includes a data line extended in the second direction, and the vertical connecting line can be electrically connected to the data line and the horizontal connecting line.

[0012] The above substrate includes a display area and a peripheral area outside the display area, and the vertical connection wiring can be electrically connected to the data wiring in the peripheral area.

[0013] The above vertical connection wiring and the above data wiring may be a single unit.

[0014] The above horizontal connecting wire can be electrically connected to the above vertical connecting wire within the above display area.

[0015] The above vertical connection wiring is connected to the above horizontal connection wiring through a contact hole, and the above second connection electrode layer may further provide an auxiliary horizontal connection wiring that is spaced apart from the above horizontal connection wiring, is electrically insulated from the above horizontal connection wiring and the above data wiring, and has an extension axis identical to the extension axis of the above horizontal connection wiring.

[0016] The above vertical connecting wire is connected to the above horizontal connecting wire through a contact hole, and the above third connecting electrode layer may further provide an auxiliary vertical connecting wire that is spaced apart from the above vertical connecting wire, is electrically insulated from the above horizontal connecting wire and the above vertical connecting wire, and has an extension axis identical to the extension axis of the above vertical connecting wire.

[0017] The third connecting electrode layer may further include an additional vertical connecting wire that extends in the second direction and is electrically connected to the horizontal connecting wire within the display area.

[0018] The third connecting electrode layer may further comprise an auxiliary additional vertical connecting wire that is spaced apart from the additional vertical connecting wire, is electrically insulated from the horizontal connecting wire and the additional vertical connecting wire, and has an extension axis identical to the extension axis of the additional vertical connecting wire.

[0019] The third connecting electrode layer further includes a data line extended in the second direction, and the substrate includes a display area and a peripheral area outside the display area, and the horizontal connecting line can be electrically connected to the data line in the display area.

[0020] The above data wiring can be connected to the above horizontal connection wiring through a contact hole.

[0021] The second connection electrode layer may further include an auxiliary horizontal connection wire that is spaced apart from the horizontal connection wire, is electrically insulated from the horizontal connection wire and the data wire, and has an extension axis identical to the extension axis of the horizontal connection wire.

[0022] The above vertical connection wiring can be electrically insulated from the above data wiring and the above horizontal connection wiring.

[0023] The above vertical connecting wire may intersect with the above horizontal connecting wire.

[0024] The third connecting electrode layer may further include an additional vertical connecting wire that extends in the second direction and is electrically connected to the horizontal connecting wire within the display area.

[0025] The third connecting electrode layer may further comprise an auxiliary additional vertical connecting wire that is spaced apart from the additional vertical connecting wire, is electrically insulated from the horizontal connecting wire and the additional vertical connecting wire, and has an extension axis identical to the extension axis of the additional vertical connecting wire.

[0026] According to one aspect of the present invention, a display device is provided comprising: an organic light-emitting diode; a driving transistor capable of controlling the amount of current flowing from a first node connected to a driving voltage line in response to a voltage applied to a second node; a switching transistor capable of transmitting a data signal from a data line to the first node in response to a voltage applied to a scan line; an initialization transistor capable of applying an initialization voltage from an initialization voltage line to the second node in response to a voltage applied to a previous scan line, and comprising an initialization semiconductor layer located on an insulating layer covering a driving semiconductor layer included in the driving transistor; a transmission wire located on an insulating layer covering an initialization gate electrode included in the initialization transistor and electrically connecting the initialization semiconductor layer to the driving gate electrode included in the driving transistor; a horizontal connection wire located on an insulating layer covering the transmission wire and extended in a first direction; and a vertical connection wire located on an insulating layer covering the horizontal connection wire and extended in a second direction intersecting the first direction.

[0027] The vertical connecting wire can be electrically connected to the horizontal connecting wire through a contact hole formed in the insulating layer covering the horizontal connecting wire.

[0028] The above driving semiconductor layer includes polysilicon, and the above initialization semiconductor layer may include an oxide semiconductor.

[0029] The above data line and the above vertical connection wiring may be located on the same layer.

[0030] The above data line can be extended in the above second direction.

[0031] The above driving voltage line and the above vertical connection wiring may be located on the same layer.

[0032] Other aspects, features, and advantages other than those described above will become clear from the specific details, claims, and drawings for implementing the invention below. Effects of the invention

[0033] According to one embodiment of the present invention as described above, a display device capable of displaying high-quality images while reducing the area of ​​dead space can be implemented. Of course, the scope of the present invention is not limited by this effect. Brief explanation of the drawing

[0034] FIG. 1 is a plan view schematically illustrating a part of a display device according to one embodiment of the present invention. FIG. 2 is a side view schematically illustrating the display device of FIG. 1. FIG. 3 is a plan view schematically illustrating a part of the display device of FIG. 1. FIGS. 4 and FIGS. 5 are schematic plan views showing enlarged portion A of the display device shown in FIG. 3. Figure 6 is an equivalent circuit diagram of one pixel included in the display device of Figure 1. FIG. 7 is a schematic layout diagram illustrating the locations of transistors and capacitors, etc., in pixels included in the display device of FIG. 1. FIGS. 8 to 15 are layout diagrams schematically illustrating, layer by layer, the components such as transistors and capacitors of the display device shown in FIG. 7. FIG. 16 is a cross-sectional view schematically illustrating cross-sections taken along the lines I-I', II-II', and III-III' of the display device shown in FIG. 7. FIG. 17 is a plan view schematically illustrating a part of a display device according to one embodiment of the present invention. FIG. 18 is a plan view schematically illustrating a part of a display device according to one embodiment of the present invention. FIGS. 19 and FIGS. 20 are plan views illustrating enlarged sections B and C of the display device of FIG. 18. FIGS. 21 and FIGS. 22 are plan views illustrating enlarged portions of a display device according to one embodiment of the present invention. FIG. 23 is a plan view schematically illustrating a part of a display device according to one embodiment of the present invention. FIG. 24 is a plan view showing an enlarged view of part D of the display device of FIG. 23. FIG. 25 is a plan view schematically illustrating a part of a display device according to one embodiment of the present invention. Specific details for implementing the invention

[0035] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0036] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0037] In the following embodiments, when various components such as layers, films, regions, and plates are described as being "on" another component, this includes not only cases where they are "directly on" another component, but also cases where other components are interposed between them. Furthermore, for convenience of explanation, the size of components in the drawings may be exaggerated or reduced. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is depicted.

[0038] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to three axes in an orthogonal coordinate system and can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0039] FIG. 1 is a plan view schematically illustrating a part of a display device according to one embodiment of the present invention, and FIG. 2 is a side view schematically illustrating the display device of FIG. 1. Although a part of the display device according to the present embodiment is bent as shown in FIG. 2, it is depicted as not bent for convenience in FIG. 1.

[0040] As illustrated in FIGS. 1 and 2, the display device according to the present embodiment includes a display panel (10). Any display device that includes a display panel (10) is possible. For example, the display device may be various products such as a smartphone, tablet, laptop, television, or billboard.

[0041] The display panel (10) includes a display area (DA) and a peripheral area (PA) outside the display area (DA). The display area (DA) is a portion that displays an image, and a plurality of pixels may be arranged in the display area (DA). When viewed from a direction approximately perpendicular to the display panel (10), the display area (DA) may have various shapes, such as a circle, an ellipse, a polygon, or a specific geometric shape. In FIG. 1, the display area (DA) is shown having a shape of an approximately rectangular shape with rounded corners.

[0042] A peripheral area (PA) may be positioned on the outer side of a display area (DA). The peripheral area (PA) may include a first peripheral area (PA1) that partially encloses one corner portion (in the -y direction and -x direction) of the display area (DA), and a second peripheral area (PA2) located on one side (in the -y direction) outside the display area (DA). The second peripheral area (PA2) may be located adjacent to the first peripheral area (PA1). That is, the second peripheral area (PA2) may be located in the direction of the center of the display panel (10) relative to the first peripheral area (PA1). The width (in the x-axis direction) of the second peripheral area (PA2) may be narrower than the width (in the x-axis direction) of the display area (DA). Through this structure, at least a portion of the second peripheral area (PA2) can be easily bent as described below.

[0043] Of course, since the display panel (10) includes a substrate (100, see FIG. 3), it can be said that the substrate (100) has a display area (DA) and a peripheral area (PA) as described above. For convenience, the following description assumes that the substrate (100) has a display area (DA) and a peripheral area (PA).

[0044] The display panel (10) may also have a main area (MR), a bending area (BR) outside the main area (MR), and a sub-area (SR) located opposite the main area (MR) with the bending area (BR) at the center. In the bending area (BR), the display panel (10) is bent as shown in FIG. 2, so that when viewed in the z-axis direction, at least a portion of the sub-area (SR) overlaps with the main area (MR). Of course, the present invention is not limited to a bent display device and can also be applied to a non-bent display device. The sub-area (SR) may be a non-display area as described below. By causing the display panel (10) to bend in the bending area (BR), the non-display area may not be visible when the display device is viewed from the front (-z direction), or even if it is visible, the visible area may be minimized.

[0045] A driving chip (20) may be disposed in a sub-region (BR) of a display panel (10). The driving chip (20) may include an integrated circuit that drives the display panel (10). Such an integrated circuit may be a data driving integrated circuit that generates a data signal, but the present invention is not limited thereto.

[0046] The driving chip (20) may be mounted on a sub-region (SR) of the display panel (10). The driving chip (20) is mounted on the same surface as the display area (DA), but as the display panel (10) is bent in the bending area (BR) as described above, the driving chip (20) may be located on the back surface of the main area (MR).

[0047] A printed circuit board (30), etc., may be attached to the end of the sub-region (SR) of the display panel (10). Such a printed circuit board (30), etc., may be electrically connected to a driving chip (20), etc., through a pad (not shown) on the board.

[0048] In the following description, an organic light-emitting display device is used as an example to describe a display device according to one embodiment of the present invention, but the display device of the present invention is not limited thereto. As another embodiment, the display device of the present invention may be an inorganic light-emitting display (Inorganic Light Emitting Display or Inorganic EL Display Device) or a display device such as a quantum dot light-emitting display. For example, the light-emitting layer of a display element included in the display device may include an organic material or an inorganic material. In addition, the display device may include a light-emitting layer and a quantum dot located on the path of light emitted from the light-emitting layer.

[0049] FIG. 3 is a plan view schematically illustrating a part of the display panel (10) included in the display device of FIG. 1.

[0050] The display panel (10) includes a substrate (100). Various components included in the display panel (10) may be located on the substrate (100). The substrate (100) may include glass, metal, or polymer resin. As described above, when the display panel (10) is bent in a bending region (BR), the substrate (100) needs to have flexible or bendable properties. In this case, the substrate (100) may include a polymer resin such as, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Of course, the substrate (100) may have a multilayer structure including two layers containing such a polymer resin and a barrier layer containing an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride) interposed between the layers, and various other variations are possible.

[0051] A plurality of pixels (P) are located in the display area (DA). Each of the pixels (P) represents a sub-pixel and may include a display element such as an organic light-emitting diode (OLED). The pixels (P) may emit light, for example, red, green, blue, or white.

[0052] A pixel (P) can be electrically connected to outer circuits placed in a peripheral area (PA). A first scan driving circuit (11), a second scan driving circuit (12), a light emission control driving circuit (13), a terminal (14), a first power supply wiring (15), and a second power supply wiring (16) may be placed in the peripheral area (PA).

[0053] The first scan driving circuit (11) can provide a scan signal to a pixel (P) through a scan line (SL). The second scan driving circuit (12) can be arranged parallel to the first scan driving circuit (11) with a display area (DA) in between. Some of the pixels (P) placed in the display area (DA) can be electrically connected to the first scan driving circuit (11), and the rest can be connected to the second scan driving circuit (12). If necessary, the second scan driving circuit (12) can be omitted, and all pixels (P) placed in the display area (DA) can be electrically connected to the first scan driving circuit (11).

[0054] The light emission control driving circuit (13) is positioned on the side of the first scan driving circuit (11) and can provide a light emission control signal to the pixel (P) through the light emission control line (EL). Although FIG. 3 shows the light emission control driving circuit (13) positioned only on one side of the display area (DA), the light emission control driving circuit (13) may be positioned on both sides of the display area (DA), just like the first scan driving circuit (11) and the second scan driving circuit (12).

[0055] The terminal (14) may be placed in the second peripheral region (PA2) of the substrate (100). The terminal (14) may be exposed without being covered by an insulating layer and may be electrically connected to the printed circuit board (30). The terminal (34) of the printed circuit board (30) may be electrically connected to the terminal (14) of the display panel (10).

[0056] The printed circuit board (30) transmits a signal or power from a control unit (not shown) to the display panel (10). The control signal generated by the control unit can be transmitted to the driving circuits (11, 12, 13) respectively through the printed circuit board (30). Additionally, the control unit can transmit a first power voltage (ELVDD, see FIG. 4) to the first power supply line (15) and provide a second power voltage (ELVSS, see FIG. 4) to the second power supply line (16). The first power voltage (ELVDD or driving voltage) is transmitted to each pixel (P) through a driving voltage line (PL) connected to the first power supply line (15), and the second power voltage (ELVSS or common voltage) can be transmitted to the opposing electrode of the pixel (P) connected to the second power supply line (16). The first power supply wiring (15) may have a shape extending in one direction (e.g., x-axis direction) from the lower side of the second area (DA2). The second power supply wiring (16) may have a loop shape with one side open, and may have a shape that partially surrounds the display area (DA).

[0057] Meanwhile, the control unit generates a data signal, and the generated data signal is transmitted to the input line (IL) through the driving chip (20) and can be transmitted to the pixel (P) through the data line (DL) connected to the input line (IL).

[0058] For reference, "line" may mean "wiring." This applies to the embodiments and variations described below.

[0059] FIGS. 4 and FIGS. 5 are schematic plan views showing enlarged portion A of the display device shown in FIG. 3.

[0060] Various signals may be applied to the display area (DA). For example, data signals for controlling the brightness of each pixel may be applied to the display area (DA). To this end, as shown in FIG. 4, data lines (DL1 to DL6) that are arranged in a first direction (x-axis direction) so as to be approximately parallel to each other and extend in a second direction (y-axis direction) that intersects the first direction may be located within the display area (DA). If necessary, the data lines (DL1 to DL6) may have a shape that extends from the surrounding area (PA) into the display area (DA), as shown in FIG. 4. Of course, various wirings other than the data lines (DL1 to DL6), such as power wiring (not shown) or scan lines (not shown), may also be located inside or outside the display area (DA).

[0061] In the peripheral area (PA), specifically the second peripheral area (PA2), the first input line (IL1) to the sixth input line (IL6) may be located. These first input line (IL1) to the sixth input line (IL6) may be connected to a driving chip (20) to receive data signals. The first data line (DL1) to the sixth data line (DL6) may be electrically connected to the first input line (IL1) to the sixth input line (IL6) to transmit data signals to pixels within the display area (DA).

[0062] In FIGS. 4 and 5, six input lines and six data lines are shown for convenience of explanation. However, the present invention is not limited thereto, and the number of input lines and data lines may be greater than that.

[0063] The first input line (IL1) to the sixth input line (IL6) can be sequentially arranged from the edge (in the direction of the first peripheral area (PA1)) of the second peripheral area (PA2) toward the center (+x direction) of the second peripheral area (PA2).

[0064] In one embodiment, the first input line (IL1), the third input line (IL3), and the fifth input line (IL5) located at odd-numbered positions may be electrically connected to the first data line (DL1), the third data line (DL3), and the fifth data line (DL5) which are arranged adjacently and continuously. Each of these first input line (IL1), the third input line (IL3), and the fifth input line (IL5) may be formed integrally with the corresponding one of the first data line (DL1), the third data line (DL3), and the fifth data line (DL5), and as shown in FIGS. 4 and 5, each of the first input line (IL1), the third input line (IL3), and the fifth input line (IL5) may be electrically connected to the corresponding one of the first data line (DL1), the third data line (DL3), and the fifth data line (DL5) through a first contact hole (CNT1). In the latter case, as illustrated in FIG. 5, the first data line (DL1), the third data line (DL3), and the fifth data line (DL5) may be located on an insulating layer covering the first input line (IL1), the third input line (IL3), and the fifth input line (IL5). The first data line (DL1), the third data line (DL3), and the fifth data line (DL5) may receive data signals from the first input line (IL1), the third input line (IL3), and the fifth input line (IL5).

[0065] The second input line (IL2), the fourth input line (IL4), and the sixth input line (IL6), which are located at even numbers, can be electrically connected to the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6), which are arranged adjacently and continuously, through the first data transmission line (DTL1) to the third data transmission line (DTL3), as shown in FIG. 4. That is, the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6) can receive data signals from the second input line (IL2), the fourth input line (IL4), and the sixth input line (IL6) through the first data transmission line (DTL1), the second data transmission line (DTL2), and the third data transmission line (DTL3).

[0066] The first data transmission line (DTL1) to the third data transmission line (DTL3) may be arranged to pass through a part of the display area (DA) adjacent to the surrounding area (PA), that is, to pass through the display area (DA). The second input line (IL2) is electrically connected to the second data line (DL2) through the first data transmission line (DTL1), the fourth input line (IL4) is electrically connected to the fourth data line (DL4) through the second data transmission line (DTL2), and the sixth input line (IL6) is electrically connected to the sixth data line (DL6) through the third data transmission line (DTL3).

[0067] One end of each of the first data transmission line (DTL1), the second data transmission line (DTL2), and the third data transmission line (DTL3) is electrically connected to the second input line (IL2), the fourth input line (IL4), and the sixth input line (IL6) through the second contact hole (CNT2), and the other end of each of the first data transmission line (DTL1), the second data transmission line (DTL2), and the third data transmission line (DTL3) can be connected to the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6). In FIGS. 4 and 5, the second contact hole (CNT2) is shown as being located in the peripheral area (PA), but the present invention is not necessarily limited thereto. For example, the second contact hole (CNT2) may be located within the display area (DA).

[0068] Through this structure, the second input line (IL2) can transmit a data signal to the second data line (DL2), the fourth input line (IL4) can transmit a data signal to the fourth data line (DL4), and the sixth input line (IL6) can transmit a data signal to the sixth data line (DL6).

[0069] FIG. 5 illustrates in detail the exemplary configuration of the first data transmission line (DTL1), the second data transmission line (DTL2), and the third data transmission line (DTL3) of FIG. 4.

[0070] As illustrated in FIG. 5, the second input line (IL2), the fourth input line (IL4), and the sixth input line (IL6) can be electrically connected to the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6) through the first data transmission line (DTL1), the second data transmission line (DTL2), and the third data transmission line (DTL3). In this case, the first data transmission line (DTL1) may include a first vertical connection line (DV1'), a first horizontal connection line (DH1), and a first additional vertical connection line (DV1). Similarly, the second data transmission line (DTL2) may include a second vertical connection line (DV2'), a second horizontal connection line (DH2), and a second additional vertical connection line (DV2). The third data transmission line (DTL3) may also include a third vertical connection line (DV3'), a third horizontal connection line (DH3), and a third additional vertical connection line (DV3).

[0071] The first vertical connection line (DV1') to the third vertical connection line (DV3') and the first additional vertical connection line (DV1) to the third additional vertical connection line (DV3) may be arranged approximately parallel to the first data line (DL1) to the sixth data line (DL6). The first horizontal connection line (DH1) to the third horizontal connection line (DH3) may have a shape that extends in a first direction (x-axis direction) that intersects with the second direction (y-axis direction) in which the first data line (DL1) to the sixth data line (DL6) is extended.

[0072] Each of the second input line (IL2), the fourth input line (IL4), and the sixth input line (IL6) can be electrically connected to the corresponding first additional vertical connection line (DV1), the second additional vertical connection line (DV2), and the third additional vertical connection line (DV3) through the second contact hole (CNT2). Each of the first horizontal connection line (DH1), the second horizontal connection line (DH2), and the third horizontal connection line (DH3) can be electrically connected to the corresponding first additional vertical connection line (DV1), the second additional vertical connection line (DV2), and the third additional vertical connection line (DV3) through the first connection contact hole (DH-CNT1) located at one end. Each of the first horizontal connection line (DH1), the second horizontal connection line (DH2), and the third horizontal connection line (DH3) can be electrically connected to a corresponding one of the first vertical connection line (DV1'), the second vertical connection line (DV2'), and the third vertical connection line (DV3') through a second connection contact hole (DH-CNT2) located at the other end. Each of the first vertical connection line (DV1'), the second vertical connection line (DV2'), and the third vertical connection line (DV3') can be integral with a corresponding one of the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6).

[0073] The first data lines (DL1) through the sixth data lines (DL6), the first vertical connection lines (DV1') through the third vertical connection lines (DV3'), and the first additional vertical connection lines (DV1) through the third additional vertical connection lines (DV3) may be located on the same layer. Additionally, the first horizontal connection lines (DH1) through the third horizontal connection lines (DH3) may be located on a different layer from the first data lines (DL1) through the sixth data lines (DL6). In FIG. 5, the first data lines (DL1) through the sixth data lines (DL6), etc., are shown as being located on an insulating layer covering the first horizontal connection lines (DH1) through the third horizontal connection lines (DH3). For reference, the statement that certain components are located on the same layer may mean that those components are simultaneously formed from the same material through the same mask process. In this case, those components will contain the same material.

[0074] When viewed from a direction perpendicular to the substrate (100) (z-axis direction), the first horizontal connection line (DH1) intersects the first data line (DL1), the second horizontal connection line (DH2) intersects the first data line (DL1) to the third data line (DL3), and the third horizontal connection line (DH3) may intersect the first data line (DL1) to the fifth data line (DL5). Therefore, in order to prevent the first horizontal connection line (DH1) to the third horizontal connection line (DH3) from coming into contact with the intersecting data lines, the first horizontal connection line (DH1) to the third horizontal connection line (DH3) may be located below the first data line (DL1) to the sixth data line (DL6) as described above.

[0075] Meanwhile, as illustrated in FIG. 5, the display device according to the present embodiment may further include dummy wiring.

[0076] As illustrated in FIG. 5, the display device according to the present embodiment may have a first auxiliary horizontal connection line (ADH1) that is spaced apart from the first horizontal connection line (DH1), is electrically insulated from the first horizontal connection line (DH1) and the second data line (DL2), and has an extension axis identical to the extension axis of the first horizontal connection line (DH1). In particular, the display device may have a first auxiliary horizontal connection line (ADH1) located on one side (-x direction) of the first horizontal connection line (DH1) and a first auxiliary horizontal connection line (ADH1) located on the other side (+x direction). Likewise, the display device may have a second auxiliary horizontal connection line (ADH2) located on one side (-x direction) of the second horizontal connection line (DH2) and a second auxiliary horizontal connection line (ADH2) located on the other side (+x direction), and may have a third auxiliary horizontal connection line (ADH3) located on one side (-x direction) of the third horizontal connection line (DH3) and a third auxiliary horizontal connection line (ADH3) located on the other side (+x direction).

[0077] Through this, structural differences can be minimized between pixels through which the first horizontal connection line (DH1) to the third horizontal connection line (DH3) passes and pixels through which the first horizontal connection line (DH1) to the third horizontal connection line (DH3) does not pass. As a result, when the same electrical signal is applied to the pixels, the difference in brightness realized in the pixels is minimized, thereby enabling the implementation of a display device capable of displaying high-quality images. These first auxiliary horizontal connection line (ADH1) to the third auxiliary horizontal connection line (ADH3) and the first horizontal connection line (DH1) to the third horizontal connection line (DH3) can be located on the same layer.

[0078] Similarly, the display device according to the present embodiment may have a first auxiliary vertical connection line (ADV1') which is spaced apart from the first vertical connection line (DV1'), is electrically insulated from the first vertical connection line (DV1') and the first horizontal connection line (DH1), and has an extension axis identical to the extension axis of the first vertical connection line (DV1') and is located on one side (+y direction) of the first vertical connection line (DV1'). Likewise, the display device may have a second auxiliary vertical connection line (ADV2') located on one side (+y direction) of the second vertical connection line (DV2'), and a third auxiliary vertical connection line (ADV3') located on one side (+y direction) of the third vertical connection line (DV3'). The first auxiliary vertical connection line (ADV1') to the third auxiliary vertical connection line (ADV3') and the first vertical connection line (DV1') to the third vertical connection line (DV3') may be located on the same layer.

[0079] Additionally, the display device according to the present embodiment may have a first auxiliary additional vertical connection line (ADV1) which is spaced apart from the first additional vertical connection line (DV1), is electrically insulated from the first additional vertical connection line (DV1) and the first horizontal connection line (DH1), and has an extension axis identical to the extension axis of the first additional vertical connection line (DV1) and is located on one side (+y direction) of the first additional vertical connection line (DV1). Likewise, the display device may have a second auxiliary vertical connection line (ADV2) located on one side (+y direction) of the second additional vertical connection line (DV2), and a third auxiliary vertical connection line (ADV3) located on one side (+y direction) of the third additional vertical connection line (DV3). The first auxiliary additional vertical connection line (ADV1) to the third auxiliary additional vertical connection line (ADV3) and the first additional vertical connection line (DV1) to the third additional vertical connection line (DV3) may be located on the same layer.

[0080] Through this, structural differences can be minimized between pixels through which the first additional vertical connection line (DV1) to the third additional vertical connection line (DV3) passes and pixels through which the first additional vertical connection line (DV1') to the third additional vertical connection line (DV3') does not pass. Additionally, structural differences can be minimized between pixels through which the first additional vertical connection line (DV1) to the third additional vertical connection line (DV3) passes and pixels through which the first additional vertical connection line (DV1) to the third additional vertical connection line (DV3) does not pass. As a result, when the same electrical signal is applied to the pixels, the difference in luminance realized in the pixels is minimized, thereby enabling the implementation of a display device capable of displaying high-quality images.

[0081] FIG. 6 is an equivalent circuit diagram of a pixel (P) included in the display device of FIG. 1. As shown in FIG. 6, the pixel (P) may include a pixel circuit (PC) and an organic light-emitting diode (OLED) electrically connected thereto.

[0082] The pixel circuit (PC) may include a plurality of thin-film transistors (T1 to T7) and a storage capacitor (Cst) as illustrated in FIG. 6. The plurality of thin-film transistors (T1 to T7) and the storage capacitor (Cst) may be connected to signal lines (SL1, SL2, SLp, SLn, EL, DL), a first initialization voltage line (VL1), a second initialization voltage line (VL2), and a driving voltage line (PL). At least one of these lines, for example, the driving voltage line (PL), may be shared among neighboring pixels (P).

[0083] A plurality of thin-film transistors (T1 to T7) may include a driving transistor (T1), a switching transistor (T2), a compensation transistor (T3), a first initialization transistor (T4), an operation control transistor (T5), a light emission control transistor (T6), and a second initialization transistor (T7).

[0084] An organic light-emitting diode (OLED) may include a first electrode (e.g., a pixel electrode) and a second electrode (e.g., a counter electrode), wherein the first electrode of the organic light-emitting diode (OLED) is connected to a driving transistor (T1) via a light-emitting control transistor (T6) to receive a driving current, and the second electrode may receive a second power supply voltage (ELVSS). The organic light-emitting diode (OLED) may generate light of brightness corresponding to the driving current.

[0085] Some of the plurality of thin-film transistors (T1 to T7) may be NMOS (n-channel MOSFETs) and the remainder may be PMOS (p-channel MOSFETs). For example, among the plurality of thin-film transistors (T1 to T7), the compensation transistor (T3) and the first initialization transistor (T4) may be NMOS (n-channel MOSFETs) and the remainder may be PMOS (p-channel MOSFETs). Alternatively, among the plurality of thin-film transistors (T1 to T7), the compensation transistor (T3), the first initialization transistor (T4), and the second initialization transistor (T7) may be NMOS and the remainder may be PMOS. Alternatively, all of the plurality of thin-film transistors (T1 to T7) may be NMOS or all may be PMOS. The plurality of thin-film transistors (T1 to T7) may include amorphous silicon or polysilicon. If necessary, the thin-film transistors that are NMOS may include oxide semiconductors. For convenience, the following description explains the case where the compensation transistor (T3) and the first initialization transistor (T4) are NMOS (n-channel MOSFET) containing oxide semiconductor, and the rest are PMOS (p-channel MOSFET).

[0086] The signal line may include a first scan line (SL1) that transmits a first scan signal (Sn), a second scan line (SL2) that transmits a second scan signal (Sn'), a previous scan line (SLp) that transmits a previous scan signal (Sn-1) to a first initialization transistor (T4), a subsequent scan line (SLn) that transmits a subsequent scan signal (Sn+1) to a second initialization transistor (T7), a light emission control line (EL) that transmits a light emission control signal (En) to an operation control transistor (T5) and a light emission control transistor (T6), and a data line (DL) that intersects with the first scan line (SL1) and transmits a data signal (Dm).

[0087] The driving voltage line (PL) can transmit a driving voltage (ELVDD) to the driving transistor (T1), the first initialization voltage line (VL1) can transmit a first initialization voltage (Vint1) that initializes the driving transistor (T1), and the second initialization voltage line (VL2) can transmit a second initialization voltage (Vint2) that initializes the first electrode of the organic light-emitting diode (OLED).

[0088] The driving gate electrode of the driving transistor (T1) is connected to the storage capacitor (Cst) through the second node (N2), and either the source region or the drain region of the driving transistor (T1) is connected to the driving voltage line (PL) via the operation control transistor (T5) through the first node (N1), and the other of the source region or the drain region of the driving transistor (T1) can be electrically connected to the first electrode (pixel electrode) of the organic light-emitting diode (OLED) via the light emission control transistor (T6) through the third node (N3). The driving transistor (T1) can receive a data signal (Dm) according to the switching operation of the switching transistor (T2) and supply a driving current to the organic light-emitting diode (OLED). That is, the driving transistor (T1) can control the amount of current flowing from the first node (N1), which is electrically connected to the driving voltage line (PL), to the organic light-emitting diode (OLED) in response to the voltage applied to the second node (N2) which changes according to the data signal (Dm).

[0089] The switching gate electrode of the switching transistor (T2) is connected to the first scan line (SL1) that transmits the first scan signal (Sn), and either the source region or the drain region of the switching transistor (T2) is connected to the data line (DL), and the other of the source region and the drain region of the switching transistor (T2) can be connected to the driving transistor (T1) through the first node (N1) and connected to the driving voltage line (PL) via the operation control transistor (T5). The switching transistor (T2) can transmit a data signal (Dm) from the data line (DL) to the first node (N1) in response to the voltage applied to the first scan line (SL1). That is, the switching transistor (T2) can perform a switching operation in which it is turned on according to the first scan signal (Sn) received through the first scan line (SL1) and transmits the data signal (Dm) transmitted to the data line (DL) to the driving transistor (T1) through the first node (N1).

[0090] The compensation gate electrode of the compensation transistor (T3) is connected to the second scan line (SL2). Either the source region or the drain region of the compensation transistor (T3) can be connected to the first electrode of the organic light-emitting diode (OLED) via the third node (N3) and the light-emitting control transistor (T6). The other source region or the drain region of the compensation transistor (T3) can be connected to the first capacitor electrode (CE1) of the storage capacitor (Cst) and the driving gate electrode of the driving transistor (T1) via the second node (N2). This compensation transistor (T3) can be turned on according to the second scan signal (Sn') received through the second scan line (SL2) to diode-connect the driving transistor (T1).

[0091] The first initialization gate electrode of the first initialization transistor (T4) can be connected to the previous scan line (SLp). Either the source region or the drain region of the first initialization transistor (T4) can be connected to the first initialization voltage line (VL1). The other of the source region and the drain region of the first initialization transistor (T4) can be connected to the first capacitor electrode (CE1) of the storage capacitor (Cst) and the driving gate electrode of the driving transistor (T1), etc., through the second node (N2). The first initialization transistor (T4) can apply the first initialization voltage (Vint1) from the first initialization voltage line (VL1) to the second node (N2) in response to the voltage applied to the previous scan line (SLp). That is, the first initialization transistor (T4) can be turned on according to the previous scan signal (Sn-1) received through the previous scan line (SLp) to transmit the first initialization voltage (Vint1) to the driving gate electrode of the driving transistor (T1) and perform an initialization operation to initialize the voltage of the driving gate electrode of the driving transistor (T1).

[0092] The operation control gate electrode of the operation control transistor (T5) is connected to the light emission control line (EL), and either the source region or the drain region of the operation control transistor (T5) is connected to the driving voltage line (PL), while the other can be connected to the driving transistor (T1) and the switching transistor (T2) through the first node (N1).

[0093] The light-emitting control gate electrode of the light-emitting control transistor (T6) is connected to the light-emitting control line (EL), and either the source region or the drain region of the light-emitting control transistor (T6) is connected to the driving transistor (T1) and the compensation transistor (T3) through the third node (N3), and the other of the source region and the drain region of the light-emitting control transistor (T6) can be electrically connected to the first electrode (pixel electrode) of the organic light-emitting diode (OLED).

[0094] The operation control transistor (T5) and the light emission control transistor (T6) are simultaneously turned on according to the light emission control signal (En) received through the light emission control line (EL), so that the driving voltage (ELVDD) is transmitted to the organic light-emitting diode (OLED) and the driving current flows through the organic light-emitting diode (OLED).

[0095] The second initialization gate electrode of the second initialization transistor (T7) is subsequently connected to the scan line (SLn), and either the source region or the drain region of the second initialization transistor (T7) is connected to the first electrode (pixel electrode) of the organic light-emitting diode (OLED), and the other of the source region or the drain region of the second initialization transistor (T7) is connected to the second initialization voltage line (VL2) to receive the second initialization voltage (Vint2). The second initialization transistor (T7) is subsequently turned on according to the scan signal (Sn+1) received through the scan line (SLn) to initialize the first electrode (pixel electrode) of the organic light-emitting diode (OLED). The scan line (SLn) may be the same as the first scan line (SL1). In this case, the scan line can transmit the same electrical signal with a time difference to function as a first scan line (SL1) and as a next scan line (SLn). That is, the subsequent scan line (SLn) may be a first scan line of a pixel electrically connected to a data line (DL) as a pixel adjacent to the pixel (P) shown in FIG. 6.

[0096] The second initialization transistor (T7) may be connected to the first scan line (SL1) as shown in FIG. 6. However, the present invention is not limited thereto, and the second initialization transistor (T7) may be connected to the light emission control line (EL) and driven according to the light emission control signal (En).

[0097] The storage capacitor (Cst) may include a first capacitor electrode (CE1) and a second capacitor electrode (CE2). The first capacitor electrode (CE1) of the storage capacitor (Cst) is connected to the driving gate electrode of the driving transistor (T1) through the second node (N2), and the second capacitor electrode (CE2) of the storage capacitor (Cst) is connected to the driving voltage line (PL). The storage capacitor (Cst) may store a charge corresponding to the difference between the driving gate electrode voltage of the driving transistor (T1) and the driving voltage (ELVDD).

[0098] The specific operation of each pixel (P) according to one embodiment is as follows.

[0099] During the initialization period, when a previous scan signal (Sn-1) is supplied through the previous scan line (SLp), the first initialization transistor (T4) is turned on in response to the previous scan signal (Sn-1), and the driving transistor (T1) is initialized by the first initialization voltage (Vint1) supplied from the first initialization voltage line (VL1).

[0100] During the data programming period, when a first scan signal (Sn) and a second scan signal (Sn') are supplied through the first scan line (SL1) and the second scan line (SL2), the switching transistor (T2) and the compensation transistor (T3) are turned on in response to the first scan signal (Sn) and the second scan signal (Sn'). At this time, the driving transistor (T1) is diode-connected by the turned-on compensation transistor (T3) and is forward-biased. Then, a compensation voltage (Dm+Vth, where Vth is a negative value) that is reduced by the threshold voltage (Vth) of the driving transistor (T1) from the data signal (Dm) supplied from the data line (DL) is applied to the driving gate electrode (G1) of the driving transistor (T1). A driving voltage (ELVDD) and a compensation voltage (Dm+Vth) are applied across the storage capacitor (Cst), and a charge corresponding to the voltage difference across the storage capacitor (Cst) is stored.

[0101] During the light emission period, the operation control transistor (T5) and the light emission control transistor (T6) are turned on by the light emission control signal (En) supplied from the light emission control line (EL). A driving current is generated according to the voltage difference between the voltage of the driving gate electrode (G1) of the driving transistor (T1) and the driving voltage (ELVDD), and the driving current is supplied to the organic light-emitting diode (OLED) through the light emission control transistor (T6).

[0102] As described above, some of the plurality of thin-film transistors (T1 to T7) may include oxide semiconductors. For example, the compensation transistor (T3) and the first initialization transistor (T4) may include oxide semiconductors.

[0103] Since polysilicon has high reliability, it can be controlled to ensure that the intended current flows accurately. Therefore, the driving transistor (T1), which directly affects the brightness of the display device, can be configured to include a semiconductor layer composed of polysilicon with high reliability, thereby enabling the realization of a high-resolution display device. Meanwhile, oxide semiconductors have high carrier mobility and low leakage current, so the voltage drop is not significant even if the driving time is long. That is, in the case of oxide semiconductors, the color change of the image due to voltage drop is not significant even during low-frequency driving, so low-frequency driving is possible. Therefore, the compensation transistor (T3) and the first initialization transistor (T4) can be configured to include oxide semiconductors, thereby preventing the occurrence of leakage current and enabling the realization of a display device with reduced power consumption.

[0104] Meanwhile, such oxide semiconductors are sensitive to light, so fluctuations in current amount, etc. may occur due to light from the outside. Therefore, a metal layer can be placed below the oxide semiconductor to absorb or reflect light from the outside. Accordingly, as shown in FIG. 6, the gate electrodes of the compensation transistor (T3) and the first initialization transistor (T4), each containing the oxide semiconductor, can be located above and below the oxide semiconductor layer, respectively. That is, when viewed from a direction perpendicular to the upper surface of the substrate (100) (z-axis direction), the metal layer located below the oxide semiconductor can overlap with the oxide semiconductor.

[0105] FIG. 7 is a schematic layout diagram showing the locations of transistors and capacitors, etc., in pixels included in the display device of FIG. 1, FIG. 8 to FIG. 15 are schematic layout diagrams showing the components of the display device shown in FIG. 7, such as transistors and capacitors, in layers, FIG. 16 is a schematic cross-sectional view showing cross-sections taken along the lines I-I', II-II', and III-III' of the display device shown in FIG. 7.

[0106] As illustrated in these drawings, the display device may include a first pixel (P1) and a second pixel (P2) adjacent to each other. The first pixel (P1) and the second pixel (P2) may be symmetrical with respect to an imaginary line, as illustrated in FIG. 7, etc. Of course, alternatively, the first pixel (P1) and the second pixel (P2) may have the same structure rather than a symmetrical structure. The first pixel (P1) may include a first pixel circuit (PC1), and the second pixel (P2) may include a second pixel circuit (PC2). For convenience of explanation, some conductive patterns are described below with respect to the first pixel circuit (PC1), but these conductive patterns may also be symmetrically arranged in the second pixel circuit (PC2).

[0107] A buffer layer (111, see FIG. 16) comprising silicon oxide, silicon nitride, or silicon oxynitride may be located on the substrate (100). The buffer layer (111) can prevent metal atoms or impurities from the substrate (100) from diffusing to the first semiconductor layer (1100) located thereon. Additionally, the buffer layer (111) can control the rate of heat supply during the crystallization process for forming the first semiconductor layer (1100) so that the first semiconductor layer (1100) can be crystallized uniformly.

[0108] A first semiconductor layer (1100), such as that illustrated in FIG. 8, may be disposed on a buffer layer (111). The first semiconductor layer (1100) may include a silicon semiconductor. For example, the first semiconductor layer (1100) may include amorphous silicon or polysilicon. Specifically, the first semiconductor layer (1100) may include polysilicon crystallized at low temperature. If necessary, ions may be implanted in at least a portion of the first semiconductor layer (1100).

[0109] The driving transistor (T1), switching transistor (T2), operation control transistor (T5), light emission control transistor (T6), and second initialization transistor (T7) may be PMOS as described above, in which case these thin-film transistors are located along the first semiconductor layer (1100) as shown in FIG. 8.

[0110] A first gate insulating layer (113) (see FIG. 15) covers a first semiconductor layer (1100) and can be disposed on a substrate (100). The first gate insulating layer (113) may include an insulating material. For example, the first gate insulating layer (113) may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, etc.

[0111] A first gate layer (1200) as shown in FIG. 9 may be located on a first gate insulating layer (113). In FIG. 9, for convenience, the first gate layer (1200) is shown together with a first semiconductor layer (1100). The first gate layer (1200) may include a first gate wiring (1210), a first gate electrode (1220), and a second gate wiring (1230).

[0112] The first gate wiring (1210) may be extended in a first direction (x-axis direction). The first gate wiring (1210) may be the first scan line (SL1) of FIG. 6 or the subsequent scan line (SLn). That is, for a pixel (P1) such as that shown in FIG. 9, the first gate wiring (1210) corresponds to the first scan line (SL1) of FIG. 6, and for a pixel adjacent to the pixel (P1) (in the +y direction), the first gate wiring (1210) may correspond to the subsequent scan line (SLn) of FIG. 6. Accordingly, the first scan signal (Sn) and the subsequent scan signal (Sn+1) may be applied to the pixels through the first gate wiring (1210). The parts overlapping with the first semiconductor layer (1100) of the first gate wiring (1210) may be the switching gate electrode of the switching transistor (T2) and the second initialization gate electrode of the second initialization transistor (T7).

[0113] The first gate electrode (1220) may have an isolated shape. The first gate electrode (1220) is the driving gate electrode of the driving transistor (T1). For reference, the portion overlapping with the first gate electrode (1220) of the first semiconductor layer (1100) and the portion near it may be the driving semiconductor layer.

[0114] The second gate wiring (1230) may be extended in the first direction (x-axis direction). The second gate wiring (1230) may correspond to the light emission control line (EL) of FIG. 6. The parts of the second gate wiring (1230) that overlap with the first semiconductor layer (1100) may be the operation control gate electrode of the operation control transistor (T5) and the light emission control gate electrode of the light emission control transistor (T6). A light emission control signal (En) may be applied to pixels through the second gate wiring (1230).

[0115] The first gate layer (1200) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the first gate layer (1200) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The first gate layer (1200) may have a multilayer structure, for example, the first gate layer (1200) may have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo.

[0116] The second gate insulating layer (115, see FIG. 15) covers the first gate layer (1200) and may be located on the first gate insulating layer (113). The second gate insulating layer (115) may include an insulating material identical or similar to that of the first gate insulating layer (113).

[0117] The second gate layer (1300) may be located on the second gate insulating layer (115). The second gate layer (1300) may include a third gate wiring (1310), a fourth gate wiring (1320), a capacitor upper electrode (1330), and a first initialization voltage wiring (1340) (i.e., the first initialization voltage line (VL1) of FIG. 6).

[0118] The third gate wiring (1310) may be extended in the first direction (x-axis direction). The third gate wiring (1310) may correspond to the previous scan line (SLp) of FIG. 6. When viewed from a direction perpendicular to the substrate (100) (z-axis direction), the third gate wiring (1310) may be spaced apart from the first gate wiring (1210). The previous scan signal (Sn-1) may be applied to pixels through the third gate wiring (1310). The portion of the third gate wiring (1310) that overlaps with the second semiconductor layer (1400) described later may be the first initialization lower gate electrode of the first initialization transistor (T4).

[0119] The fourth gate wiring (1320) may also be extended in the first direction (x-axis direction). The fourth gate wiring (1320) may correspond to the second scan line (SL2) of FIG. 6. When viewed from a direction perpendicular to the substrate (100) (z-axis direction), the fourth gate wiring (1320) may be spaced apart from the first gate wiring (1210) and the third gate wiring (1310). The second scan signal (Sn') may be applied to pixels through the fourth gate wiring (1320). The portion of the fourth gate wiring (1320) that overlaps with the second semiconductor layer (1400) described later may be the compensation lower gate electrode of the compensation transistor (T3).

[0120] The third gate wiring (1310) and the fourth gate wiring (1320) are located below the second semiconductor layer (1400) described later with reference to FIG. 11, and in addition to serving as gate electrodes, they can serve as a lower protective metal that protects the portions overlapping with the third gate wiring (1310) and the fourth gate wiring (1320) of the second semiconductor layer (1400).

[0121] The capacitor upper electrode (1330) overlaps with the first gate electrode (1220) and can be extended in the first direction (x-axis direction). This capacitor upper electrode (1330) can form a storage capacitor (Cst) together with the first gate electrode (1220) corresponding to the second capacitor electrode (CE2) of FIG. 6. A driving voltage (ELVDD) can be applied to the capacitor upper electrode (1330). Additionally, a hole penetrating the capacitor upper electrode (1330) may be formed in the capacitor upper electrode (1330), and at least a portion of the first gate electrode (1220) may overlap with this hole.

[0122] The first initialization voltage wiring (1340) corresponding to the first initialization voltage line (VL1) of FIG. 6 may be extended in a first direction (x-axis direction). When viewed from a direction perpendicular to the substrate (100) (z-axis direction), the first initialization voltage wiring (1340) may be spaced apart from the third gate wiring (1310). The first initialization voltage (Vint1) may be applied to pixels through the first initialization voltage wiring (1340). The first initialization voltage wiring (1340) overlaps at least partially with the second semiconductor layer (1400) to be described later, and may transmit the first initialization voltage (Vint1) to the second semiconductor layer (1400). The first initial voltage wiring (1340) can be electrically connected to the second semiconductor layer (1400) through contact holes (1680CNT1, 1680CNT2 and 1680CNT3) described later with reference to FIG. 13.

[0123] The second gate layer (1300) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the second gate layer (1300) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The second gate layer (1300) may have a multilayer structure, for example, the second gate layer (1300) may have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo.

[0124] The first interlayer insulating layer (117, see FIG. 16) covers the second gate layer (1300) and may be located on the second gate insulating layer (115). The first interlayer insulating layer (117) may include an insulating material. For example, the first interlayer insulating layer (117) may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, etc.

[0125] A second semiconductor layer (1400), as illustrated in FIG. 11, may be located on the first interlayer insulating layer (117). As described above, the second semiconductor layer (1400) may include an oxide semiconductor. The second semiconductor layer (1400) may be placed on a different layer from the first semiconductor layer (1100) and may not overlap with the first semiconductor layer (1100) when viewed from a direction perpendicular to the substrate (100) (z-axis direction).

[0126] A third gate insulating layer (118, see FIG. 16) covers the second semiconductor layer (1400) and may be placed on the first interlayer insulating layer (117). The third gate insulating layer may include an insulating material. Of course, as shown in FIG. 16, the third gate insulating layer (118) may be located only on a part of the second semiconductor layer (1400) and not on the first interlayer insulating layer (117). In the latter case, as shown in FIG. 16, the third gate insulating layer (118) may have the same pattern as the third gate layer (1500) described later with reference to FIG. 12. That is, when viewed from a direction perpendicular to the substrate (100) (z-axis direction), the third gate insulating layer (118) may perfectly or nearly perfectly overlap with the second gate layer (1500). This is because the third gate insulating layer (118) and the second gate layer (1500) are patterned simultaneously. Therefore, the source regions and drain regions of the second semiconductor layer (1400) may not be covered by the third gate insulating layer (118), except for the channel regions that overlap with the third gate layer (1500). These source regions and drain regions may come into direct contact with the second interlayer insulating layer (119) as shown in FIG. 16. The third gate insulating layer (118) may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, etc.

[0127] A third gate layer (1500), as illustrated in FIG. 12, may be located on the third gate insulating layer (118). The third gate layer (1500) may include a fifth gate wiring (1520), a sixth gate wiring (1530), and a first transfer wiring (1540).

[0128] The fifth gate wiring (1520) may be extended in a first direction (x-axis direction). When viewed from a direction perpendicular to the substrate (100) (z-axis direction), the fifth gate wiring (1520) may overlap with the third gate wiring (1310). The portion of the fifth gate wiring (1520) that overlaps with the second semiconductor layer (1400) may be the first initialization upper gate electrode of the first initialization transistor (T4). The portion of the second semiconductor layer (1400) that overlaps with the fifth gate electrode (1520) and the portion near it may be the first initialization semiconductor layer. The fifth gate wiring (1520) may be electrically connected to the third gate wiring (1310). For example, the fifth gate wire (1520) may be electrically connected to the third gate wire (1310) through a contact hole formed in the insulating layer between the fifth gate wire (1520) and the third gate wire (1310). Such a contact hole may be located within the display area (DA) or in the peripheral area (PA). Accordingly, the fifth gate wire (1520) may correspond to the previous scan line (SLp) of FIG. 6 together with the third gate wire (1310). Accordingly, the previous scan signal (Sn-1) may be applied to pixels through the fifth gate wire (1520) and / or the third gate wire (1310).

[0129] The sixth gate wiring (1530) may be extended in a first direction (x-axis direction). When viewed from a direction perpendicular to the substrate (100) (z-axis direction), the sixth gate wiring (1530) may overlap with the fourth gate wiring (1320). The portion of the sixth gate wiring (1530) that overlaps with the second semiconductor layer (1400) may be the compensation upper gate electrode of the compensation transistor (T3). The sixth gate wiring (1530) may be electrically connected to the fourth gate wiring (1320). For example, the sixth gate wiring (1530) may be electrically connected to the fourth gate wiring (1320) through a contact hole formed in the insulating layer between the sixth gate wiring (1530) and the fourth gate wiring (1320). Such a contact hole may be located within the display area (DA) or in the peripheral area (PA). Accordingly, the sixth gate wire (1530) can correspond to the second scan line (SL2) of FIG. 6 together with the fourth gate wire (1320). Accordingly, the second scan signal (Sn') can be applied to pixels through the sixth gate wire (1530) and / or the fourth gate wire (1320).

[0130] The first transmission wire (1540) can be electrically connected to the first gate electrode (1220), which is the driving gate electrode, through a contact hole (1540CNT) passing through the opening (1330-OP) of the upper electrode (1330) of the capacitor. The first transmission wire (1540) can transmit the first initialization voltage (Vint1) transmitted through the first initialization transistor (T4) to the first gate electrode (1220).

[0131] The third gate layer (1500) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the third gate layer (1500) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The third gate layer (1500) may have a multilayer structure, for example, the third gate layer (1500) may have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo.

[0132] The second interlayer insulating layer (119, see FIG. 16) may cover at least a portion of the third gate layer (1500) of FIG. 12. The second interlayer insulating layer (119) may include an insulating material. For example, the second interlayer insulating layer (119) may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, etc.

[0133] A first connecting electrode layer (1600), as illustrated in FIG. 13, may be located on a second interlayer insulating layer (119). The first connecting electrode layer (1600) may include a second transfer wire (1620), a second initial voltage wire (1630), a third transfer wire (1640), a fourth transfer wire (1650), a fifth transfer wire (1670), and a sixth transfer wire (1680).

[0134] The second transmission wire (1620) can be electrically connected to the first semiconductor layer (1100) through the contact hole (1620 CNT). A data signal (Dm) from the data wire (1810), which will be described later with reference to FIG. 15, can be transmitted to the first semiconductor layer (1100) through the second transmission wire (1620) and applied to the switching transistor (T2).

[0135] The second initialization voltage wiring (1630) can be extended in the first direction (x-axis direction). The second initialization voltage wiring (1630) corresponding to the second initialization voltage line (VL2) of FIG. 6 can apply the second initialization voltage (Vint2) to the pixels. This second initialization voltage wiring (1630) is electrically connected to the first semiconductor layer (1100) through a contact hole (1630CNT), so that the second initialization voltage (Vint2) is transmitted to the first semiconductor layer (1100) and can be applied to the second initialization transistor (T7).

[0136] The third transfer wire (1640) can electrically connect the second semiconductor layer (1400) and the first transfer wire (1540) through contact holes (1640CNT1, 1640CNT2) formed on one side and the other side. Since the first transfer wire (1540) is electrically connected to the first gate electrode (1220), which is the driving gate electrode, the third transfer wire (1640) can consequently electrically connect the first initialization semiconductor layer, which is part of the second semiconductor layer (1400), to the driving gate electrode. The first initialization voltage (Vint1) can be transmitted to the first gate electrode (1220), which is the driving gate electrode, through the second semiconductor layer (1400), the third transfer wire (1640), and the first transfer wire (1540).

[0137] The fourth transmission wire (1650) can electrically connect the second semiconductor layer (1400) and the first semiconductor layer (1100) through contact holes (1650CNT1, 1650CNT2) formed on one side and the other side. That is, the fourth transmission wire (1650) can electrically connect the compensation transistor (T3) and the driving transistor (T1).

[0138] The fifth transfer wire (1670) can be electrically connected to the first semiconductor layer (1100) through a contact hole (1670 CNT). The fifth transfer wire (1670) can transmit a driving current or a second initialization voltage (Vint2) from the first semiconductor layer (1100) to an organic light-emitting diode (OLED).

[0139] The sixth transfer wire (1680) can be electrically connected to the second semiconductor layer (1400) through contact holes (1680CNT2 and 1680CNT3). The sixth transfer wire (1680) can also be electrically connected to the first initialization voltage wire (1340) of FIG. 10 through a contact hole (1680CNT1). Through this, the sixth transfer wire (1680) can transfer the first initialization voltage (Vint1) from the first initialization voltage wire (1340) to the first initialization transistor (T4).

[0140] The first connecting electrode layer (1600) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the first connecting electrode layer (1600) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The first connecting electrode layer (1600) may have a multilayer structure, for example, the first connecting electrode layer (1600) may have a two-layer structure of Ti / Al or a three-layer structure of Ti / Al / Ti.

[0141] The first flattening insulating layer (121) covers the first connecting electrode layer (1600) and may be located on the second interlayer insulating layer (119). The first flattening insulating layer (121) may include an organic insulating material. For example, the first flattening insulating layer (121) may include photoresist, BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0142] A second connecting electrode layer (1700), as illustrated in FIG. 14, may be located on the first flattening insulating layer (121). The second connecting electrode layer (1700) may include a horizontal connecting wire (1710), a seventh transfer wire (1720), an eighth transfer wire (1760), and a ninth transfer wire (1770).

[0143] The horizontal connection wiring (1710) may be extended in a first direction (x-axis direction). Depending on the position of the pixel, the horizontal connection wiring (1710) may be any one of the first horizontal connection line (DH1) to the third horizontal connection line (DH3) and the first auxiliary horizontal connection line (ADH1) to the third auxiliary horizontal connection line (ADH3) described above with reference to FIG. 5. That is, the second connection electrode layer (1700) may include horizontal connection wiring and / or auxiliary horizontal connection wiring. This will be described later together with the vertical connection wiring (1820) of FIG. 15.

[0144] The seventh transmission wire (1720) can be electrically connected to the aforementioned second transmission wire (1620) through a contact hole (1720CNT). A data signal (Dm) from the data wire (1810), described later with reference to FIG. 15, can be transmitted to the first semiconductor layer (1100) through the seventh transmission wire (1720) and the second transmission wire (1620) and applied to the switching transistor (T2).

[0145] The eighth transmission wire (1760) can be extended in the first direction (x-axis direction). The driving voltage (ELVDD) from the driving voltage wire (1830), which will be described later with reference to FIG. 15, is transmitted to the eighth transmission wire (1760). The eighth transmission wire (1260), which is electrically connected to the first semiconductor layer (1100) through the contact hole (1760CNT1), can transmit the driving voltage (ELVDD) to the first semiconductor layer (1100), specifically to the operation control transistor (T5). Additionally, the eighth transmission wire (1260), which is electrically connected to the capacitor upper electrode (1330) (i.e., the second capacitor electrode (CE2) in FIG. 6) through the contact hole (1760CNT), can transmit the driving voltage (ELVDD) to the capacitor upper electrode (1330).

[0146] The ninth transmission wire (1770) can be electrically connected to the fifth transmission wire (1670) through a contact hole (1770 CNT). The ninth transmission wire (1770) can receive a driving current from the first semiconductor layer (1100) or a second initialization voltage (Vint2) from the fifth transmission wire (1670) and transmit it to an organic light-emitting diode (OLED).

[0147] The second connecting electrode layer (1700) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the second connecting electrode layer (1700) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The second connecting electrode layer (1700) may have a multilayer structure, for example, the second connecting electrode layer (1700) may have a two-layer structure of Ti / Al or a three-layer structure of Ti / Al / Ti.

[0148] A second planarizing insulating layer (123, see FIG. 16) covers the second connecting electrode layer (1700) and may be located on the first planarizing insulating layer (121). The second planarizing insulating layer (123) may include an organic insulating material. For example, the second planarizing insulating layer (123) may include a photoresist, BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0149] A third connecting electrode layer (1800), as illustrated in FIG. 15, may be located on the second flattening insulating layer (123). The third connecting electrode layer (1800) may include a data wiring (1810), a vertical connecting wiring (1820), a driving voltage wiring (1830), and a tenth transmission wiring (1840).

[0150] The data line (1810) may be extended in a second direction (y-axis direction). The data line (1810) may correspond to the data line (DL) of FIG. 6. The data line (1810) is electrically connected to the seventh transmission line (1720) through a contact hole (1810CNT), so that a data signal (Dm) from the data line (1810) is transmitted to the first semiconductor layer (1100) through the seventh transmission line (1720) and the second transmission line (1620) and can be applied to the switching transistor (T2). The data line (1810) may be any one of the first data line (DL1) to the sixth data line (DL6) described above with reference to FIG. 5.

[0151] The vertical connection wiring (1820) may extend approximately in the second direction (y-axis direction). Depending on the position of the pixel, the vertical connection wiring (1820) may be any one of the first vertical connection line (DV1') to the third vertical connection line (DV3'), the first additional vertical connection line (DV1) to the third additional vertical connection line (DV3), the first auxiliary vertical connection line (ADV1') to the third auxiliary vertical connection line (ADV3'), and the first auxiliary additional vertical connection line (ADV1) to the third additional auxiliary vertical connection line (ADV3) described above with reference to FIG. 5. That is, the third connection electrode layer (1800) may include a vertical connection wiring, an additional vertical connection wiring, an auxiliary vertical connection wiring, and / or an additional auxiliary vertical connection wiring.

[0152] For example, the data wiring (1810) of FIG. 15 may be the sixth data line (DL6) of FIG. 5, the vertical connection wiring (1820) of FIG. 15 may be the third vertical connection line (DV3') of FIG. 5, and the horizontal connection wiring (1710) of FIG. 14 may be the second auxiliary horizontal connection line (ADH2) of FIG. 5. Alternatively, the data wiring (1810) of FIG. 15 may be the fifth data line (DL5) of FIG. 5, the vertical connection wiring (1820) of FIG. 15 may be the third auxiliary vertical connection line (DV3) of FIG. 5, and the horizontal connection wiring (1710) of FIG. 14 may be the first auxiliary horizontal connection line (ADH1) of FIG. 5.

[0153] Alternatively, the data wiring (1810) of FIG. 15 may be the fifth data line (DL5) of FIG. 5, the vertical connection wiring (1820) of FIG. 15 may be the third additional vertical connection line (DV3) of FIG. 5, and the horizontal connection wiring (1710) of FIG. 14 may be the third horizontal connection line (DH3) of FIG. 5. In this case, the vertical connection wiring (1820) and the horizontal connection wiring (1710) may be electrically connected within the display area (DA, see FIG. 5) through a contact hole (not shown in FIG. 15) formed in the insulating layer between the vertical connection wiring (1820) and the horizontal connection wiring (1710). The contact hole formed in the insulating layer between the vertical connection wiring (1820) and the horizontal connection wiring (1710) may be the first connection contact hole (DH-CNT1) described above with reference to FIG. 5.

[0154] Alternatively, the data wiring (1810) of FIG. 15 may be the fourth data line (DL4) of FIG. 5, the vertical connection wiring (1820) of FIG. 15 may be the second auxiliary vertical connection line (ADV2') of FIG. 5, and the horizontal connection wiring (1710) of FIG. 14 may be the third horizontal connection line (DH3) of FIG. 5. Alternatively, the data wiring (1810) of FIG. 15 may be the third data line (DL3) of FIG. 5, the vertical connection wiring (1820) of FIG. 15 may be the second additional auxiliary vertical connection line (ADV2) of FIG. 5, and the horizontal connection wiring (1710) of FIG. 14 may be the third horizontal connection line (DH3) of FIG. 5.

[0155] Of course, depending on the position of the pixel, the data line (1810) of FIG. 15 may be the sixth data line (DL6) of FIG. 5, the vertical connection line (1820) of FIG. 15 may be the third vertical connection line (DV3') of FIG. 5, and the horizontal connection line (1710) of FIG. 14 may be the third horizontal connection line (DH3) of FIG. 5. In this case, the vertical connection line (1820) and the horizontal connection line (1710) may be electrically connected within the display area (DA, see FIG. 5) through a contact hole (not shown in FIG. 15) formed in the insulating layer between the vertical connection line (1820) and the horizontal connection line (1710). The contact hole formed in the insulating layer between the vertical connection line (1820) and the horizontal connection line (1710) may be the second connection contact hole (DH-CNT2) described above with reference to FIG. 5. Of course, the vertical connection wiring (1820) can be electrically connected to the data wiring (1810) in a peripheral area (PA) outside the display area (DA) in a manner that is integral with the data wiring (1810) as described above with reference to FIG. 5.

[0156] Referring to FIG. 5, the first input line (IL1) to the sixth input line (IL6) described above may be located below the vertical connection wiring (1820). That is, the first input line (IL1) to the sixth input line (IL6) may be located in the first gate layer (1200), in the second gate layer (1300), in the third gate layer (1500), in the first connection electrode layer (1600), or in the second connection electrode layer (1700). Alternatively, the first input line (IL1) to the sixth input line (IL6) may have a structure in which at least two of the conductive layer located in the first gate layer (1200), the conductive layer located in the second gate layer (1300), the conductive layer located in the third gate layer (1500), the conductive layer located in the first connecting electrode layer (1600), and the conductive layer located in the second connecting electrode layer (1700) are connected to each other through contact holes.

[0157] As described above with reference to FIG. 12, the fifth gate wiring (1520), which extends in the first direction (x-axis direction) and has a portion overlapping with the second semiconductor layer (1400) of the fifth gate wiring (1520) that becomes the first initialization upper gate electrode of the first initialization transistor (T4), intersects the vertical connection wiring (1820) when viewed from a direction perpendicular to the substrate (100) (z-axis direction). If the distance between the fifth gate wiring (1520) and the vertical connection wiring (1820) is short, noise may be generated in the electrical signal transmitted through the fifth gate wiring (1520) or in the electrical signal transmitted through the vertical connection wiring (1820) due to the coupling effect. However, in the case of the display device according to the present embodiment, the fifth gate wiring (1520) is located in the third gate layer (1500) and the vertical connection wiring (1820) is located in the third connection electrode layer (1800), so the second interlayer insulation layer (119), the first flattening insulation layer (121), and the second flattening insulation layer (123) are interposed between them. Therefore, the distance between the fifth gate wiring (1520) and the vertical connection wiring (1820) becomes sufficiently far, so that the coupling effect occurring between the fifth gate wiring (1520) and the vertical connection wiring (1820) can be effectively prevented or minimized.

[0158] The driving voltage wiring (1830) can be extended approximately in the second direction (y-axis direction). The driving voltage wiring (1830) can correspond to the driving voltage line (PL) of FIG. 6. The driving voltage wiring (1830) can apply a driving voltage (ELVDD) to the pixels. The driving voltage wiring (1830) can be electrically connected to the eighth transmission wiring (1760) through the contact hole (1830CNT) so that the driving voltage (ELVDD) can be transmitted to the operation control transistor (T5) and the capacitor upper electrode (1330) as described above. The driving voltage wiring (1830) of this first pixel circuit (PC1) can be integral with the driving voltage wiring (1830) of the adjacent second pixel circuit (PC2).

[0159] The 10th transmission wire (1840) is electrically connected to the 9th transmission wire (1770) through a contact hole (1840CNT1), so that the driving current or the 2nd initialization voltage (Vint2) from the 1st semiconductor layer (1100) can be received from the 5th transmission wire (1670) and the 9th transmission wire (1770). Additionally, the 10th transmission wire (1840) can transmit the driving current or the 2nd initialization voltage (Vint2) from the 1st semiconductor layer (1100) to the 1st electrode (pixel electrode) of the organic light-emitting diode (OLED) through a contact hole (1840CNT2) formed in the insulating layer located above it.

[0160] The third connecting electrode layer (1800) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the third connecting electrode layer (1800) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The third connecting electrode layer (1800) may have a multilayer structure, for example, the third connecting electrode layer (1800) may have a two-layer structure of Ti / Al or a three-layer structure of Ti / Al / Ti.

[0161] A third planarizing insulating layer (125), such as that shown in FIG. 16, covers the third connecting electrode layer (1800) and may be disposed on the second planarizing insulating layer (123). The third planarizing insulating layer (125) may include an organic insulating material. For example, the third planarizing insulating layer (125) may include BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0162] An organic light-emitting diode (OLED) may be positioned on the third planarized insulating layer (125). The organic light-emitting diode (OLED) may include a pixel electrode (210) which is a first electrode, an intermediate layer (220) including a light-emitting layer, and a counter electrode (230) which is a second electrode.

[0163] The pixel electrode (210) may be a (semi)transparent electrode or a reflective electrode. For example, the pixel electrode (210) may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or semitransparent electrode layer located on the reflective layer. The transparent or semitransparent electrode layer may have at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). For example, the pixel electrode (210) may have a three-layer structure of ITO / Ag / ITO.

[0164] A pixel defining film (127) may be disposed on the third flattening insulating layer (125). The pixel defining film (127) can prevent arcs from occurring at the edge of the pixel electrode (210) by increasing the distance between the edge of the pixel electrode (210) and the opposing electrode (230) above the pixel electrode (210).

[0165] The pixel definition film (127) can be formed by a method such as spin coating, using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene and phenolic resin.

[0166] At least a portion of the intermediate layer (220) of the organic light-emitting diode (OLED) may be located within an opening (OP) formed by the pixel defining film (127). The light-emitting region (EA) of the organic light-emitting diode (OLED) may be defined by the opening (OP).

[0167] The intermediate layer (220) may include a light-emitting layer. The light-emitting layer may include an organic material containing a fluorescent or phosphorescent material that emits red, green, blue, or white light. The light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be optionally further disposed below and above the light-emitting layer.

[0168] The light-emitting layer may have a patterned shape corresponding to each of the pixel electrodes (210). Various variations are possible, such as the layer other than the light-emitting layer included in the intermediate layer (220) being integral across the plurality of pixel electrodes (210).

[0169] The counter electrode (230) may be a transparent electrode or a reflective electrode. For example, the counter electrode (230) may be a transparent or translucent electrode and may include a metal thin film with a low work function, including Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof. Additionally, the counter electrode (230) may further include a TCO (transparent conductive oxide) film, such as ITO, IZO, ZnO, or In2O3, located on the metal thin film. The counter electrode (230) may be formed integrally across the entire front surface of the display area (DA) and may be placed on top of the intermediate layer (220) and the pixel defining film (127).

[0170] In FIG. 5, the first vertical connection line (DV1'), the second vertical connection line (DV2'), and the third vertical connection line (DV3') are each shown as being integral with the corresponding second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6). However, the present invention is not limited thereto. For example, as shown in FIG. 17, which is a plan view schematically illustrating a part of a display device according to one embodiment of the present invention, the first vertical connection line (DV1') may be electrically connected to the second data line (DL2) through the first horizontal intermediate line (DH1'), the second vertical connection line (DV2') may be electrically connected to the fourth data line (DL4) through the second horizontal intermediate line (DH2'), and the third vertical connection line (DV3') may be electrically connected to the sixth data line (DL6) through the third horizontal intermediate line (DH3').

[0171] As the third connecting electrode layer (1800) as shown in FIG. 15 may include a first vertical connecting line (DV1'), a second vertical connecting line (DV2'), a third vertical connecting line (DV3'), a second data line (DL2), a fourth data line (DL4), and a sixth data line (DL6), the first horizontal intermediate line (DH1'), the second horizontal intermediate line (DH2'), and the third horizontal intermediate line (DH3') may be located in the conductive layer located below it. For example, the second connecting electrode layer (1700) as shown in FIG. 14 may include a first horizontal intermediate line (DH1'), a second horizontal intermediate line (DH2'), and a third horizontal intermediate line (DH3').

[0172] FIG. 18 is a plan view schematically illustrating a part of a display device according to an embodiment of the present invention. The difference between the display device according to the present embodiment and the display device described above with reference to FIG. 5 is that the first horizontal connection line (DH1), the second horizontal connection line (DH2), and the third horizontal connection line (DH3) are electrically connected to the corresponding of the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6) within the display area (DA) through a contact hole. FIG. 18 illustrates that each of the first horizontal connection line (DH1), the second horizontal connection line (DH2), and the third horizontal connection line (DH3) is electrically connected to the corresponding of the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6) through a second connection contact hole (DH-CNT2) located at the other end (-x direction). Each of the first horizontal connection line (DH1), the second horizontal connection line (DH2), and the third horizontal connection line (DH3) can be electrically connected to a corresponding first additional vertical connection line (DV1), the second additional vertical connection line (DV2), and the third additional vertical connection line (DV3) through a first connection contact hole (DH-CNT1) located at one end (+x direction). Through this, the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6) can receive data signals from the second input line (IL2), the fourth input line (IL4), and the sixth input line (IL6).

[0173] Meanwhile, the first vertical connection line (DV1'), the second vertical connection line (DV2'), and the third vertical connection line (DV3') may not be electrically connected to data lines or horizontal connection lines. Therefore, the first vertical connection line (DV1'), the second vertical connection line (DV2'), and the third vertical connection line (DV3') that intersect the first horizontal connection line (DH1), the second horizontal connection line (DH2), or the third horizontal connection line (DH3) may be omitted. However, in order to ensure that the pixels through which the first data line (DL1) and the first additional vertical connection line (DV1) pass, the pixels through which the third data line (DL3) and the second additional vertical connection line (DV2) pass, and the pixels through which the fifth data line (DL5) and the third additional vertical connection line (DV3) pass have a structure as identical or similar as possible to the pixels through which the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6) pass, the first vertical connection line (DV1') may pass through the pixels through which the second data line (DL2) passes, the second vertical connection line (DV2') may pass through the pixels through which the fourth data line (DL4) passes, and the third vertical connection line (DV3') may pass through the pixels through which the sixth data line (DL6) passes. Through this, a display device that displays a high-quality image can be implemented.

[0174] As illustrated in FIG. 18, the display device according to the present embodiment may have a first auxiliary horizontal connection line (ADH1) that is spaced apart from the first horizontal connection line (DH1), is electrically insulated from the first horizontal connection line (DH1) and the second data line (DL2), and has an extension axis identical to the extension axis of the first horizontal connection line (DH1). In particular, the display device may have a first auxiliary horizontal connection line (ADH1) located on one side (-x direction) of the first horizontal connection line (DH1) and a first auxiliary horizontal connection line (ADH1) located on the other side (+x direction). Likewise, the display device may have a second auxiliary horizontal connection line (ADH2) located on one side (-x direction) of the second horizontal connection line (DH2) and a second auxiliary horizontal connection line (ADH2) located on the other side (+x direction), and may have a third auxiliary horizontal connection line (ADH3) located on one side (-x direction) of the third horizontal connection line (DH3) and a third auxiliary horizontal connection line (ADH3) located on the other side (+x direction).

[0175] Through this, structural differences can be minimized between pixels through which the first horizontal connection line (DH1) to the third horizontal connection line (DH3) passes and pixels through which the first horizontal connection line (DH1) to the third horizontal connection line (DH3) does not pass. As a result, when the same electrical signal is applied to the pixels, the difference in brightness realized in the pixels is minimized, thereby enabling the implementation of a display device capable of displaying high-quality images. These first auxiliary horizontal connection line (ADH1) to the third auxiliary horizontal connection line (ADH3) and the first horizontal connection line (DH1) to the third horizontal connection line (DH3) can be located on the same layer.

[0176] Similarly, the display device according to the present embodiment may have a first auxiliary additional vertical connection line (ADV1) which is spaced apart from the first additional vertical connection line (DV1), is electrically insulated from the first additional vertical connection line (DV1) and the first horizontal connection line (DH1), and has an extension axis identical to the extension axis of the first additional vertical connection line (DV1) and is located on one side (+y direction) of the first additional vertical connection line (DV1). Likewise, the display device may have a second auxiliary vertical connection line (ADV2) located on one side (+y direction) of the second additional vertical connection line (DV2), and a third auxiliary vertical connection line (ADV3) located on one side (+y direction) of the third additional vertical connection line (DV3). The first auxiliary additional vertical connection line (ADV1) to the third auxiliary additional vertical connection line (ADV3) and the first additional vertical connection line (DV1) to the third additional vertical connection line (DV3) may be located on the same layer.

[0177] Through this, structural differences can be minimized between pixels through which the first additional vertical connection line (DV1) to the third additional vertical connection line (DV3) passes and pixels through which the first additional vertical connection line (DV1) to the third additional vertical connection line (DV3) does not pass. As a result, when the same electrical signal is applied to the pixels, the difference in brightness realized in the pixels is minimized, thereby enabling the implementation of a display device capable of displaying high-quality images.

[0178] The description given above with reference to FIG. 5 can be applied to the display device shown in FIG. 18, except for the differences between the details shown in FIG. 5 and the details shown in FIG. 18 as described above.

[0179] FIGS. 19 and FIGS. 20 are plan views illustrating enlarged portions B and C of the display device of FIG. 18. As described above with reference to FIG. 18, the second horizontal connection line (DH2) is electrically connected to the fourth data line (DL4) through the second connection contact hole (DH-CNT2) located at the other end (-x direction). As shown in FIG. 19, the second horizontal connection line (DH2), which extends approximately in the first direction (x-axis direction), has a portion that protrudes in the second direction (y-axis direction) where the fourth data line (DL4) extends from the portion overlapping with the fourth data line (DL4), and can be connected to the fourth data line (DL4) through the second connection contact hole (DH-CNT2) at the protruding portion.

[0180] And, as described above with reference to FIG. 18, the second horizontal connection line (DH2) is electrically connected to the second additional vertical connection line (DV2) through the first connection contact hole (DH-CNT1) located at the other end (+x direction). At this time, as shown in FIG. 20, the third data line (DL3) intersects the second horizontal connection line (DH2) but is not electrically connected to the second horizontal connection line (DH2). Nevertheless, an island located on the same layer as the second horizontal connection line (DH2) and containing the same material, but spaced apart from the second horizontal connection line (DH2), is located below the third data line (DL3), and the third data line (DL3) can be electrically connected to such an island through the contact hole. Through this, the third data line (DL3) as shown in FIG. 20 can have a contact hole connection structure that is almost similar to the fourth data line (DL4) as shown in FIG. 19, so that the pixels can have the same or similar structure.

[0181] FIGS. 21 and 22 are plan views illustrating enlarged portions of a display device according to an embodiment of the present invention. As shown in FIG. 21, unlike the prior art with reference to FIG. 19, the second horizontal connection line (DH2) extended in approximately the first direction (x-axis direction) may not have a protrusion. Instead, the second vertical connection line (DV2') may be cut at the front and back of the first portion overlapping with the second horizontal connection line (DH2), and the first portion overlapping with the second horizontal connection line (DH2) may be made integral with the fourth data line (DL4). Furthermore, the second horizontal connection line (DH2) may be connected to the fourth data line (DL4) through the second connection contact hole (DH-CNT2) at the first portion overlapping with the second horizontal connection line (DH2). In this case, unlike the above description with reference to FIG. 20, as shown in FIG. 22, there may not be an island at the bottom of the third data line (DL3). This is because even if there is no island, the third data line (DL3) as shown in FIG. 22 can be made to have a structure almost similar to the fourth data line (DL4) as shown in FIG. 21.

[0182] FIG. 23 is a plan view schematically illustrating a part of a display device according to one embodiment of the present invention. The difference between the display device according to the present embodiment and the display device described above with reference to FIG. 5 is that the length of the first vertical connection line (DV1') and the first additional vertical connection line (DV1) of FIG. 23 is longer than the length of the first vertical connection line (DV1') and the first additional vertical connection line (DV1) of FIG. 5, and the length of the third vertical connection line (DV3') and the third additional vertical connection line (DV3) of FIG. 23 is shorter than the length of the third vertical connection line (DV3') and the third additional vertical connection line (DV3) of FIG. 5.

[0183] As illustrated in FIG. 23, among the first horizontal connection line (DH1) to the third horizontal connection line (DH3), the length of the first horizontal connection line (DH1) may be the longest and the length of the third horizontal connection line (DH3) may be the shortest. Accordingly, the lengths of the third vertical connection line (DV3') and the third additional vertical connection line (DV3) electrically connected to the longest first horizontal connection line (DH1) may be made the shortest, and the lengths of the first vertical connection line (DV1') and the first additional vertical connection line (DV1) electrically connected to the shortest third horizontal connection line (DH3) may be made the longest, so that the connection distance between the sixth data line (DL6) and the sixth input line (IL6), the connection distance between the fourth data line (DL4) and the fourth input line (IL4), and the connection distance between the second data line (DL2) and the second input line (IL2) may be the same or similar. This allows for the minimization of data signal distortion caused by voltage drop and other factors as the connection distance changes.

[0184] The part marked C in FIG. 23 may have a structure similar to that described above with reference to FIG. 20 or FIG. 22. The part where the second vertical connection line (DV2') and the second horizontal connection line (DH2) are electrically connected, marked D in FIG. 23, may have a structure similar to that shown in FIG. 24. As shown in FIG. 24, the fourth data line (DL4) extends in the second direction (y-axis direction) by intersecting the second auxiliary horizontal connection line (ADH2), and the second vertical connection line (DV2') may be electrically connected to the second horizontal connection line (DH2) through a contact hole.

[0185] FIG. 25 is a plan view schematically illustrating a part of a display device according to one embodiment of the present invention. The difference between the display device according to the present embodiment and the display device described above with reference to FIG. 18 is that the length of the first additional vertical connection line (DV1) of FIG. 25 is longer than the length of the first additional vertical connection line (DV1) of FIG. 18, and the length of the third additional vertical connection line (DV3) of FIG. 25 is shorter than the length of the third additional vertical connection line (DV3) of FIG. 18.

[0186] As illustrated in FIG. 25, among the first horizontal connection line (DH1) to the third horizontal connection line (DH3), the length of the first horizontal connection line (DH1) may be the longest and the length of the third horizontal connection line (DH3) may be the shortest. Accordingly, the length of the third additional vertical connection line (DV3) electrically connected to the longest first horizontal connection line (DH1) may be the shortest, and the length of the first additional vertical connection line (DV1) electrically connected to the shortest third horizontal connection line (DH3) may be the longest, so that the connection distance between the sixth data line (DL6) and the sixth input line (IL6), the connection distance between the fourth data line (DL4) and the fourth input line (IL4), and the connection distance between the second data line (DL2) and the second input line (IL2) may be the same or similar. Through this, the distortion of the data signal due to voltage drop, etc., as the connection distance changes can be minimized.

[0187] As such, the present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0188] 100: Substrate 1100: First semiconductor layer 1200: 1st Gate Floor 1300: 2nd Gate Floor 1400: Second semiconductor layer 1500: 2nd Gate Floor 1600: First connecting electrode layer 1700: Second connecting electrode layer 1710: Horizontal connection wiring 1800: Third connecting electrode layer 1810: Data wiring 1820: Vertical connection wiring IL1 to IL6: Input lines DL1 to DL6: Data lines DTL1 to DTL3: Data transmission lines DH1, DH2 DH3: Horizontal connection lines DV1, DV2, DV3: Additional vertical connection lines DV1', DV2', DV3': Vertical connection lines

Claims

Claim 1 A display device comprising: a first semiconductor layer disposed on a substrate; a first gate layer located above the first semiconductor layer and including a driving gate electrode; a second gate layer located above the first gate layer and including a capacitor upper electrode; a first connection electrode layer located above the second gate layer and including a transmission line; a second semiconductor layer located between the second gate layer and the first connection electrode layer; a third gate layer located between the second semiconductor layer and the first connection electrode layer and including a compensation gate electrode; a second connection electrode layer located above the first connection electrode layer and including a horizontal connection line extended in a first direction; and a third connection electrode layer located above the second connection electrode layer and including a vertical connection line extended in a second direction intersecting the first direction and a data line extended in the second direction on the same layer. Claim 2 A display device according to claim 1, further comprising: a light-emitting diode including a pixel electrode disposed above the vertical connection wiring; and an insulating layer disposed between the vertical connection wiring and the pixel electrode. Claim 3 A display device according to claim 1, wherein the third gate layer further comprises a gate wiring extended in the first direction. Claim 4 In paragraph 3, the gate wiring intersects the vertical connection wiring, in a display device. Claim 5 A display device according to claim 1, wherein the first semiconductor layer comprises polysilicon and the second semiconductor layer comprises an oxide semiconductor. Claim 6 A display device according to claim 1, wherein the vertical connecting wire is electrically connected to the data wire and the horizontal connecting wire. Claim 7 A display device according to claim 6, wherein the substrate comprises a display area and a peripheral area outside the display area, and the vertical connection wiring is electrically connected to the data wiring in the peripheral area. Claim 8 A display device according to claim 7, wherein the vertical connection wiring and the data wiring are integral. Claim 9 In claim 7, the display device wherein the horizontal connecting wire is electrically connected to the vertical connecting wire within the display area. Claim 10 A display device according to claim 7, wherein the vertical connection wiring is electrically connected to the horizontal connection wiring through a contact hole, and the second connection electrode layer further comprises an auxiliary horizontal connection wiring that is spaced apart from the horizontal connection wiring, is electrically insulated from the horizontal connection wiring and the data wiring, and has an extension axis identical to the extension axis of the horizontal connection wiring. Claim 11 A display device according to claim 7, wherein the vertical connecting wire is electrically connected to the horizontal connecting wire through a contact hole, and the third connecting electrode layer further comprises an auxiliary vertical connecting wire that is spaced apart from the vertical connecting wire, is electrically insulated from the horizontal connecting wire and the vertical connecting wire, and has an extension axis identical to the extension axis of the vertical connecting wire. Claim 12 A display device according to claim 7, wherein the third connecting electrode layer further comprises an additional vertical connecting wire that extends in the second direction and is electrically connected to the horizontal connecting wire within the display area. Claim 13 A display device according to claim 12, wherein the third connecting electrode layer further comprises an auxiliary additional vertical connecting wire that is spaced apart from the additional vertical connecting wire, is electrically insulated from the horizontal connecting wire and the additional vertical connecting wire, and has an extension axis identical to the extension axis of the additional vertical connecting wire. Claim 14 A display device according to claim 1, wherein the substrate includes a display area and a peripheral area outside the display area, and the horizontal connecting wire is electrically connected to the data wire in the display area. Claim 15 A display device according to claim 14, wherein the data wiring is electrically connected to the horizontal connection wiring through a contact hole. Claim 16 A display device according to claim 15, wherein the second connecting electrode layer further comprises an auxiliary horizontal connecting wire that is spaced apart from the horizontal connecting wire and is electrically insulated from the horizontal connecting wire and the data wire, and has an extension axis identical to the extension axis of the horizontal connecting wire.

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