Decoder for Block Orthogonal Sparse Superposition Codes and the method thereof

Abstract

A decoder for a block orthogonal sparse overlapping code according to an embodiment of the present invention is a decoder for decoding a signal received through a transmission channel in a communication system, and is characterized by comprising: a rearrangement unit that generates a plurality of rearranged vectors by multiplying a plurality of random permutation unit matrices (P0~P31) by the received signal (r); an operation unit that generates a plurality of output vectors in parallel by multiplying a plurality of rearranged vectors generated by the rearrangement unit by a block diagonal Hadamard matrix; an extraction unit that generates message vector candidates by extracting pairs of maximum-minimum values ​​from each output vector generated by the operation unit; a calculation unit that calculates a reliability score from the generated message vector candidates; and an output unit that outputs a message vector of the maximum value of the calculated reliability score.

Description

Technology Field

[0001] The present invention relates to a decoder for block orthogonal sparse overlap codes and a method thereof, and in particular, to a decoder for block orthogonal sparse overlap codes and a method thereof that can operate the entire operation with low latency and high efficiency by providing BOSS decoder hardware of an IMMT structure and an FWHT-based MVM operator, and can minimize area-time (AT) complexity while reducing the total area of ​​the decoder. Background Technology

[0003] Sparse superposition code (SPARC) is a family of capacity-achieving codes. In SPARC, codewords are represented as a combination of sparse linear columns in a dictionary matrix. Through a Gaussian random dictionary matrix for encoding and adaptive continuous threshold decoding, SPARC asymptotically achieves Gaussian channel capacity as block lengths approach infinity with polynomial-time decoding complexity. Despite its theoretical basis, SPARC provides sub-standard block-error-rate (BLER) performance in the short block length range, which is attracting significant interest for ultra-reliable low-latency communications (URLLC).

[0004] Next-generation communication defines URLLC scenarios and requires the simultaneous achievement of high reliability, low latency, and low power performance during the communication process. To meet the requirements of URLLC scenarios, error correction codes using short block lengths and low code rates are required. Conventional error correction codes, including 5G polar codes and 5G LDPC, cannot simultaneously achieve high reliability, low latency, and low power when using short block lengths and low code rates.

[0005] Recently developed BOSS (Block Orthogonal Sparse Superposition) code was developed as a technology capable of achieving high-reliability, low-latency performance at very short block lengths and low code rates, presenting the potential to meet the requirements of URLLC scenarios.

[0006] However, BOSS decoding operates based on the maximum-a-postriori algorithm, which has the problem of increased hardware implementation costs and poor energy efficiency because it involves computationally complex matrix-vector multiplication and sorting operations. The problem to be solved

[0008] To solve the aforementioned problems, a decoder and a method for block orthogonal sparse nested code are provided, which can operate the entire operation with low latency and high efficiency by providing FWHT-based MVM operators and BOSS decoder hardware of IMMT structure, and can minimize area-time (AT) complexity while reducing the total area of ​​the decoder.

[0009] However, the technical problems that the present invention aims to solve are not limited to those described above, and other unmentioned problems will be clearly understood by those skilled in the art from the description of the invention below. means of solving the problem

[0011] A decoder for a block orthogonal sparse overlapping code according to one embodiment of the present invention is a decoder for decoding a signal received through a transmission channel in a communication system, wherein a plurality of random permutation unit matrices (P0~P 31 The invention is characterized by comprising: a rearrangement unit that generates a plurality of rearranged vectors by multiplying the plurality of rearranged vectors generated by the rearrangement unit and a block diagonal Hadamard matrix to generate a plurality of output vectors in parallel; an extraction unit that generates message vector candidates by extracting pairs of maximum and minimum values ​​from each output vector generated by the operation unit; an output unit that calculates a reliability score from the generated message vector candidates; and an output unit that outputs a message vector of the maximum value of the calculated reliability score.

[0012] Here, in particular, the rearrangement unit includes four parallel operation lanes, and each operation lane is composed of eight units, using a Permutation Unit (PU) to handle the received signal and 32 permutation unit matrices (P0~P 31 Its characteristic feature is that it generates 32 rearranged vectors from ).

[0013] Here, in particular, the rearrangement unit includes four parallel operation lanes, and each operation lane is composed of eight units, using a permutation unit (PU) to handle the received signal and 32 permutation unit matrices (P0~P 31 Its characteristic feature is that it generates 32 rearranged vectors from ).

[0014] Here, in particular, the operation unit is characterized by performing identity matrix-vector multiplication based on the Fast Walsh-Hadamard Transform (FWHT) using the rearranged 32 vectors and the Hadamard matrix.

[0015] Here, in particular, the 128×128 of the above Hadamard matrix is ​​configured as a 16x16 block diagonal identity matrix to perform parallel operations based on 8 fast Walsh-Hadamard transformations.

[0016] Here, in particular, the operation unit performs matrix-vector multiplication (MVM) on the 32 rearranged vectors and the block diagonal 128x128 Hadamard matrix to obtain 32 128x1 output vectors (U0r~ U 31 r or HP0r~HP 31 Its characteristic lies in the fact that it generates r).

[0017] Here, in particular, the extraction unit is characterized by applying four iterative max-min trees (IMMT) to extract four max-min pairs from 128 message vector candidates.

[0018] Here, in particular, the iterative Max-Min Tree (IMMT) configuration is characterized by including: an index checker that removes previous maximum / minimum values; a comparison switch that outputs two 64-x1 message vector candidates in units of 64 CAS from a 128-x1 message vector candidate output from the operation unit; a maximum tree that outputs a maximum value from the 64-x1 message vector candidate output from the comparison switch; and a minimum tree that outputs a minimum value from the 64-x1 message vector candidate output from the comparison switch.

[0019] In addition, a decoding method for a block orthogonal sparse overlapping code according to an embodiment of the present invention is characterized in that, in a method for decoding a signal received through a transmission channel in a communication system, the method comprises: a step of generating a plurality of rearranged vectors using data of the received signal and a plurality of permutation unit matrices; a step of generating a plurality of output vectors in parallel using the plurality of rearranged vectors and a block diagonal Hadamard matrix; a step of generating message vector candidates by extracting pairs of maximum and minimum values ​​from the generated output vectors; a step of calculating reliability from the generated message vector candidates; and a step of outputting a message vector of the maximum value of the calculated reliability.

[0020] Here, particularly in the rearrangement step, each operation lane is composed of 8 units, including 4 parallel operation lanes, and using a Permutation Unit (PU), the received signal and 32 permutation unit matrices (P0~P 31 Its characteristic feature is that it generates 32 rearranged vectors from ).

[0021] Here, in particular, it is characterized by performing identity matrix-vector multiplication based on the Fast Walsh-Hadamard Transform (FWHT) using the 32 rearranged vectors and the Hadamard matrix.

[0022] Here, in particular, the 128×128 of the above Hadamard matrix is ​​configured as a 16x16 block diagonal identity matrix to perform parallel operations based on 8 fast Walsh-Hadamard transformations.

[0023] Here, particularly in the step of generating the output vectors, matrix-vector multiplication (MVM) is performed on the 32 rearranged vectors and the block diagonal 128x128 Hadamard matrix to obtain 32 128x1 output vectors (U0r~ U 31 r or HP0r~HP 31Its characteristic lies in the fact that it generates r).

[0024] Here, in particular, the step of generating the message vector candidates is characterized by applying four iterative max-min trees (IMMT) to extract four max-min pairs from 128x1 message vector candidates.

[0025] Here, in particular, the extraction of maximum-minimum pairs in the iterative max-min tree (IMMT) is characterized by the fact that, when the previous maximum / minimum values ​​are removed to output the 128-x1 message vector candidates into two 64-x1 message vector candidates in units of 64 CAS, the maximum value is output from the outputted 64-x1 message vector candidates and the minimum value is output from the outputted 64-x1 message vector candidates. Effects of the invention

[0027] According to one embodiment of the present invention described above, by providing FWHT-based MVM operator and BOSS decoder hardware of IMMT structure, the entire operation can be operated with low latency and high efficiency, and area-time (AT) complexity can be minimized while reducing the total area of ​​the decoder.

[0028] However, the effects obtainable through the present invention are not limited to those described above, and other unmentioned technical effects will be clearly understood by those skilled in the art from the description of the invention below. Brief explanation of the drawing

[0030] FIG. 1 is a diagram schematically illustrating the overall concept of a communication system to which the URLLC scenario of the present invention is applied. FIG. 2 is a schematic diagram illustrating the configuration of a decoder for a block orthogonal sparse overlapping code according to an embodiment of the present invention. FIG. 3 is a diagram visualizing the overall structure of the block orthogonal sparse superposition decoder (BOSS decoder) of the present invention. FIG. 4 is a diagram illustrating a structured processing process performed in the FWHT-based computation unit of the present invention. FIG. 5 is a diagram showing a comparison of the processing results of the FWHT of the present invention. FIG. 6 is a diagram illustrating the structured processing performed in the fast maximum-minimum tree (IMMT)-based extraction unit of the present invention. FIG. 7 is a diagram showing an example of a maximum-minimum pair output by two modes in the IMMT processing process of the present invention. FIG. 8 is a diagram showing a comparison of the processing results of the IMMT of the present invention. FIG. 9 is a diagram showing a comparison table of error correction codes of the block orthogonal sparse superposition decoder (BOSS decoder) of the present invention. FIG. 10 is a diagram schematically illustrating the sequence of a decoding method for a block orthogonal sparse nested code according to an embodiment of the present invention. Specific details for implementing the invention

[0031] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments will be described in detail with reference to the drawings. However, this is not intended to limit the invention to specific embodiments, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention. Similar reference numerals have been used for similar components in the description of each drawing.

[0032] Terms such as first, second, A, B, etc., may be used to describe various components, but said components shall not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" includes a combination of multiple related description items or any of the multiple related description items.

[0033] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0034] Throughout the specification and claims, when a part is described as including a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0036] FIG. 1 is a diagram schematically illustrating the overall concept of a communication system to which the URLLC scenario of the present invention is applied; FIG. 2 is a diagram schematically illustrating the configuration of a decoder for a block orthogonal sparse nested code according to an embodiment of the present invention; FIG. 3 is a diagram visualizing the overall structure of the block orthogonal sparse nested decoder (BOSS decoder) of the present invention; FIG. 4 is a diagram structuring and illustrating the processing process performed in the FWHT-based operation unit of the present invention; FIG. 5 is a diagram showing a comparison of the processing results of the FWHT of the present invention; FIG. 6 is a diagram structuring and illustrating the processing process performed in the fast max-min tree (IMMT)-based extraction unit of the present invention; FIG. 7 is a diagram showing examples of max-min pairs output by two modes in the IMMT processing process of the present invention; and FIG. 8 is a diagram showing a comparison of the processing results of the IMMT of the present invention.

[0038] As illustrated in FIG. 1, the communication system of the present invention may include at least one transmitter for simultaneously transmitting a plurality of information symbols through a communication channel and a receiver for receiving one or more of the symbols transmitted by the transmitter in the form of independent signals. Here, the communication between the encoder of the transmitter and the decoder of the receiver applies a URLLC scenario, and high reliability, low latency, and low power performance can be simultaneously satisfied during the communication process. Such Ultra-Reliable Low-Latency Communication (URLC) is one of the key elements of next-generation communication technology (particularly 5G). URLLC is a communication technology designed to support applications and services that require very high reliability and low latency.

[0040] As illustrated in FIGS. 2 and 3, a decoder (100) for a block orthogonal sparse nested code according to one embodiment of the present invention may be configured to include a rearrangement unit (110), an operation unit (120), an extraction unit (130), a calculation unit (140), and an output unit (150).

[0042] The rearrangement unit (110) is a decoder for decoding a signal received through a transmission channel in a communication system, and generates a plurality of rearranged vectors using the data of the received signal and a plurality of permutation unit matrices.

[0043] More specifically, the rearrangement unit (110) includes four parallel operation lanes, and each operation lane consists of eight permutation units (PU) that generate a rearranged vector from the received signal. The 32 permutation units (PU) of the rearrangement unit (110) consist of the received signal and a matrix of 32 permutation units (P0~P 31 32 rearranged vectors are generated from ). That is, the rearrangement unit (110) reconstructs or rearranges the order of data transmitted from the transmitter to increase computational efficiency in the next processing step. Here, permutation-based matrix-vector multiplication (MVM) may be applied to the rearrangement unit (110).

[0045] The operation unit (120) generates an output vector by performing identity matrix-vector multiplication based on the Fast Walsh-Hadamard Transform (FWHT) using the 32 rearranged vectors and the Hadamard matrix.

[0047] More specifically, the operation unit (120) performs matrix-vector multiplication using the 32 rearranged vectors and the block diagonal Hadamard matrix. The matrix-vector multiplication (MVM) is performed using a Fast Walsh-Hadamard Transform (FWHT)-based MVM. Here, the Fast Walsh-Hadamard Transform-based MVM is a highly efficient transformation technique for large vectors and matrices, operating in a manner similar to the Fast Fourier Transform (FFT), and reduces the complexity of vector-matrix multiplication from O(N^2) to O(N log N). That is, by utilizing the orthogonality and binary structure of the Hadamard matrix, FWHT operations are performed without a multiplier, enabling the implementation of efficient and fast computation. In other words, it can be implemented using only simple addition operations without a multiplier, thereby reducing hardware costs by 95%.

[0048] In addition, for an efficient FWHT-based MVM operator that applies the unique properties (sparseness, orthogonality) of the Hadamard matrix, the Hadamard matrix is ​​selected as the base matrix (H) and utilized in the Fast Walsh-Hadamard Transform (FWHT).

[0049] For example, a 128x128 Hadamard matrix is ​​converted into a 128x128 elementary matrix (H).

[0050] Then, the elementary matrix (H), which is a 128x128 Hadamard matrix, is divided into 16x16 block diagonal identity matrices to perform 8 parallel operations.

[0051] Accordingly, the operation unit (120) performs matrix-vector multiplication (MVM) on the 32 rearranged vectors and the block diagonal 128x128 Hadamard matrix to obtain 32 128x1 output vectors (U0r~ U 31 r or HP0r~HP 31 r) will be generated

[0052] Additionally, referring to FIG. 4 regarding the configuration of FIG. 3, the Fast Walsh-Hadamard Transform (FWHT) based MVM, which is the operation unit (120), shows that a low-cost FWHT-based MVM operator was designed using three optimization structures to reduce the hardware complexity of a general MVM calculator required for BOSS decoding.

[0053] First, based on the fact that a permutation of the identity matrix is ​​also an identity matrix, 32 different identity matrices (U0–U31) are constructed by multiplying a single base matrix (H) by 32 different permutation matrices (P0–P31). To construct a parallel decoder, an NF (<=32) MVM operator shared with 32 / NF PUs is instantiated. Thanks to this permutation-based identity matrix, a standard MVM operator can be replaced with a constant MVM operator (fixed matrix input H), thereby reducing area cost by 51%.

[0054] Additionally, to reduce computational complexity, two constraints are applied to design a low-cost basic matrix H: making it a Hadamard matrix and configuring it as a block diagonal matrix.

[0055] Here, if H is selected as a 128 x 128 Hadamard matrix, cost-effective FWHT processing can be used to perform the proposed constant MVM. Thanks to the unique properties of the Hadamard matrix, the FWHT-based MVM operator can be realized using only simple addition operations without using multipliers, which can reduce hardware costs by 95%.

[0056] In addition, by introducing a block diagonal identity matrix, 128x128 FWHT operations can be decomposed into smaller 16x16 operations, which can further reduce area costs by 43%.

[0057] Referring to Figure 5, the interaction between total decoder latency and area is analyzed by finally adjusting the NF while using a low-cost MVM calculator. Selecting NF=4 minimizes area-time (AT) complexity while reducing the total decoder area by 86% compared to a standard architecture using a standard MVM calculator. This allows for an additional 43% reduction in hardware area costs.

[0059] The extraction unit (130) extracts pairs of maximum and minimum values ​​from the output vector generated by the operation unit to generate message vector candidates.

[0060] More specifically, the extraction unit (130) applies four iterative max-min trees (IMMT) to extract four max-min pairs from 128 message vector candidates. Here, the iterative max-min tree (IMMT) configuration may be configured to include an index checker (131) that removes previous max / min values, a comparison switch (132) that outputs two 64x1 message vector candidates from the 128x1 message vector candidates output from the operation unit in units of 64 CAS, a max tree (133) that outputs a max value from the 64x1 message vector candidates output from the comparison switch, and a min tree (134) that outputs a min value from the 64x1 message vector candidates output from the comparison switch.

[0061] Additionally, referring to FIG. 6 regarding the configuration of FIG. 3, the extraction unit (130) aims to find four maximum-minimum pairs for each Uxr in the 4-stage IMMT structure, namely (Imax1, Imin1), (Imax2, Imin2), (Imax3, Imin3), and (Imax4, Imin4), as message candidates, where Imaxk (or Imink) represents the index of the first k-th maximum (or minimum) element of the Uxr. At this time, Imaxk and Imink cannot both be even or odd at the same time.

[0062] In addition, the IMMT of the extraction unit (130) of the present invention applies an iterative search architecture that sequentially generates four maximum-minimum pairs over four cycles.

[0063] The index checker (131) of the extraction unit (130) removes the previous maximum / minimum value so that the next IMMT operation can properly find the next maximum-minimum pair. The comparison switch (132) creates two outputs of size 64 from the 128 x 1 result of Uxr with 64 CAS units, which are passed to the search tree to find the maximum value, the minimum value and their indices.

[0064] Additionally, as illustrated in FIG. 7, to obtain valid max-min pairs, the comparison switch (132) provides two computation modes by dynamically changing the input according to the previous result. Mode 1 is defined in the first IMMT iteration and activates the min tree with 64 elements from the CAS unit. Mode 2 is defined for the remaining IMMT iterations and simply passes odd or even index elements to the min tree according to the previous max index.

[0065] These two computation modes enable finding four valid pairs within four cycles without additional cycles. Selecting the number of IMMT (NT) is important for achieving the optimal balance between latency and complexity.

[0066] Therefore, as shown in FIG. 8, it can be seen that the decoder (100) of the present invention uses 16 IMMTs to reduce area costs by 79% while maintaining the same delay time as a standard design using a conventional bitonic sorter.

[0068] The output unit (140) calculates a reliability score from the generated message vector candidates. It calculates a reliability score from the four output message vector candidates of maximum-minimum valid pairs. Here, the reliability score may be the sum of the absolute values ​​of each pair. Accordingly, the output unit (140) calculates and outputs the absolute value of each maximum-minimum valid pair.

[0070] The output unit (150) outputs a message vector of the maximum value of the calculated reliability score. That is, it selects and outputs a maximum-minimum pair having the maximum value from the absolute values ​​of each maximum-minimum valid pair output from the output unit (140). This outputs the message vector value that is finally determined and output from the message vector candidates.

[0071] Meanwhile, FIG. 9 is a diagram showing a comparison table of error correction codes of the block orthogonal sparse superposition decoder (BOSS decoder) of the present invention.

[0072] As shown in Fig. 9, the measurement results of a prototype BOSS decoder fabricated in a 28nm CMOS process are displayed. At a nominal supply voltage of 0.95V, the decoder (128, 15) achieved a short delay time of 21.9 ns and a power consumption of 33.3 mW to decode a codeword. These results surpass conventional short-length FEC solutions [2-3] and provide a Frame-error rate (FER) comparable to that of medium-length LDPC codes [4]. The implementation results of the URLLC FEC decoder [2-6] show that it requires Eb / N0=5.2dB for a target FER of 10^-5, and achieves the lowest delay time, best area efficiency (15.78 Gbps / mm2), and best energy efficiency (5.7 pJ / b) compared to [2-6].

[0074] FIG. 10 is a diagram schematically illustrating the sequence of a decoding method for a block orthogonal sparse nested code according to an embodiment of the present invention. Here, a detailed description of the decoding method for a block orthogonal sparse nested code is omitted with reference to FIG. 2 to FIG. 9 described above.

[0076] As illustrated in FIG. 10, the decoding method for a block orthogonal sparse nested code of the present invention first comprises a signal received through a transmission channel in a communication system and a total of 32 permutation unit matrices (P0~P 31 The step of generating 32 rearranged vectors from ) is performed (S110). Here, each operation lane is configured with 8 units, including 4 parallel operation lanes, and using a Permutation Unit (PU), the received signal and 32 permutation unit matrices (P0~P 3132 rearranged vectors are generated from ). At this time, identity matrix-vector multiplication is performed based on the Fast Walsh-Hadamard Transform (FWHT) using the 32 rearranged vectors and the Hadamard matrix. Here, the 128x128 of the Hadamard matrix is ​​configured as a 16x16 block diagonal identity matrix to perform parallel operations based on 8 Fast Walsh-Hadamard Transforms.

[0078] Then, the above rearranged permutation unit matrix (PU) is generated into a Hadamard matrix, divided into block diagonal unit matrices, and then parallel operations are performed to generate an output vector (S120).

[0079] Here, the rearranged permutation identity matrix (PU) is transformed to generate a Hadamard matrix based on the Fast Walsh-Hadamard Transform (FWHT) and fixed as the base matrix (H). After transforming the Hadamard matrix into a 128x128 base matrix (H), it is divided into 16x16 block diagonal identity matrices to perform 8 parallel operations. Then, matrix-vector multiplication (MVM) is performed on the 32 rearranged vectors and the block diagonal 128x128 Hadamard matrix to produce 32 128x1 output vectors (U0r~ U 31 r or HP0r~HP 31 r) will be generated

[0081] Next, a step is performed to generate message vector candidates by extracting pairs of maximum and minimum values ​​from the generated output vector (S130). Here, four iterative max-min trees (IMMT) are applied to extract four maximum-minimum pairs from the 128-x1 message vector candidates to generate message vector candidates. At this time, the extraction of maximum-minimum pairs in the iterative max-min tree (IMMT) involves removing the previous maximum / minimum values ​​to output the 128-x1 message vector candidates into two 64-x1 message vector candidates in units of 64 CAS, and then outputting the maximum value from the outputted 64-x1 message vector candidates and the minimum value from the outputted 64-x1 message vector candidates.

[0083] Next, a step of calculating reliability from the generated message vector candidates is performed (S140). Reliability scores are calculated from the four output message vector candidates of maximum-minimum valid pairs. Here, the reliability score may be the sum of the absolute values ​​of each pair. Accordingly, the absolute value of each maximum-minimum valid pair is calculated and output.

[0085] Then, the step of outputting the message vector of the maximum value of the calculated confidence is performed (S150). The maximum-minimum pair having the maximum value among the absolute values ​​of each outputted maximum-minimum valid pair is selected and output. This outputs the message vector value that is finally determined and output from the message vector candidates.

[0087] Accordingly, according to the present invention described above, area-time (AT) complexity can be minimized while reducing the total area of ​​the decoder by 86% compared to a decoder architecture using a general MVM calculator.

[0088] In addition, the BOSS decoder of the present invention can reduce area costs by 79% by using 16 IMMTs while maintaining the same delay time as a design method using a bitonic sorter.

[0090] One embodiment of the present invention may also be implemented in the form of a recording medium containing computer-executable instructions, such as program modules executed by a computer. A computer-readable medium may be any available medium accessible by a computer and includes both volatile and non-volatile media, and both removable and non-removable media. Additionally, a computer-readable medium may include both computer storage media and communication media. A computer storage medium includes both volatile and non-volatile, removable and non-removable media implemented by any method or technique for storing information, such as computer-readable instructions, data structures, program modules, or other data. A communication medium typically includes computer-readable instructions, data structures, program modules, or other data of modulated data signals such as carrier waves, or other transmission mechanisms, and includes any information transmission medium.

[0091] Although the method and system of the present invention have been described in relation to specific embodiments, some or all of their components or operations may be implemented using a computer system having a general-purpose hardware architecture.

[0092] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical spirit or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single unit may be implemented in a distributed manner, and components described as distributed may likewise be implemented in a combined form.

[0093] The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0095] 110: Rearrangement section 120: Operation unit 130: Extraction section 131: Index Checker 132: Comparative exchange 133: Maximum tree 134: Minimum Tree 140: Output section 150: Output section

Claims

Claim 1 In a decoder for decoding a signal received through a transmission channel in a communication system, a plurality of random permutation unit matrices (P0~P) are applied to the received signal (r). 31 A decoder for a block orthogonal sparse nested code comprising: a rearrangement unit that generates a plurality of rearranged vectors by multiplying the plurality of rearranged vectors generated by the rearrangement unit and a block diagonal Hadamard matrix to generate a plurality of output vectors in parallel; an extraction unit that generates message vector candidates by extracting pairs of maximum and minimum values ​​from the output vectors generated by the operation unit; an output unit that calculates a confidence score from the generated message vector candidates; and an output unit that outputs a message vector of the maximum value of the calculated confidence score. Claim 2 In claim 1, the rearrangement unit includes four parallel operation lanes, and each operation lane is composed of eight units, using a permutation unit (PU) to handle the received signal and 32 permutation unit matrices (P0~P 31 A decoder for block orthogonal sparse nested codes characterized by generating 32 rearranged vectors from ). Claim 3 A decoder for a block orthogonal sparse nested code according to claim 1, wherein the operation unit performs identity matrix-vector multiplication based on the Fast Walsh-Hadamard Transform (FWHT) using the rearranged 32 vectors and the Hadamard matrix. Claim 4 A decoder for a block orthogonal sparse nested code according to claim 3, characterized by configuring the 128×128 of the Hadamard matrix into a 16x16 block diagonal identity matrix and performing parallel operations based on 8 fast Walsh-Hadamard transforms. Claim 5 In paragraph 4, the operation unit performs matrix-vector multiplication (MVM) on the 32 rearranged vectors and the block diagonal 128x128 Hadamard matrix to obtain 32 128x1 output vectors (U0r~ U 31 r or HP0r~HP 31 A decoder for block orthogonal sparse nested codes characterized by generating r). Claim 6 A decoder for block orthogonal sparse nested codes according to claim 1, wherein the extraction unit extracts 4 maximum-minimum pairs from 128 message vector candidates by applying 4 iterative max-min trees (IMMT). Claim 7 A decoder for a block orthogonal sparse nested code according to claim 6, wherein the iterative Max-Min Tree (IMMT) configuration comprises: an index checker that removes previous maximum / minimum values; a comparison switch that outputs two 64-X1 message vector candidates in units of 64 CAS from a 128-X1 message vector candidate output from the operation unit; a max tree that outputs a maximum value from the 64-X1 message vector candidate output from the comparison switch; and a min tree that outputs a minimum value from the 64-X1 message vector candidate output from the comparison switch. Claim 8 A decoding method for a block orthogonal sparse nested code comprising: a step of generating a plurality of rearranged vectors using data of the received signal and a plurality of permutation unit matrices; a step of generating a plurality of output vectors in parallel using the plurality of rearranged vectors and a block diagonal Hadamard matrix; a step of generating message vector candidates by extracting pairs of maximum and minimum values ​​from the generated output vectors; a step of calculating confidence from the generated message vector candidates; and a step of outputting a message vector of the maximum value of the calculated confidence. Claim 9 In claim 8, in the rearrangement step, each operation lane is composed of 8 units, including 4 parallel operation lanes, and the received signal and 32 permutation unit matrices (P0~P) are used with permutation units (PU). 31 A decoding method for block orthogonal sparse nested codes characterized by generating 32 rearranged vectors from ). Claim 10 A decoding method for block orthogonal sparse nested codes according to claim 8, characterized by performing identity matrix-vector multiplication based on the Fast Walsh-Hadamard Transform (FWHT) using the rearranged 32 vectors and the Hadamard matrix. Claim 11 A decoding method for block orthogonal sparse nested codes according to claim 10, characterized by constructing the 128×128 of the Hadamard matrix into a 16x16 block diagonal identity matrix and performing parallel operations based on 8 fast Walsh-Hadamard transforms. Claim 12 In claim 11, in the step of generating the output vector, matrix-vector multiplication (MVM) is performed on the 32 rearranged vectors and the block diagonal 128x128 Hadamard matrix to obtain 32 128x1 output vectors (U0r~ U 31 r or HP0r~HP 31 A decoding method for block orthogonal sparse nested codes characterized by generating r). Claim 13 A decoding method for block orthogonal sparse nested codes according to claim 8, characterized in that, in the step of generating the message vector candidates, four iterative max-min trees (IMMT) are applied to extract four max-min pairs from 128-x1 message vector candidates. Claim 14 A decoding method for block orthogonal sparse nested codes according to claim 13, wherein the extraction of maximum-minimum pairs in the iterative max-min tree (IMMT) is characterized by removing the previous maximum / minimum value to output the 128-x1 message vector candidate into two 64-x1 message vector candidates in units of 64 CAS, outputting the maximum value from the outputted 64-x1 message vector candidates, and outputting the minimum value from the outputted 64-x1 message vector candidates.

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