Semiconductor device

Abstract

The present disclosure relates to a semiconductor device, wherein a semiconductor device according to one embodiment comprises a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type different from the first conductivity type located on the first semiconductor layer, a third semiconductor layer having the first conductivity type located on the second semiconductor layer, a gate electrode located on the third semiconductor layer, a semiconductor pattern having the second conductivity type located on the third semiconductor layer, an anode electrode located on the semiconductor pattern, and a cathode electrode located on the lower surface of the first semiconductor layer, wherein the semiconductor pattern comprises a first pattern located on the lower surface of the anode electrode and comprising a semiconductor material having a first energy band gap, and a second pattern located between the first pattern and the third semiconductor layer and comprising a semiconductor material having a second energy band gap larger than the first energy band gap.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor device. Background Technology

[0002] In modern society, semiconductor devices are closely related to daily life. In particular, the importance of power semiconductor devices is steadily increasing, as they are used in various fields such as transportation (electric vehicles, railways, and electric trams), renewable energy systems (solar and wind power), and mobile devices. Power semiconductor devices are semiconductor components used to handle high voltage or high current, performing functions such as power conversion and control in large-scale power systems or high-output electronic devices. Power semiconductor devices possess the capability to handle high power and durability, allowing them to process large amounts of current and withstand high voltages. For example, power semiconductor devices can handle voltages ranging from hundreds to thousands of volts and currents ranging from tens to thousands of amperes. Power semiconductor devices can improve the efficiency of electrical energy by minimizing power loss. Furthermore, power semiconductor devices can operate stably even in environments such as high temperatures.

[0003] These power semiconductor devices can be classified according to their materials, such as SiC power semiconductor devices and GaN power semiconductor devices. By manufacturing power semiconductor devices using SiC or GaN instead of conventional silicon wafers (Si wafers), the disadvantages of silicon, which has unstable characteristics at high temperatures, can be compensated for. SiC power semiconductor devices are resistant to high temperatures and have low power loss, making them suitable for electric vehicles and renewable energy systems. Among these, semiconductor devices with a super junction structure are widely used to improve the trade-off between the forward characteristics and breakdown voltage of power semiconductor devices. The problem to be solved

[0004] The embodiments are intended to provide a semiconductor device that can improve reliability. means of solving the problem

[0005] A semiconductor device according to one embodiment comprises a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type different from the first conductivity type located on the first semiconductor layer, a third semiconductor layer having the first conductivity type located on the second semiconductor layer, a gate electrode located on the third semiconductor layer, a semiconductor pattern having the second conductivity type located on the third semiconductor layer, an anode electrode located on the semiconductor pattern, and a cathode electrode located on the lower surface of the first semiconductor layer, wherein the semiconductor pattern includes a first pattern located on the lower surface of the anode electrode and comprising a semiconductor material having a first energy band gap, and a second pattern located between the first pattern and the third semiconductor layer and comprising a semiconductor material having a second energy band gap larger than the first energy band gap.

[0006] A semiconductor device according to one embodiment comprises a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type different from the first conductivity type located on the first semiconductor layer, a third semiconductor layer having the first conductivity type located on the second semiconductor layer, a gate electrode located on the third semiconductor layer, a semiconductor pattern having the second conductivity type located on the third semiconductor layer and comprising a first element and a second element which are semiconductor elements, an anode electrode located on the semiconductor pattern, and a cathode electrode located on the lower surface of the first semiconductor layer, wherein the semiconductor pattern includes a first pattern and a second pattern located between the first pattern and the third semiconductor layer, and the content (at%) of the second element in the second pattern is greater than the content (at%) of the second element in the first pattern.

[0007] A semiconductor device according to one embodiment comprises a substrate including a first surface and a second surface facing each other, a first semiconductor layer of a first conductivity type located on the first surface of the substrate, a second semiconductor layer of a second conductivity type different from the first conductivity type located on the first semiconductor layer, a third semiconductor layer of the first conductivity type located on the second semiconductor layer and containing SiC, a gate electrode located on the third semiconductor layer, a semiconductor pattern of the second conductivity type located on the third semiconductor layer and containing SiC, an anode electrode located on the semiconductor pattern, and a cathode electrode located on the lower surface of the first semiconductor layer, wherein the semiconductor pattern includes a first pattern having a first energy band gap and containing Si of a first content (at%), and a second pattern located between the first pattern and the third semiconductor layer and containing Si of a second content (at%) smaller than the first content (at%).

[0008] A method for manufacturing a semiconductor device according to one embodiment comprises the steps of: sequentially forming a second semiconductor layer of a second conductivity type and a third semiconductor layer of the first conductivity type on a first semiconductor layer of a first conductivity type; forming a semiconductor pattern of a second conductivity type on the third semiconductor layer, the second pattern including a semiconductor material having a second energy band gap and a first pattern including a semiconductor material having a first energy band gap smaller than the second energy band gap; patterning the semiconductor pattern to expose at least a portion of the third semiconductor layer; and forming a gate electrode on the third semiconductor layer, forming an anode electrode on the semiconductor pattern, and forming a cathode electrode on the lower surface of the first semiconductor layer.

[0009] The step of forming the semiconductor pattern above can be performed by using epitaxial growth that utilizes the third semiconductor layer as a seed to form the semiconductor pattern.

[0010] The first semiconductor layer may include a material having a third energy band gap that is equal to or greater than the second energy band gap.

[0011] The first pattern and the second pattern include a first element and a second element, and the content (at%) of the first element in the second pattern may be smaller than the content (at%) of the first element in the first pattern.

[0012] The first semiconductor layer comprises the first element and the second element, and the content (at%) of the first element in the second pattern may be greater than or equal to the content (at%) of the first element in the first semiconductor layer.

[0013] The first element above includes Si, and the second element above may include C.

[0014] The first semiconductor layer comprises the first element and the second element, and the second pattern comprises the first element, the second element, and a third element which is a semiconductor element different from the first element and the second element, and the content (at%) of the second element in the second pattern may be less than or equal to the content (at%) of the second element in the first semiconductor layer.

[0015] The first element above includes Si, the second element includes C, and the third element may include Ge.

[0016] The second pattern above includes the first element, the second element, and the third element, which are semiconductor elements, and the content (at%) of the second element of the second pattern may be greater than the content (at%) of the second element of the first pattern. Effects of the invention

[0017] The semiconductor device according to the embodiments can improve the reliability of the semiconductor device. Brief explanation of the drawing

[0018] FIG. 1 is a cross-sectional view showing a semiconductor device according to one embodiment. FIG. 2 is a graph showing the semiconductor pattern of a semiconductor device and the content of the material constituting the third semiconductor layer according to one embodiment. FIGS. 3 to 8 are graphs illustrating the semiconductor pattern of a semiconductor device and the content of a material constituting a third semiconductor layer according to some embodiments. FIG. 9 is a cross-sectional view showing a semiconductor device according to some embodiments. FIGS. 10 to 12 are graphs illustrating the semiconductor pattern of a semiconductor device and the content of a material constituting a third semiconductor layer according to an embodiment of FIG. 9. FIG. 13 is a cross-sectional view showing a semiconductor device according to some embodiments. FIGS. 14 to 17 are cross-sectional views of an intermediate process step illustrating a method for manufacturing a semiconductor device according to one embodiment. Specific details for implementing the invention

[0019] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0020] To clearly explain the present invention, parts unrelated to the description have been omitted, and the same reference numerals are used for identical or similar components throughout the specification.

[0021] Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thicknesses have been enlarged in the drawings to clearly represent various layers and regions. Additionally, for convenience of explanation, the thickness of some layers and regions has been exaggerated in the drawings.

[0022] Furthermore, when a part such as a layer, membrane, region, or plate is said to be "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Also, being "on" or "on" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "on" in the direction opposite to gravity.

[0023] Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0024] Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side.

[0025] Hereinafter, a semiconductor device according to one embodiment will be described with reference to FIG. 1.

[0026] FIG. 1 is a plan view showing a semiconductor device according to one embodiment.

[0027] A semiconductor device according to one embodiment may be a thyristor. For example, a semiconductor device according to one embodiment may be a Gate Turn-Off thyristor (GTO) device with improved turn-off characteristics, but is not limited thereto. The thyristor may have a structure in which a PNP Bipolar Junction Transistor (BJT) and an NPN Bipolar Junction Transistor (BJT) are combined. In an exemplary embodiment, the thyristor may be a combination of a PNP transistor and an NPN transistor to handle high voltage and high current through mutual current amplification action, etc. For example, the thyristor may be used as a power device, but is not limited thereto, and its application may be varied.

[0028] Referring to FIG. 1, a semiconductor device according to one embodiment includes a substrate (110), a first semiconductor layer (131) located on a first surface (110a) of the substrate (110), a second semiconductor layer (132) located on the first semiconductor layer (131), a third semiconductor layer (133) located on the second semiconductor layer (132), a gate electrode (150) located on the third semiconductor layer (133), a semiconductor pattern (300) located on the third semiconductor layer (133), an anode electrode (173) located on the semiconductor pattern (300), and a cathode electrode (175) located on a second surface (110b) of the substrate (110).

[0029] The substrate (110) may be a semiconductor substrate including SiC. For example, the substrate (110) may be made of a 4H SiC substrate. In some cases, the substrate (110) may be made of a 3C SiC substrate, a 6H SiC substrate, etc. The substrate (110) may be doped with a first conductivity type impurity. For example, the first conductivity type impurity may be an n-type impurity. In other words, the substrate (110) may be doped with n-type. The substrate (110) may be doped with a high concentration of n-type. The resistivity of the substrate (110) may be about 0.005 Ωcm or more and about 0.035 Ωcm or less. The thickness of the substrate (110) may be about 10 µm or more and about 700 µm or less. The material, doping type, doping concentration, resistivity, thickness, etc. of the substrate (110) are not limited thereto and may be varied in many ways.

[0030] The substrate (110) may include a first surface (110a) and a second surface (110b) facing each other. For example, the first surface (110a) of the substrate (110) may refer to the upper surface of the substrate (110), and the second surface (100b) of the substrate (110) may refer to the lower surface of the substrate (110).

[0031] The first semiconductor layer (131) may be located on the first surface (110a) of the substrate (110), i.e., the upper surface. The lower surface of the first semiconductor layer (131) may be in contact with the first surface (110a) of the substrate (110). However, this is not limited thereto, and a predetermined other layer may be located between the substrate (110) and the first semiconductor layer (131). The first semiconductor layer (131) may be an epitaxial layer formed from the substrate (110) using an epitaxial growth method. The first semiconductor layer (131) may include SiC. For example, the first semiconductor layer (131) may include 4H SiC. The first semiconductor layer (131) may have a first conductivity type. The first conductivity type may be an n-type. For example, the first semiconductor layer (131) may be doped with n-type. The first semiconductor layer (131) may be doped with a low concentration of n-type. The doping concentration of the first semiconductor layer (131) may be lower than the doping concentration of the substrate (110). The doping concentration of the first semiconductor layer (131) is approximately 1*10 15 cm -3 More than approximately 1*10 17 cm -3 It may be less than or equal to. The thickness of the first semiconductor layer (131) may be about 1 µm or more and about 13 µm or less.

[0032] The second semiconductor layer (132) may be located on the first semiconductor layer (131). The second semiconductor layer (132) may be located on top of the first semiconductor layer (131). The second semiconductor layer (132) may include SiC. For example, the second semiconductor layer (132) may include 4H SiC. The second semiconductor layer (132) may be an epitaxial layer formed from the first semiconductor layer (131) using epitaxial growth. The second semiconductor layer (132) may have a second conductivity type different from the first conductivity type. The second conductivity type may be p-type. For example, the second semiconductor layer (132) may be doped with p-type. The second semiconductor layer (132) may be low-concentration doped with p-type. The doping concentration of the second semiconductor layer (132) is approximately 1*10 17 cm -3 More than approximately 1*10 19 cm -3 The material, doping type, doping concentration, etc. of the second semiconductor layer (132) are not limited to these and can be varied.

[0033] The third semiconductor layer (133) may be located on the second semiconductor layer (132). The third semiconductor layer (133) may be located on top of the second semiconductor layer (132). The third semiconductor layer (133) may include SiC. For example, the third semiconductor layer (133) may include 4H SiC. The third semiconductor layer (133) may have a first conductivity type. The first conductivity type may be n-type. For example, the third semiconductor layer (133) may be doped with n-type. The doping concentration of the third semiconductor layer (133) may be less than or equal to the doping concentration of the first semiconductor layer (131), but is not limited thereto. The material, doping type, doping concentration, etc. of the third semiconductor layer (133) are not limited thereto and may be changed in various ways.

[0034] The gate electrode (150) may be positioned on the third semiconductor layer (133). The gate electrode (150) may be positioned on the side of the semiconductor pattern (300) to be described later. The gate electrode (150) may be positioned spaced apart from the semiconductor pattern (300) to be described later in a first direction (X direction). The gate electrode (150) may be non-overlapping with the semiconductor pattern (300) to be described later in a third direction (Z direction). Here, the third direction (Z direction) may mean a vertical direction perpendicular to the thickness direction of the substrate (110) and / or the first surface (110a) of the substrate (110). The gate electrode (150) may include a conductive material. For example, the gate electrode (150) may include impurity-doped polysilicon. As another example, the gate electrode (150) may comprise a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, a conductive metal nitride, or a combination thereof. The gate electrode (150) may be composed of a single layer or multiple layers.

[0035] The semiconductor pattern (300) may be positioned on the third semiconductor layer (133). The semiconductor pattern (300) may be positioned between the third semiconductor layer (133) and the anode electrode (173) to be described later. The semiconductor pattern (300) may be positioned spaced apart from the gate electrode (150) in the first direction (X direction). The semiconductor pattern (300) may be non-overlapping with the gate electrode (150) in the third direction (Z direction).

[0036] A semiconductor device according to one embodiment may include a plurality of semiconductor patterns (300) spaced apart along a first direction (X direction) on a third semiconductor layer (133). The plurality of semiconductor patterns (300) may be located directly above the third semiconductor layer (133). A gate electrode (150) may be located between the plurality of semiconductor patterns (300). The width of each of the plurality of semiconductor patterns (300) along the first direction (X direction) may be substantially the same as each other, but is not limited thereto. The length of each of the plurality of semiconductor patterns (300) along the third direction (Z direction) may be substantially the same as each other, but is not limited thereto.

[0037] The semiconductor pattern (300) may include a semiconductor material. The work function of the semiconductor pattern (300) may be greater than or equal to the work function of the anode electrode (173). The semiconductor pattern (300) may include the same material as the first semiconductor layer (131), the second semiconductor layer (132), and the third semiconductor layer (133). For example, the semiconductor pattern (300) may include a first element which is a semiconductor element and a second element different from the first element. Here, the first element may include Si, and the second element may include C. For example, the semiconductor pattern (300) may include Si x C 1-x (0 <x<1)일 수 있다. 일 예로, 제1 반도체층(131), 제2 반도체층(132), 제3 반도체층(133), 및 반도체 패턴(300) 모두는 Si x C 1-x(0 <x<1)를 포함할 수 있다. 반도체 패턴(300)은 제3 반도체층(133)으로부터 에피택시얼 성장법(epitaxial growth)을 이용하여 형성된 에피택시 층(epitaxy layer)일 수 있다. 일 예로, 반도체 패턴(300)은 초격자층으로 이루어질 수 있다. 반도체 패턴(300)이 초격자층으로 이루어진 경우, 주변의 물질층과 격자상수 및 열팽창계수의 차이를 완화될 수 있다. 반도체 패턴(300)은 제2 도전형을 가질 수 있다. 제2 도전형은 p타입일 수 있다. 반도체 패턴(300)은 제2 도전형 불순물로 도핑되어 있을 수 있다. 반도체 패턴(300)의 제2 도전형 불순물의 도핑 농도는 제2 반도체층(132)의 제2 도전형 불순물의 도핑 농도보다 크거나 같을 수 있으나, 이에 한정되는 것은 아니다. 실시예에 따라 반도체 패턴(300)의 제2 도전형 불순물의 도핑 농도는 제2 반도체층(132)의 제2 도전형 불순물의 도핑 농도보다 작을 수도 있다.

[0038] As another example, the first semiconductor layer (131), the second semiconductor layer (132), the third semiconductor layer (133), and the semiconductor pattern (300) may all include GaN. In this case, the first element may be Ga and the second element may be N.

[0039] The semiconductor pattern (300) may include a plurality of layers having different energy band gaps. For example, the semiconductor pattern (300) may include a first pattern (310) having a semiconductor material having a first energy band gap and a second pattern (320) having a semiconductor material having a second energy band gap larger than the first energy band gap.

[0040] The first pattern (310) may be positioned on the third semiconductor layer (133). The first pattern (310) may be positioned on the lower surface (173_B) of the anode electrode (173) to be described later. The first pattern (310) may be positioned between the third semiconductor layer (133) and the anode electrode (173) to be described later. The first pattern (310) may be in contact with the lower surface (173_B) of the anode electrode (173). The first pattern (310) may be non-overlapping with the gate electrode (150) in the third direction (Z direction).

[0041] The first pattern (310) may include a semiconductor material. The work function of the first pattern (310) may be greater than or equal to the work function of the anode electrode (173). The first pattern (310) may include the same material as the first semiconductor layer (131), the second semiconductor layer (132), and the third semiconductor layer (133). For example, the first pattern (310) may include a first element and a second element. Here, the first element may be Si and the second element may be C, but is not limited thereto. For example, the first pattern (310) may be Si x C 1-x (0 <x<1)일 수 있다. 이때, 제1 패턴(310)을 구성하는 반도체 물질은 제1 에너지 밴드 갭(도 2의 BE1)을 가질 수 있다. 이에 관한 설명은 도 2를 참조하여 후술하기로 한다.

[0042] The second pattern (320) may be located between the first pattern (310) and the third semiconductor layer (133). The second pattern (320) may be located on the lower surface of the first pattern (310). The second pattern (320) may be in contact with the lower surface of the first pattern (310), but is not limited thereto. The second pattern (320) may be non-overlapping with the gate electrode (150) in the third direction (Z direction).

[0043] The second pattern (320) may include a semiconductor material. The second pattern (320) may include the same material as the first pattern (310). The second pattern (320) may include the same material as the first semiconductor layer (131), the second semiconductor layer (132), and the third semiconductor layer (133). For example, the second pattern (320) may include a first element and a second element. Here, the first element may be Si and the second element may be C, but is not limited thereto. For example, the second pattern (320) may be Si x C 1-x (0 <x<1)일 수 있다. 이때, 제2 패턴(320)을 구성하는 반도체 물질은 제2 에너지 밴드 갭(도 2의 BE2)을 가질 수 있다. 이에 관한 설명은 도 2를 참조하여 후술하기로 한다.

[0044] In FIG. 1, the semiconductor pattern (300) is illustrated as including two patterns (310, 320), but the number of patterns (310, 320) is not limited thereto. For example, as in the embodiment of FIG. 9 to 12, the semiconductor pattern (300) may include three patterns (310, 320, 330). As another example, the semiconductor pattern (300) may include four or more patterns. An explanation regarding this will be provided later with reference to FIG. 9 to 12.

[0045] A semiconductor device according to one embodiment may further include an interlayer insulating layer (140) located on a semiconductor pattern (300) and a third semiconductor layer (133).

[0046] The interlayer insulating layer (140) may be positioned on the upper surface of the semiconductor pattern (300), the side surface of the semiconductor pattern (300), and the upper surface of the third semiconductor layer (133). The interlayer insulating layer (140) may be positioned conformally on the upper surface of the semiconductor pattern (300), the side surface of the semiconductor pattern (300), and the upper surface of the third semiconductor layer (133). The thickness of the interlayer insulating layer (140) may be nearly constant. The interlayer insulating layer (140) may be in contact with the semiconductor pattern (300) and the third semiconductor layer (133), but is not limited thereto. In an embodiment, the gate electrode (150) may penetrate the interlayer insulating layer (140) and be in contact with the third semiconductor layer (133). In an embodiment, the anode electrode (173), which will be described later, may penetrate the interlayer insulating layer (140) and be in contact with the semiconductor pattern (300). The interlayer insulating layer (140) may include an insulating material. For example, the interlayer insulating layer (140) may include SiO2. However, it is not limited thereto, and the material of the interlayer insulating layer (140) may be varied. As another example, the interlayer insulating layer (140) may include SiN, SiON, SiC, SiCN, or a combination thereof. The interlayer insulating layer (140) may be composed of a single layer or multiple layers.

[0047] The anode electrode (173) may be positioned on the semiconductor pattern (300). The anode electrode (173) may be electrically connected to the semiconductor pattern (300) by penetrating the interlayer insulating layer (140). The anode electrode (173) may not overlap with the gate electrode (150) in a third direction (Z direction).

[0048] A semiconductor device according to one embodiment may include a plurality of anode electrodes (173) spaced apart along a first direction (X direction) on a semiconductor pattern (300). The plurality of anode electrodes (173) may be located directly above the semiconductor pattern (300). The width of each of the plurality of anode electrodes (173) along the first direction (X direction) may be substantially the same as each other, but is not limited thereto. The length of each of the plurality of anode electrodes (173) along the third direction (Z direction) may be substantially the same as each other, but is not limited thereto.

[0049] The anode electrode (173) may include a conductive material. The anode electrode (173) may include the same material as the gate electrode (150), but is not limited thereto. The anode electrode (173) may include a material different from the gate electrode (150). For example, the anode electrode (173) may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal nitride. For example, the anode electrode (173) is titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbide nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbide nitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), It may include, but is not limited to, molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. The anode electrode (173) may be made of a single layer or multiple layers.

[0050] The cathode electrode (175) may be positioned on the second surface (100b) of the substrate (110), i.e., the bottom surface. The upper surface of the cathode electrode (175) may be in contact with the bottom surface of the substrate (110). The cathode electrode (175) may be in ohmic contact with the substrate (110). The region within the substrate (110) in contact with the cathode electrode (175) may be doped at a relatively high concentration compared to other regions. However, this is not limited thereto, and a certain other layer may be additionally located between the cathode electrode (175) and the substrate (110). For example, a silicide layer may be located between the cathode electrode (175) and the substrate (110). The silicide layer may include a metal silicide material. The cathode electrode (175) and the substrate (110) may be electrically connected smoothly by the metal silicide layer.

[0051] The cathode electrode (175) may include a conductive material. For example, the cathode electrode (175) may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal nitride. The cathode electrode (175) may be made of the same material as the anode electrode (173) and / or the gate electrode (150), or it may be made of a different material. The cathode electrode (175) may be made of a single layer or multiple layers.

[0052] A semiconductor device according to one embodiment may be a thyristor. For example, a semiconductor device according to one embodiment may be a Gate Turn-Off thyristor (GTO) device with improved turn-off characteristics, but is not limited thereto. Specifically, the second semiconductor layer (132), the third semiconductor layer (133), and the semiconductor pattern (300) may constitute a PNP transistor. The third semiconductor layer (133) may be the base region of the PNP transistor. The first semiconductor layer (131), the second semiconductor layer (132), and the third semiconductor layer (133) may constitute an NPN transistor. The second semiconductor layer (132) may be the base region of the second NPN transistor. A gate electrode (150) may be electrically connected to the third semiconductor layer (133).

[0053] In an exemplary embodiment, a thyristor may be formed by combining a PNP transistor and an NPN transistor to handle high voltage and high current through mutual current amplification. For example, a thyristor may be used as a power device, but is not limited thereto, and its application can be varied.

[0054] Hereinafter, patterns (310, 320) of a semiconductor device according to one embodiment will be described in detail with further reference to FIG. 2.

[0055] FIG. 2 is a graph illustrating the content of a material constituting a semiconductor pattern and a third semiconductor layer of a semiconductor device according to one embodiment. FIG. 2 illustrates the energy band gap and the content of a first element of the anode electrode (173), the first pattern (310), the second pattern (320), and the third semiconductor layer (133) according to the direction (-Z direction) from the anode electrode (173) toward the first surface (110a) of the substrate (110). Here, 'content' may mean atomic percent (at%).

[0056] As described above, the third semiconductor layer (133), the first pattern (310), and the second pattern (320) of a semiconductor device according to one embodiment may include the same material. For example, the third semiconductor layer (133), the first pattern (310), and the second pattern (320) may include a first element which is a semiconductor element and a second element different from the first element. Here, the first element may be Si and the second element may be C, but is not limited thereto. The third semiconductor layer (133), the first pattern (310), and the second pattern (320) are Si x C 1-x (0 <x<1)일 수 있다.

[0057] Referring further to FIG. 2, the first pattern (310), the second pattern (320), and the third semiconductor layer (133) may include a material having a predetermined energy band gap. In this case, the energy band gap may be determined according to the content (at%) of the first element and the second element of the semiconductor material constituting the first pattern (310), the second pattern (320), and the third semiconductor layer (133). Specifically, as the content (at%) of the first element, which is a semiconductor element, increases, the energy band gap tends to become smaller. That is, as the content (at%) of the second element increases, the energy band gap tends to become larger. For example, the first pattern (310) of the semiconductor device according to one embodiment may include a material having a first energy band gap (BE1), the second pattern (320) may include a material having a second energy band gap (BE2), and the third semiconductor layer (133) may include a material having a third energy band gap (BE3). The energy band gap of the anode electrode (173) can be approximately '0'.

[0058] The semiconductor pattern (300) may include a portion having a different energy band gap. For example, the energy band gap of the upper portion of the semiconductor pattern (300) may be smaller than the energy band gap of the lower portion of the semiconductor pattern (300). As an example, the energy band gap of the semiconductor material constituting the semiconductor pattern (300) may increase in a stepwise manner along the direction (-Z direction) toward the first surface (110a) of the substrate (110) from the lower surface (173_B) of the anode electrode (173). However, it is not limited thereto, and the energy band gap of the semiconductor pattern (300) may be varied within the range of increasing along the direction (-Z direction) toward the first surface (110a) of the substrate (110) from the lower surface (173_B) of the anode electrode (173). A detailed description regarding this will be provided later with reference to FIGS. 3 to 7.

[0059] Specifically, the first energy band gap (BE1) of the first pattern (310) may be smaller than the second energy band gap (BE2) of the second pattern (320). The first energy band gap (BE1) and the second energy band gap (BE2) may have substantially constant sizes, but are not limited thereto. Accordingly, the energy band gap of the upper part of the semiconductor pattern (300) may be smaller than the energy band gap of the lower part of the semiconductor pattern (300). The conductivity of the first pattern (310) may be greater than the conductivity of the second pattern (320). The work function of the first pattern (310) may be smaller than the work function of the second pattern (320).

[0060] According to the embodiment, the content (N1) of the first element in the first pattern (310) may differ from the content (N2) of the first element in the second pattern (320). For example, as the content of the first element, which is a semiconductor element, tends to increase, the energy band gap may decrease; therefore, the content (N1) of the first element in the first pattern (310) may be greater than the content (N2) of the first element in the second pattern (320). The content of the second element in the first pattern (310) may be smaller than the content of the second element in the second pattern (320). Here, the first element may be Si and the second element may be C, but is not limited thereto.

[0061] Additionally, the second energy band gap (BE2) of the second pattern (320) may be smaller than the third energy band gap (BE3) of the third semiconductor layer (133). The second energy band gap (BE2) and the third energy band gap (BE3) may have substantially constant sizes, but are not limited thereto. The conductivity of the second pattern (320) may be greater than the conductivity of the third semiconductor layer (133).

[0062] According to the embodiment, the content (N2) of the first element in the second pattern (320) may differ from the content (N3) of the first element in the third semiconductor layer (133). For example, as the content of the first element, which is a semiconductor element, tends to increase, the energy band gap may decrease; therefore, the content (N2) of the first element in the second pattern (320) may be greater than the content (N3) of the first element in the third semiconductor layer (133), but is not limited thereto. The content of the second element in the second pattern (320) may be smaller than the content of the second element in the third semiconductor layer (133). Here, the first element may be Si and the second element may be C, but is not limited thereto.

[0063] A semiconductor pattern (300) of a semiconductor device according to one embodiment may include a portion having a smaller energy band gap as it gets closer to the anode electrode (173). For example, the first energy band gap (BE1) of the first pattern (310) in contact with the lower surface (173_B) of the anode electrode (173) may be smaller than the second energy band gap (BE2) of the second pattern (320). The material constituting the semiconductor pattern (300) of the semiconductor device according to one embodiment has a tendency for the Fermi level of the material to rise as the energy band gap becomes smaller, and the work function of the material has a tendency to decrease. Accordingly, the work function of the first pattern (310) containing a material with a relatively small energy band gap may decrease, and accordingly, the contact characteristics between the anode electrode (173) and the first pattern (310) may be improved. In addition, since the first pattern (310) has a small energy band gap, the activation energy is reduced, and the conductivity of the semiconductor pattern (300) can be increased. Here, the activation energy may refer to the amount of energy required for a hole to be conducted to the valence band. Accordingly, the reliability of the semiconductor device according to one embodiment can be improved.

[0064] Additionally, when a hole moves from the semiconductor pattern (300) to the third semiconductor layer (133), the mobility of the hole can be determined by the size of the energy barrier between the material layers. For example, the lower the energy barrier of the material layer, the lower the required activation energy, and the easier the hole can move into the material layer. Here, the activation energy may refer to the amount of energy required for a hole to conduct to the valence band.

[0065] A semiconductor device according to one embodiment may include a first pattern (310) having a first energy band gap (BE1) that is smaller than the third energy band gap (BE3) of the third semiconductor layer (133). As the first pattern (310) includes a material with a small energy band gap, the hole density within the first pattern (310) may increase, and holes may move easily.

[0066] Additionally, the semiconductor pattern (300) of the semiconductor device according to one embodiment may include a second pattern (320) having a second energy band gap (BE2) that is larger than the first energy band gap (BE1) of the first pattern (310) and smaller than the third energy band gap (BE3) of the third semiconductor layer (133). Accordingly, an energy barrier of relatively low height is formed between the first pattern (310) and the second pattern (320) and between the second pattern (320) and the third semiconductor layer (133), allowing holes to move easily. Therefore, the reliability of the semiconductor device according to one embodiment can be improved.

[0067] Additionally, the content of the first element (N2) of the second pattern (320) may be smaller than the content of the first element (N1) of the first pattern (310) and larger than the content of the first element (N3) of the third semiconductor layer (133). As the content of the first element increases sequentially along the third semiconductor layer (133), the second pattern (320), and the first pattern (310), it is possible to prevent defects from occurring due to differences in lattice constants at the interface between materials of different content (at%). Accordingly, the reliability of the semiconductor device according to one embodiment can be improved.

[0068] Hereinafter, semiconductor patterns of semiconductor devices according to several embodiments will be described with reference to FIGS. 3 to 8.

[0069] FIGS. 3 to 8 are graphs illustrating the semiconductor pattern of a semiconductor device and the content of a material constituting a third semiconductor layer according to some embodiments.

[0070] FIGS. 3 to 8 illustrate various variations of a semiconductor device according to an embodiment illustrated in FIGS. 1 and 2. Since the embodiments illustrated in FIGS. 3 to 8 share significant identical parts with the embodiments illustrated in FIGS. 1 and 2, a description thereof is omitted, and the differences are described in detail. Additionally, the same reference numerals are used for components identical to those in the preceding embodiments.

[0071] Referring to FIGS. 1 and FIGS. 3, the second energy band gap (BE2) of the second pattern (320) of the semiconductor device according to some embodiments may be substantially the same as the third energy band gap (BE3) of the third semiconductor layer (133). The second energy band gap (BE2) and the third energy band gap (BE3) may have substantially constant sizes, but are not limited thereto. The conductivity of the second pattern (320) may be substantially the same as the conductivity of the third semiconductor layer (133), but is not limited thereto.

[0072] According to the embodiment, the content of the first element (N2) of the second pattern (320) may be substantially the same as the content of the first element (N3) of the third semiconductor layer (133). The content of the second element of the second pattern (320) may be substantially the same as the content of the second element of the third semiconductor layer (133). Here, the first element may be Si and the second element may be C, but is not limited thereto.

[0073] In the embodiment of FIG. 3, the second energy band gap (BE2) of the second pattern (320) may be substantially the same as the third energy band gap (BE3) of the third semiconductor layer (133). Even in this case, since the second pattern (320) has a p-type and the third semiconductor layer (133) has an n-type, an energy barrier exists between the second pattern (320) and the third semiconductor layer (133). Therefore, compared to the case where the second pattern (320) is absent, a relatively low energy barrier is formed between the first pattern (310) and the second pattern (320) and between the second pattern (320) and the third semiconductor layer (133), allowing holes to move easily. Accordingly, the reliability of the semiconductor device according to one embodiment can be improved.

[0074] Referring to FIGS. 1 and FIGS. 4 through 7, a semiconductor pattern (300) of a semiconductor device according to some embodiments may include a portion in which the energy band gap increases as it moves away from the lower surface (173_B) of the anode electrode (173). For example, the energy band gap of the first pattern (310) and the second pattern (320) may increase as it moves away from the lower surface (173_B) of the anode electrode (173).

[0075] According to the embodiment, the content of the first element (N1) of the first pattern (310) and the content of the first element (N2) of the second pattern (320) may vary along the direction (-Z direction) toward the first surface (110a) of the substrate (110) from the lower surface (173_B) of the anode electrode (173). For example, the content of the first element (N1) of the first pattern (310) may decrease along the direction (-Z direction) toward the first surface (110a) of the substrate (110) from the lower surface (173_B) of the anode electrode (173). The content of the first element (N2) of the second pattern (320) may decrease along the direction (-Z direction) toward the first surface (110a) of the substrate (110) from the lower surface (173_B) of the anode electrode (173). That is, the content (N2) of the first element of the second pattern (320) can decrease as it moves further away from the first pattern (310).

[0076] At this time, the rate of change of the content of the first element (N1) of the first pattern (310) and the rate of change of the content of the second element of the second pattern (320) may vary. For example, as shown in FIG. 4, the rate of change of the content of the first element (N1) of the first pattern (310) and the rate of change of the content of the second element of the second pattern (320) may be constant. As another example, as shown in FIG. 5, the rate of change of the content of the first element (N1) of the first pattern (310) and the rate of change of the content of the second element of the second pattern (320) may increase. As yet another example, as shown in FIG. 6, the rate of change of the content of the first element (N1) of the first pattern (310) and the rate of change of the content of the second element of the second pattern (320) may decrease. Here, the rate of change of the content (N1) of the first element of the first pattern (310) and the rate of change of the content of the second element of the second pattern (320) may represent the amount of change of content per unit distance in the direction (-Z direction) from the lower surface (173_B) of the anode electrode (173) toward the first surface (110a) of the substrate (110).

[0077] According to the embodiments, the content (N1) of the first element of the first pattern (310) may have a maximum value (N1max) near the lower surface (173_B) of the anode electrode (173) and a minimum value (N1min) in the part adjacent to the second pattern (320). Additionally, the content (N2) of the first element of the second pattern (320) may have a maximum value (N2max) in the part adjacent to the first pattern (310) and a minimum value (N2min) in the part adjacent to the third semiconductor layer (133). For example, as shown in FIGS. 4 to 6, the minimum value (N1min) of the content (N1) of the first element of the first pattern (310) may be greater than the maximum value (N2max) of the content (N2) of the first element of the second pattern (320). Additionally, the minimum value (N2min) of the content (N2) of the first element in the second pattern (320) may be greater than the content (N3) of the first element in the third semiconductor layer (133). However, this is not limited thereto, and as another example, as shown in FIG. 7, the minimum value (N1min) of the content (N1) of the first element in the first pattern (310) may be substantially the same as the maximum value (N2max) of the content (N2) of the first element in the second pattern (320). Additionally, the minimum value (N2min) of the content (N2) of the first element in the second pattern (320) may be substantially the same as the content (N3) of the first element in the third semiconductor layer (133).

[0078] Accordingly, the first energy band gap (BE1) of the first pattern (310) can gradually increase along the direction (-Z direction) toward the first surface (110a) of the substrate (110) from the lower surface (173_B) of the anode electrode (173). The second energy band gap (BE2) of the second pattern (320) can gradually increase along the direction (-Z direction) toward the first surface (110a) of the substrate (110) from the lower surface (173_B) of the anode electrode (173). Thus, in the semiconductor device according to the embodiment of FIGS. 4 to 7, an energy barrier of a relatively very low height can be continuously formed, and accordingly, the reliability of the semiconductor device according to one embodiment can be improved.

[0079] Referring to FIGS. 1 and FIGS. 8, the first pattern (310) and the second pattern (320) of a semiconductor device according to some embodiments may further include a third element, which is a semiconductor element different from the first element and the second element. Here, the first element may be Si, the second element may be C, and the third element may be Ge. For example, the first pattern (310) and the second pattern (320) are Si x Ge y C 1-x-y (0 <x<1, 0<y<1)일 수 있다.

[0080] The content of the third element (M1) of the first pattern (310) may be greater than the content of the third element (M2) of the second pattern (320). At this time, the content of the first element of the first pattern (310) may be substantially the same as the content of the second element of the first pattern (310), but is not limited thereto. Also, the content of the first element of the second pattern (320) may be substantially the same as the content of the second element of the second pattern (320), but is not limited thereto.

[0081] According to the embodiment, the content of the second element in the first pattern (310) may be smaller than the content of the second element in the second pattern (320). That is, the sum of the content of the first element and the content of the third element (M1) in the first pattern (310) may be greater than the sum of the content of the first element and the content of the third element (M2) in the second pattern (320). Within this range, the first energy band gap (BE1) of the first pattern (310) may be smaller than the second energy band gap (BE2) of the second pattern (320). For example, the content of the second element in the first pattern (310) may be smaller than the content of the second element in the second pattern (320), and the content of the first element in the first pattern (310) may be smaller than or equal to the content of the first element in the second pattern (320). In this case, the content of the third element (M1) of the first pattern (310) may be greater than the content of the third element (M2) of the second pattern (320), and the first energy band gap (BE1) of the first pattern (310) may be smaller than the second energy band gap (BE2) of the second pattern (320).

[0082] As another example, the content of the second element in the first pattern (310) may be substantially the same as the content of the second element in the second pattern (320). In this case, the content of the third element (M1) in the first pattern (310) may be greater than the content of the third element (M2) in the second pattern (320). In this range, the first energy band gap (BE1) of the first pattern (310) may be smaller than the second energy band gap (BE2) of the second pattern (320).

[0083] The content of the second element in the second pattern (320) may be less than or equal to the content of the second element in the third semiconductor layer (133). Accordingly, the second energy band gap (BE2) of the second pattern (320) may be smaller than the third energy band gap (BE3) of the third semiconductor layer (133).

[0084] In some embodiments, the third semiconductor layer (133) may not contain the third element. That is, the content (M3) of the third element in the third semiconductor layer (133) may be approximately 0. However, this is not limited thereto, and the third semiconductor layer (133) may further contain the third element. In this case, the content (M3) of the third element in the third semiconductor layer (133) may be less than or equal to the content of the second element in the second pattern (320).

[0085] In some embodiments, the first pattern (310) and the second pattern (320) are Si x Ge y C 1-x-y (0 <x<1, 0<y<1)로 이루어진 경우, 제1 패턴(310) 및 제2 패턴(320) 각각의 제1 원소, 제2 원소, 및 제3 원소의 함량(at%)은 제1 패턴(310)의 제1 에너지 밴드 갭(BE1)이 제2 패턴(320)의 제2 에너지 밴드 갭(BE2)보다 작은 범위 내에서 다양하게 변경될 수 있다.

[0086] In the embodiment of FIG. 8, the first element, the second element, and the third element constituting the first pattern (310), the second pattern (320), and the third semiconductor layer (133) may be varied. For example, the first element may include Ga, which is a semiconductor element, the second element may include N, and the third element may include In. That is, the third semiconductor layer (133) may include GaN, and the first pattern (310) and the second pattern (320) may include InGaN. As an example, the first pattern (310) and the second pattern (320) are In z Ga 1-zN (0 <z<1)일 수 있다. 이 경우에도, 제1 패턴(310)의 제1 에너지 밴드 갭(BE1)이 제2 패턴(320)의 제2 에너지 밴드 갭(BE2)보다 작을 수 있고, 제2 패턴(320)의 제2 에너지 밴드 갭(BE2)은 제3 반도체층(133)의 제3 에너지 밴드 갭(BE3)보다 작거나 같을 수 있다. 일 예로, 제1 패턴(310)의 In의 함량(at%)은 제2 패턴(320)의 In의 함량(at%)보다 클 수 있다. 제1 패턴(310)의 N의 함량(at%)은 제2 패턴(320)의 N의 함량(at%)과 실질적으로 동일할 수 있다. 제1 패턴(310)의 In의 함량(at%)과 Ga의 함량(at%)의 합은 제2 패턴(320)의 In의 함량(at%)과 Ga의 함량(at%)의 합과 실질적으로 동일할 수 있으나, 이에 한정되는 것은 아니다.

[0087] Hereinafter, semiconductor patterns of semiconductor devices according to several embodiments will be described with reference to FIGS. 9 to 12.

[0088] FIG. 9 is a cross-sectional view showing a semiconductor device according to some embodiments. FIG. 10 to 12 are graphs showing the semiconductor pattern of the semiconductor device according to the embodiment of FIG. 9 and the content of the material constituting the third semiconductor layer.

[0089] FIGS. 9 to 12 illustrate various variations of a semiconductor device according to an embodiment illustrated in FIGS. 1 to 8. Since the embodiments illustrated in FIGS. 9 to 12 share a significant number of identical parts with the embodiments illustrated in FIGS. 1 to 8, a description thereof is omitted, and the differences are described in detail. Additionally, the same reference numerals are used for components identical to those in the preceding embodiments.

[0090] Referring to FIG. 9, the semiconductor pattern (300) of a semiconductor device according to some embodiments may further include a third pattern (330) located between a second pattern (320) and a third semiconductor layer (133).

[0091] The third pattern (330) may be positioned on the third semiconductor layer (133). The third pattern (330) may be positioned on the lower surface of the second pattern (320). The third pattern (330) may be in contact with the third semiconductor layer (133), but is not limited thereto. The third pattern (330) may overlap with the anode electrode (173) in the third direction (Z direction). The third pattern (330) may be positioned spaced apart from the anode electrode (173) in the third direction (Z direction).

[0092] The third pattern (330) may include a semiconductor material. The third pattern (330) may include the same material as the first pattern (310) and the second pattern (320). For example, the third pattern (330) may include a first element and a second element. Here, the first element may be Si and the second element may be C, but is not limited thereto. As an example, the first pattern (310), the second pattern (320), and the third pattern (330) are Si x C 1-x (0 <x<1)일 수 있다.

[0093] Referring to FIG. 10, the fourth energy band gap (BE4) of the third pattern (330) may be larger than the second energy band gap (BE2) of the second pattern (320). The conductivity of the third pattern (330) may be smaller than the conductivity of the second pattern (320). The content of the first element (N4) of the third pattern (330) may be different from the content of the first element (N2) of the second pattern (320). For example, as the content of the first element, which is a semiconductor element, tends to increase, the energy band gap may become smaller; therefore, the content of the first element (N4) of the third pattern (330) may be smaller than the content of the first element (N2) of the second pattern (320). The content of the second element of the third pattern (330) may be larger than the content of the second element of the second pattern (320).

[0094] Referring to FIG. 11, the maximum value (N4max) of the content (N4) of the first element in the third pattern (330) may be substantially the same as the minimum value (N2min) of the content (N2) of the first element in the second pattern (320). Additionally, the minimum value (N4min) of the content (N4) of the first element in the third pattern (330) may be substantially the same as the content (N3) of the first element in the third semiconductor layer (133).

[0095] Referring to FIG. 12, the first pattern (310), the second pattern (320), and the third pattern (330) may further include a third element, which is a semiconductor element different from the first and second elements. Here, the first element may be Si, the second element may be C, and the third element may be Ge. As an example, the first pattern (310), the second pattern (320), and the third pattern (330) are Si x Ge y C 1-x-y (0 <x<1, 0<y<1)일 수 있다.

[0096] The content of the third element (M4) of the third pattern (330) may be smaller than the content of the third element (M2) of the second pattern (320). At this time, the content of the first element of the third pattern (330) may be substantially the same as the content of the second element of the third pattern (330), but is not limited thereto.

[0097] According to the embodiment, the content of the second element in the third pattern (330) may be greater than or equal to the content of the second element in the second pattern (320). That is, the sum of the content of the first element and the content of the third element (M4) in the third pattern (330) may be less than or equal to the sum of the content of the first element and the content of the third element (M2) in the second pattern (320). In this range, the fourth energy band gap (BE4) of the third pattern (330) may be larger than the second energy band gap (BE2) of the second pattern (320). The content of the second element in the third pattern (330) may be less than or equal to the content of the second element in the third semiconductor layer (133).

[0098] In some embodiments, the first pattern (310), the second pattern (320), and the third pattern (330) are Si x Ge y C 1-x-y (0 <x<1, 0<y<1)로 이루어진 경우, 제1 패턴(310), 제2 패턴(320), 및 제3 패턴(330) 각각의 제1 원소, 제2 원소, 및 제3 원소의 함량(at%)은 제1 패턴(310)의 제1 에너지 밴드 갭(BE1)이 제2 패턴(320)의 제2 에너지 밴드 갭(BE2)보다 작고, 제2 패턴(320)의 제2 에너지 밴드 갭(BE2)이 제3 패턴(330)의 제4 에너지 밴드 갭(BE4)보다 작은 범위 내에서 다양하게 변경될 수 있다.

[0099] Hereinafter, semiconductor patterns of semiconductor devices according to some embodiments will be described with reference to FIG. 13.

[0100] FIG. 13 is a cross-sectional view showing a semiconductor device according to some embodiments.

[0101] FIG. 13 illustrates various variations of a semiconductor device according to an embodiment illustrated in FIG. 1 to 8. Since the embodiment illustrated in FIG. 13 shares a significant number of identical parts with the embodiment illustrated in FIG. 1 to 8, a description thereof is omitted, and the differences are described in detail. Additionally, the same reference numerals are used for components identical to those in the preceding embodiment.

[0102] Referring to FIG. 13, a gate electrode (150) of a semiconductor device according to some embodiments may be located on a second semiconductor layer (132). The gate electrode (150) may be located on the upper surface of the second semiconductor layer (132). The gate electrode (150) may be electrically connected to the second semiconductor layer (132). The gate electrode (150) may be located spaced apart from the third semiconductor layer (133). For example, the gate electrode (150) may be located on the side of the third semiconductor layer (133). The gate electrode (150) may overlap with the third semiconductor layer (133) in a first direction (X direction), but is not limited thereto.

[0103] A semiconductor device according to some embodiments may include a plurality of third semiconductor layers (133) spaced apart along a first direction (X direction) on a second semiconductor layer (132). The plurality of third semiconductor layers (133) may be located directly above the second semiconductor layer (132). A gate electrode (150) may be located between the plurality of third semiconductor layers (133). The width of each of the plurality of third semiconductor layers (133) along the first direction (X direction) may be substantially the same as each other, but is not limited thereto. The length of each of the plurality of third semiconductor layers (133) along the third direction (Z direction) may be substantially the same as each other, but is not limited thereto.

[0104] A semiconductor device according to some embodiments may be a thyristor. For example, a semiconductor device according to some embodiments may be a Gate Turn-Off thyristor (GTO) device with improved turn-off characteristics or a thyristor with improved turn-on characteristics. In exemplary embodiments, the thyristor may be a combination of a PNP transistor and an NPN transistor to handle high voltage and high current through mutual current amplification action, etc. For example, the thyristor may be used as a power device, but is not limited thereto, and its application may be varied.

[0105] Hereinafter, a method for manufacturing a semiconductor device according to one embodiment will be described with reference to FIGS. 14 to 17.

[0106] FIGS. 14 to 17 are cross-sectional views of an intermediate process step illustrating a method for manufacturing a semiconductor device according to one embodiment.

[0107] Referring to FIG. 14, a first semiconductor layer (131), a second semiconductor layer (132), and a third semiconductor layer (133) can be formed on a substrate (110).

[0108] The substrate (110) may be a semiconductor substrate including SiC. For example, the substrate (110) may be made of a 4H SiC substrate. In some cases, the substrate (110) may be made of a 3C SiC substrate, a 6H SiC substrate, etc. The substrate (110) may be doped with a first conductivity type impurity. For example, the first conductivity type impurity may be an n-type impurity. In other words, the substrate (110) may be doped with n-type. The substrate (110) may be doped with a high concentration of n-type. The resistivity of the substrate (110) may be about 0.005 Ωcm or more and about 0.035 Ωcm or less. The thickness of the substrate (110) may be about 10 µm or more and about 700 µm or less. The material, doping type, doping concentration, resistivity, thickness, etc. of the substrate (110) are not limited thereto and may be varied in many ways.

[0109] The substrate (110) may include a first surface (110a) and a second surface (110b) facing each other. For example, the first surface (110a) of the substrate (110) may refer to the upper surface of the substrate (110), and the second surface (100b) of the substrate (110) may refer to the lower surface of the substrate (110).

[0110] First, a first semiconductor layer (131) can be formed on a substrate (110). The first semiconductor layer (131) may be located on the first surface (110a) of the substrate (110), that is, the upper surface. The lower surface of the first semiconductor layer (131) may be in contact with the first surface (110a) of the substrate (110). However, this is not limited thereto, and a predetermined other layer may be further located between the substrate (110) and the first semiconductor layer (131). The first semiconductor layer (131) may be an epitaxial layer formed from the substrate (110) using an epitaxial growth method. The first semiconductor layer (131) may include SiC. For example, the first semiconductor layer (131) may include 4H SiC. The first semiconductor layer (131) may be doped with n-type. The first semiconductor layer (131) may be low-concentration doped as an n-type. The doping concentration of the first semiconductor layer (131) may be lower than the doping concentration of the substrate (110). The doping concentration of the first semiconductor layer (131) is approximately 1 x 10⁻¹⁰. 15 cm -3 More than approximately 1*10 17 cm -3 It may be less than or equal to. The thickness of the first semiconductor layer (131) may be about 1 µm or more and about 13 µm or less.

[0111] Next, a second semiconductor layer (132) and a third semiconductor layer (133) can be formed sequentially on the first semiconductor layer (131).

[0112] A second semiconductor layer (132) may be formed on the first semiconductor layer (131). The second semiconductor layer (132) may be located on top of the first semiconductor layer (131). The second semiconductor layer (132) may include SiC. For example, the second semiconductor layer (132) may include 4H SiC. The second semiconductor layer (132) may be an epitaxial layer formed from the first semiconductor layer (131) using epitaxial growth. The second semiconductor layer (132) may have a second conductivity type different from the first conductivity type. The second conductivity type may be p-type. For example, the second semiconductor layer (132) may be doped with p-type. The second semiconductor layer (132) may be low-concentration doped with p-type. The doping concentration of the second semiconductor layer (132) is approximately 1*10 17 cm -3 More than approximately 1*10 19 cm -3 The material, doping type, doping concentration, etc. of the second semiconductor layer (132) are not limited to these and can be varied.

[0113] A third semiconductor layer (133) may be formed on the second semiconductor layer (132). The third semiconductor layer (133) may be located on top of the second semiconductor layer (132). The third semiconductor layer (133) may include SiC. For example, the third semiconductor layer (133) may include 4H SiC. The third semiconductor layer (133) may be an epitaxial layer formed from the second semiconductor layer (132) using epitaxial growth. The third semiconductor layer (133) may have a first conductivity type. The first conductivity type may be n-type. For example, the third semiconductor layer (133) may be doped with n-type. The doping concentration of the third semiconductor layer (133) may be less than or equal to the doping concentration of the first semiconductor layer (131), but is not limited thereto. The material, doping type, doping concentration, etc. of the third semiconductor layer (133) are not limited to this and can be changed in various ways.

[0114] Referring to FIG. 15, a second pattern material layer (320L) and a first pattern material layer (310L) can be formed on the third semiconductor layer (133).

[0115] First, a second pattern material layer (320L) can be formed on the third semiconductor layer (133). The second pattern material layer (320L) may be an epitaxial layer formed from the third semiconductor layer (133) using epitaxial growth. The second pattern material layer (320L) may include a semiconductor material. The second pattern material layer (320L) may include the same material as the first semiconductor layer (131), the second semiconductor layer (132), and the third semiconductor layer (133). For example, the second pattern material layer (320L) may include a first element and a second element. Here, the first element may be Si and the second element may be C, but is not limited thereto. For example, the second pattern material layer (320L) may be Si xC 1-x (0 <x<1)일 수 있다. 이때, 제2 패턴 물질층(320L)을 구성하는 반도체 물질은 제2 에너지 밴드 갭(도 2의 BE2)을 가질 수 있다.

[0116] Next, a first pattern material layer (310L) can be formed on the second pattern material layer (320L). The first pattern material layer (310L) may be an epitaxial layer formed from the first pattern material layer (310L) using epitaxial growth. The first pattern material layer (310L) may include a semiconductor material. The work function of the first pattern material layer (310L) may be greater than or equal to the work function of the anode electrode (173). The first pattern material layer (310L) may include the same material as the first semiconductor layer (131), the second semiconductor layer (132), and the third semiconductor layer (133). For example, the first pattern material layer (310L) may include a first element and a second element. Here, the first element may be Si and the second element may be C, but is not limited thereto. For example, the first pattern material layer (310L) is Si x C 1-x (0 <x<1)일 수 있다. 이때, 제1 패턴 물질층(310L)을 구성하는 반도체 물질은 제1 에너지 밴드 갭(도 2의 BE1)을 가질 수 있다.

[0117] Referring to FIG. 16, the second pattern material layer (320L) and the first pattern material layer (310L) can be patterned to form the first pattern (310) and the second pattern (320). The process of patterning the second pattern material layer (320L) and the first pattern material layer (310L) may be carried out using a dry etching or wet etching method, but is not limited thereto. Accordingly, the upper surface of the third semiconductor layer (133) may be exposed.

[0118] Accordingly, a semiconductor device according to one embodiment may include a plurality of semiconductor patterns (300) spaced apart along a first direction (X direction) on a third semiconductor layer (133). The plurality of semiconductor patterns (300) may be located directly above the third semiconductor layer (133). The width of each of the plurality of semiconductor patterns (300) along the first direction (X direction) may be substantially the same as each other, but is not limited thereto. The length of each of the plurality of semiconductor patterns (300) along the third direction (Z direction) may be substantially the same as each other, but is not limited thereto.

[0119] Referring to FIG. 17, an interlayer insulating layer (140) can be formed on the upper surface of the semiconductor pattern (300), the side of the semiconductor pattern (300), and the upper surface of the third semiconductor layer (133), an anode electrode (173) can be formed on the semiconductor pattern (300), a gate electrode (150) can be formed on the third semiconductor layer (133), and a cathode electrode (175) can be formed on the second surface (110b) of the substrate (110).

[0120] An interlayer insulating layer (140) can be conformally formed on the upper surface of the semiconductor pattern (300), the side surface of the semiconductor pattern (300), and the upper surface of the third semiconductor layer (133). The thickness of the interlayer insulating layer (140) may be nearly constant. The interlayer insulating layer (140) may be in contact with the semiconductor pattern (300) and the third semiconductor layer (133), but is not limited thereto. The gate electrode (150) may penetrate the portion of the interlayer insulating layer (140) located on the third semiconductor layer (133). The anode electrode (173) may penetrate the portion of the interlayer insulating layer (140) located on the semiconductor pattern (300). Accordingly, a semiconductor device according to one embodiment can be formed.

[0121] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention. Explanation of the symbols

[0123] 110: Substrate 131: First semiconductor layer 132: Second semiconductor layer 133: Third semiconductor layer 140: Interlayer insulation layer 150: Gate electrode 173: Anode electrode 175: Cathode electrode 300: Semiconductor pattern 310: Pattern 1 320: Pattern 2

Claims

Claim 1 A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type different from the first conductivity type located on the first semiconductor layer; a third semiconductor layer of the first conductivity type located on the second semiconductor layer; a gate electrode located on the third semiconductor layer; a semiconductor pattern of the second conductivity type located on the third semiconductor layer; an anode electrode located on the semiconductor pattern; and a cathode electrode located on the lower surface of the first semiconductor layer, wherein the semiconductor pattern comprises a first pattern located on the lower surface of the anode electrode and comprising a semiconductor material having a first energy band gap; and a second pattern located between the first pattern and the third semiconductor layer and comprising a semiconductor material having a second energy band gap larger than the first energy band gap. Claim 2 A semiconductor device according to claim 1, wherein the third semiconductor layer comprises a material having a third energy band gap that is greater than or equal to the second energy band gap. Claim 3 A semiconductor device according to claim 1, wherein each of the first pattern and the second pattern comprises a first element and a second element which are semiconductor elements, and the content (at%) of the first element in the first pattern is greater than the content (at%) of the first element in the second pattern. Claim 4 A semiconductor device according to claim 3, wherein the third semiconductor layer comprises the first element and the second element, and the content (at%) of the first element in the second pattern is greater than or equal to the content (at%) of the first element in the third semiconductor layer. Claim 5 A semiconductor device according to claim 1, wherein the third semiconductor layer comprises a first element and a second element which are semiconductor elements, and the second pattern comprises the first element, the second element, and a third element which is a semiconductor element different from the first element and the second element, and the content (at%) of the second element in the second pattern is less than or equal to the content (at%) of the second element in the third semiconductor layer. Claim 6 In claim 5, the first pattern comprises the first element, the second element, and the third element, which are semiconductor elements, and the semiconductor device in which the content (at%) of the third element in the first pattern is greater than the content (at%) of the third element in the second pattern. Claim 7 A semiconductor device according to claim 5, wherein the first element comprises Si, the second element comprises C, and the third element comprises Ge. Claim 8 A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type different from the first conductivity type located on the first semiconductor layer; a third semiconductor layer of the first conductivity type located on the second semiconductor layer; a gate electrode located on the third semiconductor layer; a semiconductor pattern of the second conductivity type located on the third semiconductor layer and comprising a first element and a second element which are semiconductor elements; an anode electrode located on the semiconductor pattern; and a cathode electrode located on the lower surface of the first semiconductor layer, wherein the semiconductor pattern comprises a first pattern and a second pattern located between the first pattern and the third semiconductor layer, and the content (at%) of the second element in the second pattern is greater than the content (at%) of the second element in the first pattern. Claim 9 A semiconductor device according to claim 8, wherein the first pattern and the second pattern further comprise a third element which is a semiconductor material different from the first element, and the content (at%) of the third element in the second pattern is smaller than the content (at%) of the third element in the first pattern. Claim 10 A semiconductor device comprising a substrate including a first surface and a second surface facing each other, a first semiconductor layer of a first conductivity type located on the first surface of the substrate, a second semiconductor layer of a second conductivity type different from the first conductivity type located on the first semiconductor layer, a third semiconductor layer of the first conductivity type located on the second semiconductor layer and including SiC, a gate electrode located on the third semiconductor layer, a semiconductor pattern of the second conductivity type located on the third semiconductor layer and including SiC, an anode electrode located on the semiconductor pattern, and a cathode electrode located on the lower surface of the first semiconductor layer, wherein the semiconductor pattern has a first energy band gap and includes a first pattern containing Si of a first content (at%), and a second pattern located between the first pattern and the third semiconductor layer and containing Si of a second content (at%) smaller than the first content (at%).

Images